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--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
|
architecture RTL of FIFO is
function func1 (
a : integer;
constant b : integer;
signal c : std_logic;
variable v : std_logic;
file f : std_logic
) return integer;
-- Violations
function func1 (
a : integer;
constant b : integer;
signal c : std_logic;
variable v : std_logic;
file f : std_logic
) return integer;
begin
end architecture RTL;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE Font_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END Font_TB_PKG;
PACKAGE BODY Font_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END Font_TB_PKG;
|
-- from http://www.asic-world.com/code/vhdl/counter.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_counter is
port(
clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end vhdl_counter;
architecture behav of vhdl_counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3155.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03155ent IS
END c05s03b00x00p01n01i03155ent;
ARCHITECTURE c05s03b00x00p01n01i03155arch OF c05s03b00x00p01n01i03155ent IS
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block( GUARD = TRUE )
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03155"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03155 - Disconnect does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s03b00x00p01n01i03155arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3155.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03155ent IS
END c05s03b00x00p01n01i03155ent;
ARCHITECTURE c05s03b00x00p01n01i03155arch OF c05s03b00x00p01n01i03155ent IS
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block( GUARD = TRUE )
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03155"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03155 - Disconnect does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s03b00x00p01n01i03155arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3155.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p01n01i03155ent IS
END c05s03b00x00p01n01i03155ent;
ARCHITECTURE c05s03b00x00p01n01i03155arch OF c05s03b00x00p01n01i03155ent IS
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Define the disconnect specification.
disconnect SIG : RBIT after 0 ns;
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block( GUARD = TRUE )
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable pass : integer := 0;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
wait on SIG;
assert( SIG = '1' );
if ( SIG = '1' ) then
pass := pass + 1;
end if;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
wait on SIG;
assert( SIG = '0' );
if ( SIG = '0' ) then
pass := pass + 1;
end if;
wait for 50 ns;
assert NOT( pass = 2 )
report "***PASSED TEST: c05s03b00x00p01n01i03155"
severity NOTE;
assert ( pass = 2 )
report "***FAILED TEST: c05s03b00x00p01n01i03155 - Disconnect does not work properly."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s03b00x00p01n01i03155arch;
|
--------------------------------------------------------------------------------
-- FILE: BoothEncoder
-- DESC: Encoder of Booth's Multiplier
--
-- Author:
-- Create: 2015-08-14
-- Update: 2015-08-14
-- Status: TESED
-- NOTE 1:
-- Encoder:
-- 0xx -- 0
-- x0x -- positive x1x -- negative
-- xx0 -- a xx1 -- 2a
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity BoothEncoder is
port(
din: in std_logic_vector(2 downto 0);
sel: out std_logic_vector(2 downto 0)
);
end BoothEncoder;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture booth_encoder_arch of BoothEncoder is
begin
sel <= "000" when (din="000" or din="111") else -- 0
"100" when (din="001" or din="010") else -- +a
"110" when (din="101" or din="110") else -- -a
"101" when (din="011") else -- +2a
"111" when (din="100"); -- -2a
end booth_encoder_arch;
|
entity adder is
-- `i0`, `i1` and the carry-in `ci` are inputs of the adder.
-- `s` is the sum output, `co` is the carry-out.
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end adder;
architecture rtl of adder is
begin
-- This full-adder architecture contains two concurrent assignment.
-- Compute the sum.
s <= i0 xor i1 xor ci;
-- Compute the carry.
co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
end rtl;
|
----------------------------------------------------------------
-- Nombre : ROM.vhd
-- Descripcion : Memoria de programa del PIC
----------------------------------------------------------------
-- Version : 1.0
----------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity ROM is
port (
Instruction : out std_logic_vector(11 downto 0); -- Instruction bus
Program_counter : in std_logic_vector(11 downto 0));
end ROM;
architecture AUTOMATIC of ROM is
constant W0 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W1 : std_logic_vector(11 downto 0) := X"003";
constant W2 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W3 : std_logic_vector(11 downto 0) := X"0FF";
constant W4 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPL;
constant W5 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W6 : std_logic_vector(11 downto 0) :=X"000";
constant W7 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W8 : std_logic_vector(11 downto 0) := X"000";
constant W9 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W10 : std_logic_vector(11 downto 0) := X"003";
constant W11 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W12 : std_logic_vector(11 downto 0) := X"000";
constant W13 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W14 : std_logic_vector(11 downto 0) := X"041";
constant W15 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W16 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W17 : std_logic_vector(11 downto 0) :=X"045";
constant W18 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W19 : std_logic_vector(11 downto 0) := X"049";
constant W20 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W21 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W22 : std_logic_vector(11 downto 0) :=X"02E";
constant W23 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W24 : std_logic_vector(11 downto 0) := X"054";
constant W25 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W26 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W27 : std_logic_vector(11 downto 0) :=X"05C";
constant W28 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W29 : std_logic_vector(11 downto 0) := X"053";
constant W30 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W31 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W32 : std_logic_vector(11 downto 0) :=X"07E";
constant W33 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W34 : std_logic_vector(11 downto 0) :=X"0D6";
constant W35 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W36 : std_logic_vector(11 downto 0) := X"04F";
constant W37 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W38 : std_logic_vector(11 downto 0) := X"004";
constant W39 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W40 : std_logic_vector(11 downto 0) := X"04B";
constant W41 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W42 : std_logic_vector(11 downto 0) := X"005";
constant W43 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W44 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W45 : std_logic_vector(11 downto 0) :=X"000";
constant W46 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W47 : std_logic_vector(11 downto 0) := X"001";
constant W48 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W49 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W50 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W51 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W52 : std_logic_vector(11 downto 0) := X"007";
constant W53 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W54 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W55 : std_logic_vector(11 downto 0) :=X"0D6";
constant W56 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W57 : std_logic_vector(11 downto 0) := X"002";
constant W58 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W59 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W60 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W61 : std_logic_vector(11 downto 0) := X"001";
constant W62 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W63 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W64 : std_logic_vector(11 downto 0) :=X"0D6";
constant W65 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_INDXD_MEM;
constant W66 : std_logic_vector(11 downto 0) := X"010";
constant W67 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W68 : std_logic_vector(11 downto 0) :=X"023";
constant W69 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W70 : std_logic_vector(11 downto 0) := X"001";
constant W71 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W72 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W73 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W74 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W75 : std_logic_vector(11 downto 0) := X"0FF";
constant W76 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W77 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W78 : std_logic_vector(11 downto 0) :=X"0D6";
constant W79 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W80 : std_logic_vector(11 downto 0) := X"002";
constant W81 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W82 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W83 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W84 : std_logic_vector(11 downto 0) := X"009";
constant W85 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W86 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W87 : std_logic_vector(11 downto 0) :=X"0D6";
constant W88 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_INDXD_MEM;
constant W89 : std_logic_vector(11 downto 0) := X"020";
constant W90 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W91 : std_logic_vector(11 downto 0) :=X"023";
constant W92 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W93 : std_logic_vector(11 downto 0) := X"001";
constant W94 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W95 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W96 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W97 : std_logic_vector(11 downto 0) := X"002";
constant W98 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W99 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W100 : std_logic_vector(11 downto 0) :=X"0D6";
constant W101 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W102 : std_logic_vector(11 downto 0) := X"000";
constant W103 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ADD;
constant W104 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W105 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W106 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W107 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W108 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W109 : std_logic_vector(11 downto 0) := X"041";
constant W110 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W111 : std_logic_vector(11 downto 0) := X"002";
constant W112 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W113 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W114 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W115 : std_logic_vector(11 downto 0) := X"0FF";
constant W116 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W117 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W118 : std_logic_vector(11 downto 0) :=X"0D6";
constant W119 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_B;
constant W120 : std_logic_vector(11 downto 0) := X"041";
constant W121 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ADD;
constant W122 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W123 : std_logic_vector(11 downto 0) := X"031";
constant W124 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W125 : std_logic_vector(11 downto 0) :=X"023";
constant W126 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W127 : std_logic_vector(11 downto 0) := X"001";
constant W128 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W129 : std_logic_vector(11 downto 0) := X"041";
constant W130 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W131 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W132 : std_logic_vector(11 downto 0) :=X"091";
constant W133 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W134 : std_logic_vector(11 downto 0) := X"049";
constant W135 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W136 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W137 : std_logic_vector(11 downto 0) :=X"0A7";
constant W138 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W139 : std_logic_vector(11 downto 0) := X"054";
constant W140 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W141 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W142 : std_logic_vector(11 downto 0) :=X"0BD";
constant W143 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W144 : std_logic_vector(11 downto 0) :=X"0D6";
constant W145 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W146 : std_logic_vector(11 downto 0) := X"002";
constant W147 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W148 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W149 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W150 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W151 : std_logic_vector(11 downto 0) := X"009";
constant W152 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W153 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W154 : std_logic_vector(11 downto 0) :=X"0D6";
constant W155 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_INDXD_MEM & DST_A;
constant W156 : std_logic_vector(11 downto 0) := X"020";
constant W157 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W158 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W159 : std_logic_vector(11 downto 0) := X"005";
constant W160 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W161 : std_logic_vector(11 downto 0) := X"041";
constant W162 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W163 : std_logic_vector(11 downto 0) := X"004";
constant W164 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W165 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W166 : std_logic_vector(11 downto 0) :=X"000";
constant W167 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W168 : std_logic_vector(11 downto 0) := X"002";
constant W169 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W170 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W171 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W172 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W173 : std_logic_vector(11 downto 0) := X"007";
constant W174 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W175 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W176 : std_logic_vector(11 downto 0) :=X"0D6";
constant W177 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_INDXD_MEM & DST_A;
constant W178 : std_logic_vector(11 downto 0) := X"010";
constant W179 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W180 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W181 : std_logic_vector(11 downto 0) := X"005";
constant W182 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W183 : std_logic_vector(11 downto 0) := X"053";
constant W184 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W185 : std_logic_vector(11 downto 0) := X"004";
constant W186 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W187 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W188 : std_logic_vector(11 downto 0) :=X"000";
constant W189 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W190 : std_logic_vector(11 downto 0) := X"031";
constant W191 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W192 : std_logic_vector(11 downto 0) :="000011110000";
constant W193 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_AND;
constant W194 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W195 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W196 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W197 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W198 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W199 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W200 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W201 : std_logic_vector(11 downto 0) := X"004";
constant W202 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W203 : std_logic_vector(11 downto 0) := X"031";
constant W204 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W205 : std_logic_vector(11 downto 0) :="000000001111";
constant W206 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_AND;
constant W207 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W208 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W209 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W210 : std_logic_vector(11 downto 0) := X"005";
constant W211 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W212 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W213 : std_logic_vector(11 downto 0) :=X"000";
constant W214 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W215 : std_logic_vector(11 downto 0) := X"045";
constant W216 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W217 : std_logic_vector(11 downto 0) := X"004";
constant W218 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W219 : std_logic_vector(11 downto 0) := X"052";
constant W220 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W221 : std_logic_vector(11 downto 0) := X"005";
constant W222 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W223 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W224 : std_logic_vector(11 downto 0) :=X"000";
begin -- AUTOMATIC
with Program_counter select
Instruction <=
W0 when X"000",
W1 when X"001",
W2 when X"002",
W3 when X"003",
W4 when X"004",
W5 when X"005",
W6 when X"006",
W7 when X"007",
W8 when X"008",
W9 when X"009",
W10 when X"00A",
W11 when X"00B",
W12 when X"00C",
W13 when X"00D",
W14 when X"00E",
W15 when X"00F",
W16 when X"010",
W17 when X"011",
W18 when X"012",
W19 when X"013",
W20 when X"014",
W21 when X"015",
W22 when X"016",
W23 when X"017",
W24 when X"018",
W25 when X"019",
W26 when X"01A",
W27 when X"01B",
W28 when X"01C",
W29 when X"01D",
W30 when X"01E",
W31 when X"01F",
W32 when X"020",
W33 when X"021",
W34 when X"022",
W35 when X"023",
W36 when X"024",
W37 when X"025",
W38 when X"026",
W39 when X"027",
W40 when X"028",
W41 when X"029",
W42 when X"02A",
W43 when X"02B",
W44 when X"02C",
W45 when X"02D",
W46 when X"02E",
W47 when X"02F",
W48 when X"030",
W49 when X"031",
W50 when X"032",
W51 when X"033",
W52 when X"034",
W53 when X"035",
W54 when X"036",
W55 when X"037",
W56 when X"038",
W57 when X"039",
W58 when X"03A",
W59 when X"03B",
W60 when X"03C",
W61 when X"03D",
W62 when X"03E",
W63 when X"03F",
W64 when X"040",
W65 when X"041",
W66 when X"042",
W67 when X"043",
W68 when X"044",
W69 when X"045",
W70 when X"046",
W71 when X"047",
W72 when X"048",
W73 when X"049",
W74 when X"04A",
W75 when X"04B",
W76 when X"04C",
W77 when X"04D",
W78 when X"04E",
W79 when X"04F",
W80 when X"050",
W81 when X"051",
W82 when X"052",
W83 when X"053",
W84 when X"054",
W85 when X"055",
W86 when X"056",
W87 when X"057",
W88 when X"058",
W89 when X"059",
W90 when X"05A",
W91 when X"05B",
W92 when X"05C",
W93 when X"05D",
W94 when X"05E",
W95 when X"05F",
W96 when X"060",
W97 when X"061",
W98 when X"062",
W99 when X"063",
W100 when X"064",
W101 when X"065",
W102 when X"066",
W103 when X"067",
W104 when X"068",
W105 when X"069",
W106 when X"06A",
W107 when X"06B",
W108 when X"06C",
W109 when X"06D",
W110 when X"06E",
W111 when X"06F",
W112 when X"070",
W113 when X"071",
W114 when X"072",
W115 when X"073",
W116 when X"074",
W117 when X"075",
W118 when X"076",
W119 when X"077",
W120 when X"078",
W121 when X"079",
W122 when X"07A",
W123 when X"07B",
W124 when X"07C",
W125 when X"07D",
W126 when X"07E",
W127 when X"07F",
W128 when X"080",
W129 when X"081",
W130 when X"082",
W131 when X"083",
W132 when X"084",
W133 when X"085",
W134 when X"086",
W135 when X"087",
W136 when X"088",
W137 when X"089",
W138 when X"08A",
W139 when X"08B",
W140 when X"08C",
W141 when X"08D",
W142 when X"08E",
W143 when X"08F",
W144 when X"090",
W145 when X"091",
W146 when X"092",
W147 when X"093",
W148 when X"094",
W149 when X"095",
W150 when X"096",
W151 when X"097",
W152 when X"098",
W153 when X"099",
W154 when X"09A",
W155 when X"09B",
W156 when X"09C",
W157 when X"09D",
W158 when X"09E",
W159 when X"09F",
W160 when X"0A0",
W161 when X"0A1",
W162 when X"0A2",
W163 when X"0A3",
W164 when X"0A4",
W165 when X"0A5",
W166 when X"0A6",
W167 when X"0A7",
W168 when X"0A8",
W169 when X"0A9",
W170 when X"0AA",
W171 when X"0AB",
W172 when X"0AC",
W173 when X"0AD",
W174 when X"0AE",
W175 when X"0AF",
W176 when X"0B0",
W177 when X"0B1",
W178 when X"0B2",
W179 when X"0B3",
W180 when X"0B4",
W181 when X"0B5",
W182 when X"0B6",
W183 when X"0B7",
W184 when X"0B8",
W185 when X"0B9",
W186 when X"0BA",
W187 when X"0BB",
W188 when X"0BC",
W189 when X"0BD",
W190 when X"0BE",
W191 when X"0BF",
W192 when X"0C0",
W193 when X"0C1",
W194 when X"0C2",
W195 when X"0C3",
W196 when X"0C4",
W197 when X"0C5",
W198 when X"0C6",
W199 when X"0C7",
W200 when X"0C8",
W201 when X"0C9",
W202 when X"0CA",
W203 when X"0CB",
W204 when X"0CC",
W205 when X"0CD",
W206 when X"0CE",
W207 when X"0CF",
W208 when X"0D0",
W209 when X"0D1",
W210 when X"0D2",
W211 when X"0D3",
W212 when X"0D4",
W213 when X"0D5",
W214 when X"0D6",
W215 when X"0D7",
W216 when X"0D8",
W217 when X"0D9",
W218 when X"0DA",
W219 when X"0DB",
W220 when X"0DC",
W221 when X"0DD",
W222 when X"0DE",
W223 when X"0DF",
W224 when X"0E0",
X"0" & TYPE_1 & ALU_ADD when others;
end AUTOMATIC;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (14);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 1 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (140);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (16);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := 0;
constant CFG_MIG_7SERIES_MODEL : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (2);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- Dynamic Partial Reconfiguration
constant CFG_PRC : integer := 0;
constant CFG_CRC_EN : integer := 0;
constant CFG_EDAC_EN : integer := 0;
constant CFG_WORDS_BLOCK : integer := 100;
constant CFG_DCM_FIFO : integer := 0;
constant CFG_DPR_FIFO : integer := 9;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity eb_wrapper_loopback is
Generic (
C_ASYNFIFO_WIDTH : integer := 72
);
Port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
pfull : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
pempty : OUT std_logic;
empty : OUT std_logic;
data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : IN std_logic
);
end entity eb_wrapper_loopback;
architecture Behavioral of eb_wrapper_loopback is
--- 16384 x 72
component eb_fifo
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic;
rst : IN std_logic
);
end component;
--- 16384 x 64, with data count synchronized to rd_clk
component k7_eb_fifo_counted_resized
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic;
rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : IN std_logic
);
end component;
signal data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal my_din : std_logic_VECTOR(64-1 downto 0);
signal my_dout : std_logic_VECTOR(64-1 downto 0);
begin
data_count <= data_count_i;
my_din <= din(64-1 downto 0);
dout(71 downto 64) <= C_ALL_ZEROS(71 downto 64);
dout(63 downto 0) <= my_dout;
-- ------------------------------------------
Syn_EB_FIFO_data_count:
process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
data_count_i <= data_count_wire;
end if;
end process;
-- ------------------------------------------
U0:
k7_eb_fifo_counted_resized
port map (
wr_clk => wr_clk ,
wr_en => wr_en ,
din => my_din ,
prog_full => pfull ,
full => full ,
rd_clk => rd_clk ,
rd_en => rd_en ,
dout => my_dout ,
prog_empty => pempty ,
empty => empty ,
rd_data_count => data_count_wire ,
rst => rst
);
end architecture Behavioral;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: KEYBOARD_CONTROLLER Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY KEYBOARD_CONTROLLER_tb_vhd IS
END KEYBOARD_CONTROLLER_tb_vhd;
ARCHITECTURE behavior OF KEYBOARD_CONTROLLER_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT KEYBOARD_CONTROLLER
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
ASCII_OUT: out STD_LOGIC_VECTOR (7 downto 0);
ASCII_RD : out STD_LOGIC;
ASCII_WE : out STD_LOGIC);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL PS2_CLK : STD_LOGIC := '1';
SIGNAL PS2_DATA: STD_LOGIC := '1';
SIGNAL ASCII_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL ASCII_RD: STD_LOGIC := '0';
SIGNAL ASCII_WE: STD_LOGIC := '0';
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: KEYBOARD_CONTROLLER PORT MAP( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA=> PS2_DATA,
ASCII_OUT => ASCII_OUT,
ASCII_RD=> ASCII_RD,
ASCII_WE=> ASCII_WE);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 us;
report "Start VGA_Controller Test Bench" severity NOTE;
--Simulate Pressing A
--Sending the Break Code X"F0"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
--Sending the Key Code X"1C"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '0';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
wait; -- will wait forever
END PROCESS;
END;
|
-------------------------------------------------------------------------------
-- $Id: lmb_bram_if_cntlr.vhd,v 1.1.2.13 2010/11/25 12:28:48 stefana Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.13 $
-- Date: $Date: 2010/11/25 12:28:48 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library unisim;
use unisim.vcomponents.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_ENCODE : boolean;
C_USE_LUT6 : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_USE_LUT6 : boolean;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_USE_LUT6 : boolean := Family_To_LUT_Size(String_To_Family(C_FAMILY,false)) = 6;
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i;
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr;
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ipregister IS
PORT(
clk : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
wrip : IN std_logic;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END ipregister ;
architecture rtl of ipregister is
signal ipreg_s : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------
-- Instructon Pointer Register
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
ipreg_s <= RESET_IP_C; -- See cpu86pack
elsif rising_edge(clk) then
if (wrip='1') then
ipreg_s<= ipbus;
end if;
end if;
end process;
ipreg <= ipreg_s;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ipregister IS
PORT(
clk : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
wrip : IN std_logic;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END ipregister ;
architecture rtl of ipregister is
signal ipreg_s : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------
-- Instructon Pointer Register
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
ipreg_s <= RESET_IP_C; -- See cpu86pack
elsif rising_edge(clk) then
if (wrip='1') then
ipreg_s<= ipbus;
end if;
end if;
end process;
ipreg <= ipreg_s;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ipregister IS
PORT(
clk : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
wrip : IN std_logic;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END ipregister ;
architecture rtl of ipregister is
signal ipreg_s : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------
-- Instructon Pointer Register
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
ipreg_s <= RESET_IP_C; -- See cpu86pack
elsif rising_edge(clk) then
if (wrip='1') then
ipreg_s<= ipbus;
end if;
end if;
end process;
ipreg <= ipreg_s;
end rtl;
|
------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: filter.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 17:57:17 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library filter_v1_00_a;
use filter_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity filter is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
CLK_48 : in std_logic;
--RST : in std_logic;
HP_BTN : in std_logic;
BP_BTN : in std_logic;
LP_BTN : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity filter;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of filter is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 30;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity filter_v1_00_a.user_logic --work.user_logic --
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
CLK_48 => CLK_48,
RST => '0', -- disable resest so that the filter is always in the working mode.
HP_BTN => HP_BTN,
BP_BTN => BP_BTN,
LP_BTN => LP_BTN,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: filter.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 17:57:17 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library filter_v1_00_a;
use filter_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity filter is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
CLK_48 : in std_logic;
--RST : in std_logic;
HP_BTN : in std_logic;
BP_BTN : in std_logic;
LP_BTN : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity filter;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of filter is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 30;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity filter_v1_00_a.user_logic --work.user_logic --
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
CLK_48 => CLK_48,
RST => '0', -- disable resest so that the filter is always in the working mode.
HP_BTN => HP_BTN,
BP_BTN => BP_BTN,
LP_BTN => LP_BTN,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: filter.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 17:57:17 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library filter_v1_00_a;
use filter_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity filter is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
CLK_48 : in std_logic;
--RST : in std_logic;
HP_BTN : in std_logic;
BP_BTN : in std_logic;
LP_BTN : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity filter;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of filter is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 30;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity filter_v1_00_a.user_logic --work.user_logic --
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
CLK_48 => CLK_48,
RST => '0', -- disable resest so that the filter is always in the working mode.
HP_BTN => HP_BTN,
BP_BTN => BP_BTN,
LP_BTN => LP_BTN,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc593.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00593ent IS
END c03s04b01x00p01n01i00593ent;
ARCHITECTURE c03s04b01x00p01n01i00593arch OF c03s04b01x00p01n01i00593ent IS
type integer_vector is array (natural range <>) of integer;
type integer_vector_file is file of integer_vector;
BEGIN
TESTING: PROCESS
file filein : integer_vector_file open write_mode is "iofile.25";
BEGIN
for i in 1 to 100 loop
write(filein,(1,2,3,4));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00593 - The output file will be verified by test s010228.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00593arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc593.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00593ent IS
END c03s04b01x00p01n01i00593ent;
ARCHITECTURE c03s04b01x00p01n01i00593arch OF c03s04b01x00p01n01i00593ent IS
type integer_vector is array (natural range <>) of integer;
type integer_vector_file is file of integer_vector;
BEGIN
TESTING: PROCESS
file filein : integer_vector_file open write_mode is "iofile.25";
BEGIN
for i in 1 to 100 loop
write(filein,(1,2,3,4));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00593 - The output file will be verified by test s010228.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00593arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc593.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00593ent IS
END c03s04b01x00p01n01i00593ent;
ARCHITECTURE c03s04b01x00p01n01i00593arch OF c03s04b01x00p01n01i00593ent IS
type integer_vector is array (natural range <>) of integer;
type integer_vector_file is file of integer_vector;
BEGIN
TESTING: PROCESS
file filein : integer_vector_file open write_mode is "iofile.25";
BEGIN
for i in 1 to 100 loop
write(filein,(1,2,3,4));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00593 - The output file will be verified by test s010228.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00593arch;
|
------------------------------------------------------------------------------
-- superip.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: superip.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library superip_v1_00_a;
use superip_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity superip is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity superip;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of superip is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity superip_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left_out,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right_out,
SAMPLE_TRIG => SAMPLE_TRIG,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- superip.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: superip.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library superip_v1_00_a;
use superip_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity superip is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity superip;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of superip is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity superip_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left_out,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right_out,
SAMPLE_TRIG => SAMPLE_TRIG,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 16:43:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../open.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3in is
generic(
NUM_BITS: positive := 113
);
port (
A: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
s0: in STD_LOGIC;
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3in is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
begin
D(0) <= (A(0) and s0) xor B(0);
D(1) <= (A(1) and s0) xor B(1);
D(2) <= (A(2) and s0) xor B(2);
D(3) <= (A(3) and s0) xor B(3);
D(4) <= (A(4) and s0) xor B(4);
D(5) <= (A(5) and s0) xor B(5);
D(6) <= (A(6) and s0) xor B(6);
D(7) <= (A(7) and s0) xor B(7);
D(8) <= (A(8) and s0) xor B(8);
D(9) <= (A(9) and s0) xor B(9);
D(10) <= (A(10) and s0) xor B(10);
D(11) <= (A(11) and s0) xor B(11);
D(12) <= (A(12) and s0) xor B(12);
D(13) <= (A(13) and s0) xor B(13);
D(14) <= (A(14) and s0) xor B(14);
D(15) <= (A(15) and s0) xor B(15);
D(16) <= (A(16) and s0) xor B(16);
D(17) <= (A(17) and s0) xor B(17);
D(18) <= (A(18) and s0) xor B(18);
D(19) <= (A(19) and s0) xor B(19);
D(20) <= (A(20) and s0) xor B(20);
D(21) <= (A(21) and s0) xor B(21);
D(22) <= (A(22) and s0) xor B(22);
D(23) <= (A(23) and s0) xor B(23);
D(24) <= (A(24) and s0) xor B(24);
D(25) <= (A(25) and s0) xor B(25);
D(26) <= (A(26) and s0) xor B(26);
D(27) <= (A(27) and s0) xor B(27);
D(28) <= (A(28) and s0) xor B(28);
D(29) <= (A(29) and s0) xor B(29);
D(30) <= (A(30) and s0) xor B(30);
D(31) <= (A(31) and s0) xor B(31);
D(32) <= (A(32) and s0) xor B(32);
D(33) <= (A(33) and s0) xor B(33);
D(34) <= (A(34) and s0) xor B(34);
D(35) <= (A(35) and s0) xor B(35);
D(36) <= (A(36) and s0) xor B(36);
D(37) <= (A(37) and s0) xor B(37);
D(38) <= (A(38) and s0) xor B(38);
D(39) <= (A(39) and s0) xor B(39);
D(40) <= (A(40) and s0) xor B(40);
D(41) <= (A(41) and s0) xor B(41);
D(42) <= (A(42) and s0) xor B(42);
D(43) <= (A(43) and s0) xor B(43);
D(44) <= (A(44) and s0) xor B(44);
D(45) <= (A(45) and s0) xor B(45);
D(46) <= (A(46) and s0) xor B(46);
D(47) <= (A(47) and s0) xor B(47);
D(48) <= (A(48) and s0) xor B(48);
D(49) <= (A(49) and s0) xor B(49);
D(50) <= (A(50) and s0) xor B(50);
D(51) <= (A(51) and s0) xor B(51);
D(52) <= (A(52) and s0) xor B(52);
D(53) <= (A(53) and s0) xor B(53);
D(54) <= (A(54) and s0) xor B(54);
D(55) <= (A(55) and s0) xor B(55);
D(56) <= (A(56) and s0) xor B(56);
D(57) <= (A(57) and s0) xor B(57);
D(58) <= (A(58) and s0) xor B(58);
D(59) <= (A(59) and s0) xor B(59);
D(60) <= (A(60) and s0) xor B(60);
D(61) <= (A(61) and s0) xor B(61);
D(62) <= (A(62) and s0) xor B(62);
D(63) <= (A(63) and s0) xor B(63);
D(64) <= (A(64) and s0) xor B(64);
D(65) <= (A(65) and s0) xor B(65);
D(66) <= (A(66) and s0) xor B(66);
D(67) <= (A(67) and s0) xor B(67);
D(68) <= (A(68) and s0) xor B(68);
D(69) <= (A(69) and s0) xor B(69);
D(70) <= (A(70) and s0) xor B(70);
D(71) <= (A(71) and s0) xor B(71);
D(72) <= (A(72) and s0) xor B(72);
D(73) <= (A(73) and s0) xor B(73);
D(74) <= (A(74) and s0) xor B(74);
D(75) <= (A(75) and s0) xor B(75);
D(76) <= (A(76) and s0) xor B(76);
D(77) <= (A(77) and s0) xor B(77);
D(78) <= (A(78) and s0) xor B(78);
D(79) <= (A(79) and s0) xor B(79);
D(80) <= (A(80) and s0) xor B(80);
D(81) <= (A(81) and s0) xor B(81);
D(82) <= (A(82) and s0) xor B(82);
D(83) <= (A(83) and s0) xor B(83);
D(84) <= (A(84) and s0) xor B(84);
D(85) <= (A(85) and s0) xor B(85);
D(86) <= (A(86) and s0) xor B(86);
D(87) <= (A(87) and s0) xor B(87);
D(88) <= (A(88) and s0) xor B(88);
D(89) <= (A(89) and s0) xor B(89);
D(90) <= (A(90) and s0) xor B(90);
D(91) <= (A(91) and s0) xor B(91);
D(92) <= (A(92) and s0) xor B(92);
D(93) <= (A(93) and s0) xor B(93);
D(94) <= (A(94) and s0) xor B(94);
D(95) <= (A(95) and s0) xor B(95);
D(96) <= (A(96) and s0) xor B(96);
D(97) <= (A(97) and s0) xor B(97);
D(98) <= (A(98) and s0) xor B(98);
D(99) <= (A(99) and s0) xor B(99);
D(100) <= (A(100) and s0) xor B(100);
D(101) <= (A(101) and s0) xor B(101);
D(102) <= (A(102) and s0) xor B(102);
D(103) <= (A(103) and s0) xor B(103);
D(104) <= (A(104) and s0) xor B(104);
D(105) <= (A(105) and s0) xor B(105);
D(106) <= (A(106) and s0) xor B(106);
D(107) <= (A(107) and s0) xor B(107);
D(108) <= (A(108) and s0) xor B(108);
D(109) <= (A(109) and s0) xor B(109);
D(110) <= (A(110) and s0) xor B(110);
D(111) <= (A(111) and s0) xor B(111);
D(112) <= (A(112) and s0) xor B(112);
end; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze Interrupt Controller with up to 32 ports.
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.components.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_InterruptController_Device is
generic (
DEBUG : BOOLEAN := FALSE;
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
PORTS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
-- PicoBlaze interrupt interface (direct coupled)
PB_Interrupt : out STD_LOGIC;
PB_Interrupt_Ack : in STD_LOGIC;
-- Interrupt source interface
Dev_Interrupt : in STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Dev_Interrupt_Ack : out STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Dev_Interrupt_Message : in T_SLVV_8(PORTS - 1 downto 0)
);
end entity;
architecture rtl of pb_InterruptController_Device is
attribute KEEP : BOOLEAN;
constant REQUIRED_REG_BYTES : POSITIVE := div_ceil(PORTS, 8);
-- Regarding REQUIRED_REG_BYTES, the position of the enable/disable marker bit is moved from LSB to MSB
-- Example 1:
-- REQUIRED_REG_BYTES = 1
-- -> no bit is required to address the register in the field, because it's only one byte
-- => enable/disable bit is located at bit 0
--
-- Example 2:
-- REQUIRED_REG_BYTES = 3
-- -> 2 bits are required to address 3 registers in the field [23:0]
-- -> [1:0] is used to address the correct byte/register
-- => enable/disable bit is located at bit 2
constant BIT_EN_DIS : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant BIT_VEC_MES : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant REG_WO_ENABLE_BIT_VALUE : STD_LOGIC := '0';
constant REG_WO_DISABLE_BIT_VALUE : STD_LOGIC := '1';
constant REG_RO_VECTOR_BIT_VALUE : STD_LOGIC := '0';
constant REG_RO_MESSAGE_BIT_VALUE : STD_LOGIC := '1';
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_InterruptEnable_slvv : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := (others => (others => '0'));
signal Reg_InterruptEnable : STD_LOGIC_VECTOR((REQUIRED_REG_BYTES * 8) - 1 downto 0);
type T_STATE is (ST_IDLE, ST_INTERRUPT_PENDING, ST_INTERRUPT_MESSAGE);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal Interrupt_re : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal InterruptPending_r : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := (others => '0');
signal InterruptMessages_d : T_SLVV_8(PORTS - 1 downto 0) := (others => (others => '0'));
signal InterruptRequestsOpen : STD_LOGIC;
signal InterruptRequestVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal InterruptSource_Read : STD_LOGIC;
signal FSM_DataOut : T_SLV_8;
signal FSM_Arbitrate : STD_LOGIC;
signal FSM_InterruptClearVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal Arb_GrantVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal Arb_GrantVector_bin : STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
attribute KEEP of FSM_Arbitrate : signal is DEBUG;
attribute KEEP of Arb_GrantVector : signal is DEBUG;
attribute KEEP of InterruptRequestVector : signal is DEBUG;
begin
assert (PORTS <= 32)
report "InterruptController supports only up to 32 interrupt sources!"
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_Address => Address,
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Data => DataIn,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_Data => AdrDec_Data
);
process(Clock, AdrDec_WriteAddress)
variable index : NATURAL;
begin
index := to_index(AdrDec_WriteAddress(BIT_EN_DIS - 1 downto 0));
if rising_edge(Clock) then
if (Reset = '1') then
Reg_InterruptEnable_slvv <= (others => (others => '0'));
elsif (AdrDec_we = '1') then
case AdrDec_WriteAddress(BIT_EN_DIS) is
when REG_WO_ENABLE_BIT_VALUE => Reg_InterruptEnable_slvv(index) <= Reg_InterruptEnable_slvv(index) or AdrDec_Data;
when REG_WO_DISABLE_BIT_VALUE => Reg_InterruptEnable_slvv(index) <= Reg_InterruptEnable_slvv(index) and not AdrDec_Data;
when others => null;
end case;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_InterruptEnable_slvv, FSM_DataOut)
variable index : NATURAL;
begin
index := to_index(AdrDec_ReadAddress(BIT_VEC_MES - 1 downto 0));
DataOut <= FSM_DataOut;
case AdrDec_ReadAddress(BIT_VEC_MES) is
when REG_RO_VECTOR_BIT_VALUE => DataOut <= Reg_InterruptEnable_slvv(index);
when REG_RO_MESSAGE_BIT_VALUE => DataOut <= FSM_DataOut;
when others => DataOut <= (others => 'X');
end case;
InterruptSource_Read <= AdrDec_re and to_sl(AdrDec_ReadAddress(BIT_VEC_MES) = REG_RO_MESSAGE_BIT_VALUE);
end process;
Interrupt <= '0';
Message <= x"00";
genPort : for i in 0 to PORTS - 1 generate
signal Interrupt_d : STD_LOGIC := '0';
begin
Interrupt_d <= Dev_Interrupt(i) when rising_edge(Clock);
Interrupt_re(i) <= not Interrupt_d and Dev_Interrupt(i);
-- RS-FFs to latch the interrupt signal and the message
InterruptPending_r(i) <= ffrs(q => InterruptPending_r(i), rst => (Reset or FSM_InterruptClearVector(i)), set => Interrupt_re(i)) when rising_edge(Clock);
InterruptMessages_d(i) <= ffdre(q => InterruptMessages_d(i), d => Dev_Interrupt_Message(i), rst => (Reset or FSM_InterruptClearVector(i)), en => Interrupt_re(i)) when rising_edge(Clock);
end generate;
Reg_InterruptEnable <= to_slv(Reg_InterruptEnable_slvv);
InterruptRequestVector <= InterruptPending_r and Reg_InterruptEnable(InterruptPending_r'range);
InterruptRequestsOpen <= slv_or(InterruptRequestVector and not FSM_InterruptClearVector);
Arb : entity PoC.bus_Arbiter
generic map (
STRATEGY => "RR",
PORTS => PORTS,
WEIGHTS => (0 to PORTS - 1 => 1),
OUTPUT_REG => FALSE
)
port map (
Clock => Clock,
Reset => Reset,
Arbitrate => FSM_Arbitrate,
Request_Vector => InterruptRequestVector,
Grant_Vector => Arb_GrantVector,
Grant_Index => Arb_GrantVector_bin
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, InterruptRequestsOpen, Arb_GrantVector, Arb_GrantVector_bin, PB_Interrupt_Ack, InterruptSource_Read, InterruptMessages_d)
begin
NextState <= State;
PB_Interrupt <= InterruptRequestsOpen;
FSM_DataOut <= resize(Arb_GrantVector_bin, FSM_DataOut'length);
Dev_Interrupt_Ack <= (others => '0');
FSM_Arbitrate <= '0';
FSM_InterruptClearVector <= (others => '0');
case State is
when ST_IDLE =>
if (InterruptRequestsOpen = '1') then
FSM_Arbitrate <= '1';
NextState <= ST_INTERRUPT_PENDING;
end if;
when ST_INTERRUPT_PENDING =>
FSM_DataOut <= resize(Arb_GrantVector_bin, FSM_DataOut'length);
if (InterruptSource_Read = '1') then
NextState <= ST_INTERRUPT_MESSAGE;
end if;
when ST_INTERRUPT_MESSAGE =>
FSM_DataOut <= InterruptMessages_d(to_index(Arb_GrantVector_bin));
if (PB_Interrupt_Ack = '1') then
FSM_InterruptClearVector <= Arb_GrantVector;
Dev_Interrupt_Ack <= Arb_GrantVector;
if (InterruptRequestsOpen = '1') then
FSM_Arbitrate <= '1';
NextState <= ST_INTERRUPT_PENDING;
else
NextState <= ST_IDLE;
end if;
end if;
end case;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_clk_en : in std_logic;
cpu_reset : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
carry : out std_logic;
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_clk_en,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
carry => carry,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
|
------------------------------------------------------------------------------
-- This file is part of an extension to the GRLIB VHDL IP library.
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
-- Copyright (C) 2013, System Level Design (SLD) group @ Columbia University
--
-- GRLIP is a Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------------
-- Entity: ahb_rate_trace
-- File: ahb_rate_trace.vhd
-- Authors: Paolo Mantovani - SLD @ Columbia University
-- Van Bui - ARCADE @ Columbia University
-- Description: Amba 2.0 AHB Slave to Network Interface wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
use STD.textio.all;
use ieee.std_logic_textio.all;
--pragma translate_on
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.genacc.all;
library sld;
use sld.tracing.all;
entity ahb_rate_trace is
generic (
tech : integer := virtex7;
hindex : integer range 0 to NAHBSLV-1 := 5;
hmask : integer := 16#ffc#;
haddr : integer := 16#b00#;
pirq : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ipreg : in ipreg_out_type;
ahbso : out ahb_slv_out_type
);
end ahb_rate_trace;
architecture rtl of ahb_rate_trace is
-- We are interested in a period of time of roughly 2^30 cycles
-- and we try to compute the derivative of the # of DRAM accesses
-- every 2^14 cycles. We need a 2^16 words memory.
signal memout : std_logic_vector(MEM_BITS - 1 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
signal mem_selected : std_logic_vector(AHB_BITS-1 downto 0);
signal sram_input : std_logic_vector((MEM_BITS -1) downto 0);
signal rden : std_ulogic;
signal rdaddr : std_logic_vector((MEM_SIZE_LOG-1) downto 0);
signal sw : softsigs;
signal rate, rate_next : std_logic_vector(MEM_SIZE_LOG - 1 downto 0);
signal activity, activity_next : std_logic_vector(ACTIVITY_BITS-1 downto 0);
signal count, count_next : std_logic_vector(COUNT_BITS - 1 downto 0);
signal log : std_ulogic;
signal full_log : std_ulogic;
signal sample : std_ulogic;
signal irq : std_logic_vector(NAHBIRQ-1 downto 0);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_SLD, SLD_RATE_TRACE, 0, 0, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
begin -- rtl
-----------------------------------------------------------------------------
-- SRAMS interface
-----------------------------------------------------------------------------
syncram_dp_1: syncram_dp_wrapper
generic map (
tech => tech,
pirq => pirq)
port map (
rst => rst,
clk => clk,
rdaddr => rdaddr,
rden => rden,
packsigs => sram_input,
sample => sample,
reset_log => sw.reset_stats,
stop_log => sw.dump_stats,
full_log => full_log,
memout => memout,
irq => irq);
-----------------------------------------------------------------------------
-- Pack pipeline signals
-----------------------------------------------------------------------------
packer_1 : packer
port map(
rst => rst,
clk => clk,
ipreg => ipreg,
mem_selected => mem_selected,
activity => activity,
packsigs => sram_input);
-----------------------------------------------------------------------------
-- Memory access detection
-----------------------------------------------------------------------------
detect_mem_access_1 : detect_mem_access
port map (
ahbsi => ahbsi,
mem_selected => mem_selected);
-----------------------------------------------------------------------------
-- AHB signal handler
-----------------------------------------------------------------------------
decode_address: process (ahbsi, rden, rate, activity)
variable haddr : std_logic_vector(31 downto 0);
begin -- process address_decoder
haddr := "00" & ahbsi.haddr(31 downto 2);
haddr := haddr_mask and haddr;
rdaddr <= haddr(MEM_SIZE_LOG - 1 downto 0);
rate_next <= rate;
activity_next <= activity;
sw.sample_rate <= '0';
sw.sample_event <= '0';
sw.reset_stats <= '0';
sw.dump_stats <= '0';
if rden = '1' and ahbsi.htrans = HTRANS_NONSEQ
and ahbsi.hwrite = '1' then
if haddr(MEM_SIZE_LOG - 1 downto 0) = zero_adx then -- 0
sw.reset_stats <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = one_adx then -- 1
sw.dump_stats <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = ahb_adx then -- 7
activity_next <= ahb_act;
sw.sample_event <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = pc_adx then -- 4
activity_next <= pc_act;
sw.sample_event <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = inst_adx then -- 6
activity_next <= inst_act;
sw.sample_event <= '1';
else
rate_next <= haddr(MEM_SIZE_LOG - 1 downto 0);
sw.sample_rate <= '1';
end if;
end if;
end process decode_address;
update_params: process (clk,rst)
begin
if rst = '0' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '0';
rate <= conv_std_logic_vector(2, COUNT_BITS);
activity <= conv_std_logic_vector(0, ACTIVITY_BITS);
elsif clk'event and clk='1' then
if sw.reset_stats = '1' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '1';
elsif sw.dump_stats = '1' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '0';
elsif sw.sample_rate = '1' then
rate <= rate_next;
elsif sw.sample_event = '1' then
activity <= activity_next;
elsif full_log = '1' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '0';
elsif log = '1' then
count <= count_next;
if count_next = rate then
count <= one_count;
end if;
end if;
end if;
end process update_params;
sample <= '1' when ((log = '1') and (count_next = rate)) else '0';
rden <= '1' when (ahbsi.hsel(hindex) = '1' and ahbsi.hready = '1') else '0';
count_next <= count + conv_std_logic_vector(1, COUNT_BITS);
-----------------------------------------------------------------------------
-- AHB output handling
-----------------------------------------------------------------------------
hrdata(MEM_BITS - 1 downto 0) <= memout;
ahbso.hready <= '1';
ahbso.hresp <= HRESP_OKAY;
ahbso.hrdata <= hrdata;
ahbso.hsplit <= (others => '0');
-- ahbso.hirq <= (others => '0');
ahbso.hirq <= irq;
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
end rtl;
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2010/09/22 18:32:33 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.13 2010/09/22 18:32:33 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- Table for the ?< function (Section 9.2.3)
constant qlt : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | H |
('X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not (qlt (l, r) or match_logic_table (l,r));
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not qlt (l, r);
end function \?>=\;
-- %%% END FUNCTION "?>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r);
end function \?<\;
-- %%% END FUNCTION "?<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r) or match_logic_table (l,r);
end function \?<=\;
-- %%% END FUNCTION "?<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2010/09/22 18:32:33 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.13 2010/09/22 18:32:33 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- Table for the ?< function (Section 9.2.3)
constant qlt : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | H |
('X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not (qlt (l, r) or match_logic_table (l,r));
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not qlt (l, r);
end function \?>=\;
-- %%% END FUNCTION "?>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r);
end function \?<\;
-- %%% END FUNCTION "?<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r) or match_logic_table (l,r);
end function \?<=\;
-- %%% END FUNCTION "?<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2010/09/22 18:32:33 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.13 2010/09/22 18:32:33 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- Table for the ?< function (Section 9.2.3)
constant qlt : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | H |
('X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not (qlt (l, r) or match_logic_table (l,r));
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not qlt (l, r);
end function \?>=\;
-- %%% END FUNCTION "?>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r);
end function \?<\;
-- %%% END FUNCTION "?<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r) or match_logic_table (l,r);
end function \?<=\;
-- %%% END FUNCTION "?<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
-- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- SMT control unit
-- Michael Lancaster <mjl152@uclive.ac.nz>
-- 4 October 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity smt_control_unit is
Port ( CLOCK : in STD_LOGIC;
INSTRUCTION_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000110";
INSTRUCTION_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000111";
INSTRUCTION_POINTER_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
INSTRUCTION_POINTER_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG1_0 : out STD_LOGIC_VECTOR (7 downto 0) := "01000100";
ARG1_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG2_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG2_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG3_0 : out STD_LOGIC_VECTOR (7 downto 0 ):= "00000000";
ARG3_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000");
type smt_thread_register is array (1 downto 0) of std_logic_vector(7 downto 0);
function is_instruction(INSTRUCTION_REGISTER : in std_logic_vector(7 downto 0);
INSTRUCTION : in integer range 0 to 7)
return STD_LOGIC is
begin
if (INSTRUCTION_REGISTER = std_logic_vector(to_unsigned(INSTRUCTION, 8))) then
return '1';
end if;
return '0';
end is_instruction;
function initialize_register_1 return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(6, 8));
temp(1) := std_logic_vector(to_signed(7, 8));
return temp;
end initialize_register_1;
function initialize_register_2 return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(36, 8));
temp(1) := std_logic_vector(to_signed(0, 8));
return temp;
end initialize_register_2;
function initialize_zeros return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(0, 8));
temp(1) := std_logic_vector(to_signed(0, 8));
return temp;
end initialize_zeros;
function increment_instruction_pointer(instruction_pointer : in std_logic_vector (7 downto 0))
return std_logic_vector is
begin
return std_logic_vector(signed(instruction_pointer) + 4);
end increment_instruction_pointer;
end smt_control_unit;
architecture Behavioral of smt_control_unit is
component smt_adder_unit
Port ( ADDER_A, ADDER_B : in STD_LOGIC_VECTOR (7 downto 0);
ADDER_S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component smt_multiplier_unit
Port (MULTIPLIER_A, MULTIPLIER_B : in STD_LOGIC_VECTOR (7 downto 0);
MULTIPLIER_C : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component smt_ram is
port
(
DATA0 : in std_logic_vector(7 downto 0);
DATA1 : in std_logic_vector(7 downto 0);
ADDR0 : in std_logic_vector(7 downto 0);
ADDR1 : in std_logic_vector(7 downto 0);
SET0 : in std_logic := '1';
SET1 : in std_logic := '1';
RAM_CLOCK : in std_logic;
OUT0 : out std_logic_vector(7 downto 0);
OUT1 : out std_logic_vector(7 downto 0);
OUT2 : out std_logic_vector(7 downto 0);
OUT3 : out std_logic_vector(7 downto 0);
OUT4 : out std_logic_vector(7 downto 0) := "00000111";
OUT5 : out std_logic_vector(7 downto 0);
OUT6 : out std_logic_vector(7 downto 0);
OUT7 : out std_logic_vector(7 downto 0);
OUTADDR0 : in std_logic_vector(7 downto 0);
OUTADDR1 : in std_logic_vector(7 downto 0)
);
end component;
component smt_instruction_handler
Port (HANDLER_INSTRUCTION : in std_logic_vector(7 downto 0);
HANDLER_INSTRUCTION_POINTER : in std_logic_vector(7 downto 0);
HANDLER_ADDR1 : in std_logic_vector(7 downto 0);
HANDLER_ADDR2 : in std_logic_vector(7 downto 0);
HANDLER_ADDR3 : in std_logic_vector(7 downto 0);
HANDLER_CLOCK : in std_logic;
HANDLER_OUTPUT : out std_logic_vector(7 downto 0);
HANDLER_INDEX : out std_logic_vector(7 downto 0);
HANDLER_SET : out std_logic;
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE : out std_logic_vector(7 downto 0));
end component;
shared variable smt_thread_instruction_pointer : smt_thread_register := initialize_zeros;
shared variable smt_thread_instruction : smt_thread_register := initialize_register_1;
shared variable smt_thread_arg1 : smt_thread_register := initialize_register_2;
shared variable smt_thread_arg2 : smt_thread_register := initialize_zeros;
shared variable smt_thread_arg3 : smt_thread_register := initialize_zeros;
shared variable starting : std_logic := '1';
signal ADDER_A, ADDER_B, ADDER_S, MULTIPLIER_A, MULTIPLIER_B, MULTIPLIER_C,
HANDLER_INSTRUCTION, HANDLER_INSTRUCTION_POINTER, HANDLER_ADDR1, HANDLER_ADDR2,
HANDLER_ADDR3, HANDLER_OUTPUT, HANDLER_INDEX, DATA0, DATA1, ADDR0, ADDR1, OUT0,
OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUTADDR0, OUTADDR1 : std_logic_vector(7 downto 0);
signal SET0, SET1, RAM_CLOCK, HANDLER_SET, MULTIPLIER_CLOCK, ADDER_C, HANDLER_CLOCK : std_logic;
signal HANDLER_INSTRUCTION_POINTER_INTERMEDIATE : std_logic_vector(7 downto 0);
begin
adder1 : smt_adder_unit Port Map (ADDER_A => ADDER_A, ADDER_B => ADDER_B, ADDER_S => ADDER_S);
multiplier1 : smt_multiplier_unit Port Map (MULTIPLIER_A => MULTIPLIER_A,
MULTIPLIER_B => MULTIPLIER_B,
MULTIPLIER_C => MULTIPLIER_C);
handler1 : smt_instruction_handler Port Map (HANDLER_INSTRUCTION => HANDLER_INSTRUCTION,
HANDLER_INSTRUCTION_POINTER => HANDLER_INSTRUCTION_POINTER,
HANDLER_ADDR1 => HANDLER_ADDR1,
HANDLER_ADDR2 => HANDLER_ADDR2,
HANDLER_ADDR3 => HANDLER_ADDR3,
HANDLER_CLOCK => HANDLER_CLOCK,
HANDLER_OUTPUT => HANDLER_OUTPUT,
HANDLER_INDEX => HANDLER_INDEX,
HANDLER_SET => HANDLER_SET,
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE =>
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE);
ram1 : smt_ram Port Map (DATA0 => DATA0, DATA1=>DATA1, ADDR0 => ADDR0,
ADDR1 => ADDR1, SET0 => SET0, SET1 => SET1,
RAM_CLOCK => RAM_CLOCK, OUT0 => OUT0,
OUT1 => OUT1, OUT2 => OUT2, OUT3 => OUT3,
OUT4 => OUT4, OUT5 => OUT5, OUT6 => OUT6,
OUT7 => OUT7, OUTADDR0 => OUTADDR0,
OUTADDR1 => OUTADDR1);
process (CLOCK) is
begin
RAM_CLOCK <= CLOCK;
HANDLER_CLOCK <= CLOCK;
if rising_edge(CLOCK) then
if starting = '0' then
smt_thread_instruction(0) := OUT0;
smt_thread_instruction(1) := OUT4;
smt_thread_arg1(0) := OUT1;
smt_thread_arg2(0) := OUT2;
smt_thread_arg3(0) := OUT3;
smt_thread_arg1(1) := OUT5;
smt_thread_arg2(1) := OUT6;
smt_thread_arg3(1) := OUT7;
else
starting := '0';
end if;
INSTRUCTION_0 <= smt_thread_instruction(0);
INSTRUCTION_1 <= smt_thread_instruction(1);
INSTRUCTION_POINTER_0 <= smt_thread_instruction_pointer(0);
INSTRUCTION_POINTER_1 <= smt_thread_instruction_pointer(1);
ARG1_0 <= smt_thread_arg1(0);
ARG1_1 <= smt_thread_arg1(1);
ARG2_0 <= smt_thread_arg2(0);
ARG2_1 <= smt_thread_arg2(1);
ARG3_0 <= smt_thread_arg3(0);
ARG3_1 <= smt_thread_arg3(1);
case smt_thread_instruction(0) is
when "00000000" =>
ADDER_A <= smt_thread_arg1(0);
ADDER_B <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg3(0);
DATA0 <= ADDER_S;
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
case smt_thread_instruction(1) is
when "00000010" =>
-- thread 0 ifeq
if smt_thread_arg1(1) = smt_thread_arg2(1) then
smt_thread_instruction_pointer(1) := smt_thread_arg3(1);
else
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
when "00000011" =>
-- thread 0 ifgt
if smt_thread_arg1(1) > smt_thread_arg2(1) then
smt_thread_instruction_pointer(1) := smt_thread_arg3(1);
else
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
when "00000100" =>
-- thread 0 set
DATA1 <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg1(1);
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
when "00000101" =>
smt_thread_instruction_pointer(1) := smt_thread_arg1(1);
when others =>
end case;
when "00000001" =>
MULTIPLIER_A <= smt_thread_arg1(0);
MULTIPLIER_B <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg3(0);
DATA0 <= MULTIPLIER_C;
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when others =>
case smt_thread_instruction(0) is
when "00000010" =>
-- thread 0 ifeq
if smt_thread_arg1(0) = smt_thread_arg2(0) then
smt_thread_instruction_pointer(0) := smt_thread_arg3(0);
else
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
end if;
when "00000011" =>
-- thread 0 ifgt
if smt_thread_arg1(0) > smt_thread_arg2(0) then
smt_thread_instruction_pointer(0) := smt_thread_arg3(0);
else
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
end if;
when "00000100" =>
-- thread 0 set
DATA0 <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg1(0);
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when "00000101" =>
smt_thread_instruction_pointer(0) := smt_thread_arg1(0);
when "00000110" =>
smt_thread_instruction_pointer(1) := smt_thread_arg1(0);
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when "00000111" =>
when others =>
end case;
if smt_thread_instruction(1) = "00000000" then
ADDER_A <= smt_thread_arg1(1);
ADDER_B <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg3(1);
DATA1 <= ADDER_S;
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
elsif smt_thread_instruction(1) = "00000001" then
MULTIPLIER_A <= smt_thread_arg1(1);
MULTIPLIER_B <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg3(1);
DATA1 <= MULTIPLIER_C;
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
end case;
end if;
OUTADDR0 <= smt_thread_instruction_pointer(0);
OUTADDR1 <= smt_thread_instruction_pointer(1);
end process;
end Behavioral;
|
use std.textio.all;
entity test is
end entity;
architecture a of test is
type file_t is file of character;
function fun(var : boolean) return boolean is
file f : file_t;
variable l : line;
begin
file_open(f, "filename.txt", write_mode);
write(f, character'( 'x' ));
write(f, LF);
file_close(f);
return var;
end function;
begin
main : process
constant c : boolean := fun(false);
begin
wait;
end process;
end architecture;
|
use std.textio.all;
entity test is
end entity;
architecture a of test is
type file_t is file of character;
function fun(var : boolean) return boolean is
file f : file_t;
variable l : line;
begin
file_open(f, "filename.txt", write_mode);
write(f, character'( 'x' ));
write(f, LF);
file_close(f);
return var;
end function;
begin
main : process
constant c : boolean := fun(false);
begin
wait;
end process;
end architecture;
|
use std.textio.all;
entity test is
end entity;
architecture a of test is
type file_t is file of character;
function fun(var : boolean) return boolean is
file f : file_t;
variable l : line;
begin
file_open(f, "filename.txt", write_mode);
write(f, character'( 'x' ));
write(f, LF);
file_close(f);
return var;
end function;
begin
main : process
constant c : boolean := fun(false);
begin
wait;
end process;
end architecture;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------
entity multiplier is
--generic declarations
port (
a: in std_logic_vector(3 downto 0) ;
b: in std_logic_vector(3 downto 0) ;
y: out std_logic_vector(7 downto 0) ;);
end entity;
------------------------------
architecture circuit of multiplier is
--signals and declarations
begin
y <= a * b;
end architecture;
------------------------------
|
entity tb_arr07 is
end tb_arr07;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_arr07 is
signal clk : std_logic;
signal val : std_logic_vector(7 downto 0);
signal res : std_logic_vector(7 downto 0);
signal par : std_logic;
begin
dut: entity work.arr07
port map (clk => clk, val => val, res => res, par => par);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
for i in 0 to 15 loop
val <= std_logic_vector (to_unsigned(i, 4) & to_unsigned (15 - i, 4));
pulse;
end loop;
assert res = x"0f" severity failure;
val <= x"e4";
pulse;
assert res = x"1e" severity failure;
val <= x"c5";
pulse;
assert res = x"2d" severity failure;
val <= x"f6";
pulse;
assert res = x"3c" severity failure;
val <= x"57";
pulse;
assert res = x"4b" severity failure;
wait;
end process;
end behav;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
|
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--RAM模块输入为USB模块和LED模块的或
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
----------------clk_ledm 待替换-----------
------------------命名规则-----------------
---- uwr: usb with ram
---- lwr: ram with led
---- lwb: bluetooth with led
entity TD_DISPLAYER is
port
(
inclk:in std_logic;
------------DDR2------------
ddr2_clk,ddr2_n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='0';
udm,ldm:out std_logic:='0';
udm_2,ldm_2:out std_logic:='0';
udqs,ldqs:inout std_logic:='1';
udqs_2,ldqs_2:inout std_logic:='1';
odt:out std_logic:='1';
ddr2_bank:out std_logic_vector(2 downto 0);
ddr2_addr:out std_logic_vector(12 downto 0);
ddr2_data:inout std_logic_vector(31 downto 0):=x"00000000";
------------USB--------------
usb_full,usb_empty:in std_logic;
usb_clk:out std_logic;
sloe,slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
pc_rqu:in std_logic;
usb_in:in std_logic;
usb_fifoadr:out std_logic_vector(1 downto 0);
usb_data:inout std_logic_vector(15 downto 0);
-------------LED--------------
sensor:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
-----------BLUETOOTH-----------
bluetooth_rqu:in std_logic:='0';
bluetooth_ack:out std_logic:='0';
bluetooth_reset:out std_logic:='0';
bluetooth_data:inout std_logic_vector(3 downto 0):=x"0";
test:in std_logic
);
end entity;
architecture displayer of TD_DISPLAYER is
component PLL1 is
port
(
inclk0:in std_logic;
c0,c1,c2,c3:out std_logic;
locked:out std_logic
);
end component;
component PLL2 is
port
(
inclk0:in std_logic;
c0,c1,c2,c3,c4:out std_logic;
locked:out std_logic
);
end component;
component PLL3 is
port
(
inclk0:in std_logic;
c0:out std_logic;
locked:out std_logic
);
end component;
component DDR2_CONTROL is
port
(
pll_lock:in std_logic;
clk_control_p,clk_out_p,clk_out_n:in std_logic;
clk_data:in std_logic;
clk,n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='1';
udm,ldm:out std_logic:='0';
udqs_in,ldqs_in:in std_logic:='1';
udqs_out,ldqs_out:out std_logic:='1';
dqs_en:out std_logic:='0';
odt:out std_logic:='1';
bank:out std_logic_vector(2 downto 0);
addr:out std_logic_vector(12 downto 0);
ram_data_in:in std_logic_vector(15 downto 0):=x"0000";
ram_data_out:out std_logic_vector(15 downto 0):=x"0000";
ram_data_en:out std_logic:='0';
ram_reset:in std_logic:='0';
wr_rqu,rd_rqu:in std_logic:='0';
wr_ready,rd_ready:out std_logic:='0';
wr_end,rd_end:out std_logic:='1';
udm_in,ldm_in:in std_logic:='0';
write_num:in std_logic_vector(15 downto 0);
read_num:in std_logic_vector(15 downto 0);
data_other_in:in std_logic_vector(15 downto 0);
data_other_out:out std_logic_vector(15 downto 0);
bank_other:in std_logic_vector(2 downto 0);
addr_other_row:in std_logic_vector(12 downto 0);
addr_other_col:in std_logic_vector(9 downto 0)
);
end component;
component USB_RAM_BUFFER is
port
(
clk_usb_lock,clk_ram_lock:in std_logic;
clk_usb_p,clk_usb_o_p:in std_logic;
clk_ram_p:in std_logic;
usb_clk:out std_logic;
usb_full,usb_empty:in std_logic;
sloe,slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
fifoadr:out std_logic_vector(1 downto 0);
pc_rqu:in std_logic;
usb_in:in std_logic;
usb_data_in:in std_logic_vector(15 downto 0);
usb_data_out:out std_logic_vector(15 downto 0);
usb_data_en:out std_logic:='0';
ram_dm:out std_logic_vector(3 downto 0);
w_rqu,r_rqu:out std_logic;
w_ready,r_ready:in std_logic;
w_end,r_end:in std_logic;
w_num,r_num:out std_logic_vector(15 downto 0);
ram_bank:out std_logic_vector(2 downto 0);
ram_addr_row:out std_logic_vector(12 downto 0);
ram_addr_col:out std_logic_vector(9 downto 0);
ram_data_in:in std_logic_vector(15 downto 0);
ram_data_out:out std_logic_vector(15 downto 0);
ram_reset:out std_logic:='0';
usb_end:out std_logic:='0'
);
end component;
component LED is
port
(
clk_control:in std_logic;
clk_data_p:in std_logic;
sensor:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
blue_rqu:in std_logic:='0';
blue_end:out std_logic:='0';
blue_data:in std_logic_vector(7 downto 0):=x"00";
ram_data:in std_logic_vector(15 downto 0);
r_rqu:out std_logic;
r_ready:in std_logic;
ram_reset:out std_logic;
r_end:in std_logic;
r_num:out std_logic_vector(7 downto 0);
ram_dm:out std_logic_vector(3 downto 0);
ram_bank:out std_logic_vector(2 downto 0);
ram_addr_row:out std_logic_vector(12 downto 0);
ram_addr_col:out std_logic_vector(9 downto 0)
);
end component;
component BLUETOOTH_CONTROL is
port
(
clk_self,pll_lock:in std_logic;
bluetooth_rqu:in std_logic:='0';
bluetooth_ack:out std_logic:='0';
bluetooth_reset:out std_logic:='0';
bluetooth_data:inout std_logic_vector(3 downto 0):=x"0";
in_rqu:out std_logic:='0';
in_end:in std_logic:='0';
data_in:out std_logic_vector(7 downto 0)
--error:std_logic
);
end component;
-----------------------clock--------------------------
signal inclk_pll2,inclk_pll3:std_logic;
signal clk_40m_p,clk_40m_p1:std_logic;
signal clk_160m_p,clk_160m_p1,clk_160m_n1:std_logic;
signal clk_320m_p,clk_320m_n,clk_stpii:std_logic;
signal pll1_lock,pll2_lock,pll3_lock:std_logic:='0';
------------------------ram----------------------------
signal data_from_ram_1,data_from_ram_2:std_logic_vector(15 downto 0);
signal dm_s:std_logic_vector(3 downto 0);
signal rd_rqu_s,rd_ready_s,rd_end_s:std_logic;
signal rd_num_s:std_logic_vector(15 downto 0);
signal ram_bank_s:std_logic_vector(2 downto 0);
signal ram_addr_row_s:std_logic_vector(12 downto 0);
signal ram_addr_col_s:std_logic_vector(9 downto 0);
signal ram_data_in,ram_data_out:std_logic_vector(31 downto 0);
signal ram_data_en:std_logic:='0';
signal udqs_in,ldqs_in:std_logic:='1';
signal udqs_out,ldqs_out:std_logic:='1';
signal dqs_en:std_logic:='0';
signal udqs_in_2,ldqs_in_2:std_logic:='1';
signal udqs_out_2,ldqs_out_2:std_logic:='1';
signal dqs_en_2:std_logic:='0';
------------------------usb----------------------------
signal usb_data_in,usb_data_out:std_logic_vector(15 downto 0);
signal usb_data_en:std_logic:='0';
---------------------usb with ram----------------------
signal uwr_wr_rqu,uwr_rd_rqu:std_logic;
signal uwr_wr_ready,uwr_rd_ready:std_logic;
signal uwr_wr_end,uwr_rd_end:std_logic;
signal uwr_dm:std_logic_vector(3 downto 0);
signal uwr_wr_num,uwr_rd_num:std_logic_vector(15 downto 0);
signal uwr_bank:std_logic_vector(2 downto 0);
signal uwr_addr_row:std_logic_vector(12 downto 0);
signal uwr_addr_col:std_logic_vector(9 downto 0);
signal uwr_data_toram,uwr_data_tousb:std_logic_vector(15 downto 0);
signal ram_reset_s1,ram_reset_s2,ram_reset_s:std_logic;
signal usb_end_s,usb_end_last:std_logic;
---------------------led with ram----------------------
signal lwr_rd_rqu:std_logic;
signal lwr_rd_ready:std_logic;
signal lwr_rd_end:std_logic;
signal lwr_dm:std_logic_vector(3 downto 0);
signal lwr_rd_num:std_logic_vector(7 downto 0);
signal lwr_bank:std_logic_vector(2 downto 0);
signal lwr_addr_row:std_logic_vector(12 downto 0);
signal lwr_addr_col:std_logic_vector(9 downto 0);
signal lwr_data_ram:std_logic_vector(15 downto 0);
-------------------led with bluetooth-------------------
signal lwb_in_rqu:std_logic;
signal lwb_in_end:std_logic;
signal lwb_in_data:std_logic_vector(7 downto 0);
begin
PLL_1:PLL1
port map
(
inclk0=>inclk,
c0=>clk_40m_p,c1=>clk_40m_p1,c2=>inclk_pll2,c3=>inclk_pll3,
locked=>pll1_lock
);
PLL_2:PLL2
port map
(
inclk0=>inclk_pll2,
c0=>clk_160m_p,c1=>clk_160m_p1,c2=>clk_160m_n1,c3=>clk_320m_p,c4=>clk_320m_n,
locked=>pll2_lock
);
PLL_3:PLL3
port map
(
inclk0=>inclk_pll3,
c0=>clk_stpii,
locked=>pll3_lock
);
DDR2_1:DDR2_CONTROL
port map
(
pll_lock=>pll2_lock,
clk_control_p=>clk_160m_p,clk_out_p=>clk_160m_p1,clk_out_n=>clk_160m_n1,
clk_data=>clk_320m_p,
clk=>ddr2_clk,n_clk=>ddr2_n_clk,
cke=>cke,n_cs=>n_cs,n_ras=>n_ras,n_cas=>n_cas,n_we=>n_we,
udm=>udm,ldm=>ldm,
udqs_in=>udqs_in,ldqs_in=>ldqs_in,
udqs_out=>udqs_out,ldqs_out=>ldqs_out,
dqs_en=>dqs_en,
odt=>odt,
bank=>ddr2_bank,addr=>ddr2_addr,
ram_data_in=>ram_data_in(15 downto 0),
ram_data_out=>ram_data_out(15 downto 0),
ram_data_en=>ram_data_en,
ram_reset=>ram_reset_s,
wr_rqu=>uwr_wr_rqu,rd_rqu=>rd_rqu_s,
wr_ready=>uwr_wr_ready,rd_ready=>rd_ready_s,
wr_end=>uwr_wr_end,rd_end=>rd_end_s,
udm_in=>dm_s(1),ldm_in=>dm_s(0),
write_num=>uwr_wr_num,read_num=>rd_num_s,
bank_other=>ram_bank_s,
addr_other_row=>ram_addr_row_s,
addr_other_col=>ram_addr_col_s,
data_other_in=>uwr_data_toram,
data_other_out=>data_from_ram_1
);
DDR2_2:DDR2_CONTROL
port map
(
pll_lock=>pll2_lock,
clk_control_p=>clk_160m_p,clk_out_p=>clk_160m_p1,clk_out_n=>clk_160m_n1,
clk_data=>clk_320m_p,
-- clk=>ddr2_clk,n_clk=>ddr2_n_clk,
-- cke=>cke,n_cs=>n_cs,n_ras=>n_ras,n_cas=>n_cas,n_we=>n_we,
udm=>udm_2,ldm=>ldm_2,
udqs_in=>udqs_in_2,ldqs_in=>ldqs_in_2,
udqs_out=>udqs_out_2,ldqs_out=>ldqs_out_2,
dqs_en=>dqs_en_2,
-- odt=>odt,
-- bank=>ddr2_bank,addr=>ddr2_addr,
ram_data_in=>ram_data_in(31 downto 16),
ram_data_out=>ram_data_out(31 downto 16),
ram_reset=>ram_reset_s,
wr_rqu=>uwr_wr_rqu,rd_rqu=>rd_rqu_s,
-- wr_ready=>uwr_wr_ready,rd_ready=>uwr_rd_ready,
-- wr_end=>uwr_wr_end,rd_end=>uwr_rd_end,
write_num=>uwr_wr_num,read_num=>rd_num_s,
udm_in=>dm_s(3),ldm_in=>dm_s(2),
bank_other=>ram_bank_s,
addr_other_row=>ram_addr_row_s,
addr_other_col=>ram_addr_col_s,
data_other_in=>uwr_data_toram,
data_other_out=>data_from_ram_2
);
USB:USB_RAM_BUFFER
port map
(
clk_usb_lock=>pll1_lock,clk_ram_lock=>pll2_lock,
clk_usb_p=>clk_40m_p,clk_usb_o_p=>clk_40m_p1,
clk_ram_p=>clk_320m_p,
usb_clk=>usb_clk,
usb_full=>usb_full,usb_empty=>usb_empty,
sloe=>sloe,slrd=>slrd,slwr=>slwr,pktend=>pktend,
fifoadr=>usb_fifoadr,
usb_data_in=>usb_data_in,
usb_data_out=>usb_data_out,
usb_data_en=>usb_data_en,
pc_rqu=>pc_rqu,
usb_in=>usb_in,
w_rqu=>uwr_wr_rqu,r_rqu=>uwr_rd_rqu,
w_ready=>uwr_wr_ready,r_ready=>uwr_rd_ready,
w_end=>uwr_wr_end,r_end=>uwr_rd_end,
ram_dm=>uwr_dm,
w_num=>uwr_wr_num,r_num=>uwr_rd_num,
ram_bank=>uwr_bank,
ram_addr_row=>uwr_addr_row,
ram_addr_col=>uwr_addr_col,
ram_data_in=>uwr_data_tousb,
ram_data_out=>uwr_data_toram,
ram_reset=>ram_reset_s1,
usb_end=>usb_end_s
);
LED_CONTROL:LED
port map
(
clk_control=>clk_40m_p,
clk_data_p=>clk_320m_p,
sensor=>sensor,
data_buffer_a=>data_buffer_a,
data_buffer_b=>data_buffer_b,
data_buffer_c=>data_buffer_c,
en_row_a=>en_row_a,
en_row_b=>en_row_b,
en_row_c=>en_row_c,
en_col_a_1=>en_col_a_1,en_col_a_2=>en_col_a_2,en_col_a_3=>en_col_a_3,
en_col_b_1=>en_col_b_1,en_col_b_2=>en_col_b_2,en_col_b_3=>en_col_b_3,
en_col_c_1=>en_col_c_1,en_col_c_2=>en_col_c_2,en_col_c_3=>en_col_c_3,
blue_rqu=>lwb_in_rqu,
blue_end=>lwb_in_end,
blue_data=>lwb_in_data,
r_rqu=>lwr_rd_rqu,
r_ready=>lwr_rd_ready,
r_end=>lwr_rd_end,
r_num=>lwr_rd_num,
ram_reset=>ram_reset_s2,
ram_dm=>lwr_dm,
ram_bank=>lwr_bank,
ram_addr_row=>lwr_addr_row,
ram_addr_col=>lwr_addr_col,
ram_data=>lwr_data_ram
);
BLUETOOTH:BLUETOOTH_CONTROL
port map
(
clk_self=>clk_40m_p,pll_lock=>pll1_lock,
bluetooth_rqu=>bluetooth_rqu,
bluetooth_ack=>bluetooth_ack,
bluetooth_reset=>bluetooth_reset,
bluetooth_data=>bluetooth_data,
in_rqu=>lwb_in_rqu,
in_end=>lwb_in_end,
data_in=>lwb_in_data
);
RAM:process(clk_320m_p,pll2_lock)
begin
if clk_320m_p'event and clk_320m_p='1' and pll2_lock='1' then
-- case usb_data_en is
--
-- when '0' =>
-- usb_data<="ZZZZZZZZZZZZZZZZ";
-- usb_data_in<=usb_data;
--
-- when others =>
-- usb_data<=usb_data_out;
--
-- end case;
-- case dm_s is
--
-- when "0011" =>
-- uwr_data_tousb<=data_from_ram_2;
-- lwr_data_ram<=data_from_ram_2;
-- when "1100" =>
-- uwr_data_tousb<=data_from_ram_1;
-- lwr_data_ram<=data_from_ram_1;
-- when others =>
-- null;
--
-- end case;
case usb_end_last is
when '0' =>
dm_s<=uwr_dm;
ram_bank_s<=uwr_bank;
ram_addr_row_s<=uwr_addr_row;
ram_addr_col_s<=uwr_addr_col;
rd_rqu_s<=uwr_rd_rqu;
rd_num_s<=uwr_rd_num;
ram_reset_s<=ram_reset_s1;
when others =>
dm_s<=lwr_dm;
ram_bank_s<=lwr_bank;
ram_addr_row_s<=lwr_addr_row;
ram_addr_col_s<=lwr_addr_col;
rd_rqu_s<=lwr_rd_rqu;
rd_num_s(15 downto 8)<=x"00";
rd_num_s(7 downto 0)<=lwr_rd_num;
ram_reset_s<=ram_reset_s2;
end case;
usb_end_last<=usb_end_s;
-- if ram_data_out(15 downto 0)=x"0010" then
-- ram_data_out(15 downto 0)<=x"0000";
-- else
-- ram_data_out(15 downto 0)<=ram_data_out(15 downto 0)+1;
-- end if;
-- ram_data_out(31 downto 16)<=ram_data_out(15 downto 0);
end if;
end process;
with dm_s select
uwr_data_tousb<=data_from_ram_2 when "0011",
data_from_ram_1 when others;
with dm_s select
lwr_data_ram<=data_from_ram_2 when "0011",
data_from_ram_1 when others;
with usb_data_en select
usb_data <= usb_data_out when '1',
"ZZZZZZZZZZZZZZZZ" when others;
usb_data_in<=usb_data;
with dqs_en select
udqs <= udqs_out when '1',
'Z' when others;
udqs_in<=udqs;
with dqs_en select
ldqs <= ldqs_out when '1',
'Z' when others;
ldqs_in<=ldqs;
with dqs_en_2 select
udqs_2 <= udqs_out_2 when '1',
'Z' when others;
udqs_in_2<=udqs_2;
with dqs_en_2 select
ldqs_2 <= ldqs_out_2 when '1',
'Z' when others;
ldqs_in_2<=ldqs_2;
with ram_data_en select
ddr2_data <= ram_data_out when '1',
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when others;
ram_data_in<=ddr2_data;
uwr_rd_ready<=rd_ready_s;
uwr_rd_end<=rd_end_s;
lwr_rd_ready<=rd_ready_s;
lwr_rd_end<=rd_end_s;
end displayer; |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.spi_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the SPI VVC
--===============================================================================================
constant C_VVC_NAME : string := "SPI_VVC";
signal SPI_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is SPI_VVCT;
alias t_bfm_config is t_spi_bfm_config;
constant C_SPI_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_spi_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_SPI_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_SPI_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_SPI_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
tx_data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
rx_data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
tx_data => (others => '0'),
rx_data => (others => '0'),
data_exp => (others => '0'),
operation => NO_OPERATION,
msg => (others => ' ')
);
shared variable shared_spi_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_SPI_VVC_CONFIG_DEFAULT);
shared variable shared_spi_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_spi_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==============================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order to queue BFM calls
-- in the VVC command queue. The VVC will store and forward these calls to the
-- SPI BFM when the command is at the from of the VVC command queue.
-- - For details on how the BFM procedures work, see spi_bfm_pkg.vhd or the
-- quickref.
--==============================================================================
----------------------------------------------------------
-- SPI_MASTER
----------------------------------------------------------
-- Single-byte
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
);
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
);
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
);
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
);
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
);
----------------------------------------------------------
-- SPI_SLAVE
----------------------------------------------------------
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
);
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
);
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
);
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
);
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
----------------------------------------------------------
-- SPI_MASTER
----------------------------------------------------------
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data(data'length-1 downto 0) := v_normalised_data;
send_command_to_vvc(VVCT);
end procedure;
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.data_exp(data_exp'length-1 downto 0) := data_exp;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_ONLY);
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVCT);
end procedure;
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE_ONLY);
send_command_to_vvc(VVCT);
end procedure;
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK_ONLY);
shared_vvc_cmd.data_exp(data_exp'length-1 downto 0) := data_exp;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
----------------------------------------------------------
-- SPI_SLAVE
----------------------------------------------------------
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data(data'length-1 downto 0) := v_normalised_data;
send_command_to_vvc(VVCT);
end procedure;
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.data_exp(data_exp'length-1 downto 0) := data_exp;
send_command_to_vvc(VVCT);
end procedure;
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_ONLY);
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVCT);
end procedure;
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE_ONLY);
send_command_to_vvc(VVCT);
end procedure;
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK_ONLY);
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
shared_vvc_cmd.data_exp(data'length-1 downto 0) := data;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
end package body vvc_methods_pkg;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY SRAM_CONTROLLER IS
PORT(
--controls
clk : in std_logic;
rst : in std_logic;
--wishbone
bus_d : in std_logic_vector(15 downto 0);
bus_q : out std_logic_vector(15 downto 0);
bus_addr : in std_logic_vector(19 downto 0);
bus_rw : in std_logic;
bus_req : in std_logic;
bus_ack : out std_logic;
--srdqam
sram_dq : inout std_logic_vector(15 downto 0);
sram_addr : out std_logic_vector(19 downto 0);
sram_ce_n : out std_logic;
sram_oe_n : out std_logic;
sram_we_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic
);
END SRAM_CONTROLLER;
ARCHITECTURE behavioral OF SRAM_CONTROLLER IS
type States is (idle, r0, r1, w0, w1);
signal current_state : States;
signal next_state : States;
signal sram_addr_r : std_logic_vector(19 downto 0) := (others => '0');
signal sram_dq_r : std_logic_vector(15 downto 0) := (others => '0');
signal sram_we_n_r : std_logic := '0';
signal sram_oe_n_r : std_logic := '0';
signal addr_r : std_logic_vector(19 downto 0);
signal dat_o_r : std_logic_vector(15 downto 0);
signal ack_o_r : std_logic;
signal dat_i_r : std_logic_vector(15 downto 0);
signal we_i_r : std_logic;
signal oe : std_logic;
signal stb_i_r : std_logic;
signal oe_r : std_logic;
begin
-- register command
process (clk, rst) begin
if(rst = '0' and rising_edge(clk)) then
if ((stb_i_r='1')) then
stb_i_r <= '0';
elsif (bus_req = '1') then
addr_r <= bus_addr;
dat_i_r <= bus_d;
we_i_r <= bus_rw;
stb_i_r <= bus_req;
end if;
end if;
end process;
process (clk, rst) begin
if(rst = '1') then
current_state <= idle;
elsif(rising_edge(clk)) then
case (current_state) is
when idle =>
if (stb_i_r='1' and we_i_r='1') then current_state <= w0;
elsif (stb_i_r='1' and we_i_r='0') then current_state <= r0;
else current_state <= Idle;
end if;
when w0 =>
current_state <= idle;
when w1 =>
current_state <= idle;
when r0 =>
current_state <= idle;
when r1 =>
current_state <= idle;
when others =>
current_state <= idle;
end case;
end if;
end process;
-- ack_o signal
process(current_state, rst) begin
if (rst='1') then
ack_o_r <= '0';
else
if (current_state = idle) then
ack_o_r <= '0';
elsif (current_state = r0 or
current_state = w0) then
ack_o_r <= '1';
end if;
end if;
end process;
-- data
process(current_state, rst) begin
if (rst='1') then
dat_o_r <= (others => '0');
sram_dq_r <= (others => '0');
oe_r <= '0';
else
if (current_state = W0) then
sram_dq_r <= dat_i_r;
dat_o_r <= dat_i_r;
oe_r <= '1';
elsif (current_state = W1) then
sram_dq_r <= dat_i_r;
oe_r <= '1';
elsif (current_state = R0) then
dat_o_r <= sram_dq;
sram_dq_r <= (others => 'Z');
oe_r <= '0';
elsif (current_state = R1) then
dat_o_r <= sram_dq;
sram_dq_r <= (others => 'Z');
oe_r <= '0';
else
sram_dq_r <= (others => 'Z');
oe_r <= '0';
end if;
end if;
end process;
-- address
process(current_state) begin
if (current_state = W0 or current_state = R0) then
sram_addr_r <= addr_r;
end if;
end process;
-- commands
process(current_state) begin
if (current_state = R0 or current_state = R1) then
sram_oe_n_r <= '0' ;
else
sram_oe_n_r <= '1';
end if;
if (current_state = W0 or current_state = W1)then
sram_we_n_r <= '0' ;
else
sram_we_n_r <= '1';
end if;
end process;
sram_addr <= sram_addr_r;
sram_we_n <= sram_we_n_r;
sram_oe_n <= sram_oe_n_r;
sram_ub_n <= '0';
sram_lb_n <= '0';
sram_ce_n <= '0';
sram_dq <= sram_dq_r when oe_r = '1' else
(others => 'Z');
bus_q <= dat_o_r;
bus_ack <= ack_o_r;
end architecture;
|
-------------------------------------------------------------------------------
--
-- File : imx9328_wb16_wrapper.vhd
-- Related files : (none)
--
-- Author(s) : Fabrice Mousset (fabrice.mousset@laposte.net)
-- Project : i.MX wrapper to Wishbone bus
--
-- Creation Date : 2007/01/19
--
-- Description : This is the top file of the IP
-------------------------------------------------------------------------------
-- Modifications :
-----
-- 2008/03/05
-- Fabien Marteau (fabien.marteau@armadeus.com)
-- adding comments and changing some signals names
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
Entity imx9328_wb16_wrapper is
-- ----------------------------------------------------------------------------
port
(
-- i.MX Signals
imx_address : in std_logic_vector(11 downto 0); -- LSB not used
imx_data : inout std_logic_vector(15 downto 0);
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
imx_eb3_n : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Interrupt out for write error
-- int_err : out std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(12 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of imx9328_wb16_wrapper is
-- ----------------------------------------------------------------------------
signal write : std_logic;
signal read : std_logic;
signal strobe : std_logic;
signal writedata : std_logic_vector(15 downto 0);
signal address : std_logic_vector(12 downto 0);
begin
-- ----------------------------------------------------------------------------
-- External signals synchronization process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
write <= '0';
read <= '0';
strobe <= '0';
writedata <= (others => '0');
address <= (others => '0');
elsif(rising_edge(gls_clk)) then
strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb3_n);
write <= not (imx_cs_n or imx_eb3_n);
read <= not (imx_cs_n or imx_oe_n);
address <= imx_address & '0';
writedata <= imx_data;
end if;
end process;
wbm_address <= address when (strobe = '1') else (others => '0');
wbm_writedata <= writedata when (write = '1') else (others => '0');
wbm_strobe <= strobe;
wbm_write <= write;
wbm_cycle <= strobe;
imx_data <= wbm_readdata when(read = '1' ) else (others => 'Z');
end architecture RTL;
|
-- Test case from Brian Padalino
--
package p1 is
type t_byte_endianness is (LOWER_BYTE_LEFT, FIRST_BYTE_LEFT, LOWER_BYTE_RIGHT, FIRST_BYTE_RIGHT) ;
type t_slv_array is array(natural range <>) of bit_vector ;
subtype t_byte_array is t_slv_array(open)(7 downto 0) ;
function convert_byte_array_to_slv(
constant byte_array : t_byte_array ;
constant byte_endianness : t_byte_endianness
) return bit_vector ;
end package ;
package body p1 is
-- example taken directly from uvvm:
-- https://github.com/UVVM/UVVM/blob/92cb1495afa007f74ed79fb9935282196420add0/uvvm_util/src/methods_pkg.vhd#L6801
function convert_byte_array_to_slv(
constant byte_array : t_byte_array;
constant byte_endianness : t_byte_endianness
) return bit_vector is
constant c_num_bytes : integer := byte_array'length;
alias normalized_byte_array : t_byte_array(0 to c_num_bytes-1) is byte_array;
variable v_slv : bit_vector(8*c_num_bytes-1 downto 0);
begin
assert byte_array'ascending report "byte_array must be ascending" severity error;
for byte_idx in 0 to c_num_bytes-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
v_slv(8*(c_num_bytes-byte_idx)-1 downto 8*(c_num_bytes-1-byte_idx)) := normalized_byte_array(byte_idx);
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
v_slv(8*(byte_idx+1)-1 downto 8*byte_idx) := normalized_byte_array(byte_idx);
end if;
end loop;
return v_slv;
end function;
end package body ;
entity array8 is end entity ;
use work.p1.all;
architecture arch of array8 is
signal s : t_byte_array(0 to 2) := ( X"44", X"55", X"66" );
begin
process
begin
assert convert_byte_array_to_slv((X"01", X"02", X"03"), LOWER_BYTE_LEFT) = X"010203";
assert convert_byte_array_to_slv((X"01", X"02", X"03"), LOWER_BYTE_RIGHT) = X"030201";
assert convert_byte_array_to_slv(s, LOWER_BYTE_LEFT) = X"445566";
assert convert_byte_array_to_slv(s, LOWER_BYTE_RIGHT) = X"665544";
std.env.stop ;
end process;
end architecture ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1892.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01892ent IS
END c07s01b00x00p08n01i01892ent;
ARCHITECTURE c07s01b00x00p08n01i01892arch OF c07s01b00x00p08n01i01892ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
sig : s_int <= 0;
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int'(sig)) after 5 ns;
-- signal assignment label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01892 - Signal assignment labels are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01892arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1892.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01892ent IS
END c07s01b00x00p08n01i01892ent;
ARCHITECTURE c07s01b00x00p08n01i01892arch OF c07s01b00x00p08n01i01892ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
sig : s_int <= 0;
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int'(sig)) after 5 ns;
-- signal assignment label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01892 - Signal assignment labels are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01892arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1892.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01892ent IS
END c07s01b00x00p08n01i01892ent;
ARCHITECTURE c07s01b00x00p08n01i01892arch OF c07s01b00x00p08n01i01892ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
sig : s_int <= 0;
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int'(sig)) after 5 ns;
-- signal assignment label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01892 - Signal assignment labels are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01892arch;
|
entity tb_arr01 is
end tb_arr01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr01 is
signal a : std_logic_vector (31 downto 0);
signal sel : natural range 0 to 3;
signal clk : std_logic;
signal res : std_logic_vector (7 downto 0);
begin
dut: entity work.arr01
port map (a, sel, clk, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"a1b2c3d4";
sel <= 0;
pulse;
pulse;
assert res = x"a1" severity failure;
sel <= 1;
pulse;
assert res = x"a1" severity failure;
sel <= 2;
pulse;
assert res = x"b2" severity failure;
sel <= 3;
pulse;
assert res = x"c3" severity failure;
sel <= 0;
pulse;
assert res = x"d4" severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
--! @file dynamicBridgeRtl.vhd
--
--! @brief Dynamic Bridge for translating static to dynamic memory spaces
--
--! @details The Dynamic Bridge component translates a static memory mapping
--! into a dynamic memory map that can be changed during runtime.
--! This enhances the functionality of an ordinary memory mapped bridge logic.
--! Additionally several memory spaces can be configured (compilation).
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
-------------------------------------------------------------------------------
--! @brief Dynamic bridge translates a fixed address space into a flexible one.
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge has an input port with a fixed (before runtime) memory
--! mapping, which is translated to a flexible address space mapping.
--! The flexible address space can be changed during runtime in order to
--! redirect accesses from the input to other locations.
--! The base addresses for the static port are set by generic gBaseAddressArray.
--! The base addresses for the dynamic port are set through the BaseSet port
-------------------------------------------------------------------------------
entity dynamicBridge is
generic (
--! number of static address spaces
gAddressSpaceCount : natural := 2;
--! select wheather DPRAM or registers will be used as memory (false = 0, true /= 0)
gUseMemBlock : integer := 0;
--! base addresses in static address space (note: last-1 = high address)
gBaseAddressArray : tArrayStd32 := (x"0000_1000" , x"0000_2000" , x"0000_3000")
);
port (
-- Global
--! component-wide clock signal
iClk : in std_logic;
--! component-wide reset signal
iRst : in std_logic;
-- Bridge
--! address of static address space
iBridgeAddress : in std_logic_vector;
--! Request strobe
iBridgeRequest : in std_logic;
--! address of dynamic address space (translated input)
oBridgeAddress : out std_logic_vector;
--! Select signal of any address space selected
oBridgeSelectAny : out std_logic;
--! select signals of all address spaces
oBridgeSelect : out std_logic_vector(gAddressSpaceCount-1 downto 0);
--! Bridge output valid
oBridgeValid : out std_logic;
-- BaseSet Memory Mapped Write Bus
--! BaseSet write strobe
iBaseSetWrite : in std_logic;
--! BaseSet read strobe
iBaseSetRead : in std_logic;
--! BaseSet byteenable
iBaseSetByteenable : in std_logic_vector;
--! BaseSet address bus
iBaseSetAddress : in std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! BaseSet write data bus
iBaseSetData : in std_logic_vector;
--! BaseSet read data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
oBaseSetAck : out std_logic
);
end dynamicBridge;
-------------------------------------------------------------------------------
--! @brief Register Transfer Level of Dynamic Bridge device
-------------------------------------------------------------------------------
--! @details
--! The dynamic bridge rtl applies generated address decoders
--! to generate select signals for the static address spaces.
--! The select signals are forwarded register file holding the base address
--! offsets in the dynamic memory space. The input address is manipulated with
--! arithmetic operators to gain the output address. The lut file holds the
--! base addresses in the static memory space.
-------------------------------------------------------------------------------
architecture rtl of dynamicBridge is
--! Bridge cycle delay
constant cBridgeCycleDelay : natural := 3;
--! Bridge read path enable all bytes
constant cByteenableAllOnes : std_logic_vector(iBaseSetByteenable'range) :=
(others => cActivated);
--! convert address array into stream
constant cBaseAddressArrayStd : std_logic_vector
((gAddressSpaceCount+1)*cArrayStd32ElementSize-1 downto 0) :=
CONV_STDLOGICVECTOR(gBaseAddressArray, gBaseAddressArray'length);
--! Input address register
signal inAddrReg : std_logic_vector(iBridgeAddress'range);
--! Request rising edge
signal bridgeRequest_rising : std_logic;
--! Input address store strobe
signal inAddrStore : std_logic;
--! Request acknowledge terminal count strobe
signal reqAckTcnt : std_logic;
--! address decoder select signals one hot coded
signal addrDecSelOneHot : std_logic_vector(gAddressSpaceCount-1 downto 0);
--! address decoder select signals binary coded
signal addrDecSelBinary : std_logic_vector(LogDualis(gAddressSpaceCount)-1 downto 0);
--! selected static lut file base offset
signal lutFileBase : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment
signal addrSpaceOffset : std_logic_vector(inAddrReg'range);
--! Base address in bridge master environment (unregistered)
signal addrSpaceOffset_unreg : std_logic_vector(inAddrReg'range);
--! Dynamic address offset within selected static space
signal dynamicOffset : std_logic_vector(iBaseSetData'range);
--! Translated address
signal translateAddress : std_logic_vector(maximum(iBaseSetData'high, oBridgeAddress'high) downto inAddrReg'low);
begin
-- assert
assert (cBridgeCycleDelay > 0)
report "Set cBridgeCycleDelay > 0"
severity failure;
-- export
oBridgeSelect <= addrDecSelOneHot;
oBridgeSelectAny <= OR_REDUCE(addrDecSelOneHot);
oBridgeValid <= reqAckTcnt;
oBridgeAddress <= translateAddress(oBridgeAddress'range);
--! Store the input address with the request strobe
storeAddr : process(iRst, iClk)
begin
if iRst = cActivated then
inAddrReg <= (others => cInactivated);
elsif rising_edge(iClk) then
if inAddrStore = cActivated then
inAddrReg <= iBridgeAddress;
end if;
end if;
end process;
--! Get rising edge of request signaling
reqEdge : entity libcommon.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => iBridgeRequest,
oRising => bridgeRequest_rising,
oFalling => open,
oAny => open
);
inAddrStore <= bridgeRequest_rising;
--! Generate the request acknowledge signal
reqAck : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cBridgeCycleDelay+1),
gTcntVal => cBridgeCycleDelay
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => iBridgeRequest,
iSrst => cInactivated,
oCnt => open,
oTcnt => reqAckTcnt
);
--! Generate Address Decoders
genAddressDecoder : for i in 0 to gAddressSpaceCount-1 generate
insAddressDecoder : entity libcommon.addrDecode
generic map (
gAddrWidth => inAddrReg'length,
gBaseAddr => to_integer(unsigned(gBaseAddressArray(i)(inAddrReg'range))),
gHighAddr => to_integer(unsigned(gBaseAddressArray(i+1)(inAddrReg'range))-1)
)
port map (
iEnable => iBridgeRequest,
iAddress => inAddrReg,
oSelect => addrDecSelOneHot(i)
);
end generate;
--! Convert one hot from address decoder to binary
insBinaryEncoder : entity libcommon.binaryEncoder
generic map (
gDataWidth => gAddressSpaceCount
)
port map (
iOneHot => addrDecSelOneHot,
oBinary => addrDecSelBinary
);
--! select static base address in lut file
insLutFile : entity libcommon.lutFile
generic map (
gLutCount => gAddressSpaceCount,
gLutWidth => cArrayStd32ElementSize,
gLutInitValue => cBaseAddressArrayStd(cBaseAddressArrayStd'left downto cArrayStd32ElementSize)
-- omit high address of last memory map
)
port map (
iAddrRead => addrDecSelBinary,
oData => lutFileBase
);
-- calculate address offset within static space
addrSpaceOffset_unreg <= std_logic_vector(
unsigned(inAddrReg) - unsigned(lutFileBase)
);
--! Registers to break combinational path of lut file output.
regAddrSpace : process(iRst, iClk)
begin
if iRst = cActivated then
addrSpaceOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
addrSpaceOffset <= addrSpaceOffset_unreg;
end if;
end process;
REGFILE : if gUseMemBlock = 0 generate
signal dynamicOffset_unreg : std_logic_vector(dynamicOffset'range);
begin
--! select dynamic base address in register file
insRegFile : entity libcommon.registerFile
generic map (
gRegCount => gAddressSpaceCount
)
port map (
iClk => iClk,
iRst => iRst,
iWriteA => iBaseSetWrite,
iWriteB => cInactivated, -- write port B unused
iByteenableA => iBaseSetByteenable,
iByteenableB => cByteenableAllOnes,
iAddrA => iBaseSetAddress,
iAddrB => addrDecSelBinary,
iWritedataA => iBaseSetData,
oReaddataA => oBaseSetData,
iWritedataB => iBaseSetData, -- write port B unused
oReaddataB => dynamicOffset_unreg
);
regDynOff : process(iRst, iClk)
begin
if iRst = cActivated then
dynamicOffset <= (others => cInactivated);
elsif rising_edge(iClk) then
dynamicOffset <= dynamicOffset_unreg;
end if;
end process;
BASESETACK : oBaseSetAck <= iBaseSetWrite or iBaseSetRead;
end generate REGFILE;
genDPRAM : if gUseMemBlock /= 0 generate
-- Clip dpr word width to values of power 2 (e.g. 8, 16, 32)
constant cDprWordWidth : natural := 2**logDualis(iBaseSetData'length);
constant cDprAddrWidth : natural := logDualis(gAddressSpaceCount);
constant cDprReadDel : natural := 1;
type tDprPort is record
write : std_logic;
read : std_logic;
address : std_logic_vector(cDprAddrWidth-1 downto 0);
byteenable : std_logic_vector(cDprWordWidth/8-1 downto 0);
writedata : std_logic_vector(cDprWordWidth-1 downto 0);
readdata : std_logic_vector(cDprWordWidth-1 downto 0);
end record;
signal dprPortA : tDprPort;
signal dprPortA_readAck : std_logic;
signal dprPortB : tDprPort;
begin
--! This combinatoric process assigns base sets to the dpr.
--! The default assignments avoid warnings in synthesize tools.
dprAssign : process (
iBaseSetByteenable,
iBaseSetData
)
begin
--default assignments
dprPortA.byteenable <= (others => cInactivated);
dprPortA.writedata <= (others => cInactivated);
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata <= (others => cInactivated);
dprPortA.byteenable(iBaseSetByteenable'range) <= iBaseSetByteenable;
dprPortA.writedata(iBaseSetData'range) <= iBaseSetData;
dprPortB.byteenable <= (others => cInactivated);
dprPortB.writedata(iBaseSetData'range) <= iBaseSetData;
end process;
dprPortA.write <= iBaseSetWrite;
dprPortA.read <= iBaseSetRead;
dprPortA.address <= iBaseSetAddress;
oBaseSetData <= dprPortA.readdata(oBaseSetData'range);
dprPortB.write <= cInactivated; --unused
dprPortB.read <= cActivated; --unused
dprPortB.address <= addrDecSelBinary;
dynamicOffset <= dprPortB.readdata(dynamicOffset'range);
insDPRAM: entity work.dpRam
generic map(
gWordWidth => cDprWordWidth,
gNumberOfWords => gAddressSpaceCount
)
port map(
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => dprPortA.write,
iAddress_A => dprPortA.address,
iByteEnable_A => dprPortA.byteenable,
iWritedata_A => dprPortA.writedata,
oReaddata_A => dprPortA.readdata,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => dprPortB.write,
iAddress_B => dprPortB.address,
iByteEnable_B => dprPortB.byteenable,
iWritedata_B => dprPortB.writedata,
oReaddata_B => dprPortB.readdata
);
BASESETACK : oBaseSetAck <= dprPortA.write or dprPortA_readAck;
--! Generate the read acknowledge signal
rdAck : entity libcommon.cnt
generic map (
gCntWidth => logDualis(cDprReadDel+1),
gTcntVal => cDprReadDel
)
port map (
iArst => iRst,
iClk => iClk,
iEnable => dprPortA.read,
iSrst => cInactivated,
oCnt => open,
oTcnt => dprPortA_readAck
);
end generate genDPRAM;
-- calculate translated address offset in dynamic space
translateAddress <= std_logic_vector(
unsigned(dynamicOffset) + unsigned(addrSpaceOffset)
);
end rtl;
|
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_dac_4d_2c is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
pid : in std_logic_vector(7 downto 0);
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_p : out std_logic_vector(15 downto 0);
dac_data_out_n : out std_logic_vector(15 downto 0);
up_status : out std_logic_vector(7 downto 0);
up_dds_enable_int : out std_logic;
up_dds_frame_int : out std_logic;
up_dds_enable_ext : in std_logic;
up_dds_frame_ext : in std_logic;
vdma_dbg_data : out std_logic_vector(198 downto 0);
vdma_dbg_trigger : out std_logic_vector(7 downto 0);
dac_div3_clk : out std_logic;
dac_dbg_data : out std_logic_vector(195 downto 0);
dac_dbg_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
vdma_clk : in std_logic;
vdma_fs : out std_logic;
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dac_4d_2c;
architecture IMP of axi_dac_4d_2c is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
pid : in std_logic_vector(7 downto 0);
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_p : out std_logic_vector(15 downto 0);
dac_data_out_n : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
up_dds_enable_int : out std_logic;
up_dds_frame_int : out std_logic;
up_dds_enable_ext : in std_logic;
up_dds_frame_ext : in std_logic;
vdma_dbg_data : out std_logic_vector(198 downto 0);
vdma_dbg_trigger : out std_logic_vector(7 downto 0);
dac_div3_clk : out std_logic;
dac_dbg_data : out std_logic_vector(195 downto 0);
dac_dbg_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_CF_BUFTYPE => C_CF_BUFTYPE
)
port map
(
pid => pid,
dac_clk_in_p => dac_clk_in_p,
dac_clk_in_n => dac_clk_in_n,
dac_clk_out_p => dac_clk_out_p,
dac_clk_out_n => dac_clk_out_n,
dac_frame_out_p => dac_frame_out_p,
dac_frame_out_n => dac_frame_out_n,
dac_data_out_p => dac_data_out_p,
dac_data_out_n => dac_data_out_n,
vdma_clk => vdma_clk,
vdma_fs => vdma_fs,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
up_dds_enable_int => up_dds_enable_int,
up_dds_frame_int => up_dds_frame_int,
up_dds_enable_ext => up_dds_enable_ext,
up_dds_frame_ext => up_dds_frame_ext,
vdma_dbg_data => vdma_dbg_data,
vdma_dbg_trigger => vdma_dbg_trigger,
dac_div3_clk => dac_div3_clk,
dac_dbg_data => dac_dbg_data,
dac_dbg_trigger => dac_dbg_trigger,
delay_clk => delay_clk,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1460.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01460ent IS
END c08s07b00x00p04n01i01460ent;
ARCHITECTURE c08s07b00x00p04n01i01460arch OF c08s07b00x00p04n01i01460ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
begin
if delay = 0 then
m := 1;
else
k := 1;
end if;
assert NOT((m = 0) and (k = 1))
report "***PASSED TEST: c08s07b00x00p04n01i01460"
severity NOTE;
assert (m = 0) and (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01460 - conditions after the if is evalusted to be FALSE, so should treat a final else as elsif TRUE then"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01460arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1460.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01460ent IS
END c08s07b00x00p04n01i01460ent;
ARCHITECTURE c08s07b00x00p04n01i01460arch OF c08s07b00x00p04n01i01460ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
begin
if delay = 0 then
m := 1;
else
k := 1;
end if;
assert NOT((m = 0) and (k = 1))
report "***PASSED TEST: c08s07b00x00p04n01i01460"
severity NOTE;
assert (m = 0) and (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01460 - conditions after the if is evalusted to be FALSE, so should treat a final else as elsif TRUE then"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01460arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1460.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01460ent IS
END c08s07b00x00p04n01i01460ent;
ARCHITECTURE c08s07b00x00p04n01i01460arch OF c08s07b00x00p04n01i01460ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
begin
if delay = 0 then
m := 1;
else
k := 1;
end if;
assert NOT((m = 0) and (k = 1))
report "***PASSED TEST: c08s07b00x00p04n01i01460"
severity NOTE;
assert (m = 0) and (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01460 - conditions after the if is evalusted to be FALSE, so should treat a final else as elsif TRUE then"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01460arch;
|
------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: components.vhd,v 1.2 2008-11-07 04:54:32 jwdonal Exp $
--
-- Description:
-- This is a package that lists all of the components used in the design.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - pix_enab_clk_cntr.vhd
-- - image_gen.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- clock enable signals "*_ce"
-- internal version of output port used as register "*_reg"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE components IS
ATTRIBUTE BOX_TYPE: string; -- used to remove "Black Box" warning messages in the synthesis report
----------------------
-- DCM LCD Clock
----------------------
COMPONENT dcm_sys_to_lcd
PORT (
RST_IN,
CLKIN_IN : IN std_logic;
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLKDV_OUT,
CLKFX_OUT : OUT std_logic
);
END COMPONENT dcm_sys_to_lcd;
----------------------
-- CLK_LCD Cycle Counter for ENAB and
-- image_gen_bram controllers
----------------------
COMPONENT clk_lcd_cyc_cntr is
GENERIC (
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
PORT (
RSTx,
CLK_LCD,
HSYNCx,
VSYNCx : IN std_logic;
LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : OUT std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0)
);
END COMPONENT clk_lcd_cyc_cntr;
----------------------
-- Video Controller
----------------------
COMPONENT video_controller is
GENERIC (
--Video Controller
C_RL_STATUS,
C_UD_STATUS,
C_VQ_STATUS : std_logic;
--VSYNCx Controller (pass thru)
C_VSYNC_TV,
C_VSYNC_TVP,
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
--HSYNCx Controller (pass thru)
C_HSYNC_TH,
C_HSYNC_THP,
C_NUM_CLKS_WIDTH,
--CLK_LCD Cycle Counter (pass thru)
C_CLK_LCD_CYC_NUM_WIDTH,
--ENAB Controller (pass thru)
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
PORT (
RSTx,
CLK_LCD : IN std_logic;
LINE_NUM : OUT std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : OUT std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
HSYNCx,
VSYNCx,
ENAB,
RL,
UD,
VQ : OUT std_logic
);
END COMPONENT video_controller;
----------------------
-- HSYNCx Control
----------------------
COMPONENT hsyncx_control is
GENERIC (
C_HSYNC_TH,
C_HSYNC_THP,
C_NUM_CLKS_WIDTH : POSITIVE
);
PORT (
RSTx,
CLK_LCD : IN std_logic;
HSYNCx : OUT std_logic
);
END COMPONENT hsyncx_control;
----------------------
-- VSYNCx Control
----------------------
COMPONENT vsyncx_control is
GENERIC (
C_VSYNC_TV,
C_VSYNC_TVP,
C_LINE_NUM_WIDTH : POSITIVE
);
PORT (
RSTx,
CLK_LCD,
HSYNCx : IN std_logic;
LINE_NUM : OUT std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
VSYNCx : OUT std_logic
);
END COMPONENT vsyncx_control;
----------------------
-- ENAB Control
----------------------
COMPONENT enab_control is
GENERIC (
C_VSYNC_TVS,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
PORT (
RSTx,
CLK_LCD : IN std_logic;
CLK_LCD_CYC_NUM : IN std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
ENAB : OUT std_logic
);
END COMPONENT enab_control;
-----------------------
-- BRAM Image Generator
-----------------------
COMPONENT image_gen_bram is
GENERIC (
C_BIT_DEPTH,
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE,
C_BRAM_ADDR_WIDTH,
C_IMAGE_WIDTH,
C_IMAGE_HEIGHT : POSITIVE
);
PORT (
RSTx,
CLK_LCD : IN std_logic;
LINE_NUM : IN std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : IN std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
R,
G,
B : OUT std_logic_VECTOR(C_BIT_DEPTH/3-1 downto 0)
);
END COMPONENT image_gen_bram;
--------------------------
-- Image Generator BRAM --
--------------------------
--You can't simply instantiate one XCO BRAM component 3 times because all
--three components are initialized with 3 different COE files!
--We also use SINIT in place of EN port because disabling EN (i.e. making it '0')
--cuases the output ports to remain at the last output value. SINIT
--resets the output back to '0' whenever it is disabled. Which is exactly what we want
--b/c if the last value reamins (as it would with EN) the last pixel drawn for the
--image in each row would be "smeared" across the remaining pixels in the row!
COMPONENT image_gen_bram_red
PORT (
clka : IN std_logic;
addra : IN std_logic_VECTOR(17-1 downto 0);
douta : OUT std_logic_VECTOR(6-1 downto 0)
);
END COMPONENT;
ATTRIBUTE BOX_TYPE of image_gen_bram_red: component is "USER_BLACK_BOX";
COMPONENT image_gen_bram_green
PORT (
clka : IN std_logic;
addra : IN std_logic_VECTOR(17-1 downto 0);
douta : OUT std_logic_VECTOR(6-1 downto 0)
);
END COMPONENT;
ATTRIBUTE BOX_TYPE of image_gen_bram_green: component is "USER_BLACK_BOX";
COMPONENT image_gen_bram_blue
PORT (
clka : IN std_logic;
addra : IN std_logic_VECTOR(17-1 downto 0);
douta : OUT std_logic_VECTOR(6-1 downto 0)
);
END COMPONENT;
ATTRIBUTE BOX_TYPE of image_gen_bram_blue: component is "USER_BLACK_BOX";
END PACKAGE components;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc955.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n02i00955ent IS
END c06s01b00x00p10n02i00955ent;
ARCHITECTURE c06s01b00x00p10n02i00955arch OF c06s01b00x00p10n02i00955ent IS
signal PT : boolean;
subtype ONE is integer range 1 to 1;
type R1 is record
X1: ONE;
RE1: BOOLEAN;
end record;
function rr1(i : integer) return R1 is
variable vr : r1;
begin
return vr;
end rr1;
attribute AT1 : R1;
attribute AT1 of PT : signal is rr1(3);
type A1 is array (BOOLEAN) of BOOLEAN;
BEGIN
TESTING: PROCESS
variable V1: BOOLEAN;
BEGIN
V1 := PT'AT1.RE1;
assert NOT( V1=FALSE )
report "***PASSED TEST: c06s01b00x00p10n02i00955"
severity NOTE;
assert ( V1=FALSE )
report "***FAILED TEST: c06s01b00x00p10n02i00955 - The prefix of a name is a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n02i00955arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc955.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n02i00955ent IS
END c06s01b00x00p10n02i00955ent;
ARCHITECTURE c06s01b00x00p10n02i00955arch OF c06s01b00x00p10n02i00955ent IS
signal PT : boolean;
subtype ONE is integer range 1 to 1;
type R1 is record
X1: ONE;
RE1: BOOLEAN;
end record;
function rr1(i : integer) return R1 is
variable vr : r1;
begin
return vr;
end rr1;
attribute AT1 : R1;
attribute AT1 of PT : signal is rr1(3);
type A1 is array (BOOLEAN) of BOOLEAN;
BEGIN
TESTING: PROCESS
variable V1: BOOLEAN;
BEGIN
V1 := PT'AT1.RE1;
assert NOT( V1=FALSE )
report "***PASSED TEST: c06s01b00x00p10n02i00955"
severity NOTE;
assert ( V1=FALSE )
report "***FAILED TEST: c06s01b00x00p10n02i00955 - The prefix of a name is a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n02i00955arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc955.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n02i00955ent IS
END c06s01b00x00p10n02i00955ent;
ARCHITECTURE c06s01b00x00p10n02i00955arch OF c06s01b00x00p10n02i00955ent IS
signal PT : boolean;
subtype ONE is integer range 1 to 1;
type R1 is record
X1: ONE;
RE1: BOOLEAN;
end record;
function rr1(i : integer) return R1 is
variable vr : r1;
begin
return vr;
end rr1;
attribute AT1 : R1;
attribute AT1 of PT : signal is rr1(3);
type A1 is array (BOOLEAN) of BOOLEAN;
BEGIN
TESTING: PROCESS
variable V1: BOOLEAN;
BEGIN
V1 := PT'AT1.RE1;
assert NOT( V1=FALSE )
report "***PASSED TEST: c06s01b00x00p10n02i00955"
severity NOTE;
assert ( V1=FALSE )
report "***FAILED TEST: c06s01b00x00p10n02i00955 - The prefix of a name is a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n02i00955arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (EN : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (2 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end decoder;
architecture Dataflow of decoder is
begin
O <= "00000001" when I = "000" AND EN = '1' else
"00000010" when I = "001" AND EN = '1' else
"00000100" when I = "010" AND EN = '1' else
"00001000" when I = "011" AND EN = '1' else
"00010000" when I = "100" AND EN = '1' else
"00100000" when I = "101" AND EN = '1' else
"01000000" when I = "110" AND EN = '1' else
"10000000" when I = "111" AND EN = '1' else
"00000000";
end Dataflow;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ec
-- File: ddr_ec.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Lattice DDR regs
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.ODDRXB;
--pragma translate_on
entity ec_oddr_reg is
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ec_oddr_reg is
component ODDRXB
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
begin
U0 : ODDRXB port map( DA => D1, DB => D2, CLK => C1, LSR => R, Q => Q);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity outbuf_interp is
generic (
N : positive := 16;
ADDRWIDTH : positive := 12
);
port(
CLK1, spi_sck_i, addr_rst: in std_logic;
spi_miso_o: out std_logic;
addr : OUT STD_LOGIC_VECTOR(ADDRWIDTH-1 DOWNTO 0) := "0000000000";
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
end outbuf_interp;
---------------------------------------------------
architecture Behavioral of outbuf_interp is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
signal di_i: std_logic_vector (N-1 downto 0) := "0000000000000000";
signal di_req_o: std_logic;
signal wren_i: std_logic := '0';
signal spi_ssel_i: std_logic := '1';
signal cnt1_clear: std_logic;
signal cnt1_Q: unsigned (31 downto 0);
signal cnt1_Q_v: std_logic_vector (31 downto 0);
signal slower_spi_clock: std_logic := '0';
signal s_read_state: unsigned (3 downto 0) := "0000";
signal next_s_read_state: unsigned (3 downto 0) := "0010";
begin
ss1: entity work.spi_slave
generic map (N => N)
port map (
clk_i => slower_spi_clock,
spi_sck_i => spi_sck_i,
spi_ssel_i => spi_ssel_i,
di_i => di_i,
di_req_o => di_req_o,
wren_i => wren_i,
spi_miso_o => spi_miso_o
);
cnt1: entity work.counter
generic map (n => 32)
port map (
clock => CLK1,
clear => cnt1_clear,
count => '1',
Q => cnt1_Q_v
);
process(CLK1)
begin
s_read_state <= next_s_read_state;
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
end if;
end process;
process(s_read_state, CLK1)
variable currcount: unsigned (ADDRWIDTH-1 downto 0) := (OTHERS => '0');
begin
if(addr_rst = '1') then
currcount := (OTHERS => '0');
addr <= std_logic_vector(currcount);
next_s_read_state <= "0001";
spi_ssel_i <= '1';
elsif rising_edge(CLK1) then
case s_read_state is
when "0000" =>
if di_req_o = '1' then
next_s_read_state <= "0001";
end if;
when "0001" =>
next_s_read_state <= "0010";
when "0010" =>
next_s_read_state <= "0011";
di_i <= din;
currcount := currcount + 1;
addr <= std_logic_vector(currcount);
-- We toggle ssel like this because it resets the position
-- if we change our mind about di_i.
spi_ssel_i <= '0';
when "0011" =>
next_s_read_state <= "0100";
when "0100" =>
next_s_read_state <= "0101";
when "0101" =>
next_s_read_state <= "0110";
wren_i <= '1';
when "0110" =>
next_s_read_state <= "0111";
when "0111" =>
next_s_read_state <= "1000";
when "1000" =>
next_s_read_state <= "0000";
wren_i <= '0';
when others =>
next_s_read_state <= "0000";
end case;
end if;
end process;
cnt1_clear <= di_req_o;
cnt1_Q <= unsigned(cnt1_Q_v);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity outbuf_interp is
generic (
N : positive := 16;
ADDRWIDTH : positive := 12
);
port(
CLK1, spi_sck_i, addr_rst: in std_logic;
spi_miso_o: out std_logic;
addr : OUT STD_LOGIC_VECTOR(ADDRWIDTH-1 DOWNTO 0) := "0000000000";
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
end outbuf_interp;
---------------------------------------------------
architecture Behavioral of outbuf_interp is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
signal di_i: std_logic_vector (N-1 downto 0) := "0000000000000000";
signal di_req_o: std_logic;
signal wren_i: std_logic := '0';
signal spi_ssel_i: std_logic := '1';
signal cnt1_clear: std_logic;
signal cnt1_Q: unsigned (31 downto 0);
signal cnt1_Q_v: std_logic_vector (31 downto 0);
signal slower_spi_clock: std_logic := '0';
signal s_read_state: unsigned (3 downto 0) := "0000";
signal next_s_read_state: unsigned (3 downto 0) := "0010";
begin
ss1: entity work.spi_slave
generic map (N => N)
port map (
clk_i => slower_spi_clock,
spi_sck_i => spi_sck_i,
spi_ssel_i => spi_ssel_i,
di_i => di_i,
di_req_o => di_req_o,
wren_i => wren_i,
spi_miso_o => spi_miso_o
);
cnt1: entity work.counter
generic map (n => 32)
port map (
clock => CLK1,
clear => cnt1_clear,
count => '1',
Q => cnt1_Q_v
);
process(CLK1)
begin
s_read_state <= next_s_read_state;
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
end if;
end process;
process(s_read_state, CLK1)
variable currcount: unsigned (ADDRWIDTH-1 downto 0) := (OTHERS => '0');
begin
if(addr_rst = '1') then
currcount := (OTHERS => '0');
addr <= std_logic_vector(currcount);
next_s_read_state <= "0001";
spi_ssel_i <= '1';
elsif rising_edge(CLK1) then
case s_read_state is
when "0000" =>
if di_req_o = '1' then
next_s_read_state <= "0001";
end if;
when "0001" =>
next_s_read_state <= "0010";
when "0010" =>
next_s_read_state <= "0011";
di_i <= din;
currcount := currcount + 1;
addr <= std_logic_vector(currcount);
-- We toggle ssel like this because it resets the position
-- if we change our mind about di_i.
spi_ssel_i <= '0';
when "0011" =>
next_s_read_state <= "0100";
when "0100" =>
next_s_read_state <= "0101";
when "0101" =>
next_s_read_state <= "0110";
wren_i <= '1';
when "0110" =>
next_s_read_state <= "0111";
when "0111" =>
next_s_read_state <= "1000";
when "1000" =>
next_s_read_state <= "0000";
wren_i <= '0';
when others =>
next_s_read_state <= "0000";
end case;
end if;
end process;
cnt1_clear <= di_req_o;
cnt1_Q <= unsigned(cnt1_Q_v);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity outbuf_interp is
generic (
N : positive := 16;
ADDRWIDTH : positive := 12
);
port(
CLK1, spi_sck_i, addr_rst: in std_logic;
spi_miso_o: out std_logic;
addr : OUT STD_LOGIC_VECTOR(ADDRWIDTH-1 DOWNTO 0) := "0000000000";
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
end outbuf_interp;
---------------------------------------------------
architecture Behavioral of outbuf_interp is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
signal di_i: std_logic_vector (N-1 downto 0) := "0000000000000000";
signal di_req_o: std_logic;
signal wren_i: std_logic := '0';
signal spi_ssel_i: std_logic := '1';
signal cnt1_clear: std_logic;
signal cnt1_Q: unsigned (31 downto 0);
signal cnt1_Q_v: std_logic_vector (31 downto 0);
signal slower_spi_clock: std_logic := '0';
signal s_read_state: unsigned (3 downto 0) := "0000";
signal next_s_read_state: unsigned (3 downto 0) := "0010";
begin
ss1: entity work.spi_slave
generic map (N => N)
port map (
clk_i => slower_spi_clock,
spi_sck_i => spi_sck_i,
spi_ssel_i => spi_ssel_i,
di_i => di_i,
di_req_o => di_req_o,
wren_i => wren_i,
spi_miso_o => spi_miso_o
);
cnt1: entity work.counter
generic map (n => 32)
port map (
clock => CLK1,
clear => cnt1_clear,
count => '1',
Q => cnt1_Q_v
);
process(CLK1)
begin
s_read_state <= next_s_read_state;
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
end if;
end process;
process(s_read_state, CLK1)
variable currcount: unsigned (ADDRWIDTH-1 downto 0) := (OTHERS => '0');
begin
if(addr_rst = '1') then
currcount := (OTHERS => '0');
addr <= std_logic_vector(currcount);
next_s_read_state <= "0001";
spi_ssel_i <= '1';
elsif rising_edge(CLK1) then
case s_read_state is
when "0000" =>
if di_req_o = '1' then
next_s_read_state <= "0001";
end if;
when "0001" =>
next_s_read_state <= "0010";
when "0010" =>
next_s_read_state <= "0011";
di_i <= din;
currcount := currcount + 1;
addr <= std_logic_vector(currcount);
-- We toggle ssel like this because it resets the position
-- if we change our mind about di_i.
spi_ssel_i <= '0';
when "0011" =>
next_s_read_state <= "0100";
when "0100" =>
next_s_read_state <= "0101";
when "0101" =>
next_s_read_state <= "0110";
wren_i <= '1';
when "0110" =>
next_s_read_state <= "0111";
when "0111" =>
next_s_read_state <= "1000";
when "1000" =>
next_s_read_state <= "0000";
wren_i <= '0';
when others =>
next_s_read_state <= "0000";
end case;
end if;
end process;
cnt1_clear <= di_req_o;
cnt1_Q <= unsigned(cnt1_Q_v);
end Behavioral;
|
architecture RTL of FIFO is
attribute coordinate of comp_1 : component is (0.0, 17.5);
attribute coordinate of comp_1 : component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1: component is (0.0, 17.5);
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
RAMB16_S9_inst0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(31 downto 24),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(3));
RAMB16_S9_inst1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(23 downto 16),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(2));
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(15 downto 8),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(1));
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(7 downto 0),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(0));
end; --architecture logic
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
port(
-- inputs
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
-- outputs
res : out std_logic_vector(31 downto 0)
);
end adder;
architecture rtl of adder is
begin
process(a, b)
begin
res <= std_logic_vector(unsigned(a) + unsigned(b));
end process;
end rtl;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:31)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_nsga2_entity;
ARCHITECTURE fir2_nsga2_description OF fir2_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := not input3 or input3;
WHEN "00000011" =>
register1 := register1 * 5;
register3 := not input4 or input4;
WHEN "00000100" =>
register2 := register2 + register3;
register3 := not input5 or input5;
register4 := not input6 or input6;
register5 := not input7 or input7;
WHEN "00000101" =>
register6 := not input8 or input8;
register3 := register5 + register3;
WHEN "00000110" =>
register4 := register6 + register4;
register5 := not input9 or input9;
register6 := not input10 or input10;
register7 := not input11 or input11;
register2 := register2 * 15;
WHEN "00000111" =>
register5 := register7 + register5;
register3 := register3 * 17;
WHEN "00001000" =>
register5 := register5 * 19;
register7 := not input12 or input12;
register8 := not input13 or input13;
register2 := register3 + register2;
WHEN "00001001" =>
register3 := register6 + register7;
register1 := register1 + register2;
register2 := not input14 or input14;
register4 := register4 * 24;
register6 := not input15 or input15;
WHEN "00001010" =>
register6 := register6 + register8;
register7 := not input16 or input16;
WHEN "00001011" =>
register2 := register2 + register7;
register3 := register3 * 28;
register6 := register6 * 30;
register1 := register5 + register1;
WHEN "00001100" =>
register2 := register2 * 32;
register1 := register6 + register1;
WHEN "00001101" =>
register1 := register3 + register1;
WHEN "00001110" =>
register1 := register2 + register1;
WHEN "00001111" =>
register1 := register4 + register1;
WHEN "00010000" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_nsga2_description; |
-- Based on wb_fabric_pkg.vhd from Tomasz Wlostowski
-- Modified by Lucas Russo <lucas.russo@lnls.br>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Multiple size definitions as Xilinx tools does not support
-- VHDL 2008
package wb_stream_generic_pkg is
-- Must be at least 2 bits wide
constant c_wbs_adr4_width : natural := 4;
constant c_wbs_adr8_width : natural := 8;
constant c_wbs_adr16_width : natural := 16;
-- Must be at least 16 bits wide.
constant c_wbs_dat16_width : natural := 16;
constant c_wbs_dat32_width : natural := 32;
constant c_wbs_dat64_width : natural := 64;
constant c_wbs_dat128_width : natural := 128;
constant c_wbs_sel16_width : natural := c_wbs_dat16_width/8;
constant c_wbs_sel32_width : natural := c_wbs_dat32_width/8;
constant c_wbs_sel64_width : natural := c_wbs_dat64_width/8;
constant c_wbs_sel128_width : natural := c_wbs_dat128_width/8;
constant c_wbs_status_width : natural := 8;
type t_wbs_interface_width is (NARROW2, NARROW1, LARGE1, LARGE2);
subtype t_wbs_adr4 is
std_logic_vector(c_wbs_adr4_width-1 downto 0);
subtype t_wbs_adr8 is
std_logic_vector(c_wbs_adr8_width-1 downto 0);
subtype t_wbs_adr16 is
std_logic_vector(c_wbs_adr16_width-1 downto 0);
subtype t_wbs_dat16 is
std_logic_vector(c_wbs_dat16_width-1 downto 0);
subtype t_wbs_dat32 is
std_logic_vector(c_wbs_dat32_width-1 downto 0);
subtype t_wbs_dat64 is
std_logic_vector(c_wbs_dat64_width-1 downto 0);
subtype t_wbs_dat128 is
std_logic_vector(c_wbs_dat128_width-1 downto 0);
subtype t_wbs_sel16 is
std_logic_vector((c_wbs_dat16_width/8)-1 downto 0);
subtype t_wbs_sel32 is
std_logic_vector((c_wbs_dat32_width/8)-1 downto 0);
subtype t_wbs_sel64 is
std_logic_vector((c_wbs_dat64_width/8)-1 downto 0);
subtype t_wbs_sel128 is
std_logic_vector((c_wbs_dat128_width/8)-1 downto 0);
constant c_WBS_DATA : unsigned := to_unsigned(0, 32);
constant c_WBS_OOB : unsigned := to_unsigned(1, 32);
constant c_WBS_STATUS : unsigned := to_unsigned(2, 32);
constant c_WBS_USER : unsigned := to_unsigned(3, 32);
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wbs_status_reg is record
error : std_logic;
reserved : std_logic_vector(6 downto 0);
end record;
--type t_wbs_source_out is record
-- adr : std_logic_vector;
-- dat : std_logic_vector;
-- cyc : std_logic;
-- stb : std_logic;
-- we : std_logic;
-- sel : std_logic_vector;
--end record;
type t_wbs_source_out16 is record
adr : t_wbs_adr4;
dat : t_wbs_dat16;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_sel16;
end record;
type t_wbs_source_out32 is record
adr : t_wbs_adr4;
dat : t_wbs_dat32;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_sel32;
end record;
type t_wbs_source_out64 is record
adr : t_wbs_adr4;
dat : t_wbs_dat64;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_sel64;
end record;
type t_wbs_source_out128 is record
adr : t_wbs_adr4;
dat : t_wbs_dat128;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_sel128;
end record;
subtype t_wbs_sink_in16 is t_wbs_source_out16;
subtype t_wbs_sink_in32 is t_wbs_source_out32;
subtype t_wbs_sink_in64 is t_wbs_source_out64;
subtype t_wbs_sink_in128 is t_wbs_source_out128;
type t_wbs_source_com_in is record
ack : std_logic;
stall : std_logic;
err : std_logic;
rty : std_logic;
end record;
-- Convinient type names for consistency
subtype t_wbs_source_in16 is t_wbs_source_com_in;
subtype t_wbs_source_in32 is t_wbs_source_com_in;
subtype t_wbs_source_in64 is t_wbs_source_com_in;
subtype t_wbs_source_in128 is t_wbs_source_com_in;
subtype t_wbs_sink_out16 is t_wbs_source_com_in;
subtype t_wbs_sink_out32 is t_wbs_source_com_in;
subtype t_wbs_sink_out64 is t_wbs_source_com_in;
subtype t_wbs_sink_out128 is t_wbs_source_com_in;
--type t_wrf_oob is record
-- valid: std_logic;
-- oob_type : std_logic_vector(3 downto 0);
-- ts_r : std_logic_vector(27 downto 0);
-- ts_f : std_logic_vector(3 downto 0);
-- frame_id : std_logic_vector(15 downto 0);
-- port_id : std_logic_vector(5 downto 0);
--end record;
type t_wbs_source_in_array is array (natural range <>) of t_wbs_source_com_in;
type t_wbs_source_out16_array is array (natural range <>) of t_wbs_source_out16;
type t_wbs_source_out32_array is array (natural range <>) of t_wbs_source_out32;
type t_wbs_source_out64_array is array (natural range <>) of t_wbs_source_out64;
type t_wbs_source_out128_array is array (natural range <>) of t_wbs_source_out128;
type t_wbs_source_in16_array is array (natural range <>) of t_wbs_source_in16;
type t_wbs_source_in32_array is array (natural range <>) of t_wbs_source_in32;
type t_wbs_source_in64_array is array (natural range <>) of t_wbs_source_in64;
type t_wbs_source_in128_array is array (natural range <>) of t_wbs_source_in128;
subtype t_wbs_sink_out_array is t_wbs_source_in_array;
subtype t_wbs_sink_in16_array is t_wbs_source_out16_array;
subtype t_wbs_sink_in32_array is t_wbs_source_out32_array;
subtype t_wbs_sink_in64_array is t_wbs_source_out64_array;
subtype t_wbs_sink_in128_array is t_wbs_source_out128_array;
subtype t_wbs_sink_out16_array is t_wbs_source_in16_array;
subtype t_wbs_sink_out32_array is t_wbs_source_in32_array;
subtype t_wbs_sink_out64_array is t_wbs_source_in64_array;
subtype t_wbs_sink_out128_array is t_wbs_source_in128_array;
function f_marshall_wbs_status (stat : t_wbs_status_reg) return std_logic_vector;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg;
function f_packet_num_bits(packet_size : natural) return natural;
function f_conv_wbs_interface_width(wbs_interface_width : t_wbs_interface_width)
return natural;
constant cc_dummy_wbs_adr4 : std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_dat16 : std_logic_vector(c_wbs_dat16_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_dat32 : std_logic_vector(c_wbs_dat32_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_dat64 : std_logic_vector(c_wbs_dat64_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_dat128 : std_logic_vector(c_wbs_dat128_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_sel16 : std_logic_vector(c_wbs_sel16_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_sel32 : std_logic_vector(c_wbs_sel32_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_sel64 : std_logic_vector(c_wbs_sel64_width-1 downto 0) := (others => 'X');
constant cc_dummy_wbs_sel128 : std_logic_vector(c_wbs_sel128_width-1 downto 0) := (others => 'X');
constant cc_dummy_src_com_in : t_wbs_source_com_in := ('0', '0', '0', '0');
constant cc_dummy_snk_in16 : t_wbs_sink_in16 :=
(cc_dummy_wbs_adr4, cc_dummy_wbs_dat16, '0', '0', '0', cc_dummy_wbs_sel16);
constant cc_dummy_snk_in32 : t_wbs_sink_in32 :=
(cc_dummy_wbs_adr4, cc_dummy_wbs_dat32, '0', '0', '0', cc_dummy_wbs_sel32);
constant cc_dummy_snk_in64 : t_wbs_sink_in64 :=
(cc_dummy_wbs_adr4, cc_dummy_wbs_dat64, '0', '0', '0', cc_dummy_wbs_sel64);
constant cc_dummy_snk_in128 : t_wbs_sink_in128 :=
(cc_dummy_wbs_adr4, cc_dummy_wbs_dat128, '0', '0', '0', cc_dummy_wbs_sel128);
-- Convinient type names for consistency
alias cc_dummy_src_in16 is cc_dummy_src_com_in;
alias cc_dummy_src_in32 is cc_dummy_src_com_in;
alias cc_dummy_src_in64 is cc_dummy_src_com_in;
alias cc_dummy_src_in128 is cc_dummy_src_com_in;
-----------------------------
-- Components
-----------------------------
-- 16 (narrow2)/32 (narrow1)/64 (large1)/128 (large2) bit Wishbone Streaming Interfaces
component wb_stream_source_gen
generic (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width : t_wbs_interface_width := LARGE1
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Streaming Interface I/O.
-- Only the used interface should be connected. The others can be left unconnected
-- 16-bit interface
src_adr16_o : out t_wbs_adr4;
src_dat16_o : out t_wbs_dat16;
src_sel16_o : out t_wbs_sel16;
-- 32-bit interface
src_adr32_o : out t_wbs_adr4;
src_dat32_o : out t_wbs_dat32;
src_sel32_o : out t_wbs_sel32;
-- 64-bit interface
src_adr64_o : out t_wbs_adr4;
src_dat64_o : out t_wbs_dat64;
src_sel64_o : out t_wbs_sel64;
-- 128-bit interface
src_adr128_o : out t_wbs_adr4;
src_dat128_o : out t_wbs_dat128;
src_sel128_o : out t_wbs_sel128;
-- Common Wishbone Streaming lines
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_ack_i : in std_logic := '0';
src_stall_i : in std_logic := '0';
src_err_i : in std_logic := '0';
src_rty_i : in std_logic := '0';
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat16_i : in std_logic_vector(c_wbs_dat16_width-1 downto 0) := (others => '0');
sel16_i : in std_logic_vector(c_wbs_sel16_width-1 downto 0) := (others => '0');
-- 32-bit interface
adr32_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat32_i : in std_logic_vector(c_wbs_dat32_width-1 downto 0) := (others => '0');
sel32_i : in std_logic_vector(c_wbs_sel32_width-1 downto 0) := (others => '0');
-- 64-bit interface
adr64_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat64_i : in std_logic_vector(c_wbs_dat64_width-1 downto 0) := (others => '0');
sel64_i : in std_logic_vector(c_wbs_sel64_width-1 downto 0) := (others => '0');
-- 128-bit interface
adr128_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat128_i : in std_logic_vector(c_wbs_dat128_width-1 downto 0) := (others => '0');
sel128_i : in std_logic_vector(c_wbs_sel128_width-1 downto 0) := (others => '0');
-- Common lines
dvalid_i : in std_logic := '0';
sof_i : in std_logic := '0';
eof_i : in std_logic := '0';
error_i : in std_logic := '0';
dreq_o : out std_logic
);
end component;
-- 16 (narrow2)/32 (narrow1)/64 (large1)/128 (large2) bit Wishbone Streaming Interfaces
component xwb_stream_source_gen
generic (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width : t_wbs_interface_width := LARGE1
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O.
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
src16_i : in t_wbs_source_in16 := cc_dummy_src_in16;
src16_o : out t_wbs_source_out16;
-- 32-bit interface
src32_i : in t_wbs_source_in32 := cc_dummy_src_in32;
src32_o : out t_wbs_source_out32;
-- 64-bit interface
src64_i : in t_wbs_source_in64 := cc_dummy_src_in64;
src64_o : out t_wbs_source_out64;
-- 128-bit interface
src128_i : in t_wbs_source_in128 := cc_dummy_src_in128;
src128_o : out t_wbs_source_out128;
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat16_i : in std_logic_vector(c_wbs_dat16_width-1 downto 0) := (others => '0');
sel16_i : in std_logic_vector(c_wbs_sel16_width-1 downto 0) := (others => '0');
-- 32-bit interface
adr32_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat32_i : in std_logic_vector(c_wbs_dat32_width-1 downto 0) := (others => '0');
sel32_i : in std_logic_vector(c_wbs_sel32_width-1 downto 0) := (others => '0');
-- 64-bit interface
adr64_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat64_i : in std_logic_vector(c_wbs_dat64_width-1 downto 0) := (others => '0');
sel64_i : in std_logic_vector(c_wbs_sel64_width-1 downto 0) := (others => '0');
-- 128-bit interface
adr128_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := (others => '0');
dat128_i : in std_logic_vector(c_wbs_dat128_width-1 downto 0) := (others => '0');
sel128_i : in std_logic_vector(c_wbs_sel128_width-1 downto 0) := (others => '0');
-- Common lines
dvalid_i : in std_logic := '0';
sof_i : in std_logic := '0';
eof_i : in std_logic := '0';
error_i : in std_logic := '0';
dreq_o : out std_logic
);
end component;
component wb_stream_sink_gen
generic (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width : t_wbs_interface_width := LARGE1
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Streaming Interface I/O.
-- Only the used interface should be connected. The others can be left unconnected
-- 16-bit interface
snk_adr16_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat16_i : in t_wbs_dat16 := cc_dummy_wbs_dat16;
snk_sel16_i : in t_wbs_sel16 := cc_dummy_wbs_sel16;
-- 32-bit interface
snk_adr32_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat32_i : in t_wbs_dat32 := cc_dummy_wbs_dat32;
snk_sel32_i : in t_wbs_sel32 := cc_dummy_wbs_sel32;
-- 64-bit interface
snk_adr64_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat64_i : in t_wbs_dat64 := cc_dummy_wbs_dat64;
snk_sel64_i : in t_wbs_sel64 := cc_dummy_wbs_sel64;
-- 128-bit interface
snk_adr128_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat128_i : in t_wbs_dat128 := cc_dummy_wbs_dat128;
snk_sel128_i : in t_wbs_sel128 := cc_dummy_wbs_sel128;
-- Common Wishbone Streaming lines
snk_cyc_i : in std_logic := '0';
snk_stb_i : in std_logic := '0';
snk_we_i : in std_logic := '0';
snk_ack_o : out std_logic;
snk_stall_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat16_o : out std_logic_vector(c_wbs_dat16_width-1 downto 0);
sel16_o : out std_logic_vector(c_wbs_sel16_width-1 downto 0);
-- 32-bit interface
adr32_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat32_o : out std_logic_vector(c_wbs_dat32_width-1 downto 0);
sel32_o : out std_logic_vector(c_wbs_sel32_width-1 downto 0);
-- 64-bit interface
adr64_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat64_o : out std_logic_vector(c_wbs_dat64_width-1 downto 0);
sel64_o : out std_logic_vector(c_wbs_sel64_width-1 downto 0);
-- 128-bit interface
adr128_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat128_o : out std_logic_vector(c_wbs_dat128_width-1 downto 0);
sel128_o : out std_logic_vector(c_wbs_sel128_width-1 downto 0);
-- Common lines
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
dreq_i : in std_logic := '0'
);
end component;
-- 16 (narrow2)/32 (narrow1)/64 (large1)/128 (large2) bit Wishbone Streaming Interfaces
component xwb_stream_sink_gen
generic (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width : t_wbs_interface_width := LARGE1
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O.
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
snk16_i : in t_wbs_sink_in16 := cc_dummy_snk_in16;
snk16_o : out t_wbs_sink_out16;
-- 32-bit interface
snk32_i : in t_wbs_sink_in32 := cc_dummy_snk_in32;
snk32_o : out t_wbs_sink_out32;
-- 64-bit interface
snk64_i : in t_wbs_sink_in64 := cc_dummy_snk_in64;
snk64_o : out t_wbs_sink_out64;
-- 128-bit interface
snk128_i : in t_wbs_sink_in128 := cc_dummy_snk_in128;
snk128_o : out t_wbs_sink_out128;
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat16_o : out std_logic_vector(c_wbs_dat16_width-1 downto 0);
sel16_o : out std_logic_vector(c_wbs_sel16_width-1 downto 0);
-- 32-bit interface
adr32_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat32_o : out std_logic_vector(c_wbs_dat32_width-1 downto 0);
sel32_o : out std_logic_vector(c_wbs_sel32_width-1 downto 0);
-- 64-bit interface
adr64_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat64_o : out std_logic_vector(c_wbs_dat64_width-1 downto 0);
sel64_o : out std_logic_vector(c_wbs_sel64_width-1 downto 0);
-- 128-bit interface
adr128_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat128_o : out std_logic_vector(c_wbs_dat128_width-1 downto 0);
sel128_o : out std_logic_vector(c_wbs_sel128_width-1 downto 0);
-- Common lines
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
dreq_i : in std_logic := '0'
);
end component;
end wb_stream_generic_pkg;
package body wb_stream_generic_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector
is
variable tmp : std_logic_vector(c_wbs_status_width-1 downto 0) := (others => '0');
begin
tmp(0) := stat.error;
return tmp;
end;
function f_unmarshall_wbs_status(stat : std_logic_vector)
return t_wbs_status_reg
is
variable tmp : t_wbs_status_reg;
begin
tmp.error := stat(0);
return tmp;
end f_unmarshall_wbs_status;
function f_packet_num_bits(packet_size : natural)
return natural
is
-- Slightly different behaviour than the one located at wishbone_pkg.vhd
function f_ceil_log2(x : natural) return natural is
begin
if x <= 2
then return 1;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
begin
return f_ceil_log2(packet_size);
end f_packet_num_bits;
-- Convert t_wbs_dat_width type to natural
function f_conv_wbs_interface_width(wbs_interface_width : t_wbs_interface_width)
return natural
is
variable size : natural;
begin
case (wbs_interface_width) is
when NARROW2 =>
size := 16;
when NARROW1 =>
size := 32;
when LARGE1 =>
size := 64;
when LARGE2 =>
size := 128;
-- Should not happen
when others =>
size := 64;
end case;
return size;
end f_conv_wbs_interface_width;
end wb_stream_generic_pkg;
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library BananaCore;
-- A controller that generates (and manages) the core main clock
entity ClockController is
port(
-- the processor main clock
clock: buffer BananaCore.Core.Clock;
-- a enable that that allows to enabale and disable the clock
enable: in bit
);
end ClockController;
architecture ClockControllerImpl of ClockController is
begin
-- FIXME use a real hardware clock source
clock <= '1' after 0.5 ms when clock = '0' and enable = '1' else
'0' after 0.5 ms when clock = '1' and enable = '1';
end ClockControllerImpl; |
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1:component is (0.0, 17.5);
attribute coordinate of comp_1:component is (0.0, 17.5);
begin
end architecture RTL;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY sqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END sqrt;
ARCHITECTURE sqrt_arch OF sqrt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sqrt_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sqrt_arch: ARCHITECTURE IS "cordic_v6_0_11,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sqrt_arch : ARCHITECTURE IS "sqrt,cordic_v6_0_11,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sqrt_arch: ARCHITECTURE IS "sqrt,cordic_v6_0_11,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cordic,x_ipVersion=6.0,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ARCHITECTURE=2,C_CORDIC_FUNCTION=6,C_COARSE_ROTATE=0,C_DATA_FORMAT=1,C_XDEVICEFAMILY=zynq,C_HAS_ACLKEN=0,C_HAS_ACLK=1,C_HAS_S_AXIS_CARTESIAN=1,C_HAS_S_AXIS_PHASE=0,C_HAS_ARESETN=0,C_INPUT_WIDTH=16,C_ITERATIONS=0,C_OUTPUT_WIDTH=16,C_PHASE_FORMAT=0,C_PIPELINE_MODE=-2,C_PRECISION=0,C_ROUND_MODE=0,C_SCALE_COMP=0,C_THROTTLE_S" &
"CHEME=3,C_TLAST_RESOLUTION=0,C_HAS_S_AXIS_PHASE_TUSER=0,C_HAS_S_AXIS_PHASE_TLAST=0,C_S_AXIS_PHASE_TDATA_WIDTH=16,C_S_AXIS_PHASE_TUSER_WIDTH=1,C_HAS_S_AXIS_CARTESIAN_TUSER=0,C_HAS_S_AXIS_CARTESIAN_TLAST=0,C_S_AXIS_CARTESIAN_TDATA_WIDTH=16,C_S_AXIS_CARTESIAN_TUSER_WIDTH=1,C_M_AXIS_DOUT_TDATA_WIDTH=16,C_M_AXIS_DOUT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 6,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 16,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END sqrt_arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:01 11/15/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_keygen IS
END tb_keygen;
ARCHITECTURE behavior OF tb_keygen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal rc : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal z1 : std_logic_vector(15 downto 0);
signal z2 : std_logic_vector(15 downto 0);
signal z3 : std_logic_vector(15 downto 0);
signal z4 : std_logic_vector(15 downto 0);
signal z5 : std_logic_vector(15 downto 0);
signal z6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygen PORT MAP (
rc => rc,
key_in => key_in,
z1 => z1,
z2 => z2,
z3 => z3,
z4 => z4,
z5 => z5,
z6 => z6
);
key_in <= std_logic_vector(to_unsigned(1,16))&std_logic_vector(to_unsigned(2,16))&std_logic_vector(to_unsigned(3,16))&std_logic_vector(to_unsigned(4,16))&std_logic_vector(to_unsigned(5,16))&std_logic_vector(to_unsigned(6,16))&std_logic_vector(to_unsigned(7,16))&std_logic_vector(to_unsigned(8,16));
rc <= std_logic_vector(to_unsigned(0,4)), std_logic_vector(to_unsigned(1,4))after 10 ns, std_logic_vector(to_unsigned(2,4)) after 20 ns,std_logic_vector(to_unsigned(3,4)) after 30 ns,std_logic_vector(to_unsigned(4,4)) after 40 ns,std_logic_vector(to_unsigned(5,4)) after 50 ns,std_logic_vector(to_unsigned(6,4)) after 60 ns,std_logic_vector(to_unsigned(7,4)) after 70 ns,std_logic_vector(to_unsigned(8,4)) after 80 ns;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:01 11/15/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_keygen IS
END tb_keygen;
ARCHITECTURE behavior OF tb_keygen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal rc : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal z1 : std_logic_vector(15 downto 0);
signal z2 : std_logic_vector(15 downto 0);
signal z3 : std_logic_vector(15 downto 0);
signal z4 : std_logic_vector(15 downto 0);
signal z5 : std_logic_vector(15 downto 0);
signal z6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygen PORT MAP (
rc => rc,
key_in => key_in,
z1 => z1,
z2 => z2,
z3 => z3,
z4 => z4,
z5 => z5,
z6 => z6
);
key_in <= std_logic_vector(to_unsigned(1,16))&std_logic_vector(to_unsigned(2,16))&std_logic_vector(to_unsigned(3,16))&std_logic_vector(to_unsigned(4,16))&std_logic_vector(to_unsigned(5,16))&std_logic_vector(to_unsigned(6,16))&std_logic_vector(to_unsigned(7,16))&std_logic_vector(to_unsigned(8,16));
rc <= std_logic_vector(to_unsigned(0,4)), std_logic_vector(to_unsigned(1,4))after 10 ns, std_logic_vector(to_unsigned(2,4)) after 20 ns,std_logic_vector(to_unsigned(3,4)) after 30 ns,std_logic_vector(to_unsigned(4,4)) after 40 ns,std_logic_vector(to_unsigned(5,4)) after 50 ns,std_logic_vector(to_unsigned(6,4)) after 60 ns,std_logic_vector(to_unsigned(7,4)) after 70 ns,std_logic_vector(to_unsigned(8,4)) after 80 ns;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:01 11/15/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_keygen IS
END tb_keygen;
ARCHITECTURE behavior OF tb_keygen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal rc : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal z1 : std_logic_vector(15 downto 0);
signal z2 : std_logic_vector(15 downto 0);
signal z3 : std_logic_vector(15 downto 0);
signal z4 : std_logic_vector(15 downto 0);
signal z5 : std_logic_vector(15 downto 0);
signal z6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygen PORT MAP (
rc => rc,
key_in => key_in,
z1 => z1,
z2 => z2,
z3 => z3,
z4 => z4,
z5 => z5,
z6 => z6
);
key_in <= std_logic_vector(to_unsigned(1,16))&std_logic_vector(to_unsigned(2,16))&std_logic_vector(to_unsigned(3,16))&std_logic_vector(to_unsigned(4,16))&std_logic_vector(to_unsigned(5,16))&std_logic_vector(to_unsigned(6,16))&std_logic_vector(to_unsigned(7,16))&std_logic_vector(to_unsigned(8,16));
rc <= std_logic_vector(to_unsigned(0,4)), std_logic_vector(to_unsigned(1,4))after 10 ns, std_logic_vector(to_unsigned(2,4)) after 20 ns,std_logic_vector(to_unsigned(3,4)) after 30 ns,std_logic_vector(to_unsigned(4,4)) after 40 ns,std_logic_vector(to_unsigned(5,4)) after 50 ns,std_logic_vector(to_unsigned(6,4)) after 60 ns,std_logic_vector(to_unsigned(7,4)) after 70 ns,std_logic_vector(to_unsigned(8,4)) after 80 ns;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:01 11/15/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_keygen IS
END tb_keygen;
ARCHITECTURE behavior OF tb_keygen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal rc : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal z1 : std_logic_vector(15 downto 0);
signal z2 : std_logic_vector(15 downto 0);
signal z3 : std_logic_vector(15 downto 0);
signal z4 : std_logic_vector(15 downto 0);
signal z5 : std_logic_vector(15 downto 0);
signal z6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygen PORT MAP (
rc => rc,
key_in => key_in,
z1 => z1,
z2 => z2,
z3 => z3,
z4 => z4,
z5 => z5,
z6 => z6
);
key_in <= std_logic_vector(to_unsigned(1,16))&std_logic_vector(to_unsigned(2,16))&std_logic_vector(to_unsigned(3,16))&std_logic_vector(to_unsigned(4,16))&std_logic_vector(to_unsigned(5,16))&std_logic_vector(to_unsigned(6,16))&std_logic_vector(to_unsigned(7,16))&std_logic_vector(to_unsigned(8,16));
rc <= std_logic_vector(to_unsigned(0,4)), std_logic_vector(to_unsigned(1,4))after 10 ns, std_logic_vector(to_unsigned(2,4)) after 20 ns,std_logic_vector(to_unsigned(3,4)) after 30 ns,std_logic_vector(to_unsigned(4,4)) after 40 ns,std_logic_vector(to_unsigned(5,4)) after 50 ns,std_logic_vector(to_unsigned(6,4)) after 60 ns,std_logic_vector(to_unsigned(7,4)) after 70 ns,std_logic_vector(to_unsigned(8,4)) after 80 ns;
END;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_20.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book
library ieee;
use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
-- end code from book
entity fg_07_20 is
end entity fg_07_20;
library ieee;
use ieee.std_logic_1164.all;
library stimulus;
architecture test of fg_07_20 is
signal reg_addr_decoded, rd, wr, io_en,
cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
signal test_vector : std_ulogic_vector(1 to 5);
use stimulus.stimulus_generators.all;
begin
dut : entity work.reg_ctrl
port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
stimulus_proc : process is
begin
all_possible_values( bv => test_vector,
delay_between_values => 10 ns );
wait;
end process stimulus_proc;
(reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_20.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book
library ieee;
use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
-- end code from book
entity fg_07_20 is
end entity fg_07_20;
library ieee;
use ieee.std_logic_1164.all;
library stimulus;
architecture test of fg_07_20 is
signal reg_addr_decoded, rd, wr, io_en,
cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
signal test_vector : std_ulogic_vector(1 to 5);
use stimulus.stimulus_generators.all;
begin
dut : entity work.reg_ctrl
port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
stimulus_proc : process is
begin
all_possible_values( bv => test_vector,
delay_between_values => 10 ns );
wait;
end process stimulus_proc;
(reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_20.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book
library ieee;
use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
-- end code from book
entity fg_07_20 is
end entity fg_07_20;
library ieee;
use ieee.std_logic_1164.all;
library stimulus;
architecture test of fg_07_20 is
signal reg_addr_decoded, rd, wr, io_en,
cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
signal test_vector : std_ulogic_vector(1 to 5);
use stimulus.stimulus_generators.all;
begin
dut : entity work.reg_ctrl
port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
stimulus_proc : process is
begin
all_possible_values( bv => test_vector,
delay_between_values => 10 ns );
wait;
end process stimulus_proc;
(reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
end architecture test;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package mdctrom256 is
--n = 256
constant rom_lenght_br: integer:=64;
constant rom_lenght: integer:=320;
type rom_table is array (0 to rom_lenght-1) of std_logic_vector (31 downto 0);
type rom_bitrev is array (0 to rom_lenght_br-1) of std_logic_vector (31 downto 0);
constant bitrev: rom_bitrev:= rom_bitrev'(
--bitrev:
X"0000007e",
X"00000000",
X"0000003e",
X"00000040",
X"0000005e",
X"00000020",
X"0000001e",
X"00000060",
X"0000006e",
X"00000010",
X"0000002e",
X"00000050",
X"0000004e",
X"00000030",
X"0000000e",
X"00000070",
X"00000076",
X"00000008",
X"00000036",
X"00000048",
X"00000056",
X"00000028",
X"00000016",
X"00000068",
X"00000066",
X"00000018",
X"00000026",
X"00000058",
X"00000046",
X"00000038",
X"00000006",
X"00000078",
X"0000007a",
X"00000004",
X"0000003a",
X"00000044",
X"0000005a",
X"00000024",
X"0000001a",
X"00000064",
X"0000006a",
X"00000014",
X"0000002a",
X"00000054",
X"0000004a",
X"00000034",
X"0000000a",
X"00000074",
X"00000072",
X"0000000c",
X"00000032",
X"0000004c",
X"00000052",
X"0000002c",
X"00000012",
X"0000006c",
X"00000062",
X"0000001c",
X"00000022",
X"0000005c",
X"00000042",
X"0000003c",
X"00000002",
X"0000007c"
);
--T:
constant T: rom_table:= rom_table'(
X"00004000",
X"00000000",
X"00003fec",
X"fffffcdc",
X"00003fb1",
X"fffff9ba",
X"00003f4f",
X"fffff69c",
X"00003ec5",
X"fffff384",
X"00003e15",
X"fffff073",
X"00003d3f",
X"ffffed6c",
X"00003c42",
X"ffffea70",
X"00003b21",
X"ffffe782",
X"000039db",
X"ffffe4a3",
X"00003871",
X"ffffe1d5",
X"000036e5",
X"ffffdf19",
X"00003537",
X"ffffdc72",
X"00003368",
X"ffffd9e0",
X"00003179",
X"ffffd766",
X"00002f6c",
X"ffffd505",
X"00002d41",
X"ffffd2bf",
X"00002afb",
X"ffffd094",
X"0000289a",
X"ffffce87",
X"00002620",
X"ffffcc98",
X"0000238e",
X"ffffcac9",
X"000020e7",
X"ffffc91b",
X"00001e2b",
X"ffffc78f",
X"00001b5d",
X"ffffc625",
X"0000187e",
X"ffffc4df",
X"00001590",
X"ffffc3be",
X"00001294",
X"ffffc2c1",
X"00000f8d",
X"ffffc1eb",
X"00000c7c",
X"ffffc13b",
X"00000964",
X"ffffc0b1",
X"00000646",
X"ffffc04f",
X"00000324",
X"ffffc014",
X"00000000",
X"ffffc000",
X"fffffcdd",
X"ffffc014",
X"fffff9bb",
X"ffffc04f",
X"fffff69d",
X"ffffc0b1",
X"fffff385",
X"ffffc13b",
X"fffff074",
X"ffffc1eb",
X"ffffed6d",
X"ffffc2c1",
X"ffffea71",
X"ffffc3be",
X"ffffe783",
X"ffffc4df",
X"ffffe4a4",
X"ffffc625",
X"ffffe1d6",
X"ffffc78f",
X"ffffdf1a",
X"ffffc91b",
X"ffffdc73",
X"ffffcac9",
X"ffffd9e1",
X"ffffcc98",
X"ffffd767",
X"ffffce87",
X"ffffd506",
X"ffffd094",
X"ffffd2c0",
X"ffffd2bf",
X"ffffd095",
X"ffffd505",
X"ffffce88",
X"ffffd766",
X"ffffcc99",
X"ffffd9e0",
X"ffffcaca",
X"ffffdc72",
X"ffffc91c",
X"ffffdf19",
X"ffffc790",
X"ffffe1d5",
X"ffffc626",
X"ffffe4a3",
X"ffffc4e0",
X"ffffe782",
X"ffffc3bf",
X"ffffea70",
X"ffffc2c2",
X"ffffed6c",
X"ffffc1ec",
X"fffff073",
X"ffffc13c",
X"fffff384",
X"ffffc0b2",
X"fffff69c",
X"ffffc050",
X"fffff9ba",
X"ffffc015",
X"fffffcdc",
X"00003ffe",
X"00000064",
X"00003ffc",
X"0000012d",
X"00003ff7",
X"000001f6",
X"00003fef",
X"000002bf",
X"00003fe6",
X"00000388",
X"00003fda",
X"00000450",
X"00003fcb",
X"00000519",
X"00003fb9",
X"000005e1",
X"00003fa6",
X"000006aa",
X"00003f90",
X"00000772",
X"00003f77",
X"00000839",
X"00003f5c",
X"00000900",
X"00003f3f",
X"000009c7",
X"00003f1f",
X"00000a8d",
X"00003efc",
X"00000b53",
X"00003ed7",
X"00000c19",
X"00003eb0",
X"00000cde",
X"00003e86",
X"00000da3",
X"00003e5a",
X"00000e67",
X"00003e2c",
X"00000f2b",
X"00003dfb",
X"00000fee",
X"00003dc8",
X"000010b0",
X"00003d93",
X"00001172",
X"00003d5b",
X"00001233",
X"00003d20",
X"000012f3",
X"00003ce3",
X"000013b3",
X"00003ca4",
X"00001472",
X"00003c62",
X"00001530",
X"00003c1f",
X"000015ee",
X"00003bd9",
X"000016aa",
X"00003b90",
X"00001766",
X"00003b46",
X"00001820",
X"00003af9",
X"000018da",
X"00003aa9",
X"00001992",
X"00003a58",
X"00001a4a",
X"00003a04",
X"00001b01",
X"000039af",
X"00001bb7",
X"00003957",
X"00001c6b",
X"000038fc",
X"00001d1f",
X"0000389f",
X"00001dd1",
X"00003840",
X"00001e83",
X"000037e0",
X"00001f33",
X"0000377d",
X"00001fe2",
X"00003717",
X"00002090",
X"000036b0",
X"0000213c",
X"00003646",
X"000021e7",
X"000035db",
X"00002291",
X"0000356d",
X"00002339",
X"000034fe",
X"000023e1",
X"0000348c",
X"00002487",
X"00003418",
X"0000252b",
X"000033a2",
X"000025ce",
X"0000332b",
X"00002670",
X"000032b1",
X"00002710",
X"00003235",
X"000027ae",
X"000031b7",
X"0000284b",
X"00003138",
X"000028e7",
X"000030b6",
X"00002981",
X"00003033",
X"00002a19",
X"00002fae",
X"00002aaf",
X"00002f27",
X"00002b44",
X"00002e9e",
X"00002bd7",
X"00002e13",
X"00002c69",
X"00002d87",
X"00002cf9",
X"00001ffd",
X"ffffff37",
X"00001fea",
X"fffffda6",
X"00001fc2",
X"fffffc15",
X"00001f87",
X"fffffa88",
X"00001f39",
X"fffff8fd",
X"00001ed7",
X"fffff777",
X"00001e62",
X"fffff5f7",
X"00001ddb",
X"fffff47c",
X"00001d41",
X"fffff309",
X"00001c95",
X"fffff19d",
X"00001bd8",
X"fffff03a",
X"00001b09",
X"ffffeee2",
X"00001a29",
X"ffffed93",
X"0000193a",
X"ffffec50",
X"0000183b",
X"ffffeb19",
X"0000172d",
X"ffffe9f0",
X"00001610",
X"ffffe8d3",
X"000014e7",
X"ffffe7c5",
X"000013b0",
X"ffffe6c6",
X"0000126d",
X"ffffe5d7",
X"0000111e",
X"ffffe4f7",
X"00000fc6",
X"ffffe428",
X"00000e63",
X"ffffe36b",
X"00000cf7",
X"ffffe2bf",
X"00000b84",
X"ffffe225",
X"00000a09",
X"ffffe19e",
X"00000889",
X"ffffe129",
X"00000703",
X"ffffe0c7",
X"00000578",
X"ffffe079",
X"000003eb",
X"ffffe03e",
X"0000025a",
X"ffffe016",
X"000000c9",
X"ffffe003"
);
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end entity D_flipflop;
architecture behavioral of D_flipflop is
begin
q <= d when clk'event and clk = '1';
end architecture behavioral;
entity inverter is
port ( a : in bit; y : out bit );
end entity inverter;
architecture behavioral of inverter is
begin
y <= not a;
end architecture behavioral;
-- code from book
entity count2 is
port ( clk : in bit; q0, q1 : buffer bit );
end entity count2;
--------------------------------------------------
architecture buffered_outputs of count2 is
component D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end component D_flipflop;
component inverter is
port ( a : in bit; y : out bit );
end component inverter;
signal q0_n, q1_n : bit;
begin
bit0 : component D_flipflop
port map ( clk => clk, d => q0_n, q => q0 );
inv0 : component inverter
port map ( a => q0, y => q0_n );
bit1 : component D_flipflop
port map ( clk => q0_n, d => q1_n, q => q1 );
inv1 : component inverter
port map ( a => q1, y => q1_n );
end architecture buffered_outputs;
-- end code from book
entity fg_21_01 is
end entity fg_21_01;
architecture test of fg_21_01 is
signal clk, q0, q1 : bit;
begin
dut : entity work.count2(buffered_outputs)
port map ( clk => clk, q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 10 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end entity D_flipflop;
architecture behavioral of D_flipflop is
begin
q <= d when clk'event and clk = '1';
end architecture behavioral;
entity inverter is
port ( a : in bit; y : out bit );
end entity inverter;
architecture behavioral of inverter is
begin
y <= not a;
end architecture behavioral;
-- code from book
entity count2 is
port ( clk : in bit; q0, q1 : buffer bit );
end entity count2;
--------------------------------------------------
architecture buffered_outputs of count2 is
component D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end component D_flipflop;
component inverter is
port ( a : in bit; y : out bit );
end component inverter;
signal q0_n, q1_n : bit;
begin
bit0 : component D_flipflop
port map ( clk => clk, d => q0_n, q => q0 );
inv0 : component inverter
port map ( a => q0, y => q0_n );
bit1 : component D_flipflop
port map ( clk => q0_n, d => q1_n, q => q1 );
inv1 : component inverter
port map ( a => q1, y => q1_n );
end architecture buffered_outputs;
-- end code from book
entity fg_21_01 is
end entity fg_21_01;
architecture test of fg_21_01 is
signal clk, q0, q1 : bit;
begin
dut : entity work.count2(buffered_outputs)
port map ( clk => clk, q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 10 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end entity D_flipflop;
architecture behavioral of D_flipflop is
begin
q <= d when clk'event and clk = '1';
end architecture behavioral;
entity inverter is
port ( a : in bit; y : out bit );
end entity inverter;
architecture behavioral of inverter is
begin
y <= not a;
end architecture behavioral;
-- code from book
entity count2 is
port ( clk : in bit; q0, q1 : buffer bit );
end entity count2;
--------------------------------------------------
architecture buffered_outputs of count2 is
component D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end component D_flipflop;
component inverter is
port ( a : in bit; y : out bit );
end component inverter;
signal q0_n, q1_n : bit;
begin
bit0 : component D_flipflop
port map ( clk => clk, d => q0_n, q => q0 );
inv0 : component inverter
port map ( a => q0, y => q0_n );
bit1 : component D_flipflop
port map ( clk => q0_n, d => q1_n, q => q1 );
inv1 : component inverter
port map ( a => q1, y => q1_n );
end architecture buffered_outputs;
-- end code from book
entity fg_21_01 is
end entity fg_21_01;
architecture test of fg_21_01 is
signal clk, q0, q1 : bit;
begin
dut : entity work.count2(buffered_outputs)
port map ( clk => clk, q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 10 ns;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qam_dem_top_mounstrito_cos_lut_rom is
generic(
dwidth : integer := 15;
awidth : integer := 10;
mem_size : integer := 1024
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of qam_dem_top_mounstrito_cos_lut_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 to 6=> "111111111111111", 7 to 8=> "111111111111110", 9 => "111111111111101",
10 => "111111111111100", 11 => "111111111111011", 12 => "111111111111010",
13 => "111111111111001", 14 => "111111111111000", 15 => "111111111110111",
16 => "111111111110110", 17 => "111111111110101", 18 => "111111111110100",
19 => "111111111110010", 20 => "111111111110001", 21 => "111111111101111",
22 => "111111111101101", 23 => "111111111101100", 24 => "111111111101010",
25 => "111111111101000", 26 => "111111111100110", 27 => "111111111100100",
28 => "111111111100010", 29 => "111111111100000", 30 => "111111111011101",
31 => "111111111011011", 32 => "111111111011001", 33 => "111111111010110",
34 => "111111111010011", 35 => "111111111010001", 36 => "111111111001110",
37 => "111111111001011", 38 => "111111111001000", 39 => "111111111000101",
40 => "111111111000010", 41 => "111111110111111", 42 => "111111110111100",
43 => "111111110111001", 44 => "111111110110101", 45 => "111111110110010",
46 => "111111110101110", 47 => "111111110101011", 48 => "111111110100111",
49 => "111111110100011", 50 => "111111110100000", 51 => "111111110011100",
52 => "111111110011000", 53 => "111111110010100", 54 => "111111110010000",
55 => "111111110001011", 56 => "111111110000111", 57 => "111111110000011",
58 => "111111101111110", 59 => "111111101111010", 60 => "111111101110101",
61 => "111111101110001", 62 => "111111101101100", 63 => "111111101100111",
64 => "111111101100010", 65 => "111111101011101", 66 => "111111101011000",
67 => "111111101010011", 68 => "111111101001110", 69 => "111111101001001",
70 => "111111101000011", 71 => "111111100111110", 72 => "111111100111000",
73 => "111111100110011", 74 => "111111100101101", 75 => "111111100100111",
76 => "111111100100010", 77 => "111111100011100", 78 => "111111100010110",
79 => "111111100010000", 80 => "111111100001010", 81 => "111111100000011",
82 => "111111011111101", 83 => "111111011110111", 84 => "111111011110000",
85 => "111111011101010", 86 => "111111011100011", 87 => "111111011011101",
88 => "111111011010110", 89 => "111111011001111", 90 => "111111011001000",
91 => "111111011000001", 92 => "111111010111010", 93 => "111111010110011",
94 => "111111010101100", 95 => "111111010100101", 96 => "111111010011101",
97 => "111111010010110", 98 => "111111010001110", 99 => "111111010000111",
100 => "111111001111111", 101 => "111111001111000", 102 => "111111001110000",
103 => "111111001101000", 104 => "111111001100000", 105 => "111111001011000",
106 => "111111001010000", 107 => "111111001001000", 108 => "111111000111111",
109 => "111111000110111", 110 => "111111000101111", 111 => "111111000100110",
112 => "111111000011110", 113 => "111111000010101", 114 => "111111000001100",
115 => "111111000000011", 116 => "111110111111011", 117 => "111110111110010",
118 => "111110111101001", 119 => "111110111100000", 120 => "111110111010110",
121 => "111110111001101", 122 => "111110111000100", 123 => "111110110111010",
124 => "111110110110001", 125 => "111110110100111", 126 => "111110110011110",
127 => "111110110010100", 128 => "111110110001010", 129 => "111110110000001",
130 => "111110101110111", 131 => "111110101101101", 132 => "111110101100011",
133 => "111110101011000", 134 => "111110101001110", 135 => "111110101000100",
136 => "111110100111001", 137 => "111110100101111", 138 => "111110100100101",
139 => "111110100011010", 140 => "111110100001111", 141 => "111110100000101",
142 => "111110011111010", 143 => "111110011101111", 144 => "111110011100100",
145 => "111110011011001", 146 => "111110011001110", 147 => "111110011000010",
148 => "111110010110111", 149 => "111110010101100", 150 => "111110010100000",
151 => "111110010010101", 152 => "111110010001001", 153 => "111110001111110",
154 => "111110001110010", 155 => "111110001100110", 156 => "111110001011010",
157 => "111110001001110", 158 => "111110001000010", 159 => "111110000110110",
160 => "111110000101010", 161 => "111110000011110", 162 => "111110000010001",
163 => "111110000000101", 164 => "111101111111001", 165 => "111101111101100",
166 => "111101111011111", 167 => "111101111010011", 168 => "111101111000110",
169 => "111101110111001", 170 => "111101110101100", 171 => "111101110011111",
172 => "111101110010010", 173 => "111101110000101", 174 => "111101101111000",
175 => "111101101101010", 176 => "111101101011101", 177 => "111101101010000",
178 => "111101101000010", 179 => "111101100110100", 180 => "111101100100111",
181 => "111101100011001", 182 => "111101100001011", 183 => "111101011111101",
184 => "111101011101111", 185 => "111101011100001", 186 => "111101011010011",
187 => "111101011000101", 188 => "111101010110111", 189 => "111101010101000",
190 => "111101010011010", 191 => "111101010001100", 192 => "111101001111101",
193 => "111101001101110", 194 => "111101001100000", 195 => "111101001010001",
196 => "111101001000010", 197 => "111101000110011", 198 => "111101000100100",
199 => "111101000010101", 200 => "111101000000110", 201 => "111100111110111",
202 => "111100111100111", 203 => "111100111011000", 204 => "111100111001001",
205 => "111100110111001", 206 => "111100110101010", 207 => "111100110011010",
208 => "111100110001010", 209 => "111100101111010", 210 => "111100101101010",
211 => "111100101011011", 212 => "111100101001010", 213 => "111100100111010",
214 => "111100100101010", 215 => "111100100011010", 216 => "111100100001010",
217 => "111100011111001", 218 => "111100011101001", 219 => "111100011011000",
220 => "111100011001000", 221 => "111100010110111", 222 => "111100010100110",
223 => "111100010010101", 224 => "111100010000101", 225 => "111100001110100",
226 => "111100001100011", 227 => "111100001010001", 228 => "111100001000000",
229 => "111100000101111", 230 => "111100000011110", 231 => "111100000001100",
232 => "111011111111011", 233 => "111011111101001", 234 => "111011111011000",
235 => "111011111000110", 236 => "111011110110100", 237 => "111011110100010",
238 => "111011110010000", 239 => "111011101111110", 240 => "111011101101100",
241 => "111011101011010", 242 => "111011101001000", 243 => "111011100110110",
244 => "111011100100011", 245 => "111011100010001", 246 => "111011011111110",
247 => "111011011101100", 248 => "111011011011001", 249 => "111011011000111",
250 => "111011010110100", 251 => "111011010100001", 252 => "111011010001110",
253 => "111011001111011", 254 => "111011001101000", 255 => "111011001010101",
256 => "111011001000010", 257 => "111011000101110", 258 => "111011000011011",
259 => "111011000001000", 260 => "111010111110100", 261 => "111010111100001",
262 => "111010111001101", 263 => "111010110111001", 264 => "111010110100110",
265 => "111010110010010", 266 => "111010101111110", 267 => "111010101101010",
268 => "111010101010110", 269 => "111010101000010", 270 => "111010100101101",
271 => "111010100011001", 272 => "111010100000101", 273 => "111010011110000",
274 => "111010011011100", 275 => "111010011000111", 276 => "111010010110011",
277 => "111010010011110", 278 => "111010010001001", 279 => "111010001110101",
280 => "111010001100000", 281 => "111010001001011", 282 => "111010000110110",
283 => "111010000100001", 284 => "111010000001011", 285 => "111001111110110",
286 => "111001111100001", 287 => "111001111001011", 288 => "111001110110110",
289 => "111001110100000", 290 => "111001110001011", 291 => "111001101110101",
292 => "111001101011111", 293 => "111001101001010", 294 => "111001100110100",
295 => "111001100011110", 296 => "111001100001000", 297 => "111001011110010",
298 => "111001011011100", 299 => "111001011000101", 300 => "111001010101111",
301 => "111001010011001", 302 => "111001010000010", 303 => "111001001101100",
304 => "111001001010101", 305 => "111001000111111", 306 => "111001000101000",
307 => "111001000010001", 308 => "111000111111010", 309 => "111000111100011",
310 => "111000111001100", 311 => "111000110110101", 312 => "111000110011110",
313 => "111000110000111", 314 => "111000101110000", 315 => "111000101011000",
316 => "111000101000001", 317 => "111000100101010", 318 => "111000100010010",
319 => "111000011111010", 320 => "111000011100011", 321 => "111000011001011",
322 => "111000010110011", 323 => "111000010011011", 324 => "111000010000011",
325 => "111000001101011", 326 => "111000001010011", 327 => "111000000111011",
328 => "111000000100011", 329 => "111000000001011", 330 => "110111111110010",
331 => "110111111011010", 332 => "110111111000010", 333 => "110111110101001",
334 => "110111110010000", 335 => "110111101111000", 336 => "110111101011111",
337 => "110111101000110", 338 => "110111100101101", 339 => "110111100010100",
340 => "110111011111011", 341 => "110111011100010", 342 => "110111011001001",
343 => "110111010110000", 344 => "110111010010111", 345 => "110111001111101",
346 => "110111001100100", 347 => "110111001001010", 348 => "110111000110001",
349 => "110111000010111", 350 => "110110111111110", 351 => "110110111100100",
352 => "110110111001010", 353 => "110110110110000", 354 => "110110110010110",
355 => "110110101111100", 356 => "110110101100010", 357 => "110110101001000",
358 => "110110100101110", 359 => "110110100010100", 360 => "110110011111001",
361 => "110110011011111", 362 => "110110011000100", 363 => "110110010101010",
364 => "110110010001111", 365 => "110110001110101", 366 => "110110001011010",
367 => "110110000111111", 368 => "110110000100100", 369 => "110110000001001",
370 => "110101111101110", 371 => "110101111010011", 372 => "110101110111000",
373 => "110101110011101", 374 => "110101110000010", 375 => "110101101100110",
376 => "110101101001011", 377 => "110101100101111", 378 => "110101100010100",
379 => "110101011111000", 380 => "110101011011101", 381 => "110101011000001",
382 => "110101010100101", 383 => "110101010001001", 384 => "110101001101110",
385 => "110101001010010", 386 => "110101000110110", 387 => "110101000011010",
388 => "110100111111101", 389 => "110100111100001", 390 => "110100111000101",
391 => "110100110101001", 392 => "110100110001100", 393 => "110100101110000",
394 => "110100101010011", 395 => "110100100110111", 396 => "110100100011010",
397 => "110100011111101", 398 => "110100011100000", 399 => "110100011000100",
400 => "110100010100111", 401 => "110100010001010", 402 => "110100001101101",
403 => "110100001001111", 404 => "110100000110010", 405 => "110100000010101",
406 => "110011111111000", 407 => "110011111011010", 408 => "110011110111101",
409 => "110011110100000", 410 => "110011110000010", 411 => "110011101100100",
412 => "110011101000111", 413 => "110011100101001", 414 => "110011100001011",
415 => "110011011101101", 416 => "110011011010000", 417 => "110011010110010",
418 => "110011010010011", 419 => "110011001110101", 420 => "110011001010111",
421 => "110011000111001", 422 => "110011000011011", 423 => "110010111111100",
424 => "110010111011110", 425 => "110010111000000", 426 => "110010110100001",
427 => "110010110000010", 428 => "110010101100100", 429 => "110010101000101",
430 => "110010100100110", 431 => "110010100000111", 432 => "110010011101001",
433 => "110010011001010", 434 => "110010010101011", 435 => "110010010001011",
436 => "110010001101100", 437 => "110010001001101", 438 => "110010000101110",
439 => "110010000001111", 440 => "110001111101111", 441 => "110001111010000",
442 => "110001110110000", 443 => "110001110010001", 444 => "110001101110001",
445 => "110001101010001", 446 => "110001100110010", 447 => "110001100010010",
448 => "110001011110010", 449 => "110001011010010", 450 => "110001010110010",
451 => "110001010010010", 452 => "110001001110010", 453 => "110001001010010",
454 => "110001000110010", 455 => "110001000010001", 456 => "110000111110001",
457 => "110000111010001", 458 => "110000110110000", 459 => "110000110010000",
460 => "110000101101111", 461 => "110000101001110", 462 => "110000100101110",
463 => "110000100001101", 464 => "110000011101100", 465 => "110000011001011",
466 => "110000010101010", 467 => "110000010001001", 468 => "110000001101000",
469 => "110000001000111", 470 => "110000000100110", 471 => "110000000000101",
472 => "101111111100100", 473 => "101111111000010", 474 => "101111110100001",
475 => "101111110000000", 476 => "101111101011110", 477 => "101111100111101",
478 => "101111100011011", 479 => "101111011111001", 480 => "101111011010111",
481 => "101111010110110", 482 => "101111010010100", 483 => "101111001110010",
484 => "101111001010000", 485 => "101111000101110", 486 => "101111000001100",
487 => "101110111101010", 488 => "101110111001000", 489 => "101110110100101",
490 => "101110110000011", 491 => "101110101100001", 492 => "101110100111110",
493 => "101110100011100", 494 => "101110011111001", 495 => "101110011010111",
496 => "101110010110100", 497 => "101110010010001", 498 => "101110001101111",
499 => "101110001001100", 500 => "101110000101001", 501 => "101110000000110",
502 => "101101111100011", 503 => "101101111000000", 504 => "101101110011101",
505 => "101101101111010", 506 => "101101101010111", 507 => "101101100110011",
508 => "101101100010000", 509 => "101101011101101", 510 => "101101011001001",
511 => "101101010100110", 512 => "101101010000010", 513 => "101101001011111",
514 => "101101000111011", 515 => "101101000011000", 516 => "101100111110100",
517 => "101100111010000", 518 => "101100110101100", 519 => "101100110001000",
520 => "101100101100100", 521 => "101100101000000", 522 => "101100100011100",
523 => "101100011111000", 524 => "101100011010100", 525 => "101100010110000",
526 => "101100010001100", 527 => "101100001100111", 528 => "101100001000011",
529 => "101100000011110", 530 => "101011111111010", 531 => "101011111010101",
532 => "101011110110001", 533 => "101011110001100", 534 => "101011101100111",
535 => "101011101000011", 536 => "101011100011110", 537 => "101011011111001",
538 => "101011011010100", 539 => "101011010101111", 540 => "101011010001010",
541 => "101011001100101", 542 => "101011001000000", 543 => "101011000011011",
544 => "101010111110110", 545 => "101010111010000", 546 => "101010110101011",
547 => "101010110000110", 548 => "101010101100000", 549 => "101010100111011",
550 => "101010100010101", 551 => "101010011110000", 552 => "101010011001010",
553 => "101010010100100", 554 => "101010001111111", 555 => "101010001011001",
556 => "101010000110011", 557 => "101010000001101", 558 => "101001111100111",
559 => "101001111000001", 560 => "101001110011011", 561 => "101001101110101",
562 => "101001101001111", 563 => "101001100101001", 564 => "101001100000011",
565 => "101001011011100", 566 => "101001010110110", 567 => "101001010010000",
568 => "101001001101001", 569 => "101001001000011", 570 => "101001000011100",
571 => "101000111110101", 572 => "101000111001111", 573 => "101000110101000",
574 => "101000110000001", 575 => "101000101011011", 576 => "101000100110100",
577 => "101000100001101", 578 => "101000011100110", 579 => "101000010111111",
580 => "101000010011000", 581 => "101000001110001", 582 => "101000001001010",
583 => "101000000100011", 584 => "100111111111011", 585 => "100111111010100",
586 => "100111110101101", 587 => "100111110000101", 588 => "100111101011110",
589 => "100111100110111", 590 => "100111100001111", 591 => "100111011101000",
592 => "100111011000000", 593 => "100111010011000", 594 => "100111001110001",
595 => "100111001001001", 596 => "100111000100001", 597 => "100110111111001",
598 => "100110111010001", 599 => "100110110101001", 600 => "100110110000001",
601 => "100110101011001", 602 => "100110100110001", 603 => "100110100001001",
604 => "100110011100001", 605 => "100110010111001", 606 => "100110010010001",
607 => "100110001101000", 608 => "100110001000000", 609 => "100110000010111",
610 => "100101111101111", 611 => "100101111000111", 612 => "100101110011110",
613 => "100101101110101", 614 => "100101101001101", 615 => "100101100100100",
616 => "100101011111011", 617 => "100101011010011", 618 => "100101010101010",
619 => "100101010000001", 620 => "100101001011000", 621 => "100101000101111",
622 => "100101000000110", 623 => "100100111011101", 624 => "100100110110100",
625 => "100100110001011", 626 => "100100101100010", 627 => "100100100111001",
628 => "100100100001111", 629 => "100100011100110", 630 => "100100010111101",
631 => "100100010010011", 632 => "100100001101010", 633 => "100100001000000",
634 => "100100000010111", 635 => "100011111101101", 636 => "100011111000100",
637 => "100011110011010", 638 => "100011101110000", 639 => "100011101000111",
640 => "100011100011101", 641 => "100011011110011", 642 => "100011011001001",
643 => "100011010011111", 644 => "100011001110101", 645 => "100011001001011",
646 => "100011000100001", 647 => "100010111110111", 648 => "100010111001101",
649 => "100010110100011", 650 => "100010101111001", 651 => "100010101001111",
652 => "100010100100100", 653 => "100010011111010", 654 => "100010011010000",
655 => "100010010100101", 656 => "100010001111011", 657 => "100010001010000",
658 => "100010000100110", 659 => "100001111111011", 660 => "100001111010001",
661 => "100001110100110", 662 => "100001101111011", 663 => "100001101010001",
664 => "100001100100110", 665 => "100001011111011", 666 => "100001011010000",
667 => "100001010100101", 668 => "100001001111010", 669 => "100001001001111",
670 => "100001000100100", 671 => "100000111111001", 672 => "100000111001110",
673 => "100000110100011", 674 => "100000101111000", 675 => "100000101001101",
676 => "100000100100001", 677 => "100000011110110", 678 => "100000011001011",
679 => "100000010011111", 680 => "100000001110100", 681 => "100000001001000",
682 => "100000000011101", 683 => "011111111110001", 684 => "011111111000110",
685 => "011111110011010", 686 => "011111101101111", 687 => "011111101000011",
688 => "011111100010111", 689 => "011111011101100", 690 => "011111011000000",
691 => "011111010010100", 692 => "011111001101000", 693 => "011111000111100",
694 => "011111000010000", 695 => "011110111100100", 696 => "011110110111000",
697 => "011110110001100", 698 => "011110101100000", 699 => "011110100110100",
700 => "011110100001000", 701 => "011110011011100", 702 => "011110010101111",
703 => "011110010000011", 704 => "011110001010111", 705 => "011110000101010",
706 => "011101111111110", 707 => "011101111010010", 708 => "011101110100101",
709 => "011101101111001", 710 => "011101101001100", 711 => "011101100100000",
712 => "011101011110011", 713 => "011101011000110", 714 => "011101010011010",
715 => "011101001101101", 716 => "011101001000000", 717 => "011101000010011",
718 => "011100111100111", 719 => "011100110111010", 720 => "011100110001101",
721 => "011100101100000", 722 => "011100100110011", 723 => "011100100000110",
724 => "011100011011001", 725 => "011100010101100", 726 => "011100001111111",
727 => "011100001010010", 728 => "011100000100101", 729 => "011011111110111",
730 => "011011111001010", 731 => "011011110011101", 732 => "011011101110000",
733 => "011011101000010", 734 => "011011100010101", 735 => "011011011101000",
736 => "011011010111010", 737 => "011011010001101", 738 => "011011001011111",
739 => "011011000110010", 740 => "011011000000100", 741 => "011010111010111",
742 => "011010110101001", 743 => "011010101111011", 744 => "011010101001110",
745 => "011010100100000", 746 => "011010011110010", 747 => "011010011000100",
748 => "011010010010111", 749 => "011010001101001", 750 => "011010000111011",
751 => "011010000001101", 752 => "011001111011111", 753 => "011001110110001",
754 => "011001110000011", 755 => "011001101010101", 756 => "011001100100111",
757 => "011001011111001", 758 => "011001011001011", 759 => "011001010011101",
760 => "011001001101110", 761 => "011001001000000", 762 => "011001000010010",
763 => "011000111100100", 764 => "011000110110101", 765 => "011000110000111",
766 => "011000101011001", 767 => "011000100101010", 768 => "011000011111100",
769 => "011000011001101", 770 => "011000010011111", 771 => "011000001110000",
772 => "011000001000010", 773 => "011000000010011", 774 => "010111111100101",
775 => "010111110110110", 776 => "010111110000111", 777 => "010111101011001",
778 => "010111100101010", 779 => "010111011111011", 780 => "010111011001100",
781 => "010111010011110", 782 => "010111001101111", 783 => "010111001000000",
784 => "010111000010001", 785 => "010110111100010", 786 => "010110110110011",
787 => "010110110000100", 788 => "010110101010101", 789 => "010110100100110",
790 => "010110011110111", 791 => "010110011001000", 792 => "010110010011001",
793 => "010110001101010", 794 => "010110000111011", 795 => "010110000001100",
796 => "010101111011100", 797 => "010101110101101", 798 => "010101101111110",
799 => "010101101001111", 800 => "010101100011111", 801 => "010101011110000",
802 => "010101011000001", 803 => "010101010010001", 804 => "010101001100010",
805 => "010101000110010", 806 => "010101000000011", 807 => "010100111010011",
808 => "010100110100100", 809 => "010100101110100", 810 => "010100101000101",
811 => "010100100010101", 812 => "010100011100101", 813 => "010100010110110",
814 => "010100010000110", 815 => "010100001010110", 816 => "010100000100111",
817 => "010011111110111", 818 => "010011111000111", 819 => "010011110010111",
820 => "010011101101000", 821 => "010011100111000", 822 => "010011100001000",
823 => "010011011011000", 824 => "010011010101000", 825 => "010011001111000",
826 => "010011001001000", 827 => "010011000011000", 828 => "010010111101000",
829 => "010010110111000", 830 => "010010110001000", 831 => "010010101011000",
832 => "010010100101000", 833 => "010010011111000", 834 => "010010011001000",
835 => "010010010011000", 836 => "010010001100111", 837 => "010010000110111",
838 => "010010000000111", 839 => "010001111010111", 840 => "010001110100111",
841 => "010001101110110", 842 => "010001101000110", 843 => "010001100010110",
844 => "010001011100101", 845 => "010001010110101", 846 => "010001010000100",
847 => "010001001010100", 848 => "010001000100100", 849 => "010000111110011",
850 => "010000111000011", 851 => "010000110010010", 852 => "010000101100010",
853 => "010000100110001", 854 => "010000100000001", 855 => "010000011010000",
856 => "010000010011111", 857 => "010000001101111", 858 => "010000000111110",
859 => "010000000001110", 860 => "001111111011101", 861 => "001111110101100",
862 => "001111101111011", 863 => "001111101001011", 864 => "001111100011010",
865 => "001111011101001", 866 => "001111010111000", 867 => "001111010001000",
868 => "001111001010111", 869 => "001111000100110", 870 => "001110111110101",
871 => "001110111000100", 872 => "001110110010011", 873 => "001110101100010",
874 => "001110100110001", 875 => "001110100000001", 876 => "001110011010000",
877 => "001110010011111", 878 => "001110001101110", 879 => "001110000111101",
880 => "001110000001100", 881 => "001101111011010", 882 => "001101110101001",
883 => "001101101111000", 884 => "001101101000111", 885 => "001101100010110",
886 => "001101011100101", 887 => "001101010110100", 888 => "001101010000011",
889 => "001101001010001", 890 => "001101000100000", 891 => "001100111101111",
892 => "001100110111110", 893 => "001100110001101", 894 => "001100101011011",
895 => "001100100101010", 896 => "001100011111001", 897 => "001100011000111",
898 => "001100010010110", 899 => "001100001100101", 900 => "001100000110011",
901 => "001100000000010", 902 => "001011111010001", 903 => "001011110011111",
904 => "001011101101110", 905 => "001011100111100", 906 => "001011100001011",
907 => "001011011011010", 908 => "001011010101000", 909 => "001011001110111",
910 => "001011001000101", 911 => "001011000010100", 912 => "001010111100010",
913 => "001010110110001", 914 => "001010101111111", 915 => "001010101001101",
916 => "001010100011100", 917 => "001010011101010", 918 => "001010010111001",
919 => "001010010000111", 920 => "001010001010101", 921 => "001010000100100",
922 => "001001111110010", 923 => "001001111000001", 924 => "001001110001111",
925 => "001001101011101", 926 => "001001100101011", 927 => "001001011111010",
928 => "001001011001000", 929 => "001001010010110", 930 => "001001001100101",
931 => "001001000110011", 932 => "001001000000001", 933 => "001000111001111",
934 => "001000110011110", 935 => "001000101101100", 936 => "001000100111010",
937 => "001000100001000", 938 => "001000011010110", 939 => "001000010100100",
940 => "001000001110011", 941 => "001000001000001", 942 => "001000000001111",
943 => "000111111011101", 944 => "000111110101011", 945 => "000111101111001",
946 => "000111101000111", 947 => "000111100010101", 948 => "000111011100100",
949 => "000111010110010", 950 => "000111010000000", 951 => "000111001001110",
952 => "000111000011100", 953 => "000110111101010", 954 => "000110110111000",
955 => "000110110000110", 956 => "000110101010100", 957 => "000110100100010",
958 => "000110011110000", 959 => "000110010111110", 960 => "000110010001100",
961 => "000110001011010", 962 => "000110000101000", 963 => "000101111110110",
964 => "000101111000100", 965 => "000101110010010", 966 => "000101101100000",
967 => "000101100101101", 968 => "000101011111011", 969 => "000101011001001",
970 => "000101010010111", 971 => "000101001100101", 972 => "000101000110011",
973 => "000101000000001", 974 => "000100111001111", 975 => "000100110011101",
976 => "000100101101011", 977 => "000100100111000", 978 => "000100100000110",
979 => "000100011010100", 980 => "000100010100010", 981 => "000100001110000",
982 => "000100000111110", 983 => "000100000001100", 984 => "000011111011001",
985 => "000011110100111", 986 => "000011101110101", 987 => "000011101000011",
988 => "000011100010001", 989 => "000011011011110", 990 => "000011010101100",
991 => "000011001111010", 992 => "000011001001000", 993 => "000011000010110",
994 => "000010111100011", 995 => "000010110110001", 996 => "000010101111111",
997 => "000010101001101", 998 => "000010100011011", 999 => "000010011101000",
1000 => "000010010110110", 1001 => "000010010000100", 1002 => "000010001010010",
1003 => "000010000011111", 1004 => "000001111101101", 1005 => "000001110111011",
1006 => "000001110001001", 1007 => "000001101010110", 1008 => "000001100100100",
1009 => "000001011110010", 1010 => "000001011000000", 1011 => "000001010001101",
1012 => "000001001011011", 1013 => "000001000101001", 1014 => "000000111110111",
1015 => "000000111000100", 1016 => "000000110010010", 1017 => "000000101100000",
1018 => "000000100101110", 1019 => "000000011111011", 1020 => "000000011001001",
1021 => "000000010010111", 1022 => "000000001100101", 1023 => "000000000110010" );
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity qam_dem_top_mounstrito_cos_lut is
generic (
DataWidth : INTEGER := 15;
AddressRange : INTEGER := 1024;
AddressWidth : INTEGER := 10);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of qam_dem_top_mounstrito_cos_lut is
component qam_dem_top_mounstrito_cos_lut_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
qam_dem_top_mounstrito_cos_lut_rom_U : component qam_dem_top_mounstrito_cos_lut_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
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