content stringlengths 1 1.04M ⌀ |
|---|
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
sig <= 1;
wait for 1 fs;
assert sig = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
r: proc... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
use work.router_pack.all;
entity router_credit_based is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/13/2015 12:36:25 PM
-- Design Name:
-- Module Name: RegisterExtended16Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:06 01/18/2014
-- Design Name:
-- Module Name: adau1761_izedboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:06 01/18/2014
-- Design Name:
-- Module Name: adau1761_izedboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
entity tb_memmux07 is
end tb_memmux07;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux07 is
signal ad : std_logic;
signal val : std_logic_vector (1 downto 0);
signal dat, res : std_logic_vector (7 downto 0);
begin
dut : entity work.memmux07
port map (
... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_hor_vert.vhd,v 1.11 2006/06/18 10:47:01 arnim Exp $
--
-- Horizontal / Vertical Timing Generator
--
---------------------------------------------------... |
--
-- mxseq.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A
-- Author: Stephen A. Rodgers
--
-- Copyright (c) 2004,2005 Stephen A. Rodgers
--
-- Steve Rodgers <hwstar@rodgers.sdcoxmail.com>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end comparator;
architecture compare of comparator is
begin
--could be alternatived by MUX statements...3 lines... |
entity repro_rec is
end;
architecture behav of repro_rec is
type my_rec is record
s : natural;
b : bit_vector;
c : bit_vector;
end record;
subtype my_rec1 is my_rec (c (2 to 3));
signal r : my_rec1 (b (1 to 3));
signal a : bit_vector (0 to 1);
begin
process
begin
r.s <= 1;
r.b <= ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.CommonFunctions.all;
entity ClockGeneratorTB is
end entity; --ClockGenerator
architecture tb of ClockGeneratorTB is
constant G_CLOCK_FREQUE... |
-- This is the top-level of the fp68040 design, instantiating
-- all top IP blocks, connecting things to external FPGA pins
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-------------------------------------------------------------------------------
-- Title : TKT-1212, Exercise 03
-- Project :
-------------------------------------------------------------------------------
-- File : tb_adder.vhd
-- Author : Antti Rasmus
-- Company : TUT/DCS
-- Created : 2008-11... |
library ieee;
use ieee.std_logic_1164.all;
-- COMPONENT
entity a is
-- N_BITS_DATA is nowhere initialized. This problem should be catched during
-- elaboration but it isn't !
-- During simulation I found that the value of N_BITS_DATA is -2147483648 and
-- that the value of N_BITS_DATA-1 is 2147483647 !!!!
... |
library ieee;
use ieee.std_logic_1164.all;
-- COMPONENT
entity a is
-- N_BITS_DATA is nowhere initialized. This problem should be catched during
-- elaboration but it isn't !
-- During simulation I found that the value of N_BITS_DATA is -2147483648 and
-- that the value of N_BITS_DATA-1 is 2147483647 !!!!
... |
library ieee;
use ieee.std_logic_1164.all;
-- COMPONENT
entity a is
-- N_BITS_DATA is nowhere initialized. This problem should be catched during
-- elaboration but it isn't !
-- During simulation I found that the value of N_BITS_DATA is -2147483648 and
-- that the value of N_BITS_DATA-1 is 2147483647 !!!!
... |
-------------------------------------------------------------------------------
-- file: SEVEN_SEG.vhd
-- author: Rene Herthel <rene.herthel@haw-hamburg.de>
-- author: Hauke Sondermann <hauke.sondermann@haw-hamburg.de>
-------------------------------------------------------------------------------
library IEEE;
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_2_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
library ieee;
use ieee.std_logic_1164.all;
entity plong is
port (
clk, not_reset: in std_logic;
nes_data_1: in std_logic;
nes_data_2: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0);
speaker: out std_logic;
nes_clk_out: ... |
-----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
--------------... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:40:19 10/22/2015
-- Design Name:
-- Module Name: C:/Users/Colton/Nibble_Knowledge_CPU/tb_register16.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
port(
i_port1 : in std_logic;
i_port2 : in std_logic
);
end entit... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2007 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2007 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
----------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.std_logic_1164.all;
package Examples is
component Blinking is
generic (
FREQ : positive:=25e6;
SECS : positive:=1
);
port (
clk_i : in std_logic;
led_o : out std_logic
);
end component Blinking;
end package Examples;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:10:08 11/21/2012
-- Design Name:
-- Module Name: ExtensorSigno - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:10:08 11/21/2012
-- Design Name:
-- Module Name: ExtensorSigno - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... |
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity case03 is
port (a : std_logic_vector (4 downto 0);
o : out std_logic);
end case03;
architecture behav of case03 is
begin
with a select o <=
'0' when others;
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- simple mulitplexer module
-- based on labs from Altera
-- ftp://ftp.altera.com/up/pub/Altera_Material/11.1/Laboratory_Exercises/Digital_Logic/DE1/vhdl/lab1_VHDL.pdf
ENTITY testsig2 IS
PORT (
M: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END testsig2;
ARCHITECTURE Behavior... |
-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration
ENTITY not found IS
PORT (
P7 : in Std_Logic;
P6 : in Std_Logic;
P5 : in Std_Logic;
P4 : in Std_Logic;
P2 : in Std_Logic;
P1 : in Std_Logic;
... |
-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration
ENTITY not found IS
PORT (
P7 : in Std_Logic;
P6 : in Std_Logic;
P5 : in Std_Logic;
P4 : in Std_Logic;
P2 : in Std_Logic;
P1 : in Std_Logic;
... |
-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration
ENTITY not found IS
PORT (
P7 : in Std_Logic;
P6 : in Std_Logic;
P5 : in Std_Logic;
P4 : in Std_Logic;
P2 : in Std_Logic;
P1 : in Std_Logic;
... |
-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration
ENTITY not found IS
PORT (
P7 : in Std_Logic;
P6 : in Std_Logic;
P5 : in Std_Logic;
P4 : in Std_Logic;
P2 : in Std_Logic;
P1 : in Std_Logic;
... |
-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration
ENTITY not found IS
PORT (
P7 : in Std_Logic;
P6 : in Std_Logic;
P5 : in Std_Logic;
P4 : in Std_Logic;
P2 : in Std_Logic;
P1 : in Std_Logic;
... |
-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration
ENTITY not found IS
PORT (
P7 : in Std_Logic;
P6 : in Std_Logic;
P5 : in Std_Logic;
P4 : in Std_Logic;
P2 : in Std_Logic;
P1 : in Std_Logic;
... |
-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration
ENTITY not found IS
PORT (
P7 : in Std_Logic;
P6 : in Std_Logic;
P5 : in Std_Logic;
P4 : in Std_Logic;
P2 : in Std_Logic;
P1 : in Std_Logic;
... |
--Propery of Tecphos Inc. See License.txt for license details
--Latest version of all project files available at http://opencores.org/project,wrimm
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
library ieee;
use ieee.std_logic_1164.a... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Full2Lite Core's Read Controller. Please refer to the documentation
--! in plasoc_axi4_full2lite.vhd for more information.
--------------------... |
---A bulky Synchronous Fsm that scans the whole map and places the numbers around the mines
--- its divided in 9 state chains based on the position type of the tile.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Initialize is
port( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Ran... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_scaler IS
END tb_scaler;
ARCHITECTURE behavior OF tb_scaler IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pixel_scaling
PORT(
x_pixel : IN std_logic_vector(10 downto 0);
y_pixel ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:03 11/21/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:03 11/21/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00288
--
-- AUTHOR:
--
-- A. Wilm... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_jed is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_jed;
architecture behaviour of shiftreg_jed is
constant st0: std_logic_vector(2 do... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity c2n_playback_io is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
p... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
package pack is
type rec is record
x : integer;
y : integer;
z : boolean;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( r : rec );
port (
i : in bit_vector(1 to r.y);
... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'succ(1) = 2 report "TEST FAILED. succ 1 = 2" severity FAILURE;
report "TEST PASSED succ 1 = 2" severity NOTE;
assert small'succ(2) = 3 report "TEST FAILED. succ 2 = 3" ... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'succ(1) = 2 report "TEST FAILED. succ 1 = 2" severity FAILURE;
report "TEST PASSED succ 1 = 2" severity NOTE;
assert small'succ(2) = 3 report "TEST FAILED. succ 2 = 3" ... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'succ(1) = 2 report "TEST FAILED. succ 1 = 2" severity FAILURE;
report "TEST PASSED succ 1 = 2" severity NOTE;
assert small'succ(2) = 3 report "TEST FAILED. succ 2 = 3" ... |
-------------------------------------------------------------------------------
--
-- The clock generation unit.
-- PHI1 clock and input/output clock enables are generated here.
--
-- $Id: t400_clkgen-c.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- A... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_223 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_223;
architecture augh of mul_223 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_223 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_223;
architecture augh of mul_223 is
signal tmp_res : signed(... |
-------------------------------------------------------------------------------
--
-- File: InputBuffer.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 201... |
-------------------------------------------------------------------------------
-- system_push_buttons_4bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use ... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
SIlibrary IEEE;
use IEEE.std_logic_1164.all;
entity SIPO_shiftReg is
port (clock, reset, enable : in std_logic;
input_data : in std_logic;
saida : out std_logic_vector(7 downto 0):= (others => '1'));
end SIPO_shiftReg;
architecture behavioral of SIPO_shiftReg is
signal IQ: std_logic_vector(7 do... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Decoder reads the instruction from RAM and outputs
-- the datapath control signals for executing that
-- instruction
entity decoder is
Port ( instr : in STD_LOGIC_VECTOR(7 downto 0);
d_alutoreg : out STD_LOGIC;
d_alua : out STD_LOGIC_VECTOR(1 do... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, syn... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, syn... |
-- Author: Zander Blasingame
-- Class: EE 316 Spring 2017
-- Description: Seven Segment Display driver
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity seven_seg_driver is
port(
data : in std_logic_vector(15 downto 0);
address : in std_logic_vector(7 downto ... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:44:45 2019
-- Host : varun-laptop running 64-bit Service ... |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_col_mux.vhd,v 1.10 2006/06/18 10:47:01 arnim Exp $
--
-- Color Information Multiplexer
--
---------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
generic(K : natural := 2);
port (clkIn : in std_logic;
clkOut: out std_logic);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : natural;
constant halfWay : natural := K/2-1;
begin
process(... |
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