content stringlengths 1 1.04M ⌀ |
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-- $Header: /syn/cvs/rcs/compilers/vhdl/vhd/synattr.vhd,v 1.90.2.14.2.1 2003/07/08 18:06:01 akapoor Exp $
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997-2003 by Synplicity, Inc. All rig... |
-- $Header: /syn/cvs/rcs/compilers/vhdl/vhd/synattr.vhd,v 1.90.2.14.2.1 2003/07/08 18:06:01 akapoor Exp $
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997-2003 by Synplicity, Inc. All rig... |
-- $Header: /syn/cvs/rcs/compilers/vhdl/vhd/synattr.vhd,v 1.90.2.14.2.1 2003/07/08 18:06:01 akapoor Exp $
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997-2003 by Synplicity, Inc. All rig... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity AddSub4 is
port( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
sub: in std_logic;
s : out std_logic_vector(3 downto 0);
cout: out std_logic);
end AddSub4;
architecture Structural2 of AddSub4 is
signal b2... |
-- Define enumerated types for all game objects (bitmaps, sprites, collisions,
-- and NPCs). With these types, it is easy to reference any game object by name.
-- We can't simply create a constant for each object because we want to
package resource_handles_pkg is
-- Enumerated type used for referencing all bi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Processor is
Port ( rst : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC);
end Processor;
architecture Behavioral of Processor is
signal out_nPC: STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
signal data_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: I2C Bus
--
-- Authors: Patrick Lehmann
--
-- Descriptio... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
--use work.slot_bus_master_bfm_pkg.all;
entity harness_reu is
end harness_reu;
architecture harness of harness_reu is
signal clock : st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
--use work.slot_bus_master_bfm_pkg.all;
entity harness_reu is
end harness_reu;
architecture harness of harness_reu is
signal clock : st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
--use work.slot_bus_master_bfm_pkg.all;
entity harness_reu is
end harness_reu;
architecture harness of harness_reu is
signal clock : st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
--use work.slot_bus_master_bfm_pkg.all;
entity harness_reu is
end harness_reu;
architecture harness of harness_reu is
signal clock : st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
--use work.slot_bus_master_bfm_pkg.all;
entity harness_reu is
end harness_reu;
architecture harness of harness_reu is
signal clock : st... |
-- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 1 of the kernel
-- Request contents of current queue at address (cq_address + kernel_id + offset)
-- NOTE: we can get rid of this process
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
librar... |
-- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 1 of the kernel
-- Request contents of current queue at address (cq_address + kernel_id + offset)
-- NOTE: we can get rid of this process
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
librar... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split2 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split2 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pseudo_dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" --... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pseudo_dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" --... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pseudo_dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" --... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pseudo_dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" --... |
--------------------------------------------------------------------------------
--
-- Title : ctrl_rounds_rom
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Description : ROM generator for new rounds
--
-- Rules for ROM generator:
-- 1) 0-6 - number of mines, 7 - a mine; 8-9 - ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without war... |
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without war... |
---------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without war... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:48 05/28/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_clock_divider.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Des... |
library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- SHOT CONTROLLING ENTITY
--------------------------------------------------------------------------------
entity shot is
generic
(
res_x ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
entity tb_testcase is
end tb_testcase;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_testcase is
signal di : std_logic;
signal do : std_logic;
begin
dut: entity work.testcase
port map (data_in => di, data_out => do);
process
begin
di <= '1';
wait for 1 ns;
assert do = ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
entity signal9 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of signal9 is
signal vec : std_logic_vector(7 downto 0);
begin
assign_p: vec <= X"52";
count_p: process is
variable ctr : unsigned(7 downto 0) := X"00";
begin
wait for... |
entity signal9 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of signal9 is
signal vec : std_logic_vector(7 downto 0);
begin
assign_p: vec <= X"52";
count_p: process is
variable ctr : unsigned(7 downto 0) := X"00";
begin
wait for... |
entity signal9 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of signal9 is
signal vec : std_logic_vector(7 downto 0);
begin
assign_p: vec <= X"52";
count_p: process is
variable ctr : unsigned(7 downto 0) := X"00";
begin
wait for... |
entity signal9 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of signal9 is
signal vec : std_logic_vector(7 downto 0);
begin
assign_p: vec <= X"52";
count_p: process is
variable ctr : unsigned(7 downto 0) := X"00";
begin
wait for... |
entity signal9 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of signal9 is
signal vec : std_logic_vector(7 downto 0);
begin
assign_p: vec <= X"52";
count_p: process is
variable ctr : unsigned(7 downto 0) := X"00";
begin
wait for... |
-------------------------------------------------------------------------------
-- Simple interface to the maxfinder module
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with thi... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_core is
generic(
first_address : integer := 0;
last_address : integer := 0;
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
mem_init0 ... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_core is
generic(
first_address : integer := 0;
last_address : integer := 0;
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
mem_init0 ... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_core is
generic(
first_address : integer := 0;
last_address : integer := 0;
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
mem_init0 ... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_core is
generic(
first_address : integer := 0;
last_address : integer := 0;
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
mem_init0 ... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_core is
generic(
first_address : integer := 0;
last_address : integer := 0;
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
mem_init0 ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin7Seg is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0));
end Bin7Seg;
architecture Behavioral of Bin7Seg is
begin
decOut_n <= "1111001" when binInput="0001" else --1
"0100100" when ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin7Seg is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0));
end Bin7Seg;
architecture Behavioral of Bin7Seg is
begin
decOut_n <= "1111001" when binInput="0001" else --1
"0100100" when ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
use ieee.std_logic_1164.all;
use My_Lib, OtherLib.my_math_stuff.multiply;
use YetAnotherLib.std_logic;
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont255_V3.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms ... |
----------------------------------------------------------------------------------------------------
-- Pulse Extender Test-bench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
----------------------------------------... |
--------------------------------------------------------------------------------
-- Copyright 2014 Madhu Siddalingaiah
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://ww... |
library verilog;
use verilog.vl_types.all;
entity EightBitAdder_vlg_sample_tst is
port(
A : in vl_logic_vector(7 downto 0);
B : in vl_logic_vector(7 downto 0);
sampler_tx : out vl_logic
);
end EightBitAdder_vlg_sample_tst;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international... |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- $Id: artys7lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: artys7lib
-- Description: Digilent Arty S7 c... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_193 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_193;
architecture augh of cmp_193 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_193 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_193;
architecture augh of cmp_193 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
entity textio3 is
end entity;
use std.textio.all;
architecture test of textio3 is
procedure check_content(expect : in string) is
file tmp : text is "tmp.txt";
variable l : line;
variable str : string(1 to expect'length);
variable good : boolean;
variable ch : ch... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
library verilog;
use verilog.vl_types.all;
entity clock_second_vlg_check_tst is
port(
second : in vl_logic;
sampler_rx : in vl_logic
);
end clock_second_vlg_check_tst;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-------------------------------------------------------------------------------
-- Title : Simple testbench for the audio synthesizer.
-- Note! No automatic checking!
-- You must "manually" check the waveforms, which is not nice.
-- Project :
------------------------------------------... |
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
sig <= 1;
wait for 1 fs;
assert sig = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
r: proc... |
entity test_bench is
end test_bench;
architecture only of test_bench is
signal sig : integer := 0;
begin -- only
p: process
begin -- process p
sig <= 1;
wait for 1 fs;
assert sig = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
r: proc... |
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