content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
generic(K : natural := 2);
port (clkIn : in std_logic;
clkOut: out std_logic);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : natural;
constant halfWay : natural := K/2-1;
begin
process(... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
generic(K : natural := 2);
port (clkIn : in std_logic;
clkOut: out std_logic);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : natural;
constant halfWay : natural := K/2-1;
begin
process(... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
generic(K : natural := 2);
port (clkIn : in std_logic;
clkOut: out std_logic);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : natural;
constant halfWay : natural := K/2-1;
begin
process(... |
-- NEED RESULT: ARCH00048.P1: Implicit array subtype conversion occurs for slices passed
-- NEED RESULT: ARCH00048.P2: Implicit array subtype conversion occurs for slices passed
-- NEED RESULT: ARCH00048.P3: Implicit array subtype conversion occurs for slices passed
-- NEED RESULT: ARCH00048.P4: Implicit array subty... |
package gen is
generic (type t);
end gen;
entity e is
end entity;
architecture a of e is
subtype T_DATA is bit_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
package pkg is new work.gen generic map (t => t_data_vector (31 downto 0));
begin
end architecture;
|
package gen is
generic (type t);
end gen;
entity e is
end entity;
architecture a of e is
subtype T_DATA is bit_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
package pkg is new work.gen generic map (t => t_data_vector (31 downto 0));
begin
end architecture;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: VideoPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ==============================... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity nonconst1 is
end entity;
architecture test of nonconst1 is
type int_vec is array (natural range <>) of integer;
signal s, t : int_vec(8 downto 0);
begin
process is
variable k : integer;
begin
k := 9;
wait for 1 ns;
s(k downto 1) <= (others => 1);
t(8 d... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PC is
port(
clk : in std_logic;
reset_n : in std_logic;
en : in std_logic;
sel_a : in std_logic;
sel_imm : in std_logic;
add_imm : in std_logic;
imm : in ... |
package sample_pkg is
constant SAMPLE_CONSTANT : integer;
end sample_pkg;
package body sample_pkg is
constant SAMPLE_CONSTANT : integer := 160;
end sample_pkg;
|
-------------------------------------------------------------------------------
-- Title : A Register File Made of Dual Port Block RAM
-------------------------------------------------------------------------------
-- Platform : Xilinx Spartan 3A
-- Standard : VHDL'87
------------------------------------------... |
architecture RTL of FIFO is
signal sig1 : std_logic;
signal sig2 : std_logic;
-- Violations below
signal sig1 :std_logic;
signal sig2 : std_logic;
begin
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 02:01:44 PM
-- Design Name:
-- Module Name: game_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------
-- Entity implementing shiftrow operation.
-- amount<0> controls rotation by one byte to the left
-- amount<1> controls rotation by two bytes
-- Input size configurable through ge... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------
-- Entity implementing shiftrow operation.
-- amount<0> controls rotation by one byte to the left
-- amount<1> controls rotation by two bytes
-- Input size configurable through ge... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
-- Copyright (c) 2015 CERN
-- @author Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity register_file is
port (clk : in std_logic;
rst : in std_logic;
a1 : in std_logic_vector(4 downto 0);
a2 : in std_logic_vector(4 do... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library ... |
-------------------------------------------------------------------------------
-- system_dlmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b... |
-------------------------------------------------------------------------------
-- system_dlmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b... |
entity signal2 is
end entity;
architecture test of signal2 is
signal x : bit := '0';
begin
process is
begin
assert x'event;
assert x'active;
wait;
end process;
end architecture;
|
entity signal2 is
end entity;
architecture test of signal2 is
signal x : bit := '0';
begin
process is
begin
assert x'event;
assert x'active;
wait;
end process;
end architecture;
|
entity signal2 is
end entity;
architecture test of signal2 is
signal x : bit := '0';
begin
process is
begin
assert x'event;
assert x'active;
wait;
end process;
end architecture;
|
entity signal2 is
end entity;
architecture test of signal2 is
signal x : bit := '0';
begin
process is
begin
assert x'event;
assert x'active;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity axi_dynclk is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Sl... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:44 01/07/2014
-- Design Name:
-- Module Name: G:/Project_Block_Mario/TestBench_MMU.vhd
-- Project Name: Block_Mario
-- Target Device:
-- Tool versions:
-- Description... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : entity fifo_dsn.INST1(rtl);
U_INST2 : component INST2
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
);
U_INST3 : INST3
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
POR... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the ... |
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://gith... |
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://gith... |
entity err is
end;
architecture behav of err is
signal t2 : bit;
begin
t0 <= '1';
end behav;
|
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_4.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernbe... |
-- Elementos suplementarios para CORDIC
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cordic_lib is
---constant N_PF : natural := 32;
---constant N_BITS_DIR : natural := 10;
constant N_BITS : natural := 16;
constant N_EXTR : natural := N_BITS + 2; -- Precisión... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_527 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_527;
architecture augh of mul_527 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_527 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_527;
architecture augh of mul_527 is
signal tmp_res : signed(... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ==============================================... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Wed May 03 18:16:24 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major... |
-- These are core Lava built-in functions Lava programs can rely on having
-- Todo: Consider prepending lava_ to the names.
-- These are core Lava built-in functions Lava programs can rely on having
-- Todo: Consider prepending lava_ to the names. ... |
entity operator2 is
end entity;
architecture test of operator2 is
type t is (A, B);
type tv is array (integer range <>) of t;
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
function "and"... |
entity operator2 is
end entity;
architecture test of operator2 is
type t is (A, B);
type tv is array (integer range <>) of t;
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
function "and"... |
entity operator2 is
end entity;
architecture test of operator2 is
type t is (A, B);
type tv is array (integer range <>) of t;
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
function "and"... |
entity operator2 is
end entity;
architecture test of operator2 is
type t is (A, B);
type tv is array (integer range <>) of t;
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
function "and"... |
entity operator2 is
end entity;
architecture test of operator2 is
type t is (A, B);
type tv is array (integer range <>) of t;
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
function "and"... |
-- $Id: iob_reg_io_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_io_gen - syn
-- Description: Re... |
library ieee;
use ieee.std_logic_1164.all;
entity test_entity is
generic(
DO_GEN : boolean := false
);
port(
val_out : out std_logic
);
end test_entity;
architecture rtl of test_entity is
begin
set_val_1: if DO_GEN generate
val_out <= '1';
end generate;
set... |
---------------------------------------------------------------------
-- LXP32 instruction cache verification environment (self-checking
-- testbench)
--
-- Part of the LXP32 instruction cache testbench
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Parameters:
-- CACHE_BURST_SIZE: burst size for cache uni... |
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
clk : in std_logic;
d : in std_logic ;
q :out std_logic );
end test;
architecture rtl of test is
begin
process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1 is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1;
architecture behaviour of mark1 is
type state is (state1, state2, state3, state4, state5, ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use WORK.constants.all;
entity WRF is
generic (
NBIT: integer;
M: integer;
F: integer;
N: integer;
NREG: integer;
LOGNREG: integer;
LOGN: integer
);
port (
CLK: IN std_logic;
RESET: ... |
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity and_gate is
--generic declarations
port (
a: in bit ;
b: in bit ;
x: out bit);
end entity;
------------------------------
architecture circuit of and_gate is
--signals and declarat... |
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0... |
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0... |
-------------------------------------------------------------------------------
--
-- Testbench for interrupt evaluation.
--
-- $Id: tb_int.vhd,v 1.5 2006-06-05 18:50:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthe... |
architecture RTL of FIFO is
begin
for_label : for i in 0 to 7 generate
end generate;
if_label : if a = '1' generate
end generate;
case_label : case data generate
end generate;
-- Violations below
for_label : for i in 0 to 7 generate
end generate;
if_label : if a = '1' generate
end gen... |
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
postponed wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
wr_en(a, b);
end process;
-- Violations below
procedure_call_label : postponed wr_en(a, b);
procedur... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revi... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
configuration CFG of FIFO is
group group1_identifier : group1_template_name ( group_constituent1 );
group group2_identifier : group2_template_name ( group_constituent1, group_constintuent2 );
end configuration CFG;
|
architecture RTL of FIFO is
begin
process
begin
FOR_LABEL : for index in 4 to 23 loop
end loop;
FOR_LABEL : for index in 4 to 23 loop
end loop;
For_label : for index in 4 to 23 loop
end loop;
end process;
end;
|
--
-- Asymmetric port RAM
-- Port A is 256x8-bit read-and-write (write-first synchronization)
-- Port B is 64x32-bit read-and-write (write-first synchronization)
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/asymmetric_ram_2a.vhd
--
library ieee;
... |
---------------------------------------
-- Company:
-- Engineer: Alexander Geißler
--
-- Create Date: 23:40:00 02/26/2015
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 14.0
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- controller takes an error signal and uses that to modify an input
-- complex stream to produce an output complex stream.
entity controller is
port (
clk: in std_logic;
reset: in std_logic;
clear: in std_logic;
i_erro... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
-------------------------------------------------------------------------------------
-- FILE NAME : testbench_template.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - testbench_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
----------------------... |
-------------------------------------------------------------------------------
-- axi_cdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity distance2 is
generic (
COMPLEX_HALF_WIDTH: positive
);
port (
clk: in std_logic;
reset: in std_logic;
i_tvalid: in std_logic;
i_tdata: in std_logic_vector(4*COMPLEX_HALF_WIDTH-1 downto 0);
i_tlast: in std_logic... |
library ieee;
use ieee.std_logic_1164.all;
entity cont_bcd_tb is
end;
architecture cont_bcd_tb_func of cont_bcd_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component ... |
library ieee;
use ieee.std_logic_1164.all;
entity cont_bcd_tb is
end;
architecture cont_bcd_tb_func of cont_bcd_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component ... |
--------------------------------------------------------------------------------
-- FILE: Mul
-- DESC: Multiplier
--
-- Author:
-- Create: 2015-08-14
-- Update: 2015-08-14
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use i... |
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