content stringlengths 1 1.04M ⌀ |
|---|
--
-- Simul testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use STD.textio.all;
library FPGALIB;
use FPGALIB.Simul.all;
entity Simul_tb is
end en... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: minimal FIFO, common clock (cc),
-- pipeline... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: minimal FIFO, common clock (cc),
-- pipeline... |
library ieee;
use ieee.std_logic_1164.all;
entity Systolic_Array_Matrix_Multiplication is
end Systolic_Array_Matrix_Multiplication;
architecture Systolic_Array_Matrix_Multiplication_arch of Systolic_Array_Matrix_Multiplication is
begin
end Systolic_Array_Matrix_Multiplication_arch; |
--
-- Grain datapath, slow and small implementation
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain_datapath_slow is
generic (
DEBUG : boolean := false -- output debug information
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00570: Attribute declarations - composite generic subtypes with composite initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------------... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block2.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ------------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 10:10:04 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 14;
type lut_type is arr... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 14;
type lut_type is arr... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
CONFIGURATION lab10_WriteBack_Stage_struct_config OF lab10_WriteBack_Stage IS
FOR struct
END FOR;
END lab10_WriteBack_Stage_struct_config; |
library ieee;
use ieee.std_logic_1164.all;
entity concat01 is
port (a, b : in std_logic;
z : out std_logic_vector(1 downto 0));
end concat01;
architecture behav of concat01 is
begin
z <= a & b;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_183 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_183;
architecture augh of cmp_183 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_183 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_183;
architecture augh of cmp_183 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : L I K E L I H O O D
--
--
-- One observation and the reference da... |
library ieee;
use ieee.std_logic_1164.all;
ENTITY logical IS
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
B: IN std_logic_VECTOR(width-1 downto 0);
OP: IN std_logic_vector( 1 downto 0);
S: OUT std_logic_VECTOR(width-1 downto 0)
);
END logical;
ARCHITECTURE b... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DISP8 is
port (anode: out std_logic_vector(8 downto 0);
cathode: out std_logic_vector(7 downto 0);
data1: in std_logic_vector(7 downto 0); --PA
data2: in std_logic_vector(7 downto 0); --PA
addr: in std_logic_vector(15 downto 0); --PA
cl... |
-- NEED RESULT: ARCH00339.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00339.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00339.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: A... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Tue Jun 21 04:37:54 2016
-- Host : jalapeno running 64-bit unknown
-- C... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity prewitt_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_... |
architecture rtl of fifo is
begin
procedure_call(first, second(2),
third(func_call(4, 5, 6)), fourth(7),
fifth(8));
bare_procedure_call;
process begin
procedure_call(first, second(2),
third(func_call(4, 5, 6)), fourth(7),
fifth(8));... |
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal ... |
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal ... |
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal ... |
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal ... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
-------------------------------------------------------------------------------
-- Title : Instruction recording
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : instruction_record.vhd
-- Au... |
entity signal10 is
end entity;
architecture test of signal10 is
signal x, y, z : bit;
signal u : bit_vector(1 to 3);
signal v : bit_vector(2 downto 0);
begin
process is
begin
(x, y, z) <= bit_vector'("011");
wait for 1 ns;
assert x = '0';
assert y = '1';... |
entity signal10 is
end entity;
architecture test of signal10 is
signal x, y, z : bit;
signal u : bit_vector(1 to 3);
signal v : bit_vector(2 downto 0);
begin
process is
begin
(x, y, z) <= bit_vector'("011");
wait for 1 ns;
assert x = '0';
assert y = '1';... |
entity signal10 is
end entity;
architecture test of signal10 is
signal x, y, z : bit;
signal u : bit_vector(1 to 3);
signal v : bit_vector(2 downto 0);
begin
process is
begin
(x, y, z) <= bit_vector'("011");
wait for 1 ns;
assert x = '0';
assert y = '1';... |
entity signal10 is
end entity;
architecture test of signal10 is
signal x, y, z : bit;
signal u : bit_vector(1 to 3);
signal v : bit_vector(2 downto 0);
begin
process is
begin
(x, y, z) <= bit_vector'("011");
wait for 1 ns;
assert x = '0';
assert y = '1';... |
entity signal10 is
end entity;
architecture test of signal10 is
signal x, y, z : bit;
signal u : bit_vector(1 to 3);
signal v : bit_vector(2 downto 0);
begin
process is
begin
(x, y, z) <= bit_vector'("011");
wait for 1 ns;
assert x = '0';
assert y = '1';... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
-- Define the signature of the 2-input AND gate
entity AND2 is
port(
A: in std_logic;
B: in std_logic;
F: out std_logic
);
end AND2;
-- Define the implementation of the 2-input AND gate
architecture basic of AND2 is
begin
F <= A and B;
end architecture; |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_constant... |
entity repro is
end repro;
architecture behav of repro is
type msg_t is record
pfx : string;
func : string;
user : string;
end record;
procedure report_msg (m : msg_t) is
begin
report m.pfx & "." & m.func & ": " & m.user;
end report_msg;
procedure fill (pfx : string := "#err#"; usr : stri... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:35:07)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT ... |
ROM_form_S3_1K.vhd - Picoblaze Spartan-3 ROM template
Freely available from Opbasm (http://code.google.com/p/opbasm)
Copyright © 2014 Kevin Thibedeau
(kevin 'period' thibedeau 'at' gmail 'punto' com)
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated document... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr10 is
port (val : std_logic_vector(3 downto 0);
res : out natural);
end arr10;
architecture behav of arr10 is
function find (s : string; c : character) return natural is
begin
for i in s'range loop
if s (i) = c then... |
-- Hi Emacs, this is -*- mode: vhdl; -*-
----------------------------------------------------------------------------------------------------
--
-- Monocrome Text Mode Video Controller VHDL Macro
-- 80x40 characters. Pixel resolution is 640x480/60Hz
--
-- Copyright (c) 2007 Javier Valcarce Garca, javier.valcarce@gmail... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------------
-- Top SPI Speed Calculation for Widescreen (Please check my math - no warranties implied)
-- To determine top speed, look at worst case and count user clocks
-- 1) SPI_CACHE_FULL_FLAG goes high too late for tSU to react
-- 2... |
--------------------------------------------------------------------------------------------------
-- FIR Filter Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
--------------------------------------------... |
entity aggregate is
end entity;
architecture test of aggregate is
type my_enum is (A, B, C);
type my_enum_map is array (my_enum) of integer;
constant c1 : my_enum_map := (A => 1, A => 2, C => 3); -- Error
constant c2 : my_enum_map := my_enum_map'(A => 1, B => 2); -- Error
constant c3 : my_enum_m... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
entity not104 is
port (
a_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity not104;
architecture rtl of not104 is
begin
c_o <= not a_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity not104 is
port (
a_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity not104;
architecture rtl of not104 is
begin
c_o <= not a_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity not104 is
port (
a_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity not104;
architecture rtl of not104 is
begin
c_o <= not a_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity not104 is
port (
a_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity not104;
architecture rtl of not104 is
begin
c_o <= not a_i;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
... |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_lut_base.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : LUT-based Single-port Base Decoder for decoding 8b/10b
-- ... |
-------------------------------------------------------------------------------
-- $Id: or_gate_f.vhd,v 1.1.4.2 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate_f.vhd - entity/architecture pair
----------------------------------------------------... |
--! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Xilinx Spartan 6 only.
--! It is specific for the openMAC descriptor DPRAM which require
--! simultaneous write/read from the same address.
--! ... |
-------------------------------------------------------------------------------
-- VHDL Basics Altera Course: The code is not to be compiled, for study only --
-------------------------------------------------------------------------------
--
-- TODO: Describe Bahavior and Structural Modeling / Register Transfer Level
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
depth : integer;
bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
push_i, pop_i : in std_logic;
full_o, empty_o : out std_logic;
d_i : in std_logic_vector ( bi... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- $Id: sys_tst_rlink_s3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated d... |
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated d... |
Library ieee;
Use ieee.std_logic_1164.all;
Entity Blah Is
Generic (
G_blah : Std_logic
);
Port (
i_INPUT : In Std_logic;
o_OUTPUT : Out Std_logic;
io_INOUT : Inout Std_logic
);
End Entity Blah;
Architecture Rtl Of Blah Is
Constant Con_a : Std_logic;
Signal Sig_a : Std_logic;
C... |
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