content stringlengths 1 1.04M ⌀ |
|---|
entity tb_rec05 is
end tb_rec05;
library ieee;
use ieee.std_logic_1164.all;
use work.rec05_pkg.all;
architecture behav of tb_rec05 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec05
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r = (a ... |
architecture RTL of FIFO is
begin
process
begin
LOOP_LABEL: loop end loop;
LOOP_LABEL: while condition loop end loop;
LOOP_LABEL: for x in range(15 downto 0) loop end loop;
end process;
process
begin
loop end loop;
while condition loop end loop;
for x in range(15 downto 0) l... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... |
package p is
-- Reduced failure case from VESTs
type ibi is array (integer range <>, boolean range <>) of integer ;
subtype irange is integer range 1 to 5 ;
subtype brange is boolean range false to true ;
subtype ibi_s is ibi (irange, brange);
-- TODO
subtype ibi_x is ibi (brange, i... |
package p is
-- Reduced failure case from VESTs
type ibi is array (integer range <>, boolean range <>) of integer ;
subtype irange is integer range 1 to 5 ;
subtype brange is boolean range false to true ;
subtype ibi_s is ibi (irange, brange);
-- TODO
subtype ibi_x is ibi (brange, i... |
package p is
-- Reduced failure case from VESTs
type ibi is array (integer range <>, boolean range <>) of integer ;
subtype irange is integer range 1 to 5 ;
subtype brange is boolean range false to true ;
subtype ibi_s is ibi (irange, brange);
-- TODO
subtype ibi_x is ibi (brange, i... |
package p is
-- Reduced failure case from VESTs
type ibi is array (integer range <>, boolean range <>) of integer ;
subtype irange is integer range 1 to 5 ;
subtype brange is boolean range false to true ;
subtype ibi_s is ibi (irange, brange);
-- TODO
subtype ibi_x is ibi (brange, i... |
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- Un... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
-----Libraries-----
library ieee;
use ieee.std_logic_1164.all;
-----Entities-----
entity testerOinputNAND is
port( SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(0 downto 0)
);
end testerOinputNAND;
-----Architecture-----
architecture tester of testerOinputNAND is
begin
O1 : entity work.oI... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 14:49:03 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, Microsemi ProASIC3 Starter Kit
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_... |
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, Microsemi ProASIC3 Starter Kit
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clockDivider IS
PORT ( CLOCKIN : IN STD_LOGIC;
FreqIn : IN INTEGER;
freqOut : IN INTEGER;
CLOCKOUT : OUT STD_LOGIC
);
END clockDivider;
ARCHITECTURE behavior OF clockDivider IS
SIGNAL clock : STD_LOGIC := '0';
CONSTANT COU... |
entity assign3 is
end entity;
architecture test of assign3 is
begin
process is
variable x : bit_vector(7 downto 0);
variable y : bit_vector(7 downto 0) := (
0 => '1', 2 => '1', 4 => '1', 6 => '1',
others => '0' );
begin
assert x(0) = '0';
x := (others =>... |
entity assign3 is
end entity;
architecture test of assign3 is
begin
process is
variable x : bit_vector(7 downto 0);
variable y : bit_vector(7 downto 0) := (
0 => '1', 2 => '1', 4 => '1', 6 => '1',
others => '0' );
begin
assert x(0) = '0';
x := (others =>... |
entity assign3 is
end entity;
architecture test of assign3 is
begin
process is
variable x : bit_vector(7 downto 0);
variable y : bit_vector(7 downto 0) := (
0 => '1', 2 => '1', 4 => '1', 6 => '1',
others => '0' );
begin
assert x(0) = '0';
x := (others =>... |
entity assign3 is
end entity;
architecture test of assign3 is
begin
process is
variable x : bit_vector(7 downto 0);
variable y : bit_vector(7 downto 0) := (
0 => '1', 2 => '1', 4 => '1', 6 => '1',
others => '0' );
begin
assert x(0) = '0';
x := (others =>... |
entity assign3 is
end entity;
architecture test of assign3 is
begin
process is
variable x : bit_vector(7 downto 0);
variable y : bit_vector(7 downto 0) := (
0 => '1', 2 => '1', 4 => '1', 6 => '1',
others => '0' );
begin
assert x(0) = '0';
x := (others =>... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vec... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.myTypes.all;
--use ieee.numeric_std.all;
--use work.all;
entity stall_logic is
generic (
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
... |
-------------------------------------------------------------------------------
-- Title : Window comparator
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.V.
-- Pla... |
-------------------------------------------------------------------------------
-- Title : Window comparator
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.V.
-- Pla... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ie... |
entity test is
end entity test;
architecture test_arch of test is
constant CYCLES : integer := 10;
constant size : integer := 1;
type vector_t is array (0 to size-1) of integer;
signal big_vector : vector_t;
signal clk : integer := 0;
begin
main: process(clk)
begin
for i in 0 to size-1 loop
big_vecto... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev10 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
--library ims;
--use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENT... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_10.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
library IEEE;
use IEEE.std_logic_1164.all;
entity crc is
port
(
NEW_MSG : in std_logic; -- rising_edge indicates a message at port MSG, for which the CRC has to be calculated
MSG : in std_logic_vector(21-1 downto 0);
CLK : in std_logic; --clock square wav... |
library IEEE;
use IEEE.std_logic_1164.all;
entity crc is
port
(
NEW_MSG : in std_logic; -- rising_edge indicates a message at port MSG, for which the CRC has to be calculated
MSG : in std_logic_vector(21-1 downto 0);
CLK : in std_logic; --clock square wav... |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--Module Title: GenReg
--Module Description:
-- This is a general-purpose, rising edge triggered, resizeable register
----------------------------------------------------------------------------------
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:59:48 07/06/2015
-- Design Name:
-- Module Name: sigmaDeltaPWMEncoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Pulse Width Modulated ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Pulse Width Modulated ... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
sign... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
sign... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
sign... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
sign... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
sign... |
----------------------------------------------------------------------------------
-- Company: Creotech
-- Engineer: abyszuk
--
-- Create Date: 19:47:45 18/01/2013
-- Design Name:
-- Module Name: ddr_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Utilidad_RS232 is
Port ( clk : in STD_LOGIC;
Recibo : in STD_LOGIC;
Devuelvo : out STD_LOGIC := '1');
end Utilidad_RS232;
architecture arq_Utilidad_RS232 of Utilidad_RS232 is
component RS232
Port ( clk : in STD_LOGIC;
-- Trasmi... |
-- *********************************************************************
-- Author : $Author: fwi $
-- Department : MPD_BE
-- Date : $Date: 2010-03-17 12:13:46 +0100 (Wed, 17 Mar 2010) $
-- Revision : $Revision: 62 $
-- *********************************************************************
-... |
--
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: MEM_WB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Stack trace buffer on hardware level.
----------------------------------------------------------... |
------------------------------------------------------------------------------
-- Flip-Flops
--
-- Project :
-- File : $URL: svn+ssh://plessl@yosemite.ethz.ch/home/plessl/SVN/simzippy/trunk/vhdl/flipflop.vhd $
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
--... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without w... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:46:00 05/17/2016
-- Design Name:
-- Module Name: MUX-Verb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: IF_ID - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
-- file: clk_193MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: clk_193MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: clk_193MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: clk_193MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Module: XC3S_RAMB_1_PORT
-- Description: 18Kb Block SelectRAM example
-- Single Port 512 x 36 bits
-- Use template "SelectRAM_A36.vhd"
--
-- Device: Spartan-3 Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- Syntax... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of... |
Library ieee;
Use ieee.std_logic_1164.All;
Entity regn Is
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
End regn;
Architecture Behavior Of regn Is
Begin
Process (Clock)
Begin
If Clock'EVENT And Clock =... |
Library ieee;
Use ieee.std_logic_1164.All;
Entity regn Is
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
End regn;
Architecture Behavior Of regn Is
Begin
Process (Clock)
Begin
If Clock'EVENT And Clock =... |
library verilog;
use verilog.vl_types.all;
entity dcache is
port(
clock : in vl_logic;
address : in vl_logic_vector(31 downto 0);
data : inout vl_logic_vector(31 downto 0);
read : in vl_logic;
write : in vl_lo... |
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