content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
--! @file alteraOpenmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Altera
--
--! @details This is the openMAC toplevel for Altera platform.
-------------------------------------------------------------------------------
--
-- (c) B... |
-- *****************************************
-- * Banco de prueba para Autómata finito *
-- *****************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ej_af_bp is
end ej_af_bp;
architecture tb_arch of ej_af_bp is
constant T: time := 20 ns; -- Periodo ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tx_ff_ctrl is
port (
tx_wr : in std_logic;
tx_wdata :in std_logic_vector(15 downto 0);
tx_rdy :out std_logic ;
tx_first :in std_logic;
tx_last :in std_logic ;
tx_en :in std_logic ;
tx_ff... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tx_ff_ctrl is
port (
tx_wr : in std_logic;
tx_wdata :in std_logic_vector(15 downto 0);
tx_rdy :out std_logic ;
tx_first :in std_logic;
tx_last :in std_logic ;
tx_en :in std_logic ;
tx_ff... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that t... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
library std;
entity lbp_process is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in... |
-------------------------------------------------------------------------------
-- axi_vdma_rst_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rig... |
-------------------------------------------------------------------------------
-- axi_vdma_rst_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rig... |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 19:34:37 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 19:34:37 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
entity clock is
port (
clk_50Mhz : in std_logic;
rst : in std_logic;
clk_2Hz : out std_logic);
end clock;
archite... |
entity T_flip_flop is
port(T,clk,clear:in bit;
Q,QN:buffer bit
);
end T_flip_flop;
architecture internal of T_flip_flop is
begin
QN<=not Q;
process(clk,clear)
begin
if(clear='0') then Q<='0';
elsif(clk'event and clk='1') then
if T='1' then Q<= QN;
end if;
end if ;
end process;
end archite... |
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : MemoryProg
-- Date : 07/25/2016
--
-- Description : Memory block for the Miniblaze on Spartan3. Use of RAMB16_S4.
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen
--
-- Create Date: 11:24:03 09/18/2017
-- Design Name:
-- Module Name: Mux4x1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a generic 4x1 10 bit mux with... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UpDownMod16 is
generic(
MIN_COUNT : natural := 0;
MAX_COUNT : natural := 15
);
port(
clk, load, enable, up : in std_logic;
toLoad: in integer range MIN_COUNT to MAX_COUNT;
q : out integer range MIN_COUNT to MAX_COUNT;
carry : o... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY BlockStm_complete_override1 IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF BlockStm_complete_override1 IS
BEGIN
assig_process_c: PROCESS(a, b)
BEGIN
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:55:53 12/23/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_module.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:55:53 12/23/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_module.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
... |
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : dac_tb.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-05... |
-- ======================================================================
-- CBC-DES encryption/decryption testbench
-- tests according to NIST 800-17 special publication
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; yo... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity spirom is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
mosi: out std_logic;
miso: in std_logic;
sck: out std_l... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity return_stack is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logi... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
----------------------------------------------------------------------
-- Created by SmartDesign Fri Apr 14 17:06:17 2017
-- Version: v11.8 11.8.0.26
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Libraries
-------------... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:10:05 01/07/2014
-- Design Name:
-- Module Name: G:/Project_Block_Mario/TestBench_PS2.vhd
-- Project Name: Block_Mario
-- Target Device:
-- Tool versions:
-- Description... |
-- Hello world program.
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello_world is
end hello_world;
architecture behaviour of hello_world is
begin
process
variable l : line;
begin
write (l, String'("Hello world!"));
... |
entity emptyquote is
end;
architecture behav of emptyquote is
procedure proc is
begin
null;
end proc;
begin
process
begin
proc''
null;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets ... |
library verilog;
use verilog.vl_types.all;
entity SeqSideEightBitAdder_vlg_vec_tst is
end SeqSideEightBitAdder_vlg_vec_tst;
|
use IEEE.std_logic_1164.all;
use MY_LIB, OTHERLIB.my_math_stuff.multiply;
use YETANOTHERLIB.std_logic;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbta_pkg.all;
use work.wbp_pkg.all;
use work.uart_pkg.all;
entity uart_wbp is
generic (
g_clk_freq : integer := 12000000;
g_baud_rate : integer := 9600);
port (
clk_i : in std_logic;
rst_i : in std_logic;
-- serial
rx_i : in st... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.pgm_types.all;
package read_funcs is
function read_pgm_image(pgm_file_name: string) return pgm_image;
end package read_funcs;
package body read_funcs is
function read_pgm_image(pgm_file_name: string) return pgm_i... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of padframe
--
-- Generated
-- by: wig
-- on: Wed Jul 5 17:16:56 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Autho... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_NOR is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_NOR;
---------------------------------------------------------... |
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-- maurice daverveldt
-- 1531491
-- ev3a
-- dit bestand bevat alle losse componenten
library ieee;
use ieee.std_logic_1164.all;
entity opdr5_mux is
port( x,y : in std_logic_vector(7 downto 0);
s : in std_logic;
f : out std_logic_vector(7 downto 0));
end opdr5_mux;
architecture RTL of opdr5_mux is
begin
proce... |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- ------------------------------------------... |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- ------------------------------------------... |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- ------------------------------------------... |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- ------------------------------------------... |
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- ------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package signal_sources_pkg is
component source_sine is
generic (
DATA_WIDTH : positive;
AMPLITUDE : real;
SIGNAL_FREQUENCY : real;
SAMPLING_FREQUENCY : real);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package signal_sources_pkg is
component source_sine is
generic (
DATA_WIDTH : positive;
AMPLITUDE : real;
SIGNAL_FREQUENCY : real;
SAMPLING_FREQUENCY : real);
... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PIPO is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC);
end PIPO;
architecture Behavioral of PIPO is
signal aux : std_logic_vector(3 downto 0) := "0000";
begin
Q <= aux;
proce... |
-----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Audio Interface
-- Author : Jan Dürre
-- Last update : 18.04.2016
-- Description : -
---------------------------------------------------------------------------------... |
architecture rtl of fifo is begin
s_foo <= (
item => 12,
another_item => 34
);
s_foo <= (
item => 12,
another_item => 34
);
s_foo <= ( item1 => 12,
item2 => f(a, b ,c),
item3 => 36
);
s_... |
------------------------ four bit adder --------------------------------------
-------------- Library statements -------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration four_bit_adder--
entity four_bit_adder is
port (cin : in std_logic;
A, B : in std_logic_vector(3 downto 0);
... |
-- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
-- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
-- NEED RESULT: ARCH00467.Check_It1: Locally static null discrete ranges are permited on generate statements passed
-- NEED RESULT: ARCH00467.Check_It2: Locally static null discrete ranges are permited on generate statements passed
-------------------------------------------------------------------------------
--
... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_sound is
generic (
g_tag : std_logic_vector(7 downto 0) := X"04";
rate_div : natural := 2176; -- 22050 Hz
sound_base : unsigned(27 downto 16) := X"103";
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_sound is
generic (
g_tag : std_logic_vector(7 downto 0) := X"04";
rate_div : natural := 2176; -- 22050 Hz
sound_base : unsigned(27 downto 16) := X"103";
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_sound is
generic (
g_tag : std_logic_vector(7 downto 0) := X"04";
rate_div : natural := 2176; -- 22050 Hz
sound_base : unsigned(27 downto 16) := X"103";
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_sound is
generic (
g_tag : std_logic_vector(7 downto 0) := X"04";
rate_div : natural := 2176; -- 22050 Hz
sound_base : unsigned(27 downto 16) := X"103";
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--MIPI CSI-2 byte aligner
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives raw, unaligned bytes (which could contain part of two actual bytes)
--from the SERDES and aligns them by looking for the D-PHY sync pattern
-... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity audio_spi_drv is
port(
clk: in std_logic;
data: out std_logic_vector(31 downto 0);
ready: in std_logic;
valid: out std_logic
);
end audio_spi_drv;
architecture B... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:24:47 11/14/2015
-- Design Name:
-- Module Name: register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:24:47 11/14/2015
-- Design Name:
-- Module Name: register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:24:47 11/14/2015
-- Design Name:
-- Module Name: register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:24:47 11/14/2015
-- Design Name:
-- Module Name: register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:49:49 11/27/2016
-- Design Name:
-- Module Name: E:/David/Teleco/Curso_2016-2017/DSED/Practica 3/PIC/tb_PIC.vhd
-- Project Name: PIC
-- Target Device:
-- Tool versions:
... |
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
----... |
-- 32-bit adder circuit
-- this circuit adds two 32-bit unsigned numbers together, and supports previous-carry addition and subtraction
-- all code (c) 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity adder_32_bit is
port (
-- inputs
a... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... |
entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
... |
entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
... |
entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
... |
entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
... |
entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
... |
library ieee;
use ieee.std_logic_1164.all;
--This is the initial implementation of a left right function. There is also a ready function for right shift declared in ieee.numeric_std . But we found it out later so we kept our initial implementation.
entity right_shift_by_1 is
port( data_in: in std_logic_vector(0 to ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:21:00 03/23/2015
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench_vowels is
end testbench_vowels;
architecture testbench_arch_vowels of testbench_vowels is
signal clk : std_logic;
signal enable : std_logic;
signal length_in, length_out : natural;
signal reset : std_logic;
signal load_index : nat... |
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