content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype sub_integer is integer range 42 to 69;
constant x : sub_integer;
begin
assert x = sub_integer'left report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype sub_integer is integer range 42 to 69;
constant x : sub_integer;
begin
assert x = sub_integer'left report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype sub_integer is integer range 42 to 69;
constant x : sub_integer;
begin
assert x = sub_integer'left report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
|
library ieee;
library ieee;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.LIB.ALL;
ENTITY AP_Alu IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
OP_A : IN AP_data_width;
OP_B : IN AP_data_width;
ALU_OP : IN std_l... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Mike Field <hamster@sanp.net.nz>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
-------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Mike Field <hamster@sanp.net.nz>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
-------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AdderSat is
generic (
wordLength : natural := 12
);
port (
a : in std_logic_vector(wordLength-1 downto 0);
b : in std_logic_vector(wordLength-1 downto 0);
s : out std_logic_vector(wordLength-1 downto 0)
);
end entity ; -- Ad... |
library verilog;
use verilog.vl_types.all;
entity cda_scale_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
high : in vl_logic_vector(31 downto 0);
low : in vl_logic_vector(3... |
-------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free ha... |
-------------------------------------------------------------------------------
-- axi_datamover_ms_strb_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- $Id: pdp11_dmhbpt.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmhbpt - syn
-- Description: pdp11:... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_6_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2016 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
entity tb_soc_intercon is
end entity tb_soc_intercon;
architecture testbenc... |
entity slice3 is
end entity;
architecture test of slice3 is
type bvv is array (integer range <>) of bit_vector(7 downto 0);
signal x : bvv(1 downto 0);
signal y : bit_vector(3 downto 0);
begin
process (y) is
begin
for i in x'range loop
x(i)(3 downto 0) <= y;
x(i)(7 ... |
entity slice3 is
end entity;
architecture test of slice3 is
type bvv is array (integer range <>) of bit_vector(7 downto 0);
signal x : bvv(1 downto 0);
signal y : bit_vector(3 downto 0);
begin
process (y) is
begin
for i in x'range loop
x(i)(3 downto 0) <= y;
x(i)(7 ... |
entity slice3 is
end entity;
architecture test of slice3 is
type bvv is array (integer range <>) of bit_vector(7 downto 0);
signal x : bvv(1 downto 0);
signal y : bit_vector(3 downto 0);
begin
process (y) is
begin
for i in x'range loop
x(i)(3 downto 0) <= y;
x(i)(7 ... |
entity slice3 is
end entity;
architecture test of slice3 is
type bvv is array (integer range <>) of bit_vector(7 downto 0);
signal x : bvv(1 downto 0);
signal y : bit_vector(3 downto 0);
begin
process (y) is
begin
for i in x'range loop
x(i)(3 downto 0) <= y;
x(i)(7 ... |
entity slice3 is
end entity;
architecture test of slice3 is
type bvv is array (integer range <>) of bit_vector(7 downto 0);
signal x : bvv(1 downto 0);
signal y : bit_vector(3 downto 0);
begin
process (y) is
begin
for i in x'range loop
x(i)(3 downto 0) <= y;
x(i)(7 ... |
package sumpkg is
end package;
package body sumpkg is
type int_vector is array (natural range <>) of integer;
function sum(a : int_vector) return integer is
variable result : integer := 0;
begin
for i in a'range loop
result := result + a(i);
end loop;
return re... |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_pipebuf
-- Architectures: lipif_pipebuf_rtl
-- Description:
-- This module provides a buffer for ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity main is
port (
sal: inout std_logic_vector (7 downto 0);
CLK : in std_logic;
multiplicando : inout std_logic_vector(7 downto 0) := "00000111";
arreglo : inout std_logic_vect... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity main is
port (
sal: inout std_logic_vector (7 downto 0);
CLK : in std_logic;
multiplicando : inout std_logic_vector(7 downto 0) := "00000111";
arreglo : inout std_logic_vect... |
-------------------------------------------------------------------------------
-- $Id: qspi_receive_reg.vhd
-------------------------------------------------------------------------------
-- qspi_receive_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
-... |
--------------------------------------------------------------------------------
-- FILE: Sipo
-- DESC: Generic Serial in paralle out, with RESET and ENABLE
--
-- Author:
-- Create: 2015-09-09
-- Update: 2015-09-09
-- Status: TESTED
--------------------------------------------------------------------------------
libra... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
-------------------------------------------------------------------------------
-- hard_ethernet_mac_fifo_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_ll_fifo_v1_02_a;
use ... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
signal last_x : integer := 0;
begin -- only
process (clock)
variable x : integer := 0;
begin -- process
last_x <= x;
x := x + 1;
wait for 1 fs;
assert x > last_x report "TEST FAILED" severity FAILU... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
signal last_x : integer := 0;
begin -- only
process (clock)
variable x : integer := 0;
begin -- process
last_x <= x;
x := x + 1;
wait for 1 fs;
assert x > last_x report "TEST FAILED" severity FAILU... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
signal last_x : integer := 0;
begin -- only
process (clock)
variable x : integer := 0;
begin -- process
last_x <= x;
x := x + 1;
wait for 1 fs;
assert x > last_x report "TEST FAILED" severity FAILU... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2012, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
---------------------------------------------------
-- Module: training_and_channel_delay
--
-- Description: Allow the insertion of the training patterns into the symbol
-- stream, and ensure a clean switch-over to the input channel,
--
-- Also adds the 8b10b encoder's "force negative p... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
entity TREE_G is
port(
PG: in std_logic_vector(1 downto 0);
GI: in std_logic;
GO: out std_logic
);
end TREE_G;
architecture BEHAVIORAL of tree_g is
begin
GO <= PG(1) or (PG(0) and GI);
end behavioral;
|
--------------------------------------------------------------------------------------------------
-- Multi-channel FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
---------------------------------------------... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just lws and sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : intege... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just lws and sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : intege... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just lws and sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : intege... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--
-- Front-end for SpaceWire Receiver
--
-- This entity samples the input signals DataIn and StrobeIn to detect
-- valid bit transitions. Received bits are handed to the application
-- in groups of "rxchunk" bits at a time, synchronous to the system clock.
--
-- This receiver is based on synchronous oversampling ... |
--
-- Front-end for SpaceWire Receiver
--
-- This entity samples the input signals DataIn and StrobeIn to detect
-- valid bit transitions. Received bits are handed to the application
-- in groups of "rxchunk" bits at a time, synchronous to the system clock.
--
-- This receiver is based on synchronous oversampling ... |
constant ReconfSignalsLength : integer := 9;
constant ReconfSignalsCfg : std_logic_vector(ReconfSignalsLength-1 downto 0) := "000000001";
|
constant ReconfSignalsLength : integer := 9;
constant ReconfSignalsCfg : std_logic_vector(ReconfSignalsLength-1 downto 0) := "000000001";
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pc_fsm is
port
(
clk_i, reset_i: in std_logic;
jump_decision_i: in std_logic;
lc_pfc_loop_flag_i: in std_logic;
lc_pfc_loope_i: in std_logic_vector(15 downto 0);
ctrl_i: in std... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:39:58 11/23/2015
-- Design Name:
-- Module Name: moltiplicatore_booth - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Demonstrates overloading of procedures
entity main is
end entity main;
architecture main of main is
type arr01 is array (0 to 1) of integer;
procedure p1(variable f1 : in integer; variable f2 : out integer) is
begin
f2 := f1;
end procedure p1;
procedure p1(variable f1 : in... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity zeroext_tb is
end zeroext_tb;
architecture TB of zeroext_tb is
component zeroext
port(
in0 : in std_logic_vector(15 downto 0);
out0 : out std_logic_vector(31 downto 0));
end component;
signal in0 : std_logic_vector(15 downto 0)... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
---- ----
---- gmzpu timer component testbench ----
---- ----
---- ... |
--------------------------------------------
-- Module Name: vga_mouse - behavioral --
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.vga_mouse_pkg.all;
entity vga_mouse is
port (
sclk :... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Encryption_Module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( cypher_text : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish_round : out STD_LOGIC;
plain_text : in STD_LOGIC_VECTOR (DATA_LENGTH-... |
---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warra... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY anode_sel IS
PORT(
sel_in : IN std_logic_vector(1 DOWNTO 0);
sel_out : OUT std_logic_vector(3 DOWNTO 0));
END anode_sel;
ARCHITECTURE anode_sel_arq OF anode_sel IS
BEGIN
PR... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity DISP7S_4 is
Generic
(
N : NATURAL := 20 -- 100MHz -> (2^N)/f = T*(2^N) = 10ns * (2^20) = 10ms | (1ms - 16ms)
);
Port
(
C : in S... |
-- KCPSM3 reference design
-- PicoBlaze performing programming of Intel StrataFlash NOR Flash Memory.
--
-- Design provided and tested on the Spartan-3E Starter Kit (Revision C).
--
-- Ken Chapman - Xilinx Ltd - 28th March 2006.
--
-- The JTAG loader utility is also available for rapid program development.
--
-- The... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- butterfly.vhd
--
-- Created on: 13 Jul 2017
-- Author: Fabian Meyer
--
-- Butterfly component for the FFT.
library ieee;
library work;
use ieee.std_logic_1164.all;
use work.fft_helpers.all;
entity butterfly is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
... |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ======================... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sliced_ex is
port (
clk : in std_logic;
reset : in std_logic;
arg_a : in std_logic_vector(3 downto 0);
arg_b : in std_logic_vector(3 downto 0)
);
end sliced_ex;
architecture rtl of sliced_ex is
signal aa, ab : std_... |
----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library c64roms;
use c64roms.p_char_rom.all;
entit... |
----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library c64roms;
use c64roms.p_char_rom.all;
entit... |
----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library c64roms;
use c64roms.p_char_rom.all;
entit... |
-- Author: Varun Nagpal
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
package ssg_display_shared_package is
constant DIGIT_CNT : natural := 4; -- k number of digits
constant MIN_DIGITS_C : natural := 1; -- minimum num... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sun Jun 5 17:42:57 2016
-- Host : Dries007-Arch running 64-bit unknown... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERM... |
entity fifo is
end;
architecture rtl of fifo is
begin
end;
|
-- file: clk_108MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: clk_108MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: clk_108MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (lo_1 : out std_logic_vector (1 downto 0);
lo_2 : out std_logic_vector (1 downto 0));
end entity issue;
architecture beh of issue is
function fun (arg : integer) return integer is
begin
return arg - 1;
end function;
... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
------------------------------------------------------------... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.