content stringlengths 1 1.04M ⌀ |
|---|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--
-- This file is part of top_test_sharp_screen
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_1 is
port(
clocks_c1_clk : in vl_logic;
clock_crossing_io_m0_reset_reset_bridge_in_reset_reset: in vl_logic;
clock_crossing_io_m0_address: in vl_logic_vector(21 downto 0);
clock_crossing_io_m0_... |
library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PKG.all;
package OISC_SUBLEQ_PKG is
component OISC_SUBLEQ is
generic (
log2PADDR : integer range 0 to integer'high := 8;
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean ... |
library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PKG.all;
package OISC_SUBLEQ_PKG is
component OISC_SUBLEQ is
generic (
log2PADDR : integer range 0 to integer'high := 8;
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean ... |
library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PKG.all;
package OISC_SUBLEQ_PKG is
component OISC_SUBLEQ is
generic (
log2PADDR : integer range 0 to integer'high := 8;
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean ... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "clkdiv"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_counter.vhd
-- Author : Martin Angermair
-- Company :
-- Created : ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
entity record3 is
end entity;
architecture test of record3 is
procedure add1(x : inout integer) is
begin
x := x + 1;
end procedure;
type rec is record
a, b : integer;
end record;
procedure foo(r : inout rec) is
begin
add1(r.a);
add1(r.b);
end procedure... |
entity record3 is
end entity;
architecture test of record3 is
procedure add1(x : inout integer) is
begin
x := x + 1;
end procedure;
type rec is record
a, b : integer;
end record;
procedure foo(r : inout rec) is
begin
add1(r.a);
add1(r.b);
end procedure... |
entity record3 is
end entity;
architecture test of record3 is
procedure add1(x : inout integer) is
begin
x := x + 1;
end procedure;
type rec is record
a, b : integer;
end record;
procedure foo(r : inout rec) is
begin
add1(r.a);
add1(r.b);
end procedure... |
entity record3 is
end entity;
architecture test of record3 is
procedure add1(x : inout integer) is
begin
x := x + 1;
end procedure;
type rec is record
a, b : integer;
end record;
procedure foo(r : inout rec) is
begin
add1(r.a);
add1(r.b);
end procedure... |
entity record3 is
end entity;
architecture test of record3 is
procedure add1(x : inout integer) is
begin
x := x + 1;
end procedure;
type rec is record
a, b : integer;
end record;
procedure foo(r : inout rec) is
begin
add1(r.a);
add1(r.b);
end procedure... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
-- A6500 - 6502 CPU and variants
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- Company: vienna university of technology
-- Engineer: mario faschang
-- Create Date: 11:12:56 19/01/2010
-- Module Name: tb_I2CTransferController
-- Project Name: i2c master controller
-- Description: * testbench f... |
-------------------------------------------------------------------------------
--! @file convRmiiToMii-rtl-ea.vhd
--
--! @brief RMII-to-MII converter
--
--! @details This is an RMII-to-MII converter to convert MII phy traces to RMII.
--! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC
--------------... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Forced Round robin arbiter
-- ####################################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity frr_arbiter is
generic (
g_CHANNE... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------------------... |
library verilog;
use verilog.vl_types.all;
entity cc3200_test_model is
port(
clk_in : in vl_logic;
reset_n : in vl_logic;
RX_Gate : in vl_logic;
Envelop : in vl_logic;
line_num : out vl_logic_vector(7 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity cc3200_test_model is
port(
clk_in : in vl_logic;
reset_n : in vl_logic;
RX_Gate : in vl_logic;
Envelop : in vl_logic;
line_num : out vl_logic_vector(7 downto 0);
... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
use IEEE.numeric_std.all;
entity top_synth... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm5 is
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end dcm5;
architecture BEHAVIORAL of dcm5 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic... |
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: string_generator - Behavioral
-- Description:
-- A state machine to generate potential passwords
----------------------------------------------------------------------------------
library I... |
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: string_generator - Behavioral
-- Description:
-- A state machine to generate potential passwords
----------------------------------------------------------------------------------
library I... |
-- file: clk_video.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not ... |
-------------------------------------------------------------------------------
-- Title : B
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----- Simple implementation of a four_bit_adder -----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity four_bit_adder_simple is
port(A,B : in std_logic_vector(3 downto 0);
sum : out std_logic_vector(3 downto 0);
cout : out std_logic;
cin : in std_logic);
end four_bit_add... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Elec... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity ent is
end entity;
architecture a of ent is
subtype my_low_rng is integer range 0 to 1;
subtype my_high_rng is integer range 2 to 3;
-- constant my_good_booleans : boolean_vector(0 to 3) :=
-- (0 to 1 => true, 2 to 3 => false);
constant my_bad_booleans : boolean_vector(0 to 3) :=
(my_low_rng => t... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:10:11 07/01/2017
-- Design Name:
-- Module Name: comparatore - DataFlow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
entity sampler is
generic (
g_clock_freq : natural := 50_000_000;
g_num_voices : positive := 8 );
port (
clock : in std_logic;
re... |
library ieee;
use ieee.std_logic_1164.all;
use work.encode_pkg.all;
use work.common.all;
use work.csr_pkg.all;
package test_config is
constant pipeline_tb_test_vector_input_filename : string := "sim/test3.vec";
-- arrays of instructions
type ram_t is array (natural range 0 to 256) of word;
... |
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
fpga_0_RS232_USB_... |
library ieee;
use ieee.std_logic_1164.all;
entity slv_negation is
port (
a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0)
);
end slv_negation;
architecture rtl of slv_negation is
begin
b <= not a(7 downto 0);
end rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LogicUnit is
port(input0 : in std_logic;
input1 : in std_logic;
invOut : out std_logic;
andOut : out std_logic;
orOut : out std_logic;
xorOut : out std_logic;
nandOut : out std_logic;
norOut : out std_logic);
end LogicUnit;
architecture Beh... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
term... |
-------------------------------------------------------------------------------
--
-- Title : slow2fastSync
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\lib\slow2fastSync.vhd
-- Generated : Tue Aug ... |
-------------------------------------------------------------------------------
--
-- Title : slow2fastSync
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\lib\slow2fastSync.vhd
-- Generated : Tue Aug ... |
-------------------------------------------------------------------------------
--
-- Title : slow2fastSync
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\lib\slow2fastSync.vhd
-- Generated : Tue Aug ... |
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated d... |
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated d... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use IEEE.std_logic_unsigned.all;
ENTITY sha256forBTC is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
--data input signals
data : in STD_LOGIC_VECTOR (511 downto 0);
enable : in ST... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use IEEE.std_logic_unsigned.all;
ENTITY sha256forBTC is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
--data input signals
data : in STD_LOGIC_VECTOR (511 downto 0);
enable : in ST... |
-----------------------------------------------------------------------------------------
-- SIGMA DELTA DAC WITH AHB INTERFACE
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
u... |
-----------------------------------------------------------------------------------------
-- SIGMA DELTA DAC WITH AHB INTERFACE
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
u... |
entity FIFO is
generic (
G_WIDTH : natural := 16
);
port (
I_INPUT : in std_logic;
O_OUTPUT : out std_logic;
IO_INOUT : inout std_logic
);
end entity;
architecture rtl of fifo is
function func1 (
i_input : std_logic;
o_output : std_logic;
io_inout : std_logic
) return integer ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY VGA_SYNC IS
PORT(
clock_25Mhz : IN STD_LOGIC;
red,green,blue : IN STD_LOGIC;
vga_red : OUT STD_LOGIC;
vga_green : OUT STD_LOGIC;
vga_blue : OUT STD_LOGIC;
vga_blank... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
library verilog;
use verilog.vl_types.all;
entity altaccumulate is
generic(
width_in : integer := 4;
width_out : integer := 8;
lpm_representation: string := "UNSIGNED";
extra_latency : integer := 0;
use_wys : string := "ON";
lpm_hint : ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_186 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_186;
architecture augh of sub_186 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_186 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_186;
architecture augh of sub_186 is
signal carry_inA : std_l... |
----------------------------------------------------------------------------------
-- Module Name: papilio_pro_dram_toplevel - Behavioral
-- The Bonfire Processor Project, (c) 2016,2017 Thomas Hornschuh
-- Toplevel module for Papilio Pro with 8MB SDRAM
-- License: See LICENSE or LICENSE.txt File in git project r... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clk_mgt is
port(clk50 : in std_logic;
rst : in std_logic;
clk12 : out std_logic;
clk25 : out std_logic);
end clk_mgt;
architecture... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
architecture ARCH of ENTITY1 is
begin
-- Passing
LABEL : assert boolean report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:00 2017
-- Host : DarkCube running 64-bit major re... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (burst capable)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-----... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (burst capable)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-----... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (burst capable)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-----... |
entity tb_arr04 is
end tb_arr04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr04 is
signal clk : std_logic;
signal rst : std_logic;
signal sel_i : std_logic;
signal sel_o : std_logic;
signal v : std_logic;
signal r : std_logic;
begin
dut: entity work.arr04
port map (clk => ... |
library ieee;
use ieee.MATH_REAL.all;
use ieee.NUMERIC_STD.all;
use ieee.NUMERIC_STD_UNSIGNED.all;
use ieee.std_logic_1164.all;
library work;
use work.uart_tb_bfm_pkg.all;
entity uart_tb is
end uart_tb;
architecture TB_ARCHITECTURE of uart_tb is
-- Stimulus signals - signals mapped to the input and inout ports of ... |
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
entity mwe is
end mwe;
architecture test of mwe is
begin
process
variable starttime : time := 1120 us;
variable endtime : time := 2031 us;
variable dt : time;
begin
dt := endtime - starttime;
report "Resulting frequency is: " & ... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------------------
-- $Id: util_flipflop.vhd,v 1.1 2006/09/20 09:36:32 rolandp Exp $
-------------------------------------------------------------------------------
-- util_flipflop.vhd - Entity and architecture
--
-- ****************************************... |
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