content stringlengths 1 1.04M ⌀ |
|---|
---------------------------------------------------------------------
---- ----
---- OpenCores ATA/ATAPI-5 Host Controller ----
---- PIO Timing Controller (common for all OCIDEC cores) ----
---- ... |
library ieee;
use ieee.std_logic_1164.all;
entity e is
end entity;
architecture a of e is
type t_rec is record
addr : std_logic_vector;
end record;
function init_signals(bits : natural) return t_rec is
variable result : t_rec(addr(bits - 1 downto 0));
begin
result.addr := (others => '0')... |
library ieee;
use ieee.std_logic_1164.all;
entity e is
end entity;
architecture a of e is
type t_rec is record
addr : std_logic_vector;
end record;
function init_signals(bits : natural) return t_rec is
variable result : t_rec(addr(bits - 1 downto 0));
begin
result.addr := (others => '0')... |
--------------------------------------------------------------------------------
-- Copyright 2014 Madhu Siddalingaiah
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://ww... |
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Josh Tombs
--
-- Create Date: SPRING 2015
-- Module Name: ControlUnit
-- Project Name: UMD_RISC16
-- Target Devices: Spartan-3E
-- Tool vers... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:21:25 12/06/2016
-- Design Name:
-- Module Name: /home/thomas/riscv/lxp32soc/tb_papro.vhd
-- Project Name: lxp32riscv
-- Target Device:
-- Tool versions:
-- Description:
--
--... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- File: ConcatDemo.vhd
-- Generated by MyHDL 0.10
-- Date: Wed Aug 29 14:28:03 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_010.all;
entity ConcatDemo is
port (
Res: out unsigned(6 downto 0);
ResS: out signed (6 downto 0)
)... |
--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Fri Sep 30 18:09:05 2016
--Host : graviton running 64-bit Debian GNU/Linux ... |
-- NEED RESULT: ARCH00393.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00393.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00393.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH... |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1';... |
entity null2 is
end entity;
architecture test of null2 is
signal x : bit_vector(0 downto 1);
begin
process is
begin
x <= (others => '0');
assert x'length = 0;
wait;
end process;
end architecture;
|
entity null2 is
end entity;
architecture test of null2 is
signal x : bit_vector(0 downto 1);
begin
process is
begin
x <= (others => '0');
assert x'length = 0;
wait;
end process;
end architecture;
|
entity null2 is
end entity;
architecture test of null2 is
signal x : bit_vector(0 downto 1);
begin
process is
begin
x <= (others => '0');
assert x'length = 0;
wait;
end process;
end architecture;
|
entity null2 is
end entity;
architecture test of null2 is
signal x : bit_vector(0 downto 1);
begin
process is
begin
x <= (others => '0');
assert x'length = 0;
wait;
end process;
end architecture;
|
entity null2 is
end entity;
architecture test of null2 is
signal x : bit_vector(0 downto 1);
begin
process is
begin
x <= (others => '0');
assert x'length = 0;
wait;
end process;
end architecture;
|
entity test is
type test1 is (foo);
constant test2, test3 : test1;
begin end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
library ieee;
use ieee.std_logic_1164.all;
entity bcd_segment_driver is
port (
bcd : in std_logic_vector(3 downto 0);
segments : out std_logic_vector(6 downto 0));
end;
architecture behavioral of bcd_segment_driver is
begin
segments <=
"1111110" when bcd = "0000" else -- 0
... |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.breakout_config.all;
entity controller is
port( clock : in std_logic;
reset : in std_logic;
scan_ready : in std_logic;... |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
entity prg_rom is
port (
pi_base_clk : in std_logic;
pi_ce_n : in std_logic;
pi_oe_n : in std_logic;
pi_addr : in std_logic_vector (14 downto 0);
... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
library ieee;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
variable a,b : unsigned(0 downto 0) := "1";
begin
assert a = b; -- Works
assert ieee.numeric_std."="(a, b);
end process;
end architecture;
|
library ieee;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
variable a,b : unsigned(0 downto 0) := "1";
begin
assert a = b; -- Works
assert ieee.numeric_std."="(a, b);
end process;
end architecture;
|
library ieee;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
variable a,b : unsigned(0 downto 0) := "1";
begin
assert a = b; -- Works
assert ieee.numeric_std."="(a, b);
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a
--
-- Generated
-- by: wig
-- on: Mon Aug 9 17:44:47 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
--... |
----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty E... |
----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty E... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Useful types for working with wishbone protocol, pipelined version as described
-- in the Wishbone B4 document: https://cdn.opencores.org/downloads/wbspec_b4.pdf
package wbp_pkg is
constant c_wbp_adr_width : integer := 32;
constant c_wbp_dat_... |
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:42 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_... |
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----ENTITY-----
entity Multiplexer is
port( data : out std_logic_vector(20 downto 0);
bin_in : in std_logic_vector(11 downto 0);
ab : in std_logic_vector(1 downto 0)
);
end Multiplexer;
-----ARCHITECTURE-----
archit... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Alu is
Port ( AluOp : in STD_LOGIC_VECTOR (5 downto 0);
rs1 : in STD_LOGIC_VECTOR (31 downto 0);
rs2 : in STD_LOGIC_VECTOR (31 downto 0);
c : in S... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_router_default_decode is
generic(
DEFAULT_CHANNEL : integer := 5;
\DEFAULT_WR_CHANNEL\: integer := -1;
\DEFAULT_RD_CHANNEL\: integer := -1;
DEFAULT_DESTID : integer := 5
);
port(
default_d... |
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- $Id: gcpad_rx-c.vhd,v 1.2 2004-10-08 21:18:39 arniml Exp $
--
-------------------------------------------------------------------------------
... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_560 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_560;
architecture augh of mul_560 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_560 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_560;
architecture augh of mul_560 is
signal tmp_res : signed(... |
architecture ARCH of ENTITY1 is
begin
assert boolean report "Something" severity FAILURE;
process begin
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Serial Port
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_port is
gen... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
---------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
---------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- system_dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use... |
-- $Id: tb_nexys4_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_core - sim
-- Description: T... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ----------------------------... |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ----------------------------... |
-- NEED RESULT: ARCH00041.P1: Target of a variable assignment may be a indexed name prefixed by an indexed name passed
-- NEED RESULT: ARCH00041.P2: Target of a variable assignment may be a indexed name prefixed by an indexed name passed
-- NEED RESULT: ARCH00041.P3: Target of a variable assignment may be a indexed n... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
clk : in STD_LOGIC;
A : out STD_LOGIC;
cout : out STD_LOGIC
);
end entity;
architecture beh of top is
begin
A <= y + cin;
cout <= y + A;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
clk : in STD_LOGIC;
A : out STD_LOGIC;
cout : out STD_LOGIC
);
end entity;
architecture beh of top is
begin
A <= y + cin;
cout <= y + A;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity rom is
generic(
MEM_WIDTH : integer := 32;
MEM_ADDR_BITS : integer := 11
);
port(
clockA : in vl_logic;
clockB : in vl_logic;
write_enableA : in vl_logic;
write_enableB ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_2_block2.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package custom_pkg is
type eight_bit is array (n... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.TbFuncs.all;
entity WordMuxDual_tb is
end WordMuxDual_tb;
architecture behavior of WordMuxDual_tb is
component WordMuxDual
port (
A_i : in std_logic_vector(15 downto 0);
B_i : in std_... |
-------------------------------------------------------------------------------
-- lmb_bram_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lmb_bram_elaborate is
generic (
... |
--
-- File Name: ReportPkg.vhd
-- Design Unit Name: ReportPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
-- Description:
-- Generate Final Reports
-- Elements of the... |
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