content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- $Id: util_flipflop.vhd,v 1.1 2006/09/20 09:36:32 rolandp Exp $
-------------------------------------------------------------------------------
-- util_flipflop.vhd - Entity and architecture
--
-- ****************************************... |
-------------------------------------------------------------------------------
-- $Id: util_flipflop.vhd,v 1.1 2006/09/20 09:36:32 rolandp Exp $
-------------------------------------------------------------------------------
-- util_flipflop.vhd - Entity and architecture
--
-- ****************************************... |
-------------------------------------------------------------------------------
-- $Id: util_flipflop.vhd,v 1.1 2006/09/20 09:36:32 rolandp Exp $
-------------------------------------------------------------------------------
-- util_flipflop.vhd - Entity and architecture
--
-- ****************************************... |
-------------------------------------------------------------------------------
-- $Id: util_flipflop.vhd,v 1.1 2006/09/20 09:36:32 rolandp Exp $
-------------------------------------------------------------------------------
-- util_flipflop.vhd - Entity and architecture
--
-- ****************************************... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--! @file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rotary_encoder is
generic(
--! the nominal frequency of the clock
core_frequency : natural := 100_000_000;
--! the width of the outputed counter register
counter_width : natural := 32
);
port(
--! the clk from the core... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
-------------------------------------------------------------------------------
-- Copyright (C) 2012-2021 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http:... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ebb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use work.sha1_pkg.all;
entity ztex_wrapper is
port(
fd : inout std_logic_vector(15 downto 0);
CS : in std_logic;
IFCLK : in std_logic;
--FXCLK : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
entity g_ethrx is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 12;
FIFO_AWIDTH : natural := 2;
WR_CYCLE : natural := 3;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
r... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity EightBitAdder is
port(
A : in vl_logic_vector(7 downto 0);
B : in vl_logic_vector(7 downto 0);
S : out vl_logic_vector(7 downto 0);
COUT : out vl_logic
);
end Eigh... |
-- Comments and stuff
-- end comments
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RegisterFile is
Port ( DIN : in STD_LOGIC_VECTOR (7 downto 0);
DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------------------------
-- Entity - UART Receiver
-- Receives data from RX of UART interface. Can be toggled between SIG and VALID mode.
--
-- The key has to be right aligned if it is not byte-aligned:
-- i.e. M=9 => 9 Bits => ... |
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_router is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seq_det_tb is
end entity;
architecture behav of seq_det_tb is
component seq_det is
port(
clk : in std_logic;
reset : in std_logic;
seq : in std_logic;
det : out std_logic
);
end component;
signal clk : std_logic :=... |
-------------------------------------------------------------------------------
--
-- File: DataPath.vhd
-- Author: Tudor Gherman
-- Original Project: Zmod ADC 1410 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digile... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
--
-- Baudrate generator
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions ... |
----------------------------------------
-- Memory address bus controller --
-- PORT MAPPING --
-- mar : 32 bit mar input --
-- data : 32 bit data input --
-- io_in : 32 bit io input --
-- ram_in : 32 bit ram input --
-- clk : 1 bit clock ... |
--------------------------------------------------------------------------------------------------
-- Multirate Fir Filter Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
---------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:49:24 02/26/2017
-- Design Name:
-- Module Name: gal_instrmapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependen... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity quant26bt_neg is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end quant26bt_neg;
architecture augh of quant26bt_neg is
-- Embedded RAM
type... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity quant26bt_neg is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end quant26bt_neg;
architecture augh of quant26bt_neg is
-- Embedded RAM
type... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity quant26bt_neg is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end quant26bt_neg;
architecture augh of quant26bt_neg is
-- Embedded RAM
type... |
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: packet_formation.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and... |
-- megafunction wizard: %LPM_RAM_DQ%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ===============... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fir is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- ready : in std_logic;
done : out std_logic;
-- coefficient
i_coeff_0 : in std_logic_vector(14 downto 0);
i_coeff_1 ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ---------------------------------... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
-------------------------------------------------------------------------------
-- Title : Ethernet Interface
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : EthCore.vhd
-- Author : Kurtis Nishimura
---------------... |
entity alias10 is
end entity;
package p is
signal s : bit_vector(1 to 3);
alias t : bit_vector(3 downto 1) is s;
end package;
use work.p.all;
architecture test of alias10 is
function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL)
return BIT_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Essentials
-- Module Name: RAM Double Bank
-- Project Name: Essentials
-- Tar... |
-- Signals declaration.\n
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;\n
|
-- Signals declaration.\n
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;\n
|
-- Signals declaration.\n
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;\n
|
-- Signals declaration.\n
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;\n
|
-- Signals declaration.\n
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;\n
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief General Purpose Timers with the AXI4 interface.
---------------------------------------------... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief General Purpose Timers with the AXI4 interface.
---------------------------------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Jun 3 00:16:36 2016
-- Host : Dries007-Arch running 64-bit unknown... |
-------------------------------------------------------------------------------
-- File Name : OutMux.vhd
--
-- Project : JPEG_ENC
--
-- Module : OutMux
--
-- Content : Output Multiplexer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : OutMux.vhd
--
-- Project : JPEG_ENC
--
-- Module : OutMux
--
-- Content : Output Multiplexer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : OutMux.vhd
--
-- Project : JPEG_ENC
--
-- Module : OutMux
--
-- Content : Output Multiplexer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity EqCmpDemo is
port(SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(0 downto 0));
end EqCmpDemo;
architecture Shell of EqCmpDemo is
begin
system_core : entity work.EqCmp4(Behavioral)
port map(input0 => SW(3 downto 0),
input1 =>... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 03/17/2017 11:07:04 AM
-- Design Name: RGB filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Descriptio... |
library ieee;
use ieee.std_logic_1164.all;
use work.exploration_pkg.all;
entity Explorer is port (
currentCell : in integer;
currentOrientation : in real;
currentCellsInView : in gridArray;
numberOfNuggetsToCollect : in integer;
next_goal : out integer);
end Explorer;
architecture explorer of Expl... |
-- $Id: $
-- File name: SpiSlaveFifoRam.vhd
-- Created: 3/17/2012
-- Author: David Kauer
-- Lab Section:
-- Version: 1.0 Initial Design Entry
-- Description: SPI Slave Fifo RAM or Register File (supports overwrite)
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_l... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic := '0';
I_DATA : out std_logic_vector(31 downto 0):=(others... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity DataMemory is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
-- state registers
IN_EX_MM_MemWrite... |
-- $Id: tb_nexys3_fusp_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp_cuff - sim
-- Descrip... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:50:36 05/02/2013
-- Design Name:
-- Module Name: T_flipflop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 02/19/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX4
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This fil... |
entity sub is
port (
a : in bit_vector(1 downto 0);
b, c : out bit_vector(1 downto 0);
d : out bit_vector(1 downto 0) := "00" );
end entity;
architecture test of sub is
begin
p1: (b(0), c(0)) <= a;
p2: (b(1), c(1)) <= a;
p3: d(1) <= '1';
end architecture;
-------------... |
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CSA32bits IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (31 downto 0);
SomaResult: out std_logic_vector (31 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END CSA32bits ;
ARCHITECTURE s... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-----------------------------------------------------------------------------------
--Begin Mips_Proc
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY Mips_Proc IS
PORT( clk_50 : IN STD_LOGIC; -- 50 MHz Clock in
clk : BU... |
component unsaved is
port (
clk_clk : in std_logic := 'X'; -- clk
pc_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
pc_debugaccess : in std_logic := 'X'; -- debugaccess
pc_clken : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity PHPE_CHAN is
port (
RESET: in std_logic;
CLK100: in std_logic;
WB_CLK: in std_logic;
TRAMS: in std_logic;
AREA: in std_logic;
... |
package pkg is
subtype myint is integer range integer'low to 169;
end pkg;
use work.pkg.all;
entity genint is
generic (val : myint := 5);
end genint;
architecture behav of genint is
begin
assert val = -159 or val = 9 severity failure;
end behav;
|
package pkg is
subtype myint is integer range integer'low to 169;
end pkg;
use work.pkg.all;
entity genint is
generic (val : myint := 5);
end genint;
architecture behav of genint is
begin
assert val = -159 or val = 9 severity failure;
end behav;
|
package pkg is
subtype myint is integer range integer'low to 169;
end pkg;
use work.pkg.all;
entity genint is
generic (val : myint := 5);
end genint;
architecture behav of genint is
begin
assert val = -159 or val = 9 severity failure;
end behav;
|
-- A Mealy machine has outputs that depend on both the state and
-- the inputs. When the inputs change, the outputs are updated
-- immediately, without waiting for a clock edge. The outputs
-- can be written more than once per state or per clock cycle.
library ieee;
use ieee.std_logic_1164.all;
entity mealy_4s is
... |
---------------------------------------------------------------------
---- ----
---- OpenCores ATA/ATAPI-5 Host Controller ----
---- PIO Timing Controller (common for all OCIDEC cores) ----
---- ... |
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