content stringlengths 1 1.04M ⌀ |
|---|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** TOP LEVEL ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** TOP LEVEL ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** TOP LEVEL ... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : free_queue
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------... |
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_rx.vhd,v 1.5 2004-10-09 17:05:12 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms... |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: y... |
---------------------------------------------------------------------------------------------
-- Author: Martin Kumm
-- Contact: kumm@uni-kassel.de
-- License: LGPL
-- Date: 03.04.2013
-- Compatibility: Altera Arria I,II,V and Stratix II-V FPGAs
--
-- Description:
-- Implementation... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of fsr is
constant gen_degree : integer := 8;
begin
process(EN,RST,CLK)
constant top_bit: integer := gen_degree-1;
variable content: std_logic_vector(gen_degree-1 downto 0);
variable do_inv: std_logic;
begin
if(EN='1') then
... |
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of fsr is
constant gen_degree : integer := 8;
begin
process(EN,RST,CLK)
constant top_bit: integer := gen_degree-1;
variable content: std_logic_vector(gen_degree-1 downto 0);
variable do_inv: std_logic;
begin
if(EN='1') then
... |
---------------------------------------------------------------
-- Title : Adaption from clk a to clk b
-- Project : A15
---------------------------------------------------------------
-- File : z126_01_clk_trans_wb2wb.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@me... |
package fifo_pkg is
signal sig1 : std_logic;
end package;
package fifo_pkg is
signal sig1 : std_logic;
end package;
|
package fifo_pkg is
signal sig1 : std_logic;
end package;
package fifo_pkg is
signal sig1 : std_logic;
end package;
|
library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
entity l2p_dma_bench is
generic (
constant period : time := 100 ns;
constant axis_data_width_c : integer := 64;
constant wb_address_width_c : integer := 12;
constant wb_data_width_c : integer := 64
);
... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: J.40... |
architecture Struct of PlatformHps is
-- qsys component
component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out ... |
architecture Struct of PlatformHps is
-- qsys component
component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out ... |
-------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre
-- Company : University of Southern California
-- Updated : 03/15/2010
--------------------------------------------------------------------------... |
entity tb_assert3 is
generic (with_err : boolean := False);
end tb_assert3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_assert3 is
signal v : std_logic_Vector (7 downto 0);
signal en : std_logic := '0';
signal res : natural;
begin
dut: entity work.assert3
port map (v, en, res);
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eg_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_grain is
generic (
DEBUG : boolean := false;
FAST : boolean := false
);
end entity;
architecture test of tb_grain is
-- some testvectors:
constant GRAIN_KEY1 : unsigned(79 downto 0) := (others => '0');
constant GRAIN_IV1 : unsigned(... |
-- pwm_generator.vhd
-- Author: Fred
-- Status: Tested and passed
-- This module was based on the pwm module included here:
-- http://www.alteraforum.com/forum/showthread.php?t=45531
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_generator is
port (
clock : in std_logic ... |
-- pwm_generator.vhd
-- Author: Fred
-- Status: Tested and passed
-- This module was based on the pwm module included here:
-- http://www.alteraforum.com/forum/showthread.php?t=45531
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_generator is
port (
clock : in std_logic ... |
-- pwm_generator.vhd
-- Author: Fred
-- Status: Tested and passed
-- This module was based on the pwm module included here:
-- http://www.alteraforum.com/forum/showthread.php?t=45531
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_generator is
port (
clock : in std_logic ... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "SchedulerTemporalPartitioning"
-- Project :
-------------------------------------------------------------------------------
-- File : SchedulerTemporalPartitioning_tb.vhd
-- Author : Chris... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
--
-- Automatically generated
-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output_no_default --config example/input/no_default.ini'
--
-- Do not manually edit!
--
-- VHDL 93
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package example_vhd_pkg is
... |
-- TV Interface Adapter (TIA)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
component soc_design is
port (
fpga_reset_n : in std_logic := 'X'; -- reset_n
ref_clk : in std_logic := 'X'; -- clk
uart_RXD : in std_logic := 'X'; -- RXD
uart_TXD : out std_logic -- TXD
);
end component soc_design;
u0 : component soc_design
port map (
fpga_reset_n => CO... |
component soc_design is
port (
fpga_reset_n : in std_logic := 'X'; -- reset_n
ref_clk : in std_logic := 'X'; -- clk
uart_RXD : in std_logic := 'X'; -- RXD
uart_TXD : out std_logic -- TXD
);
end component soc_design;
u0 : component soc_design
port map (
fpga_reset_n => CO... |
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity boothDecoder is
port(
md : in std_logic_vector(31 downto 0);
decMr : in std_logic_vector(2 downto 0);
out1 : out std_logic_vector(32 downto 0)
);
end boothDecoder;
architecture rtl of boothDecoder ... |
-----------------------------------------------
-- Transmit State Machine --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmit is
generic (
NDBits : natural := 8
);
port (
CLK : in std_logic... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity OR3 is port(
A,B,C: in std_logic;
Z: out std_logic
);
end OR3;
architecture OR3 of OR3 is
begin
Z<=A or B or C;
end OR3; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity OR3 is port(
A,B,C: in std_logic;
Z: out std_logic
);
end OR3;
architecture OR3 of OR3 is
begin
Z<=A or B or C;
end OR3; |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mc6847 is
generic
(
T1_VARIANT : boolean := false;
CVBS_NOT_VGA : boolean := false);
port
(
clk : in std_logic;
clk_ena ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_d_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig... |
----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Main module
-- Authors : Florian Winkler
-- Lust update : 03.09.2017
-- Description : Connects all modules with external stuff (switches, gpio pins, LED's)
-- Furthermore it displays all read sensor values on... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture rtl of fifo is begin
s_foo <= (
item => 12,
another_item => 34
);
proc_label : process is
begin
s_foo <= (
item => 12,
another_item => 34
);
end process proc_label;
s_foo <= ( item1 => 12,
ite... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:20:39 2017
-- Host : Juice-Laptop running 64-bit majo... |
architecture test of test2 is
constant foo : bar := 32d"12345";
begin end;
|
library verilog;
use verilog.vl_types.all;
entity ClientAddrData_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
mergedWrite : in vl_logic;
mergedHsize : in vl_logic_vector(1 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity ClientAddrData_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
mergedWrite : in vl_logic;
mergedHsize : in vl_logic_vector(1 downto 0);
... |
library verilog;
use verilog.vl_types.all;
entity ClientAddrData_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
mergedWrite : in vl_logic;
mergedHsize : in vl_logic_vector(1 downto 0);
... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Soma1 IS
PORT (
CarryIn, val1, val2: IN STD_LOGIC;
SomaResult, CarryOut: OUT STD_LOGIC
);
END Soma1 ;
ARCHITECTURE strc_Soma OF Soma1 IS
BEGIN
SomaResult <= (val1 XOR val2) XOR CarryIn;
CarryOut <= (val1 AND val2) OR (CarryIn AND val1) OR (CarryIn AND val... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity progmem is
port(
clk : in std_logic;
addra : in std_logic_vector(11 downto 0);
ena : in std_logic;
doa : out t_data2;
dib ... |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 19:54:39 03/20/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: uart_tx - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revisio... |
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
p1: process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This fi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity video_dither_tb is
end entity;
-- -----------------------------------------------------------------------
architecture tb of video_dither_tb is
signal clk : std_log... |
------------------------------------------------------------------------------
-- EEPROM.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CH... |
------------------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ************************************... |
library verilog;
use verilog.vl_types.all;
entity ama_accumulator_function is
generic(
width_result : integer := 1;
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
accum_sload_register: string := "UNREGISTERED";
... |
library verilog;
use verilog.vl_types.all;
entity ama_accumulator_function is
generic(
width_result : integer := 1;
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
accum_sload_register: string := "UNREGISTERED";
... |
library verilog;
use verilog.vl_types.all;
entity ama_accumulator_function is
generic(
width_result : integer := 1;
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
accum_sload_register: string := "UNREGISTERED";
... |
library verilog;
use verilog.vl_types.all;
entity ama_accumulator_function is
generic(
width_result : integer := 1;
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
accum_sload_register: string := "UNREGISTERED";
... |
library verilog;
use verilog.vl_types.all;
entity ama_accumulator_function is
generic(
width_result : integer := 1;
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
accum_sload_register: string := "UNREGISTERED";
... |
-------------------------------------------------------------------------------
-- primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary inf... |
-------------------------------------------------------------------------------
-- primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary inf... |
-------------------------------------------------------------------------------
-- primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary inf... |
-------------------------------------------------------------------------------
-- primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary inf... |
use std.env.all;
use std.textio.all;
use work.testbench_utils.all;
use work.csv_file_reader_pkg.all;
-- Testbench for the csv_file_reader_pkg package. Test the package's basic
-- operation by reading data from known test files and checking the values read
-- against their expected values.
entity csv_file_read_... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
-- Modified by Da Cheng in Summer 2010
-------------------------------------------------------------------------------
-- Description:
-- Reorder buffer is to make sure that the instructions commit in order.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOG... |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
begin
end architecture RTL;
|
-------------------------------------------------------------------------------
-- axi_cdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reser... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
-------------------------------------------------------------------------... |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Founda... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ie... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- $Id: bpgenlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: bpgenlib
-- Description: Generic Board/Part c... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: fpga_mem_test_v5_tb
-- Date:2015-01-02
-- Author: Gideon
-- Description: Testbench for FPGA mem tester
---------------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: fpga_mem_test_v5_tb
-- Date:2015-01-02
-- Author: Gideon
-- Description: Testbench for FPGA mem tester
---------------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementMergable2 IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
d : OUT STD_LOGIC;
e : OUT STD_LOGIC;
f : OUT STD_LOGIC
);
END EN... |
-- Program defined by '{psmname}.{psmext}'.
--
-- Generated by {assembler}: 2015-08-26T19:21:35.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UniSim;
use UniSim.vComponents.all;
entity main_Page1 is
port (
Clock : in std_logic;
Fetch : in std_... |
library IEEE;
use IEEE.std_logic_1164.all;
entity top is
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity top;
architecture RTL of top is
begin
inst: entity work.core
port map (
data_i => data_i,
data_o => data_o
);
end architecture RTL;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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