content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer_pkg.vhd,v 1.1 2003/02/18 19:16:01 ostlerf Exp $
-------------------------------------------------------------------------------
-- STEER_TYPES - package
--------------------------------------------------... |
library ieee;
use ieee.numeric_bit.all;
entity not23 is
port (
a_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity not23;
architecture rtl of not23 is
begin
c_o <= not a_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity not23 is
port (
a_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity not23;
architecture rtl of not23 is
begin
c_o <= not a_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity not23 is
port (
a_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity not23;
architecture rtl of not23 is
begin
c_o <= not a_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity not23 is
port (
a_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity not23;
architecture rtl of not23 is
begin
c_o <= not a_i;
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for a_clk
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-con... |
package sumpkg is
end package;
package body sumpkg is
type int_vector is array (natural range <>) of integer;
function sum(a : int_vector) return integer is
variable result : integer := 0;
begin
sumloop: for i in a'range loop
result := result + a(i);
end loop;
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the ... |
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_basic_pat_gen.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file ... |
entity record8 is
end entity;
architecture test of record8 is
type small_int is range 0 to 5;
type sub_rec is record
var : small_int;
end record;
type rec is record
vec : bit_vector(1 to 3);
num : integer;
sub : sub_rec;
end record;
signal r : rec;
begin
... |
entity record8 is
end entity;
architecture test of record8 is
type small_int is range 0 to 5;
type sub_rec is record
var : small_int;
end record;
type rec is record
vec : bit_vector(1 to 3);
num : integer;
sub : sub_rec;
end record;
signal r : rec;
begin
... |
entity record8 is
end entity;
architecture test of record8 is
type small_int is range 0 to 5;
type sub_rec is record
var : small_int;
end record;
type rec is record
vec : bit_vector(1 to 3);
num : integer;
sub : sub_rec;
end record;
signal r : rec;
begin
... |
entity record8 is
end entity;
architecture test of record8 is
type small_int is range 0 to 5;
type sub_rec is record
var : small_int;
end record;
type rec is record
vec : bit_vector(1 to 3);
num : integer;
sub : sub_rec;
end record;
signal r : rec;
begin
... |
entity record8 is
end entity;
architecture test of record8 is
type small_int is range 0 to 5;
type sub_rec is record
var : small_int;
end record;
type rec is record
vec : bit_vector(1 to 3);
num : integer;
sub : sub_rec;
end record;
signal r : rec;
begin
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- $Id: xbic_slave_attach_sngl.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_slave_attach_sngl.vhd
-----------------------------------------------------... |
component clock_control is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component clock_control;
u0 : component clock_control
port map (
inclk => CONNECTED_TO_inclk, -- altclkctrl_input.inclk
ena => CO... |
-- Execute module (implements the data ALU and Branch Address Adder
-- for the MIPS computer)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY Execute IS
PORT( Read_data_1 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Read_data_2 : IN STD_LOGI... |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_propos... |
-------------------------------------------------------------------------------
-- $Id: plbv46_opb_bridge.vhd,v 1.1.2.1 2008/12/19 20:58:34 mlovejoy Exp $
-------------------------------------------------------------------------------
-- plbv46_opb_bridge.vhd - Version v1_00_a
-----------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: plbv46_opb_bridge.vhd,v 1.1.2.1 2008/12/19 20:58:34 mlovejoy Exp $
-------------------------------------------------------------------------------
-- plbv46_opb_bridge.vhd - Version v1_00_a
-----------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dLatch IS
PORT
(
d : IN std_logic;
c : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic
);
END dLatch;
ARCHITECTURE behaviour OF dLatch IS
COMPONENT rs IS
PORT
(
r : IN std_logic;
s : IN std_logic;
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:32 11/20/2016
-- Design Name:
-- Module Name: halfAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dictionary_block_tb is
end dictionary_block_tb;
architecture Behavioral of dictionary_block_tb is
signal clk : std_logic;
signal rst : std_logic;
signal start_search : std_logic := '0';
signal search_entry : std_logic_vector(19 downto 0);
si... |
-- $Id: ibd_m9312.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ibd_m9312 - syn
-- Description: ibus dev: M9312
... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 12/04/2017 08:30:06 AM
-- Module Name: ALU - Behavioral
-- Description:
--
-- Additional Comments: Omitted MULSHU because it is a special snowflake.
--
------------------------------... |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_burst_uncompressor is
generic(
ADDR_W : integer := 16;
BURSTWRAP_W : integer := 3;
BYTE_CNT_W : integer := 4;
PKT_SYMBOLS : integer := 4;
BURST_SIZE_W : integer := 3
);
port(
... |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_burst_uncompressor is
generic(
ADDR_W : integer := 16;
BURSTWRAP_W : integer := 3;
BYTE_CNT_W : integer := 4;
PKT_SYMBOLS : integer := 4;
BURST_SIZE_W : integer := 3
);
port(
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DELAS is port(
D : in std_logic;
E : in std_logic;
PRE : in std_logic;
Q : out std_logic
);
end DELAS;
architecture behavior of DELAS is
signal S : std_logic;
begin
Main : process (D, E, PRE)
begin
if(PRE = '1') then
S <= '1';
elsif(E='1') then
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CONTROLLER is
port(
CLK : in std_logic;
RESET : in std_logic;
TOP : in std_logic;
BOTTOM : in std_logic;
UP : out std_logic
);
end CONTROLLER;
architecture CONTROLLER_BODY of CONTROLLER is
type TYP_STAV is (NAHORU, DOLU);
signal STAV, D... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CONTROLLER is
port(
CLK : in std_logic;
RESET : in std_logic;
TOP : in std_logic;
BOTTOM : in std_logic;
UP : out std_logic
);
end CONTROLLER;
architecture CONTROLLER_BODY of CONTROLLER is
type TYP_STAV is (NAHORU, DOLU);
signal STAV, D... |
-- NEED RESULT: ARCH00183.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183.P3: Multi iner... |
package pkg4 is
type my_arr is array (1 to 2) of bit_vector (7 downto 0);
end pkg4;
use work.pkg4.all;
entity ent4 is
port (v : out my_arr;
b : in bit);
end ent4;
architecture behav of ent4 is
begin
v <= (others => (others => b));
end behav;
entity top4 is
end top4;
use work.pkg4.all;
architecture be... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FtoI is
port (
clk : in std_logic;
f : in std_logic_vector(31 downto 0);
i : out std_logic_vector(31 downto 0));
end FtoI;
architecture dataflow of FtoI is
signal x_len : std_logic_vector(8 downto 0);
sign... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--------------------------------------------------------------------------------
-- Numonyx 128 Mbit EMBEDDED FLASH MEMORY J3 Version D --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> ... |
entity call7 is
end;
architecture behav of call7 is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
function get_str
return string is
begin
return "xaz";
end get_str;
begin
process
begin
check ("bac");
wait for 2 ns;
check (get_str);
report ... |
entity call7 is
end;
architecture behav of call7 is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
function get_str
return string is
begin
return "xaz";
end get_str;
begin
process
begin
check ("bac");
wait for 2 ns;
check (get_str);
report ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- used for address width calculation
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.aua_types.all;
--~ entity instr_cache is
--~ port (
--~ clk : in std_logic;
--~ reset : in std_logic;
--~
--~ -- cache/if
--~ id_instr_add... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Title : Dual-port RAM for WR core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_dpram.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma, CE... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- Title : rot
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
package pkg is
function func (s : string) return natural;
function func2 (s : natural) return natural;
function func3(x : integer) return integer;
end package;
package body pkg is
function func(s : string) return natural is
function inner_func return natural is
begin
return s'length;
end;
b... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:24:24 01/12/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/peripherics/tb_peripherics.vhd
-- Project Name: peripherics
-- Target Device:
-- Tool versions:
-- D... |
package fum is
type fie is protected
impure function foo return integer;
impure function foo(input: real) return integer; -- 4
impure function foo return integer_vector;
impure function foo (input: real) return integer_vector; -- 6
impure function foo (input: integer) retur... |
package fum is
type fie is protected
impure function foo return integer;
impure function foo(input: real) return integer; -- 4
impure function foo return integer_vector;
impure function foo (input: real) return integer_vector; -- 6
impure function foo (input: integer) retur... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY sawtooth_tb IS
END sawtooth_tb;
ARCHITECTURE behavior OF sawtooth_tb IS
COMPONENT sawtooth
PORT(
clk : in std_log... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library ieee;
use ieee.std_logic_1164.all;
entity practica_1 is
port(x, y: in std_logic_vector(1 downto 0);
z: out std_logic);
end practica_1;
architecture concurrente_sdp of practica_1 is
signal s0, s1, s2: std_logic;
signal not_x1, not_x0: std_logic;
begin
inv_0: entity work.not1 port map (x(1), not_x1);
i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/10/2016 02:10:03 AM
-- Design Name:
-- Module Name: calculator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-------------------------------------------------------------------------------
--
-- File: tb_TestConfigRelay.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent In... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_add_header - Behavioral
--
-- Description: Add the TCP header to a data stream
--
---------------------------------------------------------------------------------... |
package pack is
constant x : integer := 10;
end package;
entity e is
end entity;
architecture a of e is
procedure test1 is
constant x : integer := 5;
use work.pack.x; -- OK (work.pack.x is potentially visible and hidden
-- by local x abov... |
----------------------------------------------------------------------------------
-- Thibault Bailly
--
-- create date: 07-03-2017
-- design name:
-- module name: generic_Flip_Flop
-- description: Generic flip flop
--
-- dependencies:
--
-- revision: Initial release
--
-- additional comments:
--
--
--
-- paramete... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.caph_flow_pkg.all;
entity untokenize_flow is
generic(
IMAGE_WIDTH:integer := 320;
IMAGE_HEIGHT:integer := 240;
TOKEN_SIZE: integer := 10;
SIZE:integer:=8
);
port (
clk_caph: in std_logic;
clk_proc: in std_logic... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: Comparador21.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
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