content stringlengths 1 1.04M ⌀ |
|---|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
constant TRFSM0Length : integer := 820;
constant TRFSM0Cfg : std_logic_vector(TRFSM0Length-1 downto 0) := "00011000100000011000111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000000000... |
constant TRFSM0Length : integer := 820;
constant TRFSM0Cfg : std_logic_vector(TRFSM0Length-1 downto 0) := "00011000100000011000111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000000000... |
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in comp... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' t... |
-- Test Bench voor opdracht 3
-- Datum : 18 Mei 2007
-- E.G. van den Bor
-- Hogeschool Utrecht
--
-- In deze testbench worden een aantal constanten aan ingang A en B
-- gegeven.
-- Bij alle combinaties van de Code (deel van een ALU instructie)
-- wordt het resultaat van de aangeboden constanten gecontroleerd.
-- Deze t... |
BuzzerDo_inst : BuzzerDo PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
---- Memory ------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:04:00 11/18/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_18.11.2013/My_32bitOr_tb_948282.vhd
-- Project Name: Mips32_948282_18.11.2013
-- Target Device:
-- T... |
-------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Master_AXI is
generic (
C_MASTER_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
a... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Master_AXI is
generic (
C_MASTER_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
a... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00130
--
-- AUTHOR:
--
-- G. Tomi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:33:48 2015
-- Host : Vangelis-PC running 64-bit major rel... |
-------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <lprs2@rt-rk.com>
--
-- Module Name: top
--
-- Description:
--
-- Simple test for VGA control
--
---------------------------------------------------... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
-- NEED RESULT: ARCH00175.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00175: Old transaction... |
-- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_divide
-- ============================================================
-- File Name: lpm_divide0.vhd
-- Megafunction Name(s):
-- lpm_divide
--
-- Simulation Library Files(s):
-- lpm
-- =================================... |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
architecture RTL of FIFO is
function func1 return integer is
begin
return 0;
end function func1;
function func1 return integer is
begin
return 0;
end function;
function func1 return integer is
begin
return 0;
end func1;
function func1 return integer is
begin
end;
-- Fixes ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Odsek za racunarsku tehniku i medjuracunarske komunikacije
-- Autor: LPRS2 <lprs2@rt-rk.com>
--
-- Ime modula: ti... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- megafunction wizard: %DDR3 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- ddr3ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.09:14:26
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic ... |
-- megafunction wizard: %DDR3 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- ddr3ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.09:14:26
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic ... |
-- megafunction wizard: %DDR3 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- ddr3ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.09:14:26
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr3ctrl1 is
port (
pll_ref_clk : in std_logic ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- FIFO Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprie... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
-- test_ng.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ISSUE438 is
generic(
INFO_SIZE : integer := 1;
INFO_BITS : integer := 8
);
end entity;
architecture MODEL of ISSUE438 is
type INFO_RANGE_TYPE is record
VAL_POS : integer;
DATA_LO... |
entity test is
file foo : bar open qux is "baz";
end;
|
--
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your op... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SevenSegmentDisplayDriver is
Port (entrada: in STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
output8: out STD_LOGIC_VECTOR (7 downto 0));
end SevenSegmentDisplayDriver;
a... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/12/18 18:01:59
-- Nombre del módulo: servo_pwm_clk64kHz - Behavioral
-- Descripción:
-- Unión del controlador de servomotor ... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/12/18 18:01:59
-- Nombre del módulo: servo_pwm_clk64kHz - Behavioral
-- Descripción:
-- Unión del controlador de servomotor ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of mdec_core
--
-- Generated
-- by: wig
-- on: Mon Jun 26 16:38:04 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
--... |
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
--... |
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
--... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- 16-bit Tri-State Buffer
ENTITY tristate_16bit IS
PORT (
input : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
enable : IN STD_LOGIC;
output : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END tristate_16bit;
ARCHITECTURE behavioural OF tristate_16bit IS
BEGIN
PROCESS (input, enabl... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-------------------------------------------------------------------------------
-- axi_cdma_sg_wrap
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserv... |
-----------------------------------------------------------------------------------------------------------
--
-- STICKY STATUS LOGIC
--
-- Once some exceptions occur, corresponding bits are set in the status register. This logic keeps set the
-- status register's flag-field bits until they are modified b... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
--
-- VHDL Architecture lab10_RegFile_lib.RegReadWrite.Mixed
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 07:16:57 04/ 9/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY RegReadWrite IS
GENER... |
entity force1 is
end entity;
architecture test of force1 is
signal s : integer;
signal b : bit;
begin
p1: process is
variable v : integer;
begin
s <= force out 1; -- OK
v <= force out 1; -- Error
s <= force out 1.2; -- Error
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity laplacian_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sparcv8_v6_monociclo is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
alurs : out STD_LOGIC_VECTOR (31 downto 0)
);
end sparcv8_v6_monociclo;
architecture Behavioral of sparcv8_v6_monociclo is
component A... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:49:40 04/09/2017
-- Design Name:
-- Module Name: top_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity e is end entity;
architecture h of e is
type r1 is record a :integer; end record;
type r2 is record b :integer; end record;
type r3 is record a :r1 ; end record;
type r4 is record a :r2 ; end record;
function f(a :integer := 1) return r3 is begin return (a=>(a=>a)); end function;
function f(a... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity foo is
end;
architecture bar of foo is
type bit is ('0','1');
type index is range 3 downto 0;
type bits is array (index) of bit;
signal a : bits;
--signal c : bits;
begin
stim : process
begin
a <= (others => '0');
a <= "0000";
--a <= 0;
--b <= 0;
----c(7 downto 0) <= 0;
----(a, b) <= (0, 0);
... |
library verilog;
use verilog.vl_types.all;
entity execute_port2 is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iFREE_EX : in vl_logic;
iPREVIOUS_EX_ALU2_VALID: in vl_logic;
iPREVIOUS_EX_ALU2_WRITEBACK: in vl_logic;
iP... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll12to40.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- =========================================... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
library IEEE;
use IEEE.std_logic_1164.all;
entity pfb_core_snb is
port (
ce_1: in std_logic;
clk_1: in std_logic;
en_in: in std_logic;
pol0_in: in std_logic_vector(35 downto 0);
pol1_in: in std_logic_vector(35 downto 0);
shift_in: in std_logic_vector(31 downto 0);
sync_in: in std_lo... |
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