content stringlengths 1 1.04M ⌀ |
|---|
entity Jon is
end Jon;
use std.textio.all;
architecture Taylor of Jon is
begin
process is
variable buf:line;
variable s : string(1 to 1);
variable fstatus : file_open_status;
file readfile : text;
constant temp_string : string := "hello.txt";
begin
file_open(fstatus, readfile, temp_string, read_mode);... |
entity Jon is
end Jon;
use std.textio.all;
architecture Taylor of Jon is
begin
process is
variable buf:line;
variable s : string(1 to 1);
variable fstatus : file_open_status;
file readfile : text;
constant temp_string : string := "hello.txt";
begin
file_open(fstatus, readfile, temp_string, read_mode);... |
-- detect_start_of_pulse.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity detect_start_of_pulse is
port (
CLK : in std_logic;
RST : in std_logic;
SYNC ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
END ENTITY test;
ARCHITECTURE rtl OF test IS
TYPE test_data_t IS ARRAY (0 TO 2) OF natural;
TYPE test_vector_t IS ARRAY (0 TO 7) OF test_data_t;
CONSTANT C_TEST_VECTOR : test_vector_t := (OTHERS => test_data_t'(0, 0, 0));
BEGIN
END ARCHITECTURE rtl... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
END ENTITY test;
ARCHITECTURE rtl OF test IS
TYPE test_data_t IS ARRAY (0 TO 2) OF natural;
TYPE test_vector_t IS ARRAY (0 TO 7) OF test_data_t;
CONSTANT C_TEST_VECTOR : test_vector_t := (OTHERS => test_data_t'(0, 0, 0));
BEGIN
END ARCHITECTURE rtl... |
--
-- <counter.vhd>
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
port
(
clk : in std_logic;
rst : in std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end c... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
c <= d;
FOR_LABEL: for i in 0 to 7 generate
end generate;
a <= b;
IF_LABEL : if a = ... |
entity subent is
end entity subent;
architecture subentarch of subent is
signal a : boolean; -- commenting this out eliminates the assertion
begin
proc: process
begin
report "ok";
wait;
end process;
end architecture;
entity issue234 is
end entity issue234;
architecture testarch of issue... |
entity subent is
end entity subent;
architecture subentarch of subent is
signal a : boolean; -- commenting this out eliminates the assertion
begin
proc: process
begin
report "ok";
wait;
end process;
end architecture;
entity issue234 is
end entity issue234;
architecture testarch of issue... |
entity subent is
end entity subent;
architecture subentarch of subent is
signal a : boolean; -- commenting this out eliminates the assertion
begin
proc: process
begin
report "ok";
wait;
end process;
end architecture;
entity issue234 is
end entity issue234;
architecture testarch of issue... |
entity subent is
end entity subent;
architecture subentarch of subent is
signal a : boolean; -- commenting this out eliminates the assertion
begin
proc: process
begin
report "ok";
wait;
end process;
end architecture;
entity issue234 is
end entity issue234;
architecture testarch of issue... |
--! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- 8-bit general purpose shift register (parallel-to-serial and/or serial-to-parallel)
-- Asynchronous reset, falling-edge clk
-- Shifts up (sin => pout(0) => pout(1) etc.)
-- If ld, pin is stored to internal register
-- Else if sh, register is shift... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.0sp1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporat... |
-- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_1_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shifter is
port (
operation : in std_logic_vector(2 downto 0);
bypass : in std_logic := '0';
c_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic... |
-- A single-port 1KiB RAM with synch read as recommended by Xilinx
-- (C) Copyright 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the ... |
-- Copyright 2017 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in w... |
--
-- File: macc.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DSP48E1 is
generic (
SIZE_A : natural := 16;
SIZE_B : natural := 16;
SUB : boolean := false
); port (
clk, ce : in std_logic;
ain ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Innermost procedure
entity test is
end entity test;
architecture test_arch of test is
procedure p1(x1 : in integer) is
variable a1 : integer := 0;
procedure p2 (x2 : in integer) is
begin
a1 := x2;
end procedure p2;
begin
p2(x1);
report ... |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- GPIO block for simple von-Neumann MCU.
------------------------------------... |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- GPIO block for simple von-Neumann MCU.
------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.all;
entity com2 is
end entity com2;
architecture RTL of com2 is
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Compute_Group_tb is
end;
architecture testing of Compute_Group_tb is
component Compute_Group
PORT (
ADDRESS_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : OUT ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Compute_Group_tb is
end;
architecture testing of Compute_Group_tb is
component Compute_Group
PORT (
ADDRESS_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : OUT ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:51:15 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
library ieee;
use ieee.std_logic_1164.all;
entity dff08b is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
en : std_logic;
rst : std_logic);
end dff08b;
architecture behav of dff08b is
signal p : std_logic_vector(7 downto 0) := x"aa";... |
------------ A
------------F B
------------ G
------------E C
------------ D
------------ABCDEFG
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- Hexadecimal to 7 Segment Decoder for LED Display
ENTITY hex_7seg IS
PORT(
hex_digit : IN STD_L... |
-- File name: add_round_key.vhd
-- Created: 2009-03-30
-- Author: Zachary Curosh
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: each byte of the state is combined with the round
-- key; each round key is derived from the cipher key using the
-- key scheduler
use work.aes.al... |
----------------------------------------------------------------------
-- brdRstClk (for Kickstart Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known clock, so o_clk has BRD_OSC_... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/02/2016 06:44:29 PM
-- Design Name:
-- Module Name: generate_spi_clk_0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
--... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dbg_hub_CV is
Port (
sl_iport0_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
sl_iport1_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0_i : in STD_LOGIC_VECTOR ( 16 downto 0 );
sl_oport... |
package nested_pkg is
procedure parent_proc(signal sig : out integer;
var : inout integer);
end package;
package body nested_pkg is
procedure parent_proc(signal sig : out integer; var : inout integer) is
procedure nested_proc is
begin
assert var /= 4;
sig <= var;
... |
package nested_pkg is
procedure parent_proc(signal sig : out integer;
var : inout integer);
end package;
package body nested_pkg is
procedure parent_proc(signal sig : out integer; var : inout integer) is
procedure nested_proc is
begin
assert var /= 4;
sig <= var;
... |
package nested_pkg is
procedure parent_proc(signal sig : out integer;
var : inout integer);
end package;
package body nested_pkg is
procedure parent_proc(signal sig : out integer; var : inout integer) is
procedure nested_proc is
begin
assert var /= 4;
sig <= var;
... |
package nested_pkg is
procedure parent_proc(signal sig : out integer;
var : inout integer);
end package;
package body nested_pkg is
procedure parent_proc(signal sig : out integer; var : inout integer) is
procedure nested_proc is
begin
assert var /= 4;
sig <= var;
... |
package nested_pkg is
procedure parent_proc(signal sig : out integer;
var : inout integer);
end package;
package body nested_pkg is
procedure parent_proc(signal sig : out integer; var : inout integer) is
procedure nested_proc is
begin
assert var /= 4;
sig <= var;
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--Test bench for the SPI_module
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic func... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- William Fan
-- 01/24/2011
-- Finite State Machine RTL
library ieee;
use ieee.std_logic_1164.all;
entity FSMtimedmachine is
generic (fclk: integer := 25;
sclk: integer := 8);
port (clk,stop,rst: in std_logic;
ssd: out bit_vector(6 downto 0));
end FSMtimedmachine;
architecture tm of FSMtimedmachine is
ty... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Input buffer for simulation.
------------------------------------------------------------------------------
library ... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Input buffer for simulation.
------------------------------------------------------------------------------
library ... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Input buffer for simulation.
------------------------------------------------------------------------------
library ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roberts_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity MEMORY is
port (
clk : in std_logic;
we : in std_logic;
re : in std_logic;
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preu... |
library ieee;
use ieee.std_logic_1164.all;
entity clk_res_gen is
port(
clk_50 : out std_logic;
rst : out std_logic
);
end entity clk_res_gen;
architecture RTL of clk_res_gen is
begin
-- This process generates a 50MHz clock signal
p_clk_generate : process
begin
while TRUE loop
clk_50 <= '0';
wai... |
library ieee;
use ieee.std_logic_1164.all;
entity clk_res_gen is
port(
clk_50 : out std_logic;
rst : out std_logic
);
end entity clk_res_gen;
architecture RTL of clk_res_gen is
begin
-- This process generates a 50MHz clock signal
p_clk_generate : process
begin
while TRUE loop
clk_50 <= '0';
wai... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
package char_generator_rom_pkg is
type t_charrom_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant char_rom_array : t_charrom_array(0 to 2047) := (
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00"... |
library ieee;
use ieee.std_logic_1164.all;
package char_generator_rom_pkg is
type t_charrom_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant char_rom_array : t_charrom_array(0 to 2047) := (
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00"... |
library ieee;
use ieee.std_logic_1164.all;
package char_generator_rom_pkg is
type t_charrom_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant char_rom_array : t_charrom_array(0 to 2047) := (
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00"... |
library ieee;
use ieee.std_logic_1164.all;
package char_generator_rom_pkg is
type t_charrom_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant char_rom_array : t_charrom_array(0 to 2047) := (
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00"... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
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