content stringlengths 1 1.04M ⌀ |
|---|
entity array14 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
architecture test of array14 is
-- Reduced from UVVM string_methods_pkg.vhd
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) ... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00349
--
-- AUTHOR:
--
-- G. Tomi... |
-- $Id: nexys2_fusp_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: nexys2_fusp_dummy - syn
-- Description... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ac
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autoge... |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic
) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal cloc... |
entity main is
end entity main;
architecture main of main is
constant CYCLES : integer := 1000;
signal clk : integer := 0;
signal s : integer;
begin
main: process(clk)
variable a : integer;
begin
a := 1;
s <= 1;
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
asser... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
-- Date : Wed Sep 10 03:38:08 2014
-- Host : Dtysky running 64-bit major release ... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- twi_master_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
u... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library osvvm;
context osvvm.OsvvmContext;
entity Stimulus_Response is
generic ( CLK_PERIOD : Time := 20 ns );
port (
NRESET : in std_logic;
CLK : in std_logic;
A : out std_logic
);
end Stimulus_Response;
architecture Behavioral of Stim... |
-- $Id: nexys4dlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: nexys4dlib
-- Description: Nexys 4DDR component... |
-------------------------------------------------------------------------------
-- axi_vdma_sg_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights r... |
-------------------------------------------------------------------------------
-- axi_vdma_sg_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights r... |
-------------------------------------------------------------------------------
-- axi_vdma_sg_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights r... |
-------------------------------------------------------------------------------
-- axi_vdma_sg_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights r... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 17:14:16
-- Design Name:
-- Module Name: input_queue_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 17:14:16
-- Design Name:
-- Module Name: input_queue_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions... |
--------------------------------------------------------------------------------
--
-- Title : ctrl_key_decoder.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : K... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by M... |
-- Descp. mastermind datapath
--
-- entity name: g05_mastermind_datapath
--
-- Version 1.0
-- Author: Felix Dube; felix.dube@mail.mcgill.ca & Auguste Lalande; auguste.lalande@mail.mcgill.ca
-- Date: November 23, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_mastermind_datapath is
port (
P_SEL, G... |
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Devel... |
--=================================================================
-- MEM.VHD :: 8Kx16 RAM model loaded with Hex Format
--
-- (c) Scott L. Baker, Sierra Circuit Design
--=================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.a... |
--=================================================================
-- MEM.VHD :: 8Kx16 RAM model loaded with Hex Format
--
-- (c) Scott L. Baker, Sierra Circuit Design
--=================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.a... |
------------------------------------------------------------------------------
---- ----
---- gmzpu interrupt line component testbench ----
---- ----
----... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_hot is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_hot;
architecture behaviour of mark1_hot is
constant state1: std_logic_vector(14 downto... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_hot is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_hot;
architecture behaviour of mark1_hot is
constant state1: std_logic_vector(14 downto... |
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Sep 20 17:30:09 2017
-- Host : vldmr-PC running 64-bit Service ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity dps_extra_kick is
port(
clk : in vl_logic;
reset : in vl_logic;
phase_done : in vl_logic;
usr_phase_en : in vl_logic;
phase_en : out vl_logic
);
end dps_extra_kick;
|
library verilog;
use verilog.vl_types.all;
entity dps_extra_kick is
port(
clk : in vl_logic;
reset : in vl_logic;
phase_done : in vl_logic;
usr_phase_en : in vl_logic;
phase_en : out vl_logic
);
end dps_extra_kick;
|
library verilog;
use verilog.vl_types.all;
entity dps_extra_kick is
port(
clk : in vl_logic;
reset : in vl_logic;
phase_done : in vl_logic;
usr_phase_en : in vl_logic;
phase_en : out vl_logic
);
end dps_extra_kick;
|
library verilog;
use verilog.vl_types.all;
entity dps_extra_kick is
port(
clk : in vl_logic;
reset : in vl_logic;
phase_done : in vl_logic;
usr_phase_en : in vl_logic;
phase_en : out vl_logic
);
end dps_extra_kick;
|
library verilog;
use verilog.vl_types.all;
entity dps_extra_kick is
port(
clk : in vl_logic;
reset : in vl_logic;
phase_done : in vl_logic;
usr_phase_en : in vl_logic;
phase_en : out vl_logic
);
end dps_extra_kick;
|
clk_40_inst : clk_40 PORT MAP (
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig
);
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1') else'1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1') else'1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1') e... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- David Wolf if12b096
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_bcd is
end tb_bcd;
architecture sim of tb_bcd is
-- Intialisiere das Testobjekt
component bcd
port (
clk : in std_logic;
reset_n : in std_logic;
reset_i : in std_logic; -- ... |
----¼Ä´æÆ÷0£ºÖ¸Áî----
----¼Ä´æÆ÷1£º·µ»ØÖµ=ʶ±ðÍê³É·ñ+ʶ±ð½á¹û----
----¼Ä´æÆ÷2£º³õʼ»¯RAMдÈëÓÃ----
----¼Ä´æÆ÷3£º·µ»ØRAMдÈë״̬----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity LD3320_AXI_v1_0_S00_AXI is
generic (
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
done: out STD_LOGIC... |
----------------------------------------------------------------------
-- IniSftDiv
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Blink some LEDs to show results of initialisation attempts.
--
-- Result :
-- -assignments at declaration time will not work
-- -... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bridge_to_mem_ctrl is
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
nano_addr : in unsigned(7 downto 0);
nano_write : in std_logic;
nano_wdata : in std_logic_vector(15 downto 0);
... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
signal sig1 : std_logic;
constant con1 : std_logic := '0';
file file1 : std_logic;
alias alias1 is name;
begin
end block BLOCK_LABEL;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
package vc707_pack is
constant vc707_default_gpio_width : integer := 8;
end package;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:08:49 10/06/2010
-- Design Name:
-- Module Name: Cont0a5 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- Slave Attachment - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------... |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 12:15:56
-- Nombre del módulo: siete_segmentos_mux - Behavioral
-- Descripción:
-- Multiplexor (de frecuencia) para mo... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 12:15:56
-- Nombre del módulo: siete_segmentos_mux - Behavioral
-- Descripción:
-- Multiplexor (de frecuencia) para mo... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 12:15:56
-- Nombre del módulo: siete_segmentos_mux - Behavioral
-- Descripción:
-- Multiplexor (de frecuencia) para mo... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 12:15:56
-- Nombre del módulo: siete_segmentos_mux - Behavioral
-- Descripción:
-- Multiplexor (de frecuencia) para mo... |
--
-- Written by Ryan Kim, Digilent Inc.
-- Modified by Michael Mattioli
--
-- Description: Top level controller that controls the OLED display.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity oled_ctrl is
port ( clk : in std_logic;
... |
--------------------------------------------------------------------------------
-- Mycron® DDR SDRAM - MT46V32M16 - 8 Meg x 16 x 4 banks --
--------------------------------------------------------------------------------
-- Copyright (C)2012 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> ... |
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity top is
port( clk : in std_logic;
reset : in std_logic;
an : out std_logic_vector(3 downto 0);
disp : out std_logic_vector(6 downto 0);
dp : out std_logic;
ss : out std_logic;
... |
entity sub is
generic ( width : positive );
port (
clk : in bit;
rst : in bit;
vec : out integer_vector(1 to width) );
end entity;
architecture test of sub is
begin
g1: if width = 1 generate
p: process (clk) is
begin
if rst = '1' then
ve... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Main is
port(
-- Gera / Valida. [sel 1]
modo : in std_logic := '0';
-- Seleciona um grupo de até 16 bits. [sel 2 - 5]
k : in std_logic_vector (3 downto 0) := "1000";
-- Seleciona um valor. [sel 6~9]
s : in std_logic... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
-------------------------------------------------------------------------------
-- system_debug_module_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library mdm_v2_10_a;
use mdm_v2_10_a... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity superip_internal is
port(
-- Outputs
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 down... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:23:47 05/01/2011
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/Projects/Personal/Senior Project/FPGA Stuff/OZ4_Mandelbrot/Hardware/OZ4_Mandelbrot/mem_control_TB.vh... |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent I... |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent I... |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent I... |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent I... |
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture rtl of fifo is
signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 dow... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
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