content stringlengths 1 1.04M ⌀ |
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-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adpll_tb is
end entity;
architecture rtl of adpll_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Reference signal frequency 50 kHz
constant REF_PERIOD : time := 1... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:12 2017
-- Host : Juice-Laptop running 64-bit major re... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:12 2017
-- Host : Juice-Laptop running 64-bit major re... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_146 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_146;
architecture augh of cmp_146 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_146 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_146;
architecture augh of cmp_146 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
----------------------------------------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Electrical and Computer Engineering
-- Engineers:
--
-- Create Date: 16:43:51 02/12/2016
-- Design Name:
-- Module Name: RPN_toplevel - Behavioral
-- Project Nam... |
library verilog;
use verilog.vl_types.all;
entity MF_stratixii_pll is
generic(
operation_mode : string := "normal";
pll_type : string := "auto";
compensate_clock: string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done: string := "off";
te... |
-------------------------------------------------------------------------------
-- Digitizer2 acquisition logic test bench
--
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with t... |
entity anon02_sub is
port (i : bit_vector (7 downto 0);
o : out bit_vector (7 downto 0));
end anon02_sub;
architecture behav of anon02_sub is
begin
o <= i xor x"a5";
end behav;
entity anon02 is
port (i : bit_vector (6 downto 0);
o : out bit_vector (6 downto 0));
end anon02;
architecture behav o... |
package test_pkg is
type rec is record
f : integer;
end record;
signal s : rec;
function get_length(
constant msg_id : in natural) return natural;
end package;
package body test_pkg is
function get_length(
constant msg_id : in natural)
return natural is
begin
return 1;
end function;
end p... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:19 03/28/2014
-- Design Name:
-- Module Name: D:/XilinxProject/CPU/shit_tester.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- Th... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in ... |
architecture rtl of fifo is
begin
-- Valid formatting
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
-- Invalid formatting
process
begin
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BlockRamWinner is
Port ( Clock : in STD_LOGIC;
Row : in STD_LOGIC_VECTOR (4 downto 0);
Column : in STD_LOGIC_VECTOR (6 downto 0);
DataOutPixel : out STD_LOGIC
);
end BlockRamWinner;
architecture Behavioral of BlockRamWinner is
... |
library verilog;
use verilog.vl_types.all;
entity lcell is
port(
\in\ : in vl_logic;
\out\ : out vl_logic
);
end lcell;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ha00 is
component and00
port(
Aa: in std_logic ;
Ba: in std_logic ;
Ya: out std_logic );
end component;
component xor00
port(
Ax: in std_logic ;
Bx: in std_l... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity decoder_tb is
end decoder_tb;
architecture Behavior of decoder_tb is
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal I_en: std_logic := '1';
signal I_instr: std_logic_... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: steer_module_write.vhd,v 1.2 2003/03/17 18:31:19 ostlerf Exp $
-------------------------------------------------------------------------------
-- Steer_Module_Write - entity/architecture pair
----------------------... |
library verilog;
use verilog.vl_types.all;
entity arm_control is
port(
inst : in vl_logic_vector(31 downto 0);
reg_we : in vl_logic;
cpsr_out : in vl_logic_vector(31 downto 0);
rd_we : out vl_logic;
pc_we : out ... |
library verilog;
use verilog.vl_types.all;
entity arm_control is
port(
inst : in vl_logic_vector(31 downto 0);
reg_we : in vl_logic;
cpsr_out : in vl_logic_vector(31 downto 0);
rd_we : out vl_logic;
pc_we : out ... |
library verilog;
use verilog.vl_types.all;
entity arm_control is
port(
inst : in vl_logic_vector(31 downto 0);
reg_we : in vl_logic;
cpsr_out : in vl_logic_vector(31 downto 0);
rd_we : out vl_logic;
pc_we : out ... |
-------------------------------------------------------------------------------
-- shift8.vhd - Entity and Architecture
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- shift8.vhd - Entity and Architecture
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
library ieee;
use ieee.std_logic_1164.all;
ENTITY DecodeHex IS
PORT(
BitInput: IN std_logic_vector(3 downto 0);
HexOutput: OUT std_logic_vector(6 downto 0));
END DecodeHex;
ARCHITECTURE Behavior OF DecodeHex IS
BEGIN
WITH BitInput SELECT
HexOutput <= "1000000" WHEN "0000",
"1111001" WH... |
entity test is
end entity;
architecture test of test is
group local_ports is (signal <>); -- OK
signal s : bit;
group local_sigs : local_ports ( s ); -- OK
begin
process is
group some_var is (variable); -- OK
variable v : integer;
group g : some_var (v); -- OK
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/12/2015 08:52:54 PM
-- Design Name:
-- Module Name: RAM_Wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: IMG2.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =================================... |
-- Vhdl test bench created from schematic C:\Users\fafik\Dropbox\infa\git\ethernet\ethernet4b\CU_test1.sch - Sat Aug 30 21:03:36 2014
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that... |
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.types.all;
use work.util.all;
package vdata is
----... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : entity fifo_dsn.1CLK_FIFO
port map (
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_codec is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_codec;
architecture ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_codec is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_codec;
architecture ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_codec is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_codec;
architecture ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_codec is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_codec;
architecture ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_codec is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_codec;
architecture ... |
--
-- This should pass
--| This should pass
----------This should pass
--==================
-- This should fail
--| This should fail
----------This should pass
--
--==================
--¨
-- pragmas should be ignored
--vhdl_comp_off
--vhdl_comp_on
|
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Founda... |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare2.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
--------------------------------------------------------------------------------
-- Author: {user.name} ({user.email})
--
-- Create Date: {time:"%d-%m-%Y"}
-- Module Name: {file}
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:12:43 03/13/2017
-- Design Name:
-- Module Name: /home/julian/Projekt/Xilinx Projects/klein-vhdl/sim/klein-64_tb.vhd
-- Project Name: klein-vhdl
-- Target Device:
-- Tool versions: ... |
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_Std.all;
entity bit_AddDiv2 is
port
(
denominator : out std_logic_vector(15 downto 0) := "0000000000110100";
out_bus : out std_logic_vector(15 downto 0);
in_Bus : in std_logic_vector(... |
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later v... |
----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: ddr3k7-core
-- Module Name: ddr3_write_core - Behavioral
-- Project Name: YARR
-- Target Devices: xc7k160t
-- Tool Versions: Vivado v... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:12:25 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity SpatialAverager is
generic (
DataW : positive
);
port (
RstN : in bit1;
Clk : in bit1;
--
Vsync : in b... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 02/11/2018 03:24:43 PM
-- Module Name: sext - Behavioral
-- Description: Sign extender for immediate values
--
-- Additional Comments:
--
----------------------------------------------------------... |
architecture ARCH of ENTITY is
begin
a <= sig1 when b = '1' else
sig2 when b = '0' else
sig3;
process
begin
d <= sig1 when b = '1' else--This is a comment
sig2 when c = '0' else -- This is a comment
sig3 when d = '1' else
sig4;
end process;
-- Violations bel... |
-- $Id: tbd_serport_uart_rx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eith... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity select... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity select... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity select... |
---------------------------------------------------------------------------
-- Copyright 2015 - 2017 Systems Group, ETH Zurich
--
-- This hardware module is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, ... |
-- NEED RESULT: ARCH00371.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00371: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00371: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport ... |
entity snum05 is
port (ok : out boolean);
end snum05;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum05 is
-- add uns nat
constant a1 : signed (7 downto 0) := x"1d";
constant b1 : signed (3 downto 0) := x"5";
constant r1 : signed (11 downto 0) := a1 * b1;
... |
-- NEED RESULT: ARCH00313: Concurrent procedure call is allowed in a block passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------------------------------------------... |
--------------------------------------------------------------------------
--
-- Engineer: Jeff Gerfen
-- Create Date: 2016.02.26
-- Design Name: db_1shot_fsm
-- Module Name: db_1shot_fsm
--
-- DESCRIPTION:
-- FSM-based debouncer with integrated one-shot output.
-- One-shot output directly follows successfull comple... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity Action is
Generic (
nb_bits_Zone : natural := 8; -- 2^8 = 256 zones différentes
nb_bits_ToolSize : natural := 2; -- tailles d'outils
nb_bits_Color : natural := 12; -- couleur RGB
nb_bits_Tool ... |
--sim_pkg.vhd ---
--
--Filename: sim_pkg.vhd
--Description:
--Author: Oddbjørn Norstrand <gardintrapp@gmail.com>
--Maintainer: Oddbjørn Norstrand <gardintrapp@gmail.com>
--Created: Sat Dec 15 19:00:10 2012 (+0100)
--Version: 0.1
--Last-Updated: Sun Dec 16 17:00:44 2012 (+0100)
-- By: oddbjorn
-- Update #:... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 25-04-2016
-- Module Name: shitf-register.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logi... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity registerFile is
port (
CLK : in std_logic;
W_EN : in std_logic;
INPUT : in std_logic_vector(15 downto 0);
IN_ADR : in std_logic_vector(3 downto 0);
OUT1_ADR: in std_logic_vector(3 downto 0);
OUT2_ADR: in std_logic_vector(3 downto... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 26-04-2016
-- Module Name: p8_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international... |
--
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
-- Rob Gaddi Highland Technology. Inspired SetAlertLogPrefix /... |
--Intertime clock
library ieee;
use ieee.numeric_bit.all;
entity clock_second is
port(clk:in bit ;
second:buffer bit);
end entity clock_second;
architecture Distribution of clock_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
begin
process
begin
wait until clk'event and clk='1';
if coun... |
architecture RTL of FIFO is
begin
process
begin
end process;
process
begin
end postponed process;
-- Violations below
process
begin
end process;
process
begin
end postponed process;
end architecture RTL;
|
-- Adapted from Albert Fazakas who adapted from Alec Wyen and Mihaita Nagy
-- VGA controller sample demo
-- Copyright 2014 Digilent, Inc.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_controller is
Port ( memRead : in STD_LOGIC_VECTOR (7 downto 0)... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00507
--
-- AUTHOR:
--
-- D. Hyma... |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This p... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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