content stringlengths 1 1.04M ⌀ |
|---|
--
--
-- ZPUINO implementation on Gadget Factory 'Papilio Pro' Board
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- Vanilla Variant
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that... |
entity tb is
end;
architecture behav of tb is
begin
b : block
generic (c : natural);
generic map (c => c);
begin
assert true;
end block b;
end behav;
|
entity tb is
end;
architecture behav of tb is
begin
b : block
generic (c : natural);
generic map (c => c);
begin
assert true;
end block b;
end behav;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
--! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Altera
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contai... |
architecture RTL of FIFO is
begin
process is
begin
end process;
process
begin
end process;
-- Violations below
process is begin
end process;
a <= b;
process begin
end process;
b <= z;
end architecture RTL;
|
-- megafunction wizard: %LPM_DECODE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_decode
-- ============================================================
-- File Name: lpm_decode0.vhd
-- Megafunction Name(s):
-- lpm_decode
--
-- Simulation Library Files(s):
-- lpm
-- =================================... |
architecture rtl of fifo is
alias designator IS name;
alias designator IS name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when ... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when ... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when ... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux4x4 is
port(s : in std_logic_vector(1 downto 0);
d0, d1, d2, d3: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end mux4x4;
architecture logic of mux4x4 is
begin
with s select output <= d0 when ... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sat Oct 31 15:04:15 2015
-- Host : cascade.andrew.cmu.edu running 64-bi... |
library verilog;
use verilog.vl_types.all;
entity control_vlg_sample_tst is
port(
d7 : in vl_logic;
d711 : in vl_logic;
d2312 : in vl_logic;
eq : in vl_logic;
rb : in vl_logic;
reset ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This... |
------------------------------------------------------------------------------
--
-- File: AXI_S_to_DPTI_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent In... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
----------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity rcon is port (
next_value : in T_ENABLE; -- to be connected to next_rcon from controller
ctrl_dec : in T_ENCDEC;
reset, clock : in std_logic;
rcon_byte : out std_logic_vector (7 downto 0);
reset_key : in... |
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity rcon is port (
next_value : in T_ENABLE; -- to be connected to next_rcon from controller
ctrl_dec : in T_ENCDEC;
reset, clock : in std_logic;
rcon_byte : out std_logic_vector (7 downto 0);
reset_key : in... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- author: Madhav P. Desai
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Utility_Package.all;
package Vhpi_Foreign is
-----------------------------------------------------------------------------
-- foreign Vhpi function
------------------------------------------------------------------------... |
-----------------------------------------------------------------------------------------------------------
--
-- INTERNAL RESULTS PACKING (AND ROUNDING) LOGIC
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-----------------------------------------------------------------------------------
-- File : Mips (Data) Memory
-- Author : Wolfgang Brandt / Fabian May
-- Company : Technical University Hamburg Harburg Institute of Computer Technology
---------------------------------------------------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.all;
use Std.Textio.all;
use IEEE.std_logic_textio.all;
entity test_ram is
end test_ram;
architecture test_ram of test_ram is
component Ram
generic (width : INTEGER := 16;
ram_select : INTEGER := 4);
port (input1 : in std_logic_Vector((width - 1) downto 0);
in... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
COMPONENT sram_control
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT... |
COMPONENT sram_control
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT... |
COMPONENT sram_control
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
-- Author: Elahe Jalalpour (el.jalalpour@gmail.com)
--
-- Create Date: 27-08-2015
-- Module Name: hea.vhd
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
--
-- $Id: clock_ctrl-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- The clock control unit.
--
-------------------------------------------------------------------------------
configuration t48_clock_ctrl_rtl_c0 of t48_clock_ctrl is
... |
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant a : in integer := 0; signal b : in std_logic := 'X'; variable c : in std_logic := 'X');
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_log... |
-- Test generic clause
package PACK1 is
generic (
-- Test function
pure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
f... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
package PROTOCOL is
-- Design Subtypes
subtype ulogic_QuadWord is std_ulogic_vector (63 downto 0);
subtype ulogic_DoubleWord is std_ulogic_vector (31 downto 0);
subtype ulogic_Word is std_ulogic_vector (15 downto 0);
subtype ulogic_Byte is std_ulogic_vector (7 down... |
-- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free S... |
-- $Id: $
-- File name: tb_XmitSR.vhd
-- Created: 3/2/2012
-- Author: David Kauer
-- Lab Section: 2
-- Version: 1.0 Initial Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_SpiXmitSR is
generic
(
srWidth : integer := 8;
CLK_PERIOD : Time := 10 ... |
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - TOP FILE
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
--------------------------------------------------------------------------------------------
l... |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / ... |
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
--
-- GPIOs on DE0-Nano
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(3 downto 0);
pbs_i : in std_logic_vector(1 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:20:39 2017
-- Host : Juice-Laptop running 64-bit major re... |
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- ... |
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_pat_gen.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
architecture test of test2 is
constant foo : bar := 32sO"12345";
begin end;
|
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------
entity DECODER is
port(OP1,OP2,OP3,OP4: in integer range 0 to 255;
CLOCK: std_logic;
OUTS: out integer range 0 to 1024);
end DECODER;
---------------------... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous to... |
package pkg is
subtype s is integer (0 to 10); -- error
subtype ss is string range 2 to 5; -- error
end package pkg;
|
package pkg is
subtype s is integer (0 to 10); -- error
subtype ss is string range 2 to 5; -- error
end package pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity extimg is
generic(
Ha: integer := 96; -- Hpulse
Hb: integer := 144; -- Hpulse+HBP
Hc: integer := 784; -- Hpulse+HBP+Hactive
Hd: integer := 800; -- Hpulse+HBP+Hactive+HFP
Va: integer := 2; -- Vpulse
Vb: integer := 35; -- Vpulse+VBP
Vc: i... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity blink_10m04 is
Port (
c1_1 : inout std_logic;
c1_2 : inout std_logic;
c1_3 : inout std_logic;
c1_5 : inout std_logic;
c1_6 : inout std_logic;
c1_7 : inout std_logic;
c1_9 : inout std_logic;
c1_10 : inout std_l... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
library verilog;
use verilog.vl_types.all;
entity MF_cycloneiiigl_scale_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
high : in vl_logic_vector(31 downto 0);
low : in vl_lo... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: instruction.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==============... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Pegelgetaktetes D-FF mit Reset
-- Automatenebene, 2-Prozess-Variante
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PDFF_R_RK is
Port ( c : in bit;
D: in bit;
R: in bit; -- Reset
y: out bit;
ny : out bit
);
end PDFF_R_RK;
--
-- Reset via RK ------------------------... |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- expander_tb.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the te... |
library verilog;
use verilog.vl_types.all;
entity div_pipelined_latch is
generic(
N : integer := 4
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE : in vl_logic;
iPREVIOUS_VALID : in vl_logic;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
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