content stringlengths 1 1.04M ⌀ |
|---|
--
-- pciradio.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A
-- Author: Stephen A. Rodgers
--
-- Copyright (c) 2004,2005 Stephen A. Rodgers
--
-- Steve Rodgers <hwstar@rodgers.sdcoxmail.com>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on which ... |
use std.env.all;
entity wave7 is
end entity;
architecture test of wave7 is
signal x : integer;
begin
x <= 1 after 1 ns, 2 after 2 ns, 3 after 4 ns;
process is
begin
wait for 3 ns;
stop;
end process;
end architecture;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture RTL of SPIShifter is
signal EnableShiftReg : STD_LOGIC;
signal ShiftRegister : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal NextShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal LoadShiftReg : STD_LOGIC_VECTOR(DataWidth-1 downto 0);
signal DataInRev : STD_LOGIC_VECTOR(DataWidth-1 dow... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use i... |
--------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity cw_mem is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
OP_CODE_SIZE : integer := 6; -- Op Code Size
CW_SIZE : integer := 13); -- Control Word Size
port (
OPCODE_IN : in std_logic_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity cw_mem is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
OP_CODE_SIZE : integer := 6; -- Op Code Size
CW_SIZE : integer := 13); -- Control Word Size
port (
OPCODE_IN : in std_logic_... |
--
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis jim@synthworks.com
--
--
-- Description:
-- Alert handling and log filtering (verbosi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 02:45:16 PM
-- Module Name: load_store - Behavioral
-- Description: Handles loading, storing, and signalling between core, control, and MMU
--
-- Additional Comments:
-- If storing... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
entity koc_lock is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defin... |
--------------------------------------------------------------------------------
--Author: Jay Aurabind
--Email : aurabindo@computer.org
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.A... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end idreadback;
ar... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
package pkg is
type integer_vector is array (natural range <>) of integer;
type integer_vector_ptr is access integer_vector;
procedure get(variable vec : in integer_vector_ptr; sum : inout integer);
end package;
package body pkg is
procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is
b... |
package pkg is
type integer_vector is array (natural range <>) of integer;
type integer_vector_ptr is access integer_vector;
procedure get(variable vec : in integer_vector_ptr; sum : inout integer);
end package;
package body pkg is
procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is
b... |
package pkg is
type integer_vector is array (natural range <>) of integer;
type integer_vector_ptr is access integer_vector;
procedure get(variable vec : in integer_vector_ptr; sum : inout integer);
end package;
package body pkg is
procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is
b... |
package pkg is
type integer_vector is array (natural range <>) of integer;
type integer_vector_ptr is access integer_vector;
procedure get(variable vec : in integer_vector_ptr; sum : inout integer);
end package;
package body pkg is
procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is
b... |
package pkg is
type integer_vector is array (natural range <>) of integer;
type integer_vector_ptr is access integer_vector;
procedure get(variable vec : in integer_vector_ptr; sum : inout integer);
end package;
package body pkg is
procedure get(variable vec : in integer_vector_ptr; sum : inout integer) is
b... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
constant CFG_CLK_NOFB : intege... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
constant CFG_CLK_NOFB : intege... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
constant CFG_CLK_NOFB : intege... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
constant CFG_CLK_NOFB : intege... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
constant CFG_CLK_NOFB : intege... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
constant CFG_CLK_NOFB : intege... |
architecture rtl of fifo is
begin
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow);
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow);
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => un... |
--
-- This file is part of the lafw16 project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your op... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
Port ( button : in std_logic;
LED : out std_logic);
end test;
architecture Behavioral of test is
begin
LED <= button;
end Behavioral;
|
lpm_divide0_inst : lpm_divide0 PORT MAP (
denom => denom_sig,
numer => numer_sig,
quotient => quotient_sig,
remain => remain_sig
);
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
generic( W : natural := 4 );
port (i_data_a : in std_logic_vector(W-1 downto 0); -- input data A
i_data_b : in std_logic_vector(W-1 downto 0); -- input data B
i_data_carry : in std_logic; ... |
---- Controller --------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------... |
package foo is
-- Declaration
attribute LOCATION: COORDINATE;
attribute PIN_NO: POSITIVE;
-- Specification
attribute PIN_NO of CIN: signal is 10;
attribute PIN_NO of COUT: signal is 5;
attribute LOCATION of ADDER1: label is (10,15);
attribute LOCATION of others: label is (25,77);
attribute CAPACITANCE of all:... |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ConstRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CDiv IS
PORT ( Cin : IN std_logic ;
Cout : OUT std_logic ) ;
END CDiv ;
ARCHITECTURE Behavior OF CDiv IS
constant TC: integer := 12; --Time Constant
signal c0,c1,c2,c3: integer range 0 to 1000;
signal D: std_logic := '0';
BEGIN
PROCESS(Cin)
B... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mc6847_ntsc is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of mc6847_ntsc is
signal rom_addr : std_logic_vect... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mc6847_ntsc is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of mc6847_ntsc is
signal rom_addr : std_logic_vect... |
ARCHITECTURE RTL of ENT is
begin
end;
ARCHITECTURE RTL of ENT is
begin
end;
ARCHITECTURE RTL of ENT is
begin
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:01 10/23/2013
-- Design Name:
-- Module Name: practica1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
---- ----
---- I2C Master Testbench ----
---- ----
----... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Thu Mar 10 15:45:23 2016
--Host : minmi running 64-bit elementary OS Freya
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity I2C_ADN2816 is
port (clk_i : in std_logic;
sub_i2c_i: in std_logic;
reset_n_i : in std_logic;
sda_o : out std_logic;
sda_dir_o : out std_logic;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity I2C_ADN2816 is
port (clk_i : in std_logic;
sub_i2c_i: in std_logic;
reset_n_i : in std_logic;
sda_o : out std_logic;
sda_dir_o : out std_logic;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : ou... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Sumador is
Port ( Operador1 : in STD_LOGIC_VECTOR (31 downto 0);
Operador2 : in STD_LOGIC_VECTOR (31 downto 0);
Resultado : out STD_LOGIC_VECTOR (31 downto 0));
end Sumador;
architecture Behavioral of suma... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Sumador is
Port ( Operador1 : in STD_LOGIC_VECTOR (31 downto 0);
Operador2 : in STD_LOGIC_VECTOR (31 downto 0);
Resultado : out STD_LOGIC_VECTOR (31 downto 0));
end Sumador;
architecture Behavioral of suma... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity iq_ram is
generic (
DATA_SIZE : integer := 16;
ADDR_SIZE : integer := 13;
AXI_SIZE : integer := 32
);
port (
-- AXi
clk : in std_logic;
rst : in std_logic;
axi_addr : in std_l... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:08:42 06/06/2016
-- Design Name:
-- Module Name: C:/Users/AlvaroMoreno/Desktop/PROCESADOR2016/Sacagawea-master/test_memes.vhd
-- Project Name: Sacagawea
-- Target Device:
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logi... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart is
PORT( CLK_I : in ... |
-- a_ng.vhd
package TEST_TYPES is
type WIDTH_TYPE is record
DATA : integer;
end record;
end package;
use work.TEST_TYPES.all;
entity TEST_SUB is
generic (
WIDTH : WIDTH_TYPE
);
port (
DATA_I : in bit_vector(WIDTH.DATA-1 downto 0);
DATA_O : out bit_vector(WIDTH... |
-- a_ng.vhd
package TEST_TYPES is
type WIDTH_TYPE is record
DATA : integer;
end record;
end package;
use work.TEST_TYPES.all;
entity TEST_SUB is
generic (
WIDTH : WIDTH_TYPE
);
port (
DATA_I : in bit_vector(WIDTH.DATA-1 downto 0);
DATA_O : out bit_vector(WIDTH... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity filter_with_file_write is
port( data_ext: in std_logic_vector( 7 downto 0);
clock, start, rst: in std_logic;
mem_b_out: out std_logic_vector( 7 downto 0);
done: ou... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:59 05/12/2014
-- Design Name:
-- Module Name: encoder_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:59 05/12/2014
-- Design Name:
-- Module Name: encoder_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *****************... |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *****************... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library IEEE, LFSR;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------------------------
entity pulse_shreg is
generic (
G_period : natural := 10000
);
port(
CLK : in std_logic;
RESET : i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity guarded_fifo is
generic (
depth : integer;
bit_width : integer
);
port (
-- fast side interface
clk_fast_i : in std_logic;
rst_fast_i : in std_logic;
push_i : in std_logic;
full_o : out std_logic;... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --lo... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --lo... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --lo... |
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