content stringlengths 1 1.04M ⌀ |
|---|
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
e... |
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
e... |
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
e... |
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
e... |
use std.textio.all;
entity sliding_index is
end entity;
architecture foo of sliding_index is
type integer_vector is array (natural range <>) of integer;
function to_string(inp: integer_vector) return string is
variable retn: line;
begin
for i in inp'range loop
if i = inp'RI... |
use std.textio.all;
entity sliding_index is
end entity;
architecture foo of sliding_index is
type integer_vector is array (natural range <>) of integer;
function to_string(inp: integer_vector) return string is
variable retn: line;
begin
for i in inp'range loop
if i = inp'RI... |
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: modulo2Hz.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms o... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ctl_unit is
port(clk : in std_logic;
rst : in std_logic;
instruction_in : in std_logic_vector(11 downto 0);
instruction_addr : o... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Title : Whisbone Bus Interconnection
-- Project :
--------------------------------------------------------------------------------
-- File : wb_bus.vhd
-- Author ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
entity test is
subtype t is foo(open)(bar);
end;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
library ieee;
use ieee.std_logic_1164.all;
use work.MIPS_lib.all;
entity main_control is
port(
op_code : in std_logic_vector(5 downto 0);
RegDst : out std_logic;
ALUsrc : out std_logic;
RegWrite : out std_logic;
ALUOp : out std_logic_vector(2 downto 0);
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@... |
--
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of ... |
architecture rtl of fifo is
begin
process
begin
var1 := '0'when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0'when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' else '1';
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity regtable is
port (
clk : in std_logic;
rst : in std_logic;
raddrA : in std_logic_vector(4 downto 0);
raddrB : in std_logic_vector(4 downto 0);
wen : in std_logic;
waddr : in std_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
---------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
---------------------------------------------------------... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:45:28 2019
-- Host : varun-laptop running 64-bit Service ... |
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--**************************************************... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_Memory is
End Entity test_Memory;
Architecture test_general of test_Memory is
Component Mips8B_Core is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MA... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEUDisp22 is
Port ( Disp22 : in STD_LOGIC_VECTOR(21 downto 0);
S : out STD_LOGIC_VECTOR(31 downto 0)
);
end SEUDisp22;
architecture Behavioral of SEUDisp22 is
begin
process(Disp22)
begin
for i in 22 to 31 loop
S(i)<=Disp22(21);
end ... |
library ieee;
use ieee.std_logic_1164.all;
entity output06 is
port (i : std_logic;
o : out std_logic_vector (3 downto 0));
end output06;
architecture behav of output06 is
signal s : std_logic_vector(3 downto 0);
begin
process (i)
begin
s(0) <= i;
s (1) <= not i;
s (3) <= i;
end process;
... |
-- hdlctransmitter.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "txLast" set.
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity HdlcTransmitter is
generic (
TxReqChai... |
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:35:21 02/23/2009
-- Design Name:
-- Module Name: VideoTimingCtl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: VideoTi... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyri... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:56:43 10/15/2015
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
--type sequential32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 ... |
----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/6/14
--Last Modified: 1/22/15
--
--
--Version: 1.2
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.a... |
-------------------------------------------------------------------------------
--
-- T48 Microcontroller Core
--
-- $Id: t48_core-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-------------------------------------------------------------------------------
configuration t48_core_struct_c0 of t48_core is
for struc... |
--------------------------------------------------------------
------------------------------------------------------------
-- clock_signal_per_second.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ie... |
-- Acorn Electron for the Altera/Terasic DE1
--
-- Copright (c) 2015 David Banks
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the abo... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
-------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
entity external is
end entity;
architecture test of external is
begin
main: process is
variable i : integer;
begin
i := <<signal foo.bar : integer>>; -- OK
i := << constant x.y.z : integer >>; -- OK
i := <<variable aye.bee : integer>>; -- OK
i := << constant .x.y.z :... |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMonGODIL.vh... |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMonGODIL.vh... |
-- This is an implementation of ieee.std_logic_1164 based only on the
-- specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software... |
-- This is an implementation of ieee.std_logic_1164 based only on the
-- specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software... |
-------------------------------------------------------------------------------
-- Title : An Wishbone delay buffer
-- Project : General Cores Library (gencores)
-------------------------------------------------------------------------------
-- File : xwb_crossbar.vhd
-- Author : Wesley W. Terpstra
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_mb_700a is
generic (
g_acia : boolean := true;
g_eeprom : boolean := false;
g_dual_drive : boolean := false );
port (
CLOCK : ... |
--! @file automatic_tb.vhd
--!
--! @authors Salvatore Barone <salvator.barone@gmail.com> <br>
--! Alfonso Di Martino <alfonsodimartino160989@gmail.com> <br>
--! Sossio Fiorillo <fsossio@gmail.com> <br>
--! Pietro Liguori <pie.liguori@gmail.com> <br>
--!
--! @date 05 07 2017
--!
--! @copyright
--! Copyright 20... |
------------------------------------------------------------------------------
--
-- File: axi_dpti_v1_0.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block6.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- --------------------... |
-- Para recibir datos. Bit RxRdy = 1 cada vez que leyó todos los bits de un dato
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic (
F : natural := 50000; -- Device clock frequency [KHz]: 50 MHz
min_baud : natural := 1200;
num_data_bits : natural ... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
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