content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- Title : Testbench for design "beacon_robot"
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyrigh... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory_control is
port (clk : in std_logic;
rst : in std_logic;
cpu_vid : in std_logic;
cpu_data : in std_logic_vector(15 downto 0);
cpu_addr : in std_logic_vector(22 ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:31:35 09/02/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/P05_DM74LS151/DM74LS151_tb.vhd
-- Project Name: P05_DM74LS151
-- Target Device:
-- Tool versions:
-- Description:... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:31:35 09/02/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/P05_DM74LS151/DM74LS151_tb.vhd
-- Project Name: P05_DM74LS151
-- Target Device:
-- Tool versions:
-- Description:... |
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 19:29:54 05/09/2016
-----------... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: Hamming_tests.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK ... |
library ieee;
use ieee.std_logic_1164.all;
entity func03 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end func03;
architecture behav of func03 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (len - 1 downto 0);
be... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- $Id: ipif_control_rd.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--ipif_control_rd.vhd
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ipif_control_rd.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--ipif_control_rd.vhd
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:59:58 11/21/2015
-- Design Name:
-- Module Name: parte_operativa - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
-------------------------------------------------------------------
--
-- Fichero:
-- damero.vhd 12/7/2013
--
-- (c) J.M. Mendias
-- Diseño Automático de Sistemas
-- Facultad de Informática. Universidad Complutense de Madrid
--
-- Propósito:
-- Muestra un damero sobre un monitor compatible VGA
--
-- ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : clk_gen.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_bb
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !... |
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Testbench
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standar... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
p1: process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------------
--state machine:
--1) idle: wait for the period to start the ping sensing
--2) trigger: send the 10us trigger pulse
--3) wait echo: wait for the echo high edge, if timeout_cnt reaches 50ms, restart
--4) echo count: echo rising ed... |
------------------------------------------------------------------------------------
--state machine:
--1) idle: wait for the period to start the ping sensing
--2) trigger: send the 10us trigger pulse
--3) wait echo: wait for the echo high edge, if timeout_cnt reaches 50ms, restart
--4) echo count: echo rising ed... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
-- NEED RESULT: ARCH00631: Index constraints passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05:33:07 11/13/2013
-- Design Name:
-- Module Name: D:/Programming/gitHub/cg3207-proj/IF_test.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 05:22:49 2017
-- Host : DESKTOP-B1QME94 running 64-bit major... |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonALS.vhd... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
package p is
type int_ptr is access integer; -- OK
type bad1 is access foo; -- Error
type rec;
type rec_ptr is access rec;
type rec is record
value : integer;
link : rec_ptr;
end record;
type int_vec is array (integer range <>) of integer;
type int_... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity SRAM is
Port ( ADDR : in std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
OE : in std_logic;
WE : in st... |
-------------------------------------------------------------------------------
-- The following entity is automatically generated by Quartus (a megafunction).
-- As Altera DE1 board does not have a 25.175 MHz, but a 27 Mhz, we
-- instantiate a PLL (Phase Locked Loop) to divide out 27 MHz clock
-- and reach a satisfiab... |
-- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO... |
-- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO... |
-- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00187
--
-- AUTHOR:
--
-- G. Tomi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM1 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;... |
entity aggr1 is
end aggr1;
architecture behav of aggr1 is
procedure proc (b, c : out bit_vector) is
begin
b := (others => '0');
c := ('1', others => '0');
end proc;
begin
end behav;
|
entity aggr1 is
end aggr1;
architecture behav of aggr1 is
procedure proc (b, c : out bit_vector) is
begin
b := (others => '0');
c := ('1', others => '0');
end proc;
begin
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Entity of authenticated encryption unit.
--!
--! Entity for dummy1 core
--!
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages :... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (... |
-- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or info... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
... |
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
... |
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
... |
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
... |
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity preamp_config is
port(
preamp_done: out std_logic;
send_data: in std_logic;
busy: out std_logic;
gain_in: in std_logic_vec... |
entity e is
end entity;
architecture a of e is
signal x : real := 1.234; -- OK
type my_real is range 0.0 to 1.0; -- OK
begin
process is
variable v : my_real;
begin
x <= x + 6.1215; -- OK
x <= v; -- Error
end process;
... |
architecture RTL of FIFO is
begin
-- These are passing
SIG_LABEL : postponed a <= b;
SIG_LABEL : postponed a <= when c = '0' else '1';
SIG_LABEL : postponed with z select
a <= b when z = "000",
c when z = "001";
-- Failing variations
SIG_LABEL : postponed a <= b;
SIG_LABEL : postpo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
package test_pkg is
type t_sf_array is array (natural range <>) of sfixed;
impure function do_something(samples : integer; ret_type : sfixed) return t_sf_array;
end package;
package body test_pkg is
imp... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Dynamic adder/subtractor
-- Project :
-------------------------------------------------------------------------------
-- File : addsub.vhd
-- Author : Aylons <concordic@aylons.com>
-- Company :
-- Created ... |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal v : std_logic_vector (31 downto 0);
begin
dut: entity work.ent
port map (clk => clk, o => v);
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity FPMultiply is
port( A_in : in std_logic_vector(31 downto 0);
B_in : in std_logic_vector(31 downto 0);
R : out std_logic_vector(31 downto 0));... |
-- NEED RESULT: ARCH00430: String literals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:03 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- $Id: rb_mon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
entity proc1 is
end;
use work.pkg.all;
architecture behav of proc1 is
procedure proc (v : inout rec) is
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
end pro... |
entity proc1 is
end;
use work.pkg.all;
architecture behav of proc1 is
procedure proc (v : inout rec) is
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
end pro... |
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