content stringlengths 1 1.04M ⌀ |
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--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: timer
-- Date:2015-02-19
-- Author: Gideon
-- Description: Generic timeout timer
--------------------------------------------------------------------------------
library ie... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: timer
-- Date:2015-02-19
-- Author: Gideon
-- Description: Generic timeout timer
--------------------------------------------------------------------------------
library ie... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
ENTITY demo_make_map IS
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
PORT (clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
eaten : STD_LOGI... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
--
-- LoopCheck
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity LoopCheck is
generic (
DWIDTH : positive:=8 -- Data width
);
port (
--... |
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a... |
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a... |
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
package OV76X0Pack is
constant SccbAddrW : positive := 8;
constant SccbDataW : positive := 8;
constant SramDataW : positive := 16;
constant SramAddrW : positive := 18;
constant Pix... |
-- Configurable FIR operating on 4 round robin multiplexed channels.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity quadfir is
generic(acc_width : integer;
out_width : integer;
differentiate : boolean;
index_sample_strobe : ... |
--!
--! Copyright 2020 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity busgate4 is
port(
in_bus: in std_logic_vector(3 downto 0);
is_enabled: in std_logic;
out_bus: out std_logic_vector(3 downto 0)
);
end;
architecture logic of busgate4 is
signal tmp_enabled: std_lo... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split0 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split0 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w... |
entity tb_iassoc01 is
end tb_iassoc01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc01 is
signal a : natural;
signal b : natural;
signal res : natural;
begin
dut: entity work.iassoc01
port map (a, b, res);
process
begin
a <= 1;
b <= 5;
wait for 1 ns;
asser... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:49 11/21/2015
-- Design Name:
-- Module Name: FSM_robot - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-- NEED RESULT: ARCH00697: Positional and named associations in same association list passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-- $Id: ib_sel.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ib_sel - syn
-- Description: ibus: address select l... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phase_acc is
generic(
sine_length_bits: integer := 10
);
port(
x_out: out std_logic_vector(sine_length_bits - 1 downto 0);
freq_mult: in std_logic_vector(9 downto 0);
phase_in: in std_logic_vector(7 downto 0);
new_signal: out std_... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
END package body fifo_pkg;
|
-- NEED RESULT: ARCH00184.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P3: Multi iner... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 259]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE.... |
-- 16 Bit Adder --
--
-- A Full 16 bit adder
-- Requires: bitadder_1.VHDL
--
-- Author: Colton Schmidt
-- Last Edited: 18/10/2015
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provid... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator... |
component add
generic (
WIDTH : integer := 3;
HEIGHT : integer := 2
);
port (
clk : in std_logic;
in : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0)
);
end component add;
|
-------------------------------------------------------------------------------
-- Title : Generic clock divider
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.... |
------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/21 23:26:37 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: aurora_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.3 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
-... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/21 23:26:37 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: aurora_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.3 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
-... |
-- nios_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : inte... |
-- nios_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : inte... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_640x480 is
Port ( clk, clr : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
hc : out STD_LOGIC_VECTOR(9 downto 0);
vc : out STD_LOGIC_VECTOR(9 downto 0)... |
-------------------------------------------------------------------------------
--! @file lutFileRtl.vhd
--
--! @brief Look-up table file implementation
--
--! @details This look-up table file stores initialization values (generics)
--! in LUT resources.
-----------------------------------------------------------------... |
-- clkgen_tb.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clkgen_tb is
end entity;
architecture testbench of clkgen_tb is
signal clk_0 : std_logic;
signal... |
use Std.Textio.all;
library IEEE;
library worklib;
use ieee.std_logic_1164.ALL;
entity test_c_subtractor
is end;
architecture test_c_subtractor of test_c_subtractor is
component c_subtractor
generic(width: integer := 4);
port(input1, input2: in std_logic_vector((width-1) downto 0);
output : out std_lo... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 12:04:52 09/17/2014
-- Design Name:
-- Module Name: H:/embedded_labs/comp/tb_comp.vhd
-- Project Name: comp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL T... |
-- Testbench for com5402_wrapper
--
-- * ARP requests
-- * broadcast udp rx
-- * unicast udp rx
-- * unicast udp rx filtering
-- * udp tx with NACK from ComBlock
-- * tcp conneciton establish
-- * tcp tx with tready deasserting
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library i... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
package test_pkg is
type t_test is (ONE, TWO);
end package;
package test2_pkg is
alias t_test is work.test_pkg.t_test;
end package;
use work.test_pkg.all;
use work.test2_pkg.all;
entity test is
generic(
test_type : t_test := ONE
);
end entity test;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package poly is
generic (a, b : integer);
function apply (x : integer) return integer;
end package;
package body poly is
function apply (x : integer) return integer is
begin
return x * a + b;
end function;
end package body;
------------------------------------------------------------------... |
library ieee;
package body fifo_pkg is
end package body;
-- Violation below
package body fifo_pkg is
end package body;
-- Comments could be allowed
library ieee;
package body fifo_pkg is
end package body;
entity fifo is
end entity fifo;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------------------------------------
-- Extender
-- This unit recieves as input the immediate filed in the instruction(15-0). Depending on the value of the
-- control signal Unsigned_value it performs and unsigned sing-extension or a signed sig... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D4_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D4_C1;
architecture D4_C1 of D4_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
i... |
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mixed_clock_fifo_regbased_tb is
end mixed_clock_fifo_regbased_tb;
architecture TB_ARCHITECTURE of mixed_clock_fifo_regbased_tb is
-- Component declaration of the tested unit
component ... |
-- $Id: rlink_mon_sb.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
-------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the ALU core plus the Accumulator and the Temp Reg.
--
-- $Id: alu-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All r... |
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
process
begin
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
archit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
archit... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Testbench for design HDLC Busmaster
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
-----------------------... |
-- Twofish_ecb_tbl_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any lat... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted pr... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted pr... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted pr... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted pr... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted pr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end testbench;
architecture test of testbench is
constant clkPeriod : time := 100 ns;
signal simulationFinished : std_logic := '0';
component Function_Z3fooi is
port
(
clk : in std_logic;
reset : in std_logic;
in... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PC_override : in vl_logic;
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vecto... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PC_override : in vl_logic;
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vecto... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PC_override : in vl_logic;
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vecto... |
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