content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_528 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_528;
architecture augh of sub_528 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_528 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_528;
architecture augh of sub_528 is
signal carry_inA : std_l... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_si... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00238
--
-- AUTHOR:
--
-- A. Wilm... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-------------------------------------------------------------------------------
--
-- Title : fp23_float2fix
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : Float fp23 to signed fix ... |
-- David Wolf if12b096
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_cntr is
end tb_cntr;
architecture sim of tb_cntr is
component cntr
port (
clk50 : in std_logic; -- Takt
reset_n : in std_logic; -- Externer Reset
ctup_i : in std_logic; --... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
------------------------------------------------------------------------------
---- ----
---- zwishbone DECODE component testbench ----
---- ----
----... |
-- NEED RESULT: ARCH00672: Signal default initial values - generic subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ba
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must... |
library ieee;
use ieee.std_logic_1164.all;
package sync_pkg is
component sync is
generic
(
SYNC_STAGES : integer range 2 to integer'high;
RESET_VALUE : std_logic
);
port
(
sys_clk : in std_logic;
sys_res_n : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end ... |
library ieee;
use ieee.std_logic_1164.all;
package sync_pkg is
component sync is
generic
(
SYNC_STAGES : integer range 2 to integer'high;
RESET_VALUE : std_logic
);
port
(
sys_clk : in std_logic;
sys_res_n : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end ... |
entity e is end entity;
architecture a of e is
signal bar, boo : integer;
function func (x : integer; b : boolean) return boolean;
function func return integer;
procedure proc (x : integer);
procedure proc;
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer,... |
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESU... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_469 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_469;
architecture augh of mul_469 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_469 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_469;
architecture augh of mul_469 is
signal tmp_res : signed(... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Multisalida is
Port (
aa: in std_logic;
bb: in std_logic;
cc: in std_logic;
dd: in std_logic;
s1: out std_logic;
s2: out std_logic;
s3: out std_logic
);
end Multisalida;
a... |
---------------------------------------------------------------------------
-- NES-Controller Module
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- ilovespeccy@speccyland.net
-- Project home... |
---------------------------------------------------------------------------
-- NES-Controller Module
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- ilovespeccy@speccyland.net
-- Project home... |
entity call1 is
end;
use work.pkg.all;
architecture behav of call1 is
function func return rec is
variable res : rec_4;
begin
return res;
end func;
begin
process
variable v : rec_4 := func;
begin
wait;
end process;
end behav;
|
entity call1 is
end;
use work.pkg.all;
architecture behav of call1 is
function func return rec is
variable res : rec_4;
begin
return res;
end func;
begin
process
variable v : rec_4 := func;
begin
wait;
end process;
end behav;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:43:54 12/25/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_roundcounter.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:43:54 12/25/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_roundcounter.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:06 08/14/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac3/test_bcd_1_adder.vhd
-- Project Name: prac3
-- Target Device:
-- Tool versions:
-- Descri... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:06 08/14/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac3/test_bcd_1_adder.vhd
-- Project Name: prac3
-- Target Device:
-- Tool versions:
-- Descri... |
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;... |
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;... |
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;... |
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;... |
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:23:48 10/19/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/cap_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:23:48 10/19/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/cap_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:23:48 10/19/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/cap_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:19:56 2017
-- Host : Juice-Laptop running 64-bit majo... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:17 2017
-- Host : GILAMONSTER running 64-bit major rel... |
--
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure f... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 1 for USB host
--------------------------------------------------------------------------------
libr... |
library verilog;
use verilog.vl_types.all;
entity IF_ID_Seg is
port(
Clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
PC_Add : in vl_logic_vector(31 downto 0);
IR_out : in vl_logic_vector(31 dow... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:40 04/04/2014
-- Design Name:
-- Module Name: amplitude_adjust - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-----------------------------------------------------------------------------------------
-- Generated by WISHBONE Builder. Do not edit this file.
--
-- For defines see wb_devices.defines
--
-- Package: WBDevInterconPkg (WBDevIntercon_package.vhdl)
--
-- Generated Tue May 30 10:23:57 2017
--
-- Wishbone masters:
-- c... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram2_N_Demo is
port( KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(3 downto 0));
end Ram2_N_demo;
architecture Structural of Ram2_N_Demo is
begin
ram: entity work.Ram2_... |
-- Dynamic Partial Reconfiguration
constant CFG_PRC : integer := CONFIG_PARTIAL;
constant CFG_CRC_EN : integer := CONFIG_CRC;
constant CFG_EDAC_EN : integer := CONFIG_EDAC;
constant CFG_WORDS_BLOCK : integer := CONFIG_BLOCK;
constant CFG_DCM_FIFO : integer := CONFIG_DCM_FIFO;
constant CFG_DPR_FIFO : integer... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------... |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- ram_control.vhd
--
--
-- Memory arbitrator. Handle access to memory. Control the FIFOs in other modules
-- Incorporates SDRAM cont... |
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute i... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity bistableelement_tb is
end bistableelement_tb;
architecture TB_ARCHITECTURE of bistableelement_tb is
-- Component declaration of the tested unit
component bistableelement
port(
Q : out STD_LOGIC;
... |
entity FIFO is
port ( );
end entity FIFO;
entity FIFO is
port (
);
end entity FIFO;
entity FIFO is
port
(
)
;
end entity FIFO;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package utils_pkg is
-- Calculates the number of bits required to encode the given number
--
-- Note that this function is not intended to synthesize directly into
-- hardware, rather it is used to generate const... |
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