content stringlengths 1 1.04M ⌀ |
|---|
library verilog;
use verilog.vl_types.all;
entity transmit_test_entity is
port(
clk_in : in vl_logic;
reset_n : in vl_logic;
Sample_Gate : out vl_logic;
P : out vl_logic_vector(15 downto 0);
N : out vl_logic_ve... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: DEBOUNCER
-- AUTHORS: Jakub Cabal <xcabal05@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, please read LI... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw
--
-- Desc... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw
--
-- Desc... |
--! @file GPIOarray.vhd
--! @author Salvatore Barone <salvator.barone@gmail.com>
--! @date 07 04 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <salvator.barone@gmail.com>
--!
--! This file is part of Zynq7000DriverPack
--!
--! Zynq7000DriverPack is free software; you can redistribute it and/or modify it... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uartDevice is
generic (
-- Users to add parameters here
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
number_of_uarts: INTEGER RANGE 0 TO 16 := 1;--number of uarts which will be generated
-- User parameters... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ae_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Aut... |
-- q_one_dot_fp_multiplier.vhd
--TODO: Better way of handling -1 * -1 case?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out:... |
-- q_one_dot_fp_multiplier.vhd
--TODO: Better way of handling -1 * -1 case?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out:... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any la... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- FFD to delay a signals of N clock cycles
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Delayer IS
GENERIC (N : integer := 1);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic;
DOUT : OUT std_l... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "dc_motor_module_extended"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "dc_motor_module_extended"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-------------------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_5_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:02:48 11/30/2015
-- Design Name:
-- Module Name: IMask - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bram_DD... |
-------------------------------------------------------------------------------
--
-- Title : ALU_procedure
-- Design : de1
-- Author : phamthanh1992@hotmail.com
-- Company : homes
--
-------------------------------------------------------------------------------
--
-- File : ALU_procedure.vh... |
------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity arr02 is
port (v : std_logic_vector(0 to 7);
h : out std_logic_vector(0 to 3);
l : out std_logic_vector(3 downto 0));
end arr02;
architecture behav of arr02 is
begin
l <= v (4 to 7);
h <= v (0 to 3);
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity a2sComplement is
Generic
(
BITS : INTEGER := 4
);
Port
(
CI : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (BITS-1 downto 0);
Z : out STD_L... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:21:46 01/03/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/ram/tb_ram.vhd
-- Project Name: ram
-- Target Device:
-- Tool versions:
-- Description:
--
-- VH... |
--------------------------------------------------------------------------------
-- Title : VME Arbiter
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_arbiter.vhd
-- Author : michael.miehling@men.de
-- Organization : M... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerate... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram4 is
generic (
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkB : in std_logic;
enB : in std_logic;
weB : in std_logic;
addrB : in std_log... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
architecture rtl of fifo is
begin
process begin
loop END loop;
LOOP END LOOP;
end process;
end;
|
------------------------------------------------------------------------------
-- /home/daniw/data/studium/sem6/add/edk/IVK_HW/t01_hello/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generat... |
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code mu... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity divisorfrec is
PORT (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
salida:out STD_LOGIC
);
end divisorfrec;
architecture Behavioral of divisorfrec is
signal temporal: std_logic;
signal contador: inte... |
--Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associate... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
architecture RTL of FIFO is
file F1 : IntegerFile;
file F2 : IntegerFile is "test.dat";
file F3 : IntegerFile open WRITE_MODEW is "test.dat";
file F1, F2, F3 : IntegerFile open WRITE_MODEW is "test.dat";
file F1 : IntegerFile open WRITE_MODEM is (something(else));
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity tb is
end tb;
architecture augh of tb is
constant simu_max_cycles : natural := 100000;
constant simu_disp_cycles : std_logic := '1';
constant simu_err_end_in : std_logic := '0';
constant reset_cycles : ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity tb is
end tb;
architecture augh of tb is
constant simu_max_cycles : natural := 100000;
constant simu_disp_cycles : std_logic := '1';
constant simu_err_end_in : std_logic := '0';
constant reset_cycles : ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ent is
generic (
G : unsigned(31 downto 0)
);
port (
res : out unsigned (31 downto 0));
end;
architecture a of ent is
begin
res <= g;
end;
|
entity func is
port (a, b, c: in BIT; z: out BIT);
end entity func;
architecture netlist of func is
signal p, q, r: BIT; -- Defines the number and type of I/O buses;
begin
g1: entity WORK.Not1(gate1) port map(a, p);
-- The instance has a name (g1), the type of gate (gate1) and a clause of "port map"
... |
--!
--! Up/Down-Counter
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
package up_down_counter_pkg is
component up_down_counter is
generic (
WIDTH : positive);
port (
clk_en_p : in std_logic;
up_down_p : in std_logic;
value_p :... |
--!
--! Up/Down-Counter
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
package up_down_counter_pkg is
component up_down_counter is
generic (
WIDTH : positive);
port (
clk_en_p : in std_logic;
up_down_p : in std_logic;
value_p :... |
package badrng is
signal Sht : bit_vector(2 downtonatural range 0 to 7;
end badrng;
|
------------------------------------------------------------------------------
--! Copyright (C) 2017 , Emmanuel Amadio
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code m... |
library ieee;
use ieee.std_logic_1164.all;
--- DDR serializer.
entity ddr_ser is
generic (
data_width_g : positive;
delay_g : time);
port (
clk_i,
reset_ni : in std_ulogic;
data_i : in std_ulogic_vector(data_width_g-1 downto 0);
start_stb_i : in std_ulogic;
busy_o : out std_ulogic;
ddr_data_o,
bit... |
-- $Id: bpgenrbuslib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: bpgenrbuslib
-- Description: Generic Boar... |
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal en : std_logic;
signal a, b : std_logic;
signal p, q : std_logic;
begin
dut: entity work.top
port map (clk, en, a, b, p, q);
process
procedure pulse is
begin
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file... |
-- @license MIT
-- @brief D flip-flop based register.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity reg is
generic(
WIDTH : positive := 1;
RST_INIT : integer := 0
);
port(
i_clk : in std_logic;
in_rst : in std_logic;
i_d : in std_logic_vector(WID... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
entity irqc_tb is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Test case architecture
architecture func of irqc_tb is
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rena : std_logic; -- to dut
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity base_complementer_tb is
end entity;
architecture base_complementer_tb_arq of base_complementer_tb is
signal number_in : std_logic_vector(15 downto 0) := (others => '0');
signal number_out : std_logic_vector(15 downto 0) := (others => '0')... |
-- tb_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.09:18:23
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Binarization is
end entity tb_Binarization;
architecture rtl of tb_Binarization is
component Binarization_GN is
port (
Clock ... |
-- tb_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.09:18:23
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Binarization is
end entity tb_Binarization;
architecture rtl of tb_Binarization is
component Binarization_GN is
port (
Clock ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture RTL of ENTITY_NAME is
begin
process
begin
-- Test all possible combinations
WAIT_LABEL : wait on sig1, sig2, sig3 until some condition met for some time_expression;
WAIT_LABEL : wait on sig1, sig2, sig3 until some condition met;
WAIT_LABEL : wait on sig1, sig2, sig3 for some time... |
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