content stringlengths 1 1.04M ⌀ |
|---|
architecture RTL of FIFO is
file defaultImage : load_file_type open read_mode is load_file_name;
FILE defaultImage : load_file_type open read_mode is load_file_name;
File defaultImage : load_file_type open read_mode is load_file_name;
begin
end;
|
architecture rtl of fifo is
begin
process begin
LOOP end loop;
LOOP END LOOP;
end process;
end;
|
-----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : This is an really awesome example. The module waits
-- until an audio sample on the left or right channel
-- has been sampled. The current sample... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ax_wb_pli_pkg.all;
entity ax_wb_pli is
end entity ax_wb_pli;
architecture behav of ax_wb_pli is
constant cQUEUE_ID : integer := 0;
shared variable queue_handle : integer;
begin
init_bus_handle : process ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ax_wb_pli_pkg.all;
entity ax_wb_pli is
end entity ax_wb_pli;
architecture behav of ax_wb_pli is
constant cQUEUE_ID : integer := 0;
shared variable queue_handle : integer;
begin
init_bus_handle : process ... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- ... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- ... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity tb_snum03 is
end tb_snum03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_snum03 is
signal r : boolean;
begin
cmp03_1: entity work.snum03
port map (r);
process
begin
wait for 1 ns;
assert r severity failure;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity serializer is
port(
clk : in std_logic;
input : in std_logic_vector(0 to 512);
output : out std_logic_vector(0 to 63)
);
end serializer;
architecture Behavioral of serializer is
alias reset : std_logic is input(0);
alias vector : std_logic_vec... |
entity test is
subtype t is foo range bar'baz;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control_{{ current_var.name }} is
port (
clk: in std_logic;
reset: in std_logic;
lclear: out std_logic;
lchange: out std_logic;
lcontra: out std_logic;
gclear: in std_logic;
gchange: ... |
library verilog;
use verilog.vl_types.all;
entity frcr_timer is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iWR_ENA : in vl_logic;
iRW_COUNTER : in vl_logic_vector(63 downto 0);
oCOUNTER : out vl_logic_vector(63 do... |
----------------------------------------------------------------------
-- myCccMux (myCccMux4.vhd)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Instantiate G4 Clock Conditioning Circuit to use NonGlitching Mux
--
-----------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
package components is
component adder
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0)
);
end component;
component flopr
port (
... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Tue May 13 22:49:18 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Simple 8-bit shift register. Same as the one in Lab 5 except no STOP bit necessary.
ENTITY shift_greg is
port(clk, rst, shift_en, data_in: IN STD_LOGIC;
data_out: out STD_LOGIC_VECTOR(7 downto 0);
d... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myNand2 is
port(a : in std_logic; b : in std_logic; s : out std_logic);
end myNand2;
architecture Behavorial of myNand2 is
begin
s <= a nand b;
end Behavorial;
|
/*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:44:46 2019
-- Host : varun-laptop running 64-bit Service ... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
entity topb is
end topb;
architecture behav of topb is
signal clk : bit;
signal v : natural;
signal done : boolean := false;
begin
dut : entity work.entb
port map (clk => clk,
val => v);
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if done the... |
-- clock recovery
--
-- data is match filtered samples
-- output is clock
-- NOTE: this does not yet implement early/late, but only gives static timing
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity early_late is
generic (
width : positive := 8;
sam_per_bit :... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 11:30:11
-- Design Name:
-- Module Name: fsm_complex_abs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Rev... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
-- pragma translate_o... |
--!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: non_periodic_stimuli.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2014-04-01
--!
--!
--------------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_support.all;
use work.p... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Calc is
Port ( y0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
x0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
yi : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/OFDM_transmitter_tc.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- --------------------------... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
-------------------------------------------------------------------------------
-- Title : Big Drive
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 6
-------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:17:01 01/26/2014
-- Design Name:
-- Module Name: uc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-... |
---------------------------------------------------------------------------
-- ID/EX Pipeline Register
-- It propagates inputs coming from the decode stage to the ex stage
-- Note the use of the flush control signal: it used to flush the pipeline
-- register in case of control hazards(fluhs when the signal is asset... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Package for handling IPv4 headers, UDP and TCP packets
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_frame_pkg.byte_array;
package IPv4_packet_pkg is
subtype IPv4_addr_t is byte_array(0 to 3... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_593 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_593;
architecture augh of sub_593 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_593 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_593;
architecture augh of sub_593 is
signal carry_inA : std_l... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company: UMASS DARTMOUTH
-- Engineer: Christopher Parks (cparks13@live.com)
--
-- Create Date: 15:49:41 04/13/2016
-- Module Name: BranchPredictor - Behavioral
-- Description:
--
-- Revision:
-- Revision 0.01 - Fil... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 21 18:13:28 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 21 18:13:28 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ea_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:54 2017
-- Host : WK117 running 64-bit major release ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:06:02 09/17/2014
-- Design Name:
-- Module Name: H:/Documents/md5_test/tb_md5_working.vhd
-- Project Name: md5_test
-- Target Device:
-- Tool versions:
-- Description: ... |
library verilog;
use verilog.vl_types.all;
entity arm_barrel_shift is
port(
inst_11_0 : in vl_logic_vector(11 downto 0);
rm_data_in : in vl_logic_vector(31 downto 0);
rs_data_in : in vl_logic_vector(31 downto 0);
cpsr : in vl_logic_vector(31... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
library verilog;
use verilog.vl_types.all;
entity CMMaster3Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster3Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster3Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity repro3 is
end;
architecture behav of repro3 is
begin
process
begin
"and" (true, false);
end process;
end;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx... |
package repro6_gen_queue is
generic (type element_type);
procedure queue_add (el : element_type);
end repro6_gen_queue;
package body repro6_gen_queue is
procedure queue_add (el : element_type) is
begin
null;
end queue_add;
end repro6_gen_queue;
package repro6_gen_board is
generic (type element_type);... |
constant SensorFSMLength : integer := 850;
constant SensorFSMCfg : std_logic_vector(SensorFSMLength-1 downto 0) := "00100000110000010100111110000000000000001111100000000000000011111000000000000000111110000000000000000000000000000010100000000001000000000000000000110000110000001000000010000000001010000000000100000... |
constant SensorFSMLength : integer := 850;
constant SensorFSMCfg : std_logic_vector(SensorFSMLength-1 downto 0) := "00100000110000010100111110000000000000001111100000000000000011111000000000000000111110000000000000000000000000000010100000000001000000000000000000110000110000001000000010000000001010000000000100000... |
entity subent is
port (
a : in string(1 to 2) := "AB";
b : out string(1 to 2)
);
end entity subent;
architecture test of subent is
begin
b <= a;
end architecture test;
entity test is
end entity test;
architecture test of test is
signal b : string(1 to 2);
begin
e1: entity work.s... |
entity subent is
port (
a : in string(1 to 2) := "AB";
b : out string(1 to 2)
);
end entity subent;
architecture test of subent is
begin
b <= a;
end architecture test;
entity test is
end entity test;
architecture test of test is
signal b : string(1 to 2);
begin
e1: entity work.s... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.