content stringlengths 1 1.04M ⌀ |
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
----------------------------------------------------------------------
-- brdRstClk (for EmCraft SoC FG484 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------... |
entity fifo is
generic ( n : positive );
port (
wdata : bit_vector(1 to n) );
end entity;
architecture test of fifo is
begin
end architecture;
-------------------------------------------------------------------------------
entity neorv1 is
end entity;
architecture test of neorv1 is
signal x : bi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity maxPool is
generic (
IMAGE_WIDTH : integer := 320;
IN_SIZE : integer := 8;
OUT_SIZE : integer := 8;
CLK_PROC_FREQ : integer := 50000000
);
port (
clk_proc : in std_logic;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_rx_parser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Parses incoming pac... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_rx_parser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Parses incoming pac... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- ipif_reg_tb.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.utils_pkg.all;
entity ipif_reg_tb is
end entity;
architecture testbench of ipif_reg_tb is
cons... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity MODULUS_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Predicts the next program counters values to be used
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEUdisp22 is
Port ( disp22 : in STD_LOGIC_VECTOR (21 downto 0);
SEUdisp22 : out STD_LOGIC_VECTOR (31 downto 0));
end SEUdisp22;
architecture Behavioral of SEUdisp22 is
begin
process(disp22)
begin
if disp22(21)='1' then
SEUdisp22<="111... |
--------------------------------------------------------------------------------
-- adder.vhd
--
-- This file contains a simple N-bit full adder/subtractor using a carry chain.
-- The carry out of each bit is used to calculate that sum of the next bit.
-- This will slow the operation down slightly, but will reduce ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_modulator/wave_generator.vhd
-- Created: 2018-02-20 12:01:50
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ---------------------------------... |
package my_package is
type slv_1_t is array (natural range <>) of bit_vector;
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t;
end package my_package;
package body my_package is
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t is
variable cb_v : bit_vector(0 do... |
----- Libraries -----
library ieee;
use ieee.std_logic_1164.all;
entity Tester is
port( CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 2);
SW : in std_logic_vector(3 downto 0);
LEDR : out std_logic_vector(2 downto 0)
);
end Tester;
architecture Code_Test of Tester is
begin
cl : entity w... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_851;
architecture augh of cmp_851 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_851;
architecture augh of cmp_851 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cyp... |
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cyp... |
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cyp... |
--***************************************************************************************
--
-- File Name: CY7C1380_PL_SCD.vhd
-- Version: 1.0
-- Date: December 22nd, 2004
-- Model: BUS Functional
-- Simulator: Modelsim
--
--
-- Queries: MPD Applications
-- Website: www.cyp... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity ADDER_PROCESS is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end ADDER_PROCESS;
architecture Behavioral of ADDER_PROCESS is
begi... |
-- NEED RESULT: ARCH00085.P1: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P2: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P3: Multi transport transactions occurred on signal asg with slice n... |
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
----... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UART_VHDL is
port (
clock: in std_logic;
reset_N: in std_logic;
address: in std_logic;
writeData: in std_logic_vector(7 downto 0);
write: ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_156;
architecture augh of mul_156 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_156;
architecture augh of mul_156 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_156;
architecture augh of mul_156 is
signal tmp_res : signed(... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------... |
library verilog;
use verilog.vl_types.all;
entity Etapa1_vlg_vec_tst is
end Etapa1_vlg_vec_tst;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Instr_decoder is
Port ( instruction : in STD_LOGIC_VECTOR (31 downto 0);
index : out STD_LOGIC_VECTOR (5 downto 0)
);
end Instr_decoder;
architecture Behavioral of Instr_decoder is
--OP_SPECIAL, "100000", ADD
--OP_NORMAL , "00100... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.ceil;
use ieee.math_real.log2;
use work.sampling.all;
entity sampling_network is
generic (
num_samplers : integer := 1;
tau : positive := 20
);
port (
clk, reset : in std_ulogic;
clock_tick : out std_ulogic;
... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY register_generic IS
GENERIC(size: INTEGER);
PORT(d: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
clk, rst: IN S... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity substractor is
generic (k : integer := 4);
port( carryin : in std_logic ;
A, B : in std_logic_vector (k-1 downto 0);
S : out std_logic_vector (k-1 downto 0);
carryout : out std_logic);
end entity substractor;
archite... |
-- fichier : adder.vhd : vhdl structurelle pour un additionneur
library ieee;
use ieee.std_logic_1164.all;
-- déclaration de l'entité de l'additionneur:
entity adder is
port (
augend, addend, carry_in : in std_logic;
sum, carry_out : out std_logic
);
end adder;
-- architecture style structurell... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
architecture RTL of ENT is
begin
-- Align left = no align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
... |
-- Copyright (C) 2016 Siavoosh Payandeh, Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_pseudo is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := ... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHK_3BIT IS
PORT(DIN:IN STD_LOGIC;
CLK,RESET:IN STD_LOGIC;
BIT3:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT:OUT STD_LOGIC);
END ENTITY CHK_3BIT;
ARCHITECTURE ART1 OF CHK_3BIT IS
TYPE STATETYPE IS(S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15);
SIGNAL PRESENT_S... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 09:37:58 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TT is port(
T : in std_logic;
C : in std_logic;
Q : out std_logic
);
end TT;
architecture behavior of TT is
signal S : std_logic := '0';
begin
Main : process (T, C, S)
begin
if rising_edge(C) then
S <= T xor S;
end if;
end process;
Q <= S;
en... |
-------------------------------------------------------------------------------
--! @file dynamicBridgeRtl.vhd
--
--! @brief Dynamic Bridge for translating static to dynamic memory spaces
--
--! @details The Dynamic Bridge component translates a static memory mapping
--! into a dynamic memory map that can be changed du... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.resource_handles_pkg.all;
use work.npc_pkg.all;
package resource_handles_helper_pkg is
function get_sprite_id_from_handle(sprite_handle: sprite_handle_type) return natural;
function get_bitmap_id_from_handle(handle: bitmap_handle_type... |
--@ elab pkg_a
package pkg_a is
end package;
--!@ elab pkg_b
package pkg_b is
type BYTE is range 0 to 255;
constant K : BYTE;
end package;
--!@ elab pkg_c
package pkg_c is
use work.pkg_b.BYTE;
type SHORT is range 0 to 65535;
type INT is range 0 to 4294967295;
type PTR is access BYTE;
--type KILOBYTE is array (... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--use work.all;
use work.textmode_controller_pkg.all;
entity textmode_controller_avalon is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100;
CLK_FREQ : integer := 25000000;
DATA_WIDTH : integer := 32... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--use work.all;
use work.textmode_controller_pkg.all;
entity textmode_controller_avalon is
generic
(
ROW_COUNT : integer := 30;
COLUM_COUNT : integer := 100;
CLK_FREQ : integer := 25000000;
DATA_WIDTH : integer := 32... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup... |
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : SN74LVTH245.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernber... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 14:48:55 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reader is
... |
component Computer_System is
port (
adc_sclk : out std_logic; -- sclk
adc_cs_n : out std_logic; -- cs_n
adc_dout : in std_logic := 'X'... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Tue Mar 29 14:16:28 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 19:26:50 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:35:48 2019
-- Host : varun-laptop running 64-bit Serv... |
-- fast_Oscillator.vhd
--************************************
-- Program to simulate fast oscillator
--************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity fast_oscillator is
port (
stop : in s... |
------------------------------------------------------------------------------
-- File name: ee560_debounce_DPB_SCEN_CCEN_MCEN.vhd
-- Date: 6/10/2009
-- (C) Copyright 2009 Gandhi Puvvada
-- Description:
-- A vhdl design for debouncing a Push Button (PB) and produce the following:
-- (1) a debounced pulse DPB (D... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:34:29 12/23/2015
-- Design Name:
-- Module Name: multiplexer_4_to_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:34:29 12/23/2015
-- Design Name:
-- Module Name: multiplexer_4_to_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
-------------------------------------------------------------------------------
-- File Name : HostBFM.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostBFM
--
-- Content : Host BFM (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
--------------------------... |
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