content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... |
-------------------------------------------------------------------------------------
-- FILE NAME :
--
-- AUTHOR : Luis F Munoz
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity -
-- architecture -
--
-- LANGUAGE : VHDL
--
-------------------------------------... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_propos... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This ... |
package pack is
function "=" (L: bit; R: bit) return bit;
end package;
package body pack is
function "=" (L: bit; R: bit) return bit is
begin
if L = R then
return '1';
else
return '0';
end if;
end function;
end package body;
-----------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity RS_FF is
PORT ( S: in std_logic;
R: in std_logic;
CLOCK: in std_logic;
CLR: in std_logic;
PRESET: in std_logic;
Q: out std_logic;
QN: out std_logic);
end RS_FF;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 13;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code mu... |
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- D... |
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- D... |
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- D... |
----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- D... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
mask_lb, mask_ub: in std_log... |
-- altera_asmi_parallel.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altera_asmi_parallel is
port (
clkin : in std_logic := '0'; -- clkin.clk
fast_read : in std_logic ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package stream is
subtype valid_t is std_logic;
subtype ready_t is std_logic;
type array_ready_t is array (natural range <>) of ready_t;
type array_valid_t is array (natural range <>) of valid_t;
-- dummy functionality which needs to be s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package stream is
subtype valid_t is std_logic;
subtype ready_t is std_logic;
type array_ready_t is array (natural range <>) of ready_t;
type array_valid_t is array (natural range <>) of valid_t;
-- dummy functionality which needs to be s... |
entity test is
package a is new b generic map(inertial foo);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity sampler_tb is
end entity;
architecture tb of sampler_tb is... |
entity tb_dff05 is
end tb_dff05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff05 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff05
port map (
q => dout,
d => din... |
-- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 06/16/2017 03:07:27 PM
-- Design Name: TraceBack testbench for Convolutional Codes example project
-- Module Name: TraceBack_tb - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;... |
-- ROM package
library ieee;
use ieee.std_logic_1164.all;
package p1_rom is
constant w:integer:= 32; --width of ROM
constant l:integer:= 25; --lenght of ROM
subtype rom_word is std_logic_vector(w-1 downto 0);
type rom_table is array (0 to l-1) of rom_word;
constant rom_image:rom_table:=rom_tabl... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
signal fifo_wr : std_logic;
signal fifo_wr : std_logic_vector(3 downto 0);
signal fifo_wr : std_logic_vector(3 downto 0) := "000";
signal fifo_wr, fifo_rd, fifo_empty : std_logic := '1';
signal fifo_rd : fifo_wr'subtype;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity reg_a is
generic
(
LW : integer := 8
);
port
(
clk, ie, oe, reset : in std_logic;
data_in : in std_logic_vector(LW-1 downto 0);
data_out : out std_logic_vector(LW-1 downto 0)
);
end reg_a;
architecture behav of reg_a is
--signal reg: std_logic_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- #################################################################################################
-- # << NEO430 - Processor Test Implementation (neo430_test.vhd) >> #
-- # ********************************************************************************************* #
-- # If you do n... |
-- file: dcm_TFT9_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is no... |
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE ... |
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE ... |
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE ... |
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_3 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nodeController is
port(clk: in std_logic;
grant: in std_logic;
start: in std_logic;
count_in : in unsigned(1 downto 0);
nodeid : in std_logic_vector(1 downto 0);
req:out std_logic;
count_en : out std_logic;
data_out: out ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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