content stringlengths 1 1.04M ⌀ |
|---|
-- $Id: serport_xontx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_... |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:10:21 11/10/2013
-- Design Name:
-- Module Name: vga - Behavioral
-- Project Name: Representa... |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 12:10:21 11/10/2013
-- Design Name:
-- Module Name: vga - Behavioral
-- Project Name: Representa... |
-------------------------------------------------------------------------------
--! @file onewire_dongle_top.vhd
--! @author Johannes Walter <johannes@greenshire.io>
--! @copyright LGPL v2.1
--! @brief 1-wire ID and temperature sensor USB dongle.
-------------------------------------------------------------... |
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS Corp
-- Tool Versions : WebPACK 6.3.03i
--
-- Description:
-- SDRAM controller
--
-- Revision:
-- n.a. (because of hacking by Hellwig Geisse... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lz4_pkg.all;
entity lz4_entryDict is
generic (
constant FIFO_DEPTH : positive := 1000 -- 1 KB fifo
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryBytes_i : in std_logic_v... |
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := CONFIG_MIG_7SERIES;
constant CFG_MIG_7SERIES_MODEL : integer := CONFIG_MIG_7SERIES_MODEL;
|
-- Xilinx MIG 7-Series
constant CFG_MIG_7SERIES : integer := CONFIG_MIG_7SERIES;
constant CFG_MIG_7SERIES_MODEL : integer := CONFIG_MIG_7SERIES_MODEL;
|
-- rgb_mux.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils_v1_00_a;
use utils_v1_00_a.ipif_reg;
use utils_v1_00_a.ipif_reg_logic;
---
-- Multiplexor on RGB... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string :=... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string :=... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string :=... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string :=... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memctrl is
Port (
CLK : in std_logic;
RESET : in std_logic;
MEM_A : in std_logic_vector(19 downto 0);
MEM_DI ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
--
-- T400 Core
--
-- $Id: t400_por.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Wrapper for technology dependent power-on reset circuitry.
--
-- Altera Cyclone flavor.
--
-- Generate a reset upon power-on for specified number of cl... |
--##############################################################################
-- mcu80_mcu : light8080-based Micro Controller Unit
--##############################################################################
-- This MCU is meant as an usage example for the light8080 core. The code shows
-- how to interface the c... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : E X T R A C T O B S E R V A T I O N
--
--
-- The user function... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.test_package.all;
entity test is
generic(
MEMORY_SIZE : natural := 4096
);
port(
val_in : in std_logic_vector(63 downto 0)
);
end entity test;
architecture behaviour of test is
signal tmp : std_logic_vector... |
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--ALU
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity ALU is
generic(wid... |
entity repro2 is
generic (l : natural := 10);
end repro2;
architecture behav of repro2 is
begin
process
variable v : string (0 to l);
alias a : string is v;
begin
v := (others => ' ');
a := (others => 'x');
wait;
end process;
end behav;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
package PK_GEN_PULSO is
component GEN_PULSO is
port(
clk : in std_logic; -- clk
reset : in std_logic; -- reset
input : in std_logic; -- input
edge_detected : out std_logic -- edge_detected: pulso a 1 cuando
... |
------------------------------------------------------------------------
-- PhoenixOnBoardMemCtrl.vhd -- Digilent C1 Memory Module programming controller
------------------------------------------------------------------------
-- Author : Mircea Dabacan
-- Copyright 2005 Digilent, Inc.
---------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
entity foo is end;
architecture bar of foo is
constant TOLER: DISTANCE := 1.5 nm;
constant PI: REAL := 3.141592;
constant CYCLE_TIME: TIME := 100 ns;
constant Propagation_Delay: DELAY_LENGTH;
begin end;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ======================... |
library verilog;
use verilog.vl_types.all;
entity mist1032sa_sync_fifo is
generic(
N : integer := 16;
DEPTH : integer := 4;
D_N : integer := 2
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iR... |
--
-- Copyright 2016 Ognjen Glamocanin
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable la... |
library verilog;
use verilog.vl_types.all;
entity Mux_2 is
port(
clk : in vl_logic;
res : in vl_logic;
x : in vl_logic_vector(31 downto 0);
y : in vl_logic_vector(31 downto 0);
en : in vl_log... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_address_unpack is
port (
addr_pack : in std_logic_vector(31 downto 0);
x_addr : out std_logic_vector(9 downto 0);
y_addr : out std_logic_vector(9 downto 0)
);
end vga_address_unpack;
architecture Behavioral of vga_address_unpack is
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Title : rmii_transceiver
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: Receiver / transmitter for RMII
-- T... |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is d... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
entity rc5_key is
port( clr,clk : in std_logic; -- Asynchronous reset and Clock Signal
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom... |
library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- PLAYER CONTROLLER
--------------------------------------------------------------------------------
-- TODO:
-- Remove o... |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet.... |
-- file : boutons.vhdl
-- created : sam. oct. 30 18:56:10 CEST 2010 par whygee@f-cpu.org
-- This package wraps a single C function that reads the parallel
-- printer port's status lines (pins 10 to 13 of the DB25 connector)
--
-- compile with :
-- $ gcc -c boutons.c -o boutons_c.o
-- $ ghdl -a boutons.vhdl
-- ... |
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
architecture rtl of fifo is begin end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
-------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Reproducer: Using aliases to protect... |
--------------------------------------------------------------------------------
-- file name : sip_router_async_s1d2_x4_b_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -sip_router_async_s1d2_x4_b_stellar_cmd
-- arch_it... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k3_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_bb
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
-- --------------------------------------------------------------------
--
-- Copyright 2002 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE [Draft] Standard 1076.3
-- reduce_pkg
-- This source file may not be copied, sold, or included
-- with software that is sold wit... |
library verilog;
use verilog.vl_types.all;
entity Testbench is
end Testbench;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_ofdm_tx_tc.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -----------------------------------... |
entity bounds38 is
end entity;
architecture test of bounds38 is
type int_vec_2d is array (natural range <>, natural range <>) of integer;
function double (x : in int_vec_2d) return int_vec_2d is
variable result : int_vec_2d(x'range(2), x'range(1));
variable sum : integer;
begin
fo... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TB_ALLINALL is
end entity TB_ALLINALL;
architecture TB_ALLINALL_BODY of TB_ALLINALL is
component ALLINALL is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xil... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-- uart.vhd
-- VHDL do circuito da UART
library ieee;
use ieee.std_logic_1164.all;
entity uart is
port(
clock: in std_logic;
reset: in std_logic;
entrada: in std_logic;
recebe_dado: in std_logic;
transmite_dado: in std_logic;
dado_trans: in std_logic_vector(6 downto 0);
saida: out std_lo... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:32:44 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $... |
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