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-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
|
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BRAM_FIFO is
generic (
C_DATA_BITS : integer := 32;
C_ADDR_BITS : integer := 9
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Level : out std_logic_vector(0 to C_ADDR_BITS);
Full : out std_logic;
HalfFull : out std_logic;
HalfEmpty : out std_logic;
Overflow : out std_logic;
Underflow : out std_logic;
Empty : out std_logic
);
end entity BRAM_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of BRAM_FIFO is
component RAMB16_S36_S36
port(
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(8 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal in_address, out_address : unsigned(9 downto 0) := (others => '0');
signal addra, addrb : std_logic_vector(9 downto 0);
signal addr_diff : unsigned(9 downto 0);
signal overflow_i, underflow_i : std_logic;
signal empty_i, full_i : std_logic;
begin -- architecture IMP
addra <= CONV_STD_LOGIC_VECTOR(in_address,in_address'length);
addrb <= CONV_STD_LOGIC_VECTOR(out_address,out_address'length);
U1: RAMB16_S36_S36
port map(
DOA => open,
DOB => Data_Out,
DOPA => open,
DOPB => open,
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
CLKA => Clk,
CLKB => Clk,
DIA => Data_In,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => Reset,
SSRB => Reset,
WEA => FIFO_Write,
WEB => '0'
);
in_address_PROCESS: process (Clk,FIFO_Write)
begin
if Reset = '1' then
in_address <= (others => '0');
elsif (Clk'event and Clk='1') then
if (FIFO_Write = '1' and Clear_FIFO = '0') then
in_address <= in_address + 1;
elsif (Clear_FIFO = '1') then
in_address <= (others => '0');
end if;
end if;
end process;
out_address_PROCESS: process (Clk)
begin
if Reset = '1' then
out_address <= (others => '1');
elsif (Clk'event and Clk='1') then
if (FIFO_Read = '1' and Clear_FIFO = '0') then
out_address <= out_address + 1;
elsif (Clear_FIFO = '1') then
out_address <= (others => '1');
end if;
end if;
end process;
overflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
overflow_i <= '0';
elsif Full_i = '1' and FIFO_Write = '1' then
overflow_i <= '1';
end if;
end if;
end process;
overflow <= overflow_i;
underflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
underflow_i <= '0';
elsif Empty_i = '1' and FIFO_Read = '1' then
underflow_i <= '1';
end if;
end if;
end process;
underflow <= underflow_i;
addr_diff <= in_address - out_address - 1;
FIFO_Level <= CONV_STD_LOGIC_VECTOR(addr_diff,addr_diff'length);
HalfFull <= addr_diff(8);
HalfEmpty <= not addr_diff(8);
Empty_i <= '1' when addr_diff = 0 else '0';
Full_i <= '1' when (addr_diff = 512) else '0';
Empty <= Empty_i;
Full <= Full_i;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BRAM_FIFO is
generic (
C_DATA_BITS : integer := 32;
C_ADDR_BITS : integer := 9
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Level : out std_logic_vector(0 to C_ADDR_BITS);
Full : out std_logic;
HalfFull : out std_logic;
HalfEmpty : out std_logic;
Overflow : out std_logic;
Underflow : out std_logic;
Empty : out std_logic
);
end entity BRAM_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of BRAM_FIFO is
component RAMB16_S36_S36
port(
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(8 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal in_address, out_address : unsigned(9 downto 0) := (others => '0');
signal addra, addrb : std_logic_vector(9 downto 0);
signal addr_diff : unsigned(9 downto 0);
signal overflow_i, underflow_i : std_logic;
signal empty_i, full_i : std_logic;
begin -- architecture IMP
addra <= CONV_STD_LOGIC_VECTOR(in_address,in_address'length);
addrb <= CONV_STD_LOGIC_VECTOR(out_address,out_address'length);
U1: RAMB16_S36_S36
port map(
DOA => open,
DOB => Data_Out,
DOPA => open,
DOPB => open,
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
CLKA => Clk,
CLKB => Clk,
DIA => Data_In,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => Reset,
SSRB => Reset,
WEA => FIFO_Write,
WEB => '0'
);
in_address_PROCESS: process (Clk,FIFO_Write)
begin
if Reset = '1' then
in_address <= (others => '0');
elsif (Clk'event and Clk='1') then
if (FIFO_Write = '1' and Clear_FIFO = '0') then
in_address <= in_address + 1;
elsif (Clear_FIFO = '1') then
in_address <= (others => '0');
end if;
end if;
end process;
out_address_PROCESS: process (Clk)
begin
if Reset = '1' then
out_address <= (others => '1');
elsif (Clk'event and Clk='1') then
if (FIFO_Read = '1' and Clear_FIFO = '0') then
out_address <= out_address + 1;
elsif (Clear_FIFO = '1') then
out_address <= (others => '1');
end if;
end if;
end process;
overflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
overflow_i <= '0';
elsif Full_i = '1' and FIFO_Write = '1' then
overflow_i <= '1';
end if;
end if;
end process;
overflow <= overflow_i;
underflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
underflow_i <= '0';
elsif Empty_i = '1' and FIFO_Read = '1' then
underflow_i <= '1';
end if;
end if;
end process;
underflow <= underflow_i;
addr_diff <= in_address - out_address - 1;
FIFO_Level <= CONV_STD_LOGIC_VECTOR(addr_diff,addr_diff'length);
HalfFull <= addr_diff(8);
HalfEmpty <= not addr_diff(8);
Empty_i <= '1' when addr_diff = 0 else '0';
Full_i <= '1' when (addr_diff = 512) else '0';
Empty <= Empty_i;
Full <= Full_i;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BRAM_FIFO is
generic (
C_DATA_BITS : integer := 32;
C_ADDR_BITS : integer := 9
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Level : out std_logic_vector(0 to C_ADDR_BITS);
Full : out std_logic;
HalfFull : out std_logic;
HalfEmpty : out std_logic;
Overflow : out std_logic;
Underflow : out std_logic;
Empty : out std_logic
);
end entity BRAM_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of BRAM_FIFO is
component RAMB16_S36_S36
port(
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(8 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal in_address, out_address : unsigned(9 downto 0) := (others => '0');
signal addra, addrb : std_logic_vector(9 downto 0);
signal addr_diff : unsigned(9 downto 0);
signal overflow_i, underflow_i : std_logic;
signal empty_i, full_i : std_logic;
begin -- architecture IMP
addra <= CONV_STD_LOGIC_VECTOR(in_address,in_address'length);
addrb <= CONV_STD_LOGIC_VECTOR(out_address,out_address'length);
U1: RAMB16_S36_S36
port map(
DOA => open,
DOB => Data_Out,
DOPA => open,
DOPB => open,
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
CLKA => Clk,
CLKB => Clk,
DIA => Data_In,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => Reset,
SSRB => Reset,
WEA => FIFO_Write,
WEB => '0'
);
in_address_PROCESS: process (Clk,FIFO_Write)
begin
if Reset = '1' then
in_address <= (others => '0');
elsif (Clk'event and Clk='1') then
if (FIFO_Write = '1' and Clear_FIFO = '0') then
in_address <= in_address + 1;
elsif (Clear_FIFO = '1') then
in_address <= (others => '0');
end if;
end if;
end process;
out_address_PROCESS: process (Clk)
begin
if Reset = '1' then
out_address <= (others => '1');
elsif (Clk'event and Clk='1') then
if (FIFO_Read = '1' and Clear_FIFO = '0') then
out_address <= out_address + 1;
elsif (Clear_FIFO = '1') then
out_address <= (others => '1');
end if;
end if;
end process;
overflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
overflow_i <= '0';
elsif Full_i = '1' and FIFO_Write = '1' then
overflow_i <= '1';
end if;
end if;
end process;
overflow <= overflow_i;
underflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
underflow_i <= '0';
elsif Empty_i = '1' and FIFO_Read = '1' then
underflow_i <= '1';
end if;
end if;
end process;
underflow <= underflow_i;
addr_diff <= in_address - out_address - 1;
FIFO_Level <= CONV_STD_LOGIC_VECTOR(addr_diff,addr_diff'length);
HalfFull <= addr_diff(8);
HalfEmpty <= not addr_diff(8);
Empty_i <= '1' when addr_diff = 0 else '0';
Full_i <= '1' when (addr_diff = 512) else '0';
Empty <= Empty_i;
Full <= Full_i;
end architecture IMP;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY TEXT_DRAWER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DRAW : IN STD_LOGIC;
CHAR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
XPOS : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
YPOS : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SIZE : IN STD_LOGIC;
CHARLINEDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CHARADDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
DATA : OUT STD_LOGIC_VECTOR(20 DOWNTO 0);
DATA_QUEUE : OUT STD_LOGIC
);
END TEXT_DRAWER;
ARCHITECTURE main OF TEXT_DRAWER IS
SIGNAL STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
VARIABLE PREVCHAR : STD_LOGIC_VECTOR(6 DOWNTO 0);
VARIABLE PREVXPOS : STD_LOGIC_VECTOR(5 DOWNTO 0);
VARIABLE PREVYPOS : STD_LOGIC_VECTOR(4 DOWNTO 0);
VARIABLE PREVCOLOR : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE PREVSIZE : STD_LOGIC;
VARIABLE OUTDATA: STD_LOGIC_VECTOR(20 DOWNTO 0);
VARIABLE PIXCNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE PIXAUX : STD_LOGIC_VECTOR(2 DOWNTO 0);
VARIABLE LNCNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE LNAUX : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE XP : STD_LOGIC_VECTOR(8 DOWNTO 0);
VARIABLE YP : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(RST = '1') THEN
OUTDATA := "000000000000000000000";
PIXCNT := x"0";
LNCNT := x"0";
PREVXPOS := "111111";
XP := "000000000";
YP := "00000000";
STATE <= x"0";
DATA_QUEUE <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
CASE STATE IS
WHEN x"0" =>
--DEFINIR BOUNDARIES PARA O CARACTER
IF(DRAW = '1' AND NOT(PREVCHAR = CHAR AND PREVXPOS = XPOS AND PREVYPOS = YPOS AND PREVCOLOR = COLOR AND PREVSIZE = SIZE)) THEN
PREVCHAR := CHAR;
PREVXPOS := XPOS;
PREVYPOS := YPOS;
PREVCOLOR := COLOR;
PREVSIZE := SIZE;
LNCNT := x"0";
IF(SIZE = '1') THEN
XP := XPOS(4 DOWNTO 0) & "0000";
YP := YPOS(3 DOWNTO 0) & "0000";
IF(XP <= 304 AND YP <= 224) THEN
STATE <= x"1";
END IF;
ELSE
XP := XPOS & "000";
YP := YPOS & "000";
IF(XP <= 312 AND YP <= 232) THEN
STATE <= x"1";
END IF;
END IF;
END IF;
WHEN x"1" =>
IF(SIZE = '1') THEN
LNAUX := '0' & LNCNT(3 DOWNTO 1);
ELSE
LNAUX := LNCNT(3 DOWNTO 0);
END IF;
CHARADDR <= CHAR & LNAUX(2 DOWNTO 0);
PIXCNT := x"0";
STATE <= x"2";
WHEN x"2" =>
IF(SIZE = '1') THEN
PIXAUX := PIXCNT(3 DOWNTO 1);
ELSE
PIXAUX := PIXCNT(2 DOWNTO 0);
END IF;
OUTDATA(16 DOWNTO 0) := conv_std_logic_vector(conv_integer(PIXCNT + XP) + (320 * conv_integer(YP + LNCNT)), 17);
IF(CHARLINEDATA(conv_integer(NOT PIXAUX)) = '1') THEN
OUTDATA(20 DOWNTO 17) := COLOR;
ELSE
OUTDATA(20 DOWNTO 17) := x"0";
END IF;
DATA_QUEUE <= '1';
IF((PIXAUX = 7 AND SIZE = '0') OR (PIXCNT = 15 AND SIZE = '1')) THEN
IF((LNAUX = 7 AND SIZE = '0') OR (LNCNT = 15 AND SIZE = '1')) THEN
STATE <= x"5";
ELSE
LNCNT := LNCNT + '1';
STATE <= x"4";
END IF;
ELSE
PIXCNT := PIXCNT + '1';
STATE <= x"3";
END IF;
WHEN x"3" =>
DATA_QUEUE <= '0';
STATE <= x"2";
WHEN x"4" =>
DATA_QUEUE <= '0';
STATE <= x"1";
WHEN x"5" =>
DATA_QUEUE <= '0';
STATE <= x"0";
WHEN OTHERS =>
STATE <= x"0";
END CASE;
DATA <= OUTDATA;
END IF;
END PROCESS;
END main; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY TEXT_DRAWER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DRAW : IN STD_LOGIC;
CHAR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
XPOS : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
YPOS : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SIZE : IN STD_LOGIC;
CHARLINEDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CHARADDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
DATA : OUT STD_LOGIC_VECTOR(20 DOWNTO 0);
DATA_QUEUE : OUT STD_LOGIC
);
END TEXT_DRAWER;
ARCHITECTURE main OF TEXT_DRAWER IS
SIGNAL STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
VARIABLE PREVCHAR : STD_LOGIC_VECTOR(6 DOWNTO 0);
VARIABLE PREVXPOS : STD_LOGIC_VECTOR(5 DOWNTO 0);
VARIABLE PREVYPOS : STD_LOGIC_VECTOR(4 DOWNTO 0);
VARIABLE PREVCOLOR : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE PREVSIZE : STD_LOGIC;
VARIABLE OUTDATA: STD_LOGIC_VECTOR(20 DOWNTO 0);
VARIABLE PIXCNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE PIXAUX : STD_LOGIC_VECTOR(2 DOWNTO 0);
VARIABLE LNCNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE LNAUX : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE XP : STD_LOGIC_VECTOR(8 DOWNTO 0);
VARIABLE YP : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(RST = '1') THEN
OUTDATA := "000000000000000000000";
PIXCNT := x"0";
LNCNT := x"0";
PREVXPOS := "111111";
XP := "000000000";
YP := "00000000";
STATE <= x"0";
DATA_QUEUE <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
CASE STATE IS
WHEN x"0" =>
--DEFINIR BOUNDARIES PARA O CARACTER
IF(DRAW = '1' AND NOT(PREVCHAR = CHAR AND PREVXPOS = XPOS AND PREVYPOS = YPOS AND PREVCOLOR = COLOR AND PREVSIZE = SIZE)) THEN
PREVCHAR := CHAR;
PREVXPOS := XPOS;
PREVYPOS := YPOS;
PREVCOLOR := COLOR;
PREVSIZE := SIZE;
LNCNT := x"0";
IF(SIZE = '1') THEN
XP := XPOS(4 DOWNTO 0) & "0000";
YP := YPOS(3 DOWNTO 0) & "0000";
IF(XP <= 304 AND YP <= 224) THEN
STATE <= x"1";
END IF;
ELSE
XP := XPOS & "000";
YP := YPOS & "000";
IF(XP <= 312 AND YP <= 232) THEN
STATE <= x"1";
END IF;
END IF;
END IF;
WHEN x"1" =>
IF(SIZE = '1') THEN
LNAUX := '0' & LNCNT(3 DOWNTO 1);
ELSE
LNAUX := LNCNT(3 DOWNTO 0);
END IF;
CHARADDR <= CHAR & LNAUX(2 DOWNTO 0);
PIXCNT := x"0";
STATE <= x"2";
WHEN x"2" =>
IF(SIZE = '1') THEN
PIXAUX := PIXCNT(3 DOWNTO 1);
ELSE
PIXAUX := PIXCNT(2 DOWNTO 0);
END IF;
OUTDATA(16 DOWNTO 0) := conv_std_logic_vector(conv_integer(PIXCNT + XP) + (320 * conv_integer(YP + LNCNT)), 17);
IF(CHARLINEDATA(conv_integer(NOT PIXAUX)) = '1') THEN
OUTDATA(20 DOWNTO 17) := COLOR;
ELSE
OUTDATA(20 DOWNTO 17) := x"0";
END IF;
DATA_QUEUE <= '1';
IF((PIXAUX = 7 AND SIZE = '0') OR (PIXCNT = 15 AND SIZE = '1')) THEN
IF((LNAUX = 7 AND SIZE = '0') OR (LNCNT = 15 AND SIZE = '1')) THEN
STATE <= x"5";
ELSE
LNCNT := LNCNT + '1';
STATE <= x"4";
END IF;
ELSE
PIXCNT := PIXCNT + '1';
STATE <= x"3";
END IF;
WHEN x"3" =>
DATA_QUEUE <= '0';
STATE <= x"2";
WHEN x"4" =>
DATA_QUEUE <= '0';
STATE <= x"1";
WHEN x"5" =>
DATA_QUEUE <= '0';
STATE <= x"0";
WHEN OTHERS =>
STATE <= x"0";
END CASE;
DATA <= OUTDATA;
END IF;
END PROCESS;
END main; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY TEXT_DRAWER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DRAW : IN STD_LOGIC;
CHAR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
XPOS : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
YPOS : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SIZE : IN STD_LOGIC;
CHARLINEDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CHARADDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
DATA : OUT STD_LOGIC_VECTOR(20 DOWNTO 0);
DATA_QUEUE : OUT STD_LOGIC
);
END TEXT_DRAWER;
ARCHITECTURE main OF TEXT_DRAWER IS
SIGNAL STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
VARIABLE PREVCHAR : STD_LOGIC_VECTOR(6 DOWNTO 0);
VARIABLE PREVXPOS : STD_LOGIC_VECTOR(5 DOWNTO 0);
VARIABLE PREVYPOS : STD_LOGIC_VECTOR(4 DOWNTO 0);
VARIABLE PREVCOLOR : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE PREVSIZE : STD_LOGIC;
VARIABLE OUTDATA: STD_LOGIC_VECTOR(20 DOWNTO 0);
VARIABLE PIXCNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE PIXAUX : STD_LOGIC_VECTOR(2 DOWNTO 0);
VARIABLE LNCNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE LNAUX : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE XP : STD_LOGIC_VECTOR(8 DOWNTO 0);
VARIABLE YP : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(RST = '1') THEN
OUTDATA := "000000000000000000000";
PIXCNT := x"0";
LNCNT := x"0";
PREVXPOS := "111111";
XP := "000000000";
YP := "00000000";
STATE <= x"0";
DATA_QUEUE <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
CASE STATE IS
WHEN x"0" =>
--DEFINIR BOUNDARIES PARA O CARACTER
IF(DRAW = '1' AND NOT(PREVCHAR = CHAR AND PREVXPOS = XPOS AND PREVYPOS = YPOS AND PREVCOLOR = COLOR AND PREVSIZE = SIZE)) THEN
PREVCHAR := CHAR;
PREVXPOS := XPOS;
PREVYPOS := YPOS;
PREVCOLOR := COLOR;
PREVSIZE := SIZE;
LNCNT := x"0";
IF(SIZE = '1') THEN
XP := XPOS(4 DOWNTO 0) & "0000";
YP := YPOS(3 DOWNTO 0) & "0000";
IF(XP <= 304 AND YP <= 224) THEN
STATE <= x"1";
END IF;
ELSE
XP := XPOS & "000";
YP := YPOS & "000";
IF(XP <= 312 AND YP <= 232) THEN
STATE <= x"1";
END IF;
END IF;
END IF;
WHEN x"1" =>
IF(SIZE = '1') THEN
LNAUX := '0' & LNCNT(3 DOWNTO 1);
ELSE
LNAUX := LNCNT(3 DOWNTO 0);
END IF;
CHARADDR <= CHAR & LNAUX(2 DOWNTO 0);
PIXCNT := x"0";
STATE <= x"2";
WHEN x"2" =>
IF(SIZE = '1') THEN
PIXAUX := PIXCNT(3 DOWNTO 1);
ELSE
PIXAUX := PIXCNT(2 DOWNTO 0);
END IF;
OUTDATA(16 DOWNTO 0) := conv_std_logic_vector(conv_integer(PIXCNT + XP) + (320 * conv_integer(YP + LNCNT)), 17);
IF(CHARLINEDATA(conv_integer(NOT PIXAUX)) = '1') THEN
OUTDATA(20 DOWNTO 17) := COLOR;
ELSE
OUTDATA(20 DOWNTO 17) := x"0";
END IF;
DATA_QUEUE <= '1';
IF((PIXAUX = 7 AND SIZE = '0') OR (PIXCNT = 15 AND SIZE = '1')) THEN
IF((LNAUX = 7 AND SIZE = '0') OR (LNCNT = 15 AND SIZE = '1')) THEN
STATE <= x"5";
ELSE
LNCNT := LNCNT + '1';
STATE <= x"4";
END IF;
ELSE
PIXCNT := PIXCNT + '1';
STATE <= x"3";
END IF;
WHEN x"3" =>
DATA_QUEUE <= '0';
STATE <= x"2";
WHEN x"4" =>
DATA_QUEUE <= '0';
STATE <= x"1";
WHEN x"5" =>
DATA_QUEUE <= '0';
STATE <= x"0";
WHEN OTHERS =>
STATE <= x"0";
END CASE;
DATA <= OUTDATA;
END IF;
END PROCESS;
END main; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO_control_part_checkers;
architecture behavior of FIFO_control_part_checkers is
signal read_en_signal: std_logic;
begin
read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or (read_en_out = '1' and empty_out = '1') ) and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
--process (CTS_out, DRTS, full_out, CTS_in)
--begin
-- if (CTS_out = '0' and DRTS = '1' and full_out = '0' and CTS_in = '0') then
-- err_CTS_in <= '1';
-- else
-- err_CTS_in <= '0';
-- end if;
--end process;
process (CTS_out, DRTS, full_out, write_en_out)
begin
if (CTS_out = '0' and DRTS = '1' and full_out = '0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
process (CTS_out, DRTS, full_out, CTS_in)
begin
if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and CTS_in = '1') then
err_not_CTS_in <= '1';
else
err_not_CTS_in <= '0';
end if;
end process;
--process (CTS_out, DRTS, full_out, write_en_out)
--begin
-- if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and write_en_out = '1') then
-- err_not_write_en <= '1';
-- else
-- err_not_write_en <= '0';
-- end if;
--end process;
process (read_en_out, read_en_signal)
begin
if (read_en_out /= read_en_signal) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_control_part_checkers is
port ( DRTS: in std_logic;
CTS_out: in std_logic;
CTS_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end FIFO_control_part_checkers;
architecture behavior of FIFO_control_part_checkers is
signal read_en_signal: std_logic;
begin
read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or (read_en_out = '1' and empty_out = '1') ) and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
--process (CTS_out, DRTS, full_out, CTS_in)
--begin
-- if (CTS_out = '0' and DRTS = '1' and full_out = '0' and CTS_in = '0') then
-- err_CTS_in <= '1';
-- else
-- err_CTS_in <= '0';
-- end if;
--end process;
process (CTS_out, DRTS, full_out, write_en_out)
begin
if (CTS_out = '0' and DRTS = '1' and full_out = '0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
process (CTS_out, DRTS, full_out, CTS_in)
begin
if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and CTS_in = '1') then
err_not_CTS_in <= '1';
else
err_not_CTS_in <= '0';
end if;
end process;
--process (CTS_out, DRTS, full_out, write_en_out)
--begin
-- if ( (CTS_out = '1' or (CTS_out = '0' and DRTS = '0') or (CTS_out = '0' and DRTS = '1' and full_out = '1')) and write_en_out = '1') then
-- err_not_write_en <= '1';
-- else
-- err_not_write_en <= '0';
-- end if;
--end process;
process (read_en_out, read_en_signal)
begin
if (read_en_out /= read_en_signal) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
end behavior; |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_packetprocessor is
port(memop : in std_logic_vector(11 downto 0);
en : in boolean;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
result : out packetprocessor_types.tup3);
end;
architecture structural of packetprocessor_packetprocessor is
signal ipv : unsigned(7 downto 0);
signal w_app_arg : packetprocessor_types.tup2_0;
signal x : boolean;
signal w_app_arg_0 : std_logic_vector(19 downto 0);
signal x_0 : std_logic_vector(19 downto 0);
signal x_1 : unsigned(10 downto 0);
signal x_case_alt : unsigned(10 downto 0);
signal a : unsigned(10 downto 0);
signal w_case_alt : packetprocessor_types.tup4;
signal x_2 : unsigned(10 downto 0);
signal x_3 : boolean;
signal w_case_alt_0 : packetprocessor_types.tup4;
signal w_case_alt_1 : packetprocessor_types.tup4;
signal x_4 : boolean;
signal x_app_arg : std_logic_vector(19 downto 0);
signal x_app_arg_0 : unsigned(10 downto 0);
signal w : packetprocessor_types.tup4;
signal result_0 : unsigned(10 downto 0);
signal x_5 : unsigned(7 downto 0);
signal wraddr : unsigned(10 downto 0);
signal x_6 : boolean;
signal case_alt : std_logic_vector(8 downto 0);
signal app_arg : boolean;
signal result_1 : std_logic_vector(8 downto 0);
begin
ipv <= unsigned(memop(10 downto 3));
w_app_arg <= (tup2_0_sel0 => wraddr
,tup2_0_sel1 => ipv);
x <= w.tup4_sel1;
w_app_arg_0 <= std_logic_vector'("1" & (std_logic_vector(w_app_arg.tup2_0_sel0)
& std_logic_vector(w_app_arg.tup2_0_sel1)));
x_0 <= w.tup4_sel3;
x_1 <= w.tup4_sel0;
x_case_alt <= wraddr + to_unsigned(1,11);
a <= unsigned(memop(10 downto 0));
w_case_alt <= (tup4_sel0 => to_unsigned(0,11)
,tup4_sel1 => true
,tup4_sel2 => true
,tup4_sel3 => w_app_arg_0);
with (wraddr) select
x_2 <= to_unsigned(2047,11) when "11111111111",
x_case_alt when others;
x_3 <= x;
w_case_alt_0 <= w_case_alt when en else
(tup4_sel0 => to_unsigned(0,11)
,tup4_sel1 => false
,tup4_sel2 => false
,tup4_sel3 => std_logic_vector'("0" & "0000000000000000000"));
w_case_alt_1 <= (tup4_sel0 => a
,tup4_sel1 => false
,tup4_sel2 => true
,tup4_sel3 => std_logic_vector'("0" & "0000000000000000000"));
x_4 <= w.tup4_sel2;
x_app_arg <= x_0;
x_app_arg_0 <= x_1;
with (memop(11 downto 11)) select
w <= w_case_alt_1 when "0",
w_case_alt_0 when others;
result_0 <= x_2 when x_3 else
wraddr;
packetprocessor_readnew_x_5 : entity packetprocessor_readnew
port map
(result => x_5
,system1000 => system1000
,system1000_rstn => system1000_rstn
,w3 => x_app_arg_0
,w4 => x_app_arg);
-- register begin
packetprocessor_packetprocessor_register : process(system1000,system1000_rstn)
begin
if system1000_rstn = '0' then
wraddr <= to_unsigned(0,11);
elsif rising_edge(system1000) then
wraddr <= result_0;
end if;
end process;
-- register end
x_6 <= x_4;
case_alt <= std_logic_vector'("1" & std_logic_vector(x_5));
app_arg <= wraddr = to_unsigned(2047,11);
result_1 <= case_alt when x_6 else
std_logic_vector'("0" & "00000000");
result <= (tup3_sel0 => result_1
,tup3_sel1 => app_arg
,tup3_sel2 => app_arg);
end;
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_packetprocessor is
port(memop : in std_logic_vector(11 downto 0);
en : in boolean;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
result : out packetprocessor_types.tup3);
end;
architecture structural of packetprocessor_packetprocessor is
signal ipv : unsigned(7 downto 0);
signal w_app_arg : packetprocessor_types.tup2_0;
signal x : boolean;
signal w_app_arg_0 : std_logic_vector(19 downto 0);
signal x_0 : std_logic_vector(19 downto 0);
signal x_1 : unsigned(10 downto 0);
signal x_case_alt : unsigned(10 downto 0);
signal a : unsigned(10 downto 0);
signal w_case_alt : packetprocessor_types.tup4;
signal x_2 : unsigned(10 downto 0);
signal x_3 : boolean;
signal w_case_alt_0 : packetprocessor_types.tup4;
signal w_case_alt_1 : packetprocessor_types.tup4;
signal x_4 : boolean;
signal x_app_arg : std_logic_vector(19 downto 0);
signal x_app_arg_0 : unsigned(10 downto 0);
signal w : packetprocessor_types.tup4;
signal result_0 : unsigned(10 downto 0);
signal x_5 : unsigned(7 downto 0);
signal wraddr : unsigned(10 downto 0);
signal x_6 : boolean;
signal case_alt : std_logic_vector(8 downto 0);
signal app_arg : boolean;
signal result_1 : std_logic_vector(8 downto 0);
begin
ipv <= unsigned(memop(10 downto 3));
w_app_arg <= (tup2_0_sel0 => wraddr
,tup2_0_sel1 => ipv);
x <= w.tup4_sel1;
w_app_arg_0 <= std_logic_vector'("1" & (std_logic_vector(w_app_arg.tup2_0_sel0)
& std_logic_vector(w_app_arg.tup2_0_sel1)));
x_0 <= w.tup4_sel3;
x_1 <= w.tup4_sel0;
x_case_alt <= wraddr + to_unsigned(1,11);
a <= unsigned(memop(10 downto 0));
w_case_alt <= (tup4_sel0 => to_unsigned(0,11)
,tup4_sel1 => true
,tup4_sel2 => true
,tup4_sel3 => w_app_arg_0);
with (wraddr) select
x_2 <= to_unsigned(2047,11) when "11111111111",
x_case_alt when others;
x_3 <= x;
w_case_alt_0 <= w_case_alt when en else
(tup4_sel0 => to_unsigned(0,11)
,tup4_sel1 => false
,tup4_sel2 => false
,tup4_sel3 => std_logic_vector'("0" & "0000000000000000000"));
w_case_alt_1 <= (tup4_sel0 => a
,tup4_sel1 => false
,tup4_sel2 => true
,tup4_sel3 => std_logic_vector'("0" & "0000000000000000000"));
x_4 <= w.tup4_sel2;
x_app_arg <= x_0;
x_app_arg_0 <= x_1;
with (memop(11 downto 11)) select
w <= w_case_alt_1 when "0",
w_case_alt_0 when others;
result_0 <= x_2 when x_3 else
wraddr;
packetprocessor_readnew_x_5 : entity packetprocessor_readnew
port map
(result => x_5
,system1000 => system1000
,system1000_rstn => system1000_rstn
,w3 => x_app_arg_0
,w4 => x_app_arg);
-- register begin
packetprocessor_packetprocessor_register : process(system1000,system1000_rstn)
begin
if system1000_rstn = '0' then
wraddr <= to_unsigned(0,11);
elsif rising_edge(system1000) then
wraddr <= result_0;
end if;
end process;
-- register end
x_6 <= x_4;
case_alt <= std_logic_vector'("1" & std_logic_vector(x_5));
app_arg <= wraddr = to_unsigned(2047,11);
result_1 <= case_alt when x_6 else
std_logic_vector'("0" & "00000000");
result <= (tup3_sel0 => result_1
,tup3_sel1 => app_arg
,tup3_sel2 => app_arg);
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Fredrik Ringhage, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.i2c.all;
use gaisler.spi.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.net.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3core is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
clkapb : in std_ulogic;
clklock : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
dataen : out std_logic_vector(31 downto 0);
cbin : in std_logic_vector(7 downto 0);
cbout : out std_logic_vector(7 downto 0);
cben : out std_logic_vector(7 downto 0);
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : out std_ulogic;
gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_sclout : out std_ulogic;
i2c_sclen : out std_ulogic;
i2c_sclin : in std_ulogic;
i2c_sdaout : out std_ulogic;
i2c_sdaen : out std_ulogic;
i2c_sdain : in std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdioin : in std_logic;
emdioout : out std_logic;
emdioen : out std_logic;
emdc : out std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tdoen : out std_ulogic;
scanen : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic;
chain_tck : out std_ulogic;
chain_tckn : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic
);
end;
architecture rtl of leon3core is
--constant is_asic : integer := 1 - is_fpga(fabtech);
--constant blength : integer := 12;
--constant CFG_NCLKS : integer := 7;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal rstn, rstraw : std_ulogic;
signal rstapbn, rstapbraw : std_ulogic;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi, gpioi2 : gpio_in_type;
signal gpioo, gpioo2 : gpio_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
-- signal tck, tms, tdi, tdo : std_ulogic;
signal jtck, jtckn, jtdi, jrst, jtdo, jcapt, jshft, jupd, jiupd: std_ulogic;
signal jninst: std_logic_vector(7 downto 0);
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(CFG_SPW_NUM*2-1 downto 0);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stati : ahbstat_in_type;
-- SPW Clock Gating signals
signal enphy : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwrstn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gspwclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclko : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal lspwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclkphyo : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal crst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
constant IOAEN : integer := 0;
constant CFG_SDEN : integer := CFG_MCTRL_LEON2;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
constant OEPOL : integer := padoen_polarity(padtech);
constant CPU_FREQ : integer := 100000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
wpo.wprothit <= '0'; -- no write protection
rstgen0 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clk, clklock, rstn, rstraw, testrst);
rstgen1 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clkapb, clklock, rstapbn, rstapbraw, testrst);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahbctrl0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso,
testen, testrst, scanen, testoen);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
leon3s0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clk);
end generate;
errorn <= dbgo(0).error when OEPOL = 0 else not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= dsuen; dsui.break <= dsubre; dsuact <= dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
ahbuart0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= dsurx; dsutx <= duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, part => JTAG_EXAMPLE_PART,
hindex => CFG_NCPU+CFG_AHB_UART, scantest => scantest, oepol => OEPOL)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
jtck, jtdi, open, jrst, jcapt, jshft, jupd, jtdo, trst, tdoen, '0', jtckn, jninst, jiupd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
address <= memo.address(27 downto 0);
ramsn <= memo.ramsn(4 downto 0); romsn <= memo.romsn(1 downto 0);
oen <= memo.oen; rwen <= memo.wrn; ramoen <= memo.ramoen(4 downto 0);
writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
dataout <= memo.data(31 downto 0); dataen <= memo.vbdrive(31 downto 0);
memi.data(31 downto 0) <= datain;
sdwen <= sdo.sdwen; sdrasn <= sdo.rasn; sdcasn <= sdo.casn;
sddqm <= sdo.dqm(3 downto 0); sdcsn <= sdo.sdcsn;
cbout <= memo.cb(7 downto 0); cben <= memo.vcdrive(7 downto 0);
memi.bwidth <= prom32 & '0';
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
mctrl0 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE,
oepol => OEPOL)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdo.sdcsn <= (others => '1');
end generate;
memi.writen <= '1'; memi.wrn <= "1111";
memi.brdyn <= brdyn; memi.bexcn <= bexcn;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
memo.ramsn <= (others => '1'); memo.romsn <= (others => '1');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apbctrl0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstapbn, clkapb, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
apbuart0 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstapbn, clkapb, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
txd1 <= u1o.txd; u1i.rxd <= rxd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 9, fifosize => CFG_UART2_FIFO)
port map (rstapbn, clkapb, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
gptimer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstapbn, clkapb, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdogn <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH, oepol => OEPOL, syncrst => CFG_NOASYNC)
port map( rstapbn, clkapb, apbi, apbo(6), gpioi, gpioo);
gpioout <= gpioo.dout(CFG_GRGPIO_WIDTH-1 downto 0);
gpioen <= gpioo.oen(CFG_GRGPIO_WIDTH-1 downto 0);
gpioi.din(CFG_GRGPIO_WIDTH-1 downto 0) <= gpioin;
end generate;
nogpio : if CFG_GRGPIO_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 5, paddr => 5, pmask => 16#FFF#, pirq => 13, filter => 9)
port map (rstapbn, clkapb, apbi, apbo(5), i2ci, i2co);
i2c_sclout <= i2co.scl;
i2c_sclen <= i2co.scloen;
i2ci.scl <= i2c_sclin;
i2c_sdaout <= i2co.sda;
i2c_sdaen <= i2co.sdaoen;
i2ci.sda <= i2c_sdain;
end generate i2cm;
noi2cm: if CFG_I2C_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spictrl0 : spictrl
generic map(
pindex => 8,
paddr => 8,
pmask => 16#fff#,
pirq => 8,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
oepol => oepol,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => CFG_SPICTRL_TWEN,
maxwlen => CFG_SPICTRL_MAXWLEN,
syncram => CFG_SPICTRL_SYNCRAM,
memtech => memtech,
ft => CFG_SPICTRL_FT,
scantest => scantest)
port map(
rstn => rstapbn,
clk => clkapb,
apbi => apbi,
apbo => apbo(8),
spii => spii,
spio => spio,
slvsel => spi_slvsel);
spii.sck <= '0';
spii.mosi <= '0';
spii.miso <= spi_miso;
spi_mosi <= spio.mosi;
spi_sck <= spio.sck;
spii.astart <= '0'; --unused
spii.spisel <= '1'; --unused (master only)
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate apbo(14) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat
generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clk, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-------------------------------------------------------------------------------
-- JTAG Boundary scan
-------------------------------------------------------------------------------
bscangen: if CFG_BOUNDSCAN_EN /= 0 generate
xtapgen: if CFG_AHB_JTAG = 0 generate
t0: tap
generic map (tech => fabtech, irlen => 6, scantest => scantest, oepol => OEPOL)
port map (trst,tck,tms,tdi,tdo,
jtck,jtdi,open,jrst,jcapt,jshft,jupd,open,open,'1',jtdo,'0',jninst,jiupd,jtckn,testen,testrst,testoen,tdoen,'0');
end generate;
bc0: bscanctrl
port map (
trst,jtck,jtckn,jtdi,jninst,jiupd,jrst,jcapt,jshft,jupd,jtdo,
chain_tdi, chain_tdo, bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz,
gnd(0), testen, testrst);
chain_tck <= jtck;
chain_tckn <= jtckn;
end generate;
nobscangen: if CFG_BOUNDSCAN_EN = 0 generate
chain_tck <= '0';
chain_tckn <= '0';
chain_tdi <= '0';
bsshft <= '0';
bscapt <= '0';
bsupdi <= '0';
bsupdo <= '0';
bsdrive <= '0';
bshighz <= '0';
end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
swloop : for i in 0 to CFG_SPW_NUM-1 generate
spwi(i).clkdiv10 <=
"000" & gpioo.val(10 downto 8) & "11" when spw_clksel(1 downto 0) = "11" else
"0000" & gpioo.val(10 downto 8) & '1' when spw_clksel(1 downto 0) = "10" else
"00000" & gpioo.val(10 downto 8);
spwi(i).timerrstval <=
'0' & gpioo.val(15 downto 11) & "111111" when clksel(1 downto 0) = "11" else
"00" & gpioo.val(15 downto 11) & "11111" when clksel(1 downto 0) = "10" else
"000" & gpioo.val(15 downto 11) & "1111";
spwi(i).dcrstval <=
"00" & gpioo.val(15 downto 11) & "111" when clksel(1 downto 0) = "11" else
"000" & gpioo.val(15 downto 11) & "10" when clksel(1 downto 0) = "10" else
"0000" & gpioo.val(15 downto 11) & '0';
-- GRSPW PHY #1
spw1_input: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_input;
-- GRSPW PHY #2
spw2_input: if CFG_SPW_GRSPW = 2 generate
------------------------------------------------------------------------------
-- SpW Physical layer
------------------------------------------------------------------------------
--phy_loop : for i in 0 to CFG_SPWRTR_SPWPORTS-1 generate
rstphy0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => spwrstn(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- Only add clockgating to tech lib which supports clock gates
clkgatephygen : if (has_clkand(fabtech) = 1) generate
-- Sync clock to clock domain
spwclkreg : process(spw_clk) is
begin
if rising_edge(spw_clk) then
-- Only disable phy when rx and tx is disabled
-- TODO: Add SW register to enable/disable the router
enphy(i) <= '1';
end if;
end process;
-- Disable spw phy clock when port is not used
spw_phy0_enable : clkand
generic map (
tech => fabtech,
ren => 0)
port map (
i => spw_clk,
en => enphy(i),
o => gspwclk(i),
tsten => testen);
-- Select rx clock (Should be removed by optimization if RX and TX clock is same i.e. normal case for ASIC)
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
noclkgategen : if (has_clkand(fabtech) = 0) generate
enphy(i) <= '1';
gspwclk(i) <= spw_clk;
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
notecclkmux : if (has_clkmux(fabtech) = 0) generate
spwclkn(i) <= spw_clk when (testen = '1' and scantest = 1) else not spw_clk;
end generate;
tecclkmux : if (has_clkmux(fabtech) = 1) generate
-- Use SET protected cells
spwclkni0: clkinv generic map (tech => fabtech) port map (spw_clk, lspwclkn(i));
spwclknm0 : clkmux generic map (tech => fabtech) port map (lspwclkn(i),spw_clk,testen,spwclkn(i));
end generate;
spw_phy0 : grspw2_phy
generic map(
scantest => scantest,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => spwrstn(i),
rxclki => gspwclk(i),
rxclkin => spwclkn(i),
nrxclki => spwclkn(i),
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => rxclkphyo(i),
testrst => testrst,
testen => testen);
dtmp(i) <= spw_rxd(i); stmp(i) <= spw_rxs(i);
spw_txd(i) <= spwo(i).d(0); spw_txs(i) <= spwo(i).s(0);
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
--end generate;
end generate spw2_input;
spw1_codec: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_codec;
spw2_codec: if CFG_SPW_GRSPW = 2 generate
rstcodec0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => crst(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- TODO: Fix SW control signals
disclk(i) <= '0';
disrxclk0(i) <= '0';
disrxclk1(i) <= '0';
distxclk(i) <= '0';
distxclkn(i) <= '0';
port0_clkgate : grspw_codec_clockgate
generic map (
tech => fabtech,
scantest => scantest,
ports => CFG_SPW_PORTS,
output_type => CFG_SPW_OUTPUT,
clkgate => 1
)
port map (
rst => crst(i),
clk => spw_clk,
rxclk0 => spw_rxclk(i),
rxclk1 => '0',
txclk => spw_clk,
txclkn => '0',
testen => testen,
testrst => testrst,
disableclk => disclk(i),
disablerxclk0 => disrxclk0(i),
disablerxclk1 => disrxclk1(i),
disabletxclk => distxclk(i),
disabletxclkn => distxclkn(i),
grst => grst(i),
gclk => gclk(i),
grxclk0 => grxclk0(i),
grxclk1 => grxclk1(i),
gtxclk => gtxclk(i),
gtxclkn => gtxclkn(i)
);
grspw0 : grspw2
generic map(
tech => fabtech, -- : integer range 0 to NTECH := inferred;
hindex => maxahbmsp+i, -- : integer range 0 to NAHBMST-1 := 0;
pindex => i+10, -- : integer range 0 to NAPBSLV-1 := 0;
paddr => i+10, -- : integer range 0 to 16#FFF# := 0;
--pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq => i+10, -- : integer range 0 to NAHBIRQ-1 := 0;
rmap => CFG_SPW_RMAP, -- : integer range 0 to 2 := 0;
rmapcrc => CFG_SPW_RMAPCRC, -- : integer range 0 to 1 := 0;
fifosize1 => CFG_SPW_AHBFIFO, -- : integer range 4 to 32 := 32;
fifosize2 => CFG_SPW_RXFIFO, -- : integer range 16 to 64 := 64;
rxclkbuftype => 0, -- : integer range 0 to 2 := 0;
rxunaligned => CFG_SPW_RXUNAL, -- : integer range 0 to 1 := 0;
rmapbufs => CFG_SPW_RMAPBUF, -- : integer range 2 to 8 := 4;
ft => CFG_SPW_FT, -- : integer range 0 to 2 := 0;
scantest => scantest, -- : integer range 0 to 1 := 0;
ports => CFG_SPW_PORTS, -- : integer range 1 to 2 := 1;
dmachan => CFG_SPW_DMACHAN, -- : integer range 1 to 4 := 1;
memtech => memtech, -- : integer range 0 to NTECH := DEFMEMTECH;
techfifo => has_2pram(memtech), -- : integer range 0 to 1 := 1;
input_type => CFG_SPW_INPUT, -- : integer range 0 to 4 := 0;
output_type => CFG_SPW_OUTPUT, -- : integer range 0 to 2 := 0;
rxtx_sameclk => CFG_SPW_RTSAME, -- : integer range 0 to 1 := 0;
netlist => CFG_SPW_NETLIST -- : integer range 0 to 1 := 0;
)
port map (
rst => grst(i),
clk => gclk(i),
rxclk0 => grxclk0(i),
rxclk1 => grxclk1(i),
txclk => gtxclk(i),
txclkn => gtxclkn(i),
ahbmi => ahbmi,
ahbmo => ahbmo(maxahbmsp+i),
apbi => apbi,
apbo => apbo(i+10),
swni => spwi(i),
swno => spwo(i)
);
end generate spw2_codec;
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_txd <= (others => '0');
spw_txs <= (others => '0');
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 13, paddr => 13, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
ethi.gtx_clk <= gtx_clk;
ethi.rx_clk <= erx_clk;
ethi.rxd(7 downto 0) <= erxd;
ethi.rx_dv <= erx_dv;
ethi.tx_clk <= etx_clk;
etxd <= etho.txd(7 downto 0);
etx_en <= etho.tx_en;
etx_er <= etho.tx_er;
ethi.mdint <= emdint;
ethi.mdio_i <= emdioin;
emdioout <= etho.mdio_o;
emdioen <= etho.mdio_oe;
emdc <= etho.mdc;
ethi.rx_er <= erx_er;
ethi.rx_col <= erx_col;
ethi.rx_crs <= erx_crs;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
noam1 : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- noap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_AHBSTAT
-- generate apbo(i) <= apb_none; end generate;
noah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 ASIC Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
clk_in : in std_logic;
depth_out : out std_logic_vector(7 downto 0);
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.altera_fifo
port map(
clock => clk_in,
usedw => depth_out,
-- Production end
data => inputData_in,
wrreq => inputValid_in,
full => inputFull,
-- Consumption end
q => outputData_out,
empty => outputEmpty,
rdreq => outputReady_in
);
end architecture;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity usb1_token_crc is
port (
clock : in std_logic;
sync : in std_logic;
token_in : in std_logic_vector(10 downto 0);
crc : out std_logic_vector(4 downto 0) );
end usb1_token_crc;
architecture Gideon of usb1_token_crc is
-- signal crc_reg : std_logic_vector(4 downto 0) := (others => '0');
constant polynom : std_logic_vector(4 downto 0) := "00100";
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
for i in token_in'reverse_range loop -- LSB first!
d := token_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d; --'0';
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity usb1_token_crc is
port (
clock : in std_logic;
sync : in std_logic;
token_in : in std_logic_vector(10 downto 0);
crc : out std_logic_vector(4 downto 0) );
end usb1_token_crc;
architecture Gideon of usb1_token_crc is
-- signal crc_reg : std_logic_vector(4 downto 0) := (others => '0');
constant polynom : std_logic_vector(4 downto 0) := "00100";
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
for i in token_in'reverse_range loop -- LSB first!
d := token_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d; --'0';
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--! @file openhub-rtl-ea.vhd
--
--! @brief OpenHUB
--
--! @details This is the openHUB using RMII Rx and Tx lines.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openhub is
generic (
--! Number of ports
gPortCount : integer := 3
);
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive paths
iRx : in tRmiiPathArray(gPortCount downto 1);
--! RMII transmit paths
oTx : out tRmiiPathArray(gPortCount downto 1);
--! Determine number of internal port (to MAC)
iIntPort : in integer range 1 to gPortCount := 1;
--! Transmit mask to enable ports
iTxMask : in std_logic_vector(gPortCount downto 1) := (others => cActivated);
--! Gives the number of the currectly receiving port
oRxPort : out integer range 0 to gPortCount
);
end entity openhub;
architecture rtl of openhub is
--! All ports inactive constant
constant cPortsAreInactive : std_logic_vector(gPortCount downto 0) := (others => cInactivated);
--! Receive path array
signal rxPath : tRmiiPathArray(gPortCount downto 0);
--! Receive path array delayed by one cycle
signal rxPath_l : tRmiiPathArray(gPortCount downto 0);
--! Transmit path array
signal txPath : tRmiiPathArray(gPortCount downto 0);
--! Stored transmit mask (is taken from iTxMask when to packet transfer is in progress)
signal txMask_reg : std_logic_vector(gPortCount downto 1);
begin
rxPath <= iRx & cRmiiPathInit;
oTx <= txPath(oTx'range);
do: process (iRst, iClk)
variable vActive : boolean;
variable vMaster : integer range 0 to gPortCount;
variable vMasterAtCollision : integer range 0 to gPortCount;
variable vCollision : boolean;
variable vRxDvm : std_logic_vector(gPortCount downto 0);
begin
if iRst = cActivated then
rxPath_l <= (others => cRmiiPathInit);
txPath <= (others => cRmiiPathInit);
vActive := false;
vMaster := 0;
vMasterAtCollision := 0;
vCollision := false;
txMask_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
rxPath_l <= rxPath;
if vActive = false then
if rmiiGetEnable(rxPath_l) /= cPortsAreInactive then
for i in 1 to gPortCount loop
if (rxPath_l(i).enable = cActivated and
(rxPath_l(i).data(0) = cActivated or rxPath_l(i).data(1) = cActivated)) then
vMaster := i;
vActive := true;
exit;
end if;
end loop;
end if;
else
if rxPath_l(vMaster).enable = cInactivated and rxPath(vMaster).enable = cInactivated then
vMaster := 0;
end if;
if rmiiGetEnable(rxPath_l) = cPortsAreInactive and rmiiGetEnable(rxPath) = cPortsAreInactive then
vActive := false;
end if;
end if;
if vMaster = 0 then
txPath <= (others => cRmiiPathInit);
-- overtake new iTxMask only, when there is no active frame.
txMask_reg <= iTxMask;
else
for i in 1 to gPortCount loop -- output received frame to every port
if i /= vMaster then -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> iTxMask is set to cActivated) or the internal port (mac)
if txMask_reg(i) = cActivated or vMaster = iIntPort then
txPath(i).enable <= cActivated;
txPath(i).data <= rxPath_l(vMaster).data;
end if;
-- if there is a frame received and another is sent => collision!
if rxPath_l(i).enable = cActivated then
vCollision := true;
vMasterAtCollision := vMaster;
end if;
end if;
end loop;
end if;
if vCollision = true then
txPath(vMasterAtCollision).enable <= cActivated;
txPath(vMasterAtCollision).data <= "01";
vRxDvm := rmiiGetEnable(rxPath_l);
vRxDvm(vMasterAtCollision) := cInactivated;
if vRxDvm = cPortsAreInactive then
txPath(vMasterAtCollision) <= cRmiiPathInit;
vCollision := false;
vMasterAtCollision := 0;
end if;
end if;
-- output the master port - identifies the port (1...n) which has received the packet.
-- if master is 0, the hub is inactive.
oRxPort <= vMaster;
end if;
end process do;
end rtl;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: CELL_GENERATOR
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- Ondřej Dujiček <xdujic02@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity KURZOR_CTRL is
Port (
CLK : in std_logic; -- Vychozi hodinovy signal
RST : in std_logic; -- Vychozi synchronni reset
KEY_W : in std_logic; -- Signal znacici zmacknuti tlacitka W
KEY_S : in std_logic; -- Signal znacici zmacknuti tlacitka S
KEY_A : in std_logic; -- Signal znacici zmacknuti tlacitka A
KEY_D : in std_logic; -- Signal znacici zmacknuti tlacitka D
KEY_SPACE : in std_logic; -- Signal znacici zmacknuti tlacitka SPACE
KOMP_GEN : out std_logic; -- Generuj novou nahodnou komponentu
KURZOR_ADDR : out std_logic_vector(7 downto 0); -- Adresa pozice kurzoru
DATAIN : in std_logic_vector(31 downto 0); -- Vstupni data
DATAOUT : out std_logic_vector(31 downto 0); -- Vystupni data
ADDR : out std_logic_vector(7 downto 0); -- Vystupni data
WE : out std_logic; -- Write enable
EN : out std_logic; -- Enable pameti
ACK : in std_logic; -- Potvrzeni zapisoveho nebo cteciho prikazu
KOMP4 : in std_logic_vector (5 downto 0);
CANT_PLACE : out std_logic;
CAN_PLACE : out std_logic;
SCREEN_CODE : in std_logic_vector(2 downto 0); -- game screen code
GAME_ON : in std_logic
);
end KURZOR_CTRL;
architecture FULL of KURZOR_CTRL is
type rom_t is array (15 downto 0) of std_logic_vector(15 downto 0);
constant LEVEL2_MAP : rom_t := (
"1111111111111111",
"1111111111111111",
"1111111111111111",
"1100001000000000",
"1100001000000000",
"1100001000000000",
"1100001000000000",
"1100001000000000",
"1100001000010000",
"1100001000010000",
"1100001000010000",
"1100000000010000",
"1100000000010000",
"1100000000010000",
"1100000000010000",
"1100000000010000"
);
constant LEVEL3_MAP : rom_t := (
"1111111111111111",
"1111111111111111",
"1111111111111111",
"1100000100000000",
"1100000100000000",
"1100000100000000",
"1111000100111000",
"1100000100100000",
"1100000100100000",
"1100000100100000",
"1100000100100000",
"1100000100100000",
"1100011100100011",
"1100000000100000",
"1100000000100000",
"1100000000100000"
);
constant LEVEL4_MAP : rom_t := (
"1111111111111111",
"1111111111111111",
"1111111111111111",
"1100000100000000",
"1100100100111100",
"1100100100000000",
"1100000100100111",
"1100000100100000",
"1100100100100000",
"1100100100100100",
"1100000100100100",
"1100000100100000",
"1111100100100000",
"1100000000100100",
"1100111100100100",
"1100000000100000"
);
signal sig_kurzor_addr : std_logic_vector(7 downto 0);
signal kurzor_x : unsigned(3 downto 0);
signal kurzor_y : unsigned(3 downto 0);
signal uprdownl : std_logic_vector(3 downto 0);
signal reset_en : std_logic;
signal gen_addr : unsigned(7 downto 0);
signal gen_en : std_logic;
signal gen_ok : std_logic;
signal lvl_gen : std_logic;
signal lvl2_row : std_logic_vector(15 downto 0);
signal lvl2_wall : std_logic;
signal lvl2_komp : std_logic_vector(1 downto 0);
signal lvl3_row : std_logic_vector(15 downto 0);
signal lvl3_wall : std_logic;
signal lvl3_komp : std_logic_vector(1 downto 0);
signal lvl4_row : std_logic_vector(15 downto 0);
signal lvl4_wall : std_logic;
signal lvl4_komp : std_logic_vector(1 downto 0);
type state is (wait_on_key, read_cell_data, data_check, pipe_insert,
reset_memory, lvl2_gen, lvl3_gen, lvl4_gen);
signal present_st : state;
signal next_st : state;
constant zeros_22 : std_logic_vector(21 downto 0) := (others => '0');
begin
----------------------------------------------------------------------------
-- RIZENI KURZORU
----------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
if (GAME_ON = '1') then
if (KEY_W = '1' AND kurzor_y > 0) then
kurzor_y <= kurzor_y - 1;
elsif (KEY_S = '1' AND kurzor_y < 12) then
kurzor_y <= kurzor_y + 1;
elsif (KEY_A = '1' AND kurzor_x > 0) then
kurzor_x <= kurzor_x - 1;
elsif (KEY_D = '1' AND kurzor_x < 13) then
kurzor_x <= kurzor_x + 1;
end if;
else
kurzor_x <= "0000";
kurzor_y <= "0000";
end if;
end if;
end process;
sig_kurzor_addr <= std_logic_vector(kurzor_y & kurzor_x);
KURZOR_ADDR <= sig_kurzor_addr;
----------------------------------------------------------------------------
-- VKLADANI ROUR - STAVOVY AUTOMAT
----------------------------------------------------------------------------
-- Pametova cast stavoveho automatu
process (CLK, RST)
begin
if (RST = '1') then
present_st <= reset_memory;
elsif (rising_edge(CLK)) then
if (SCREEN_CODE = "000") then
present_st <= reset_memory;
else
present_st <= next_st;
end if;
end if;
end process;
-- Rozhodovaci cast stavoveho automatu
process (present_st, KEY_SPACE, ACK, DATAIN, GAME_ON, SCREEN_CODE, gen_ok)
begin
case present_st is
when wait_on_key => -- cekani na stisk klavesy
if (KEY_SPACE = '1' AND GAME_ON = '1') then
next_st <= read_cell_data;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= wait_on_key;
end if;
when read_cell_data => -- vycteni dat o vybranem policku
if (ACK = '1') then
next_st <= data_check;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= read_cell_data;
end if;
when data_check => -- kontrola vyctenych dat
if (DATAIN(3 downto 0) = "0000") then
next_st <= pipe_insert;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= wait_on_key;
end if;
when pipe_insert => -- vlozeni trubky (zapis dat do pameti)
if (ACK = '1') then
next_st <= wait_on_key;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= pipe_insert;
end if;
when reset_memory => -- resetovani pameti
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= reset_memory;
end if;
when lvl2_gen => -- generovani lvl2
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= lvl2_gen;
end if;
when lvl3_gen => -- generovani lvl3
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= lvl3_gen;
end if;
when lvl4_gen => -- generovani lvl4
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= lvl4_gen;
end if;
when others =>
next_st <= wait_on_key;
end case;
end process;
-- Vystupni cast stavoveho automatu
process (present_st, KOMP4, sig_kurzor_addr, uprdownl, DATAIN,
gen_addr, lvl2_komp, lvl3_komp, lvl4_komp)
begin
case present_st is
when wait_on_key =>
EN <= '0';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when read_cell_data =>
EN <= '1';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when data_check =>
EN <= '0';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CAN_PLACE <= '0';
if (DATAIN(3 downto 0) = "0000") then
CANT_PLACE <= '0';
else
CANT_PLACE <= '1';
end if;
when pipe_insert =>
EN <= '1';
WE <= '1';
ADDR <= sig_kurzor_addr;
DATAOUT <= zeros_22 & uprdownl & KOMP4;
KOMP_GEN <= '1';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '1';
when reset_memory =>
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '1';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when lvl2_gen => -- generovani levlu 2
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= "0000000000000000000000000000" & lvl2_komp & "00";
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '1';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when lvl3_gen => -- generovani levlu 3
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= "0000000000000000000000000000" & lvl3_komp & "00";
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '1';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when lvl4_gen => -- generovani levlu 4
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= "0000000000000000000000000000" & lvl4_komp & "00";
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '1';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when others =>
EN <= '0';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
end case;
end process;
with KOMP4 select
uprdownl <= "0011" when "100010", -- zahnuta zprava nahoru
"1100" when "000010", -- zahnuta zleva dolu
"1001" when "010010", -- zahnuta zleva nahoru
"0110" when "110010", -- zahnuta zprava dolu
"1010" when "000001", -- rovna zleva doprava
"0101" when "010001", -- rovna zhora dolu
"1111" when "000011", -- krizova
"0000" when others;
--LDRU
----------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTER AND OK FLAG
----------------------------------------------------------------------------
gen_en <= lvl_gen or reset_en;
process (CLK)
begin
if rising_edge(CLK) then
if (gen_en = '1') then
gen_addr <= gen_addr + 1;
else
gen_addr <= (others=>'0');
end if;
end if;
end process;
gen_ok <= '1' when (gen_addr = "11111111") else '0';
----------------------------------------------------------------------------
-- LEVEL 2 ROM
----------------------------------------------------------------------------
lvl2_row <= LEVEL2_MAP(to_integer(gen_addr(7 downto 4)));
lvl2_wall <= lvl2_row(to_integer(gen_addr(3 downto 0)));
lvl2_komp <= "11" when (lvl2_wall = '1') else "00";
----------------------------------------------------------------------------
-- LEVEL 3 ROM
----------------------------------------------------------------------------
lvl3_row <= LEVEL3_MAP(to_integer(gen_addr(7 downto 4)));
lvl3_wall <= lvl3_row(to_integer(gen_addr(3 downto 0)));
lvl3_komp <= "11" when (lvl3_wall = '1') else "00";
----------------------------------------------------------------------------
-- LEVEL 4 ROM
----------------------------------------------------------------------------
lvl4_row <= LEVEL4_MAP(to_integer(gen_addr(7 downto 4)));
lvl4_wall <= lvl4_row(to_integer(gen_addr(3 downto 0)));
lvl4_komp <= "11" when (lvl4_wall = '1') else "00";
end FULL;
|
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_dec IS
Port
( --Ports
clr : In std_logic;
clk : In std_logic;
din : In std_logic_vector(63 downto 0);
din_vld : In std_logic;
key_rdy : In std_logic;
skey : In rom;
dout : Out std_logic_vector(63 downto 0);
dout_rdy : Out std_logic
);
End rc5_dec;
Architecture rtl Of rc5_dec IS
--signals --Signals
Signal i_cnt : Std_logic_vector(3 downto 0);
Signal ab_key : Std_logic_vector(31 downto 0);
Signal a_rot : Std_logic_vector(31 downto 0);
Signal a : Std_logic_vector(31 downto 0);
Signal a_reg : Std_logic_vector(31 downto 0);
Signal a_skey0 : Std_logic_vector(31 downto 0);
Signal ba_key : Std_logic_vector(31 downto 0);
Signal b_rot : Std_logic_vector(31 downto 0);
Signal b : Std_logic_vector(31 downto 0);
Signal b_reg : Std_logic_vector(31 downto 0);
Signal b_skey1 : Std_logic_vector(31 downto 0);
--Type for state machine
Type StateType IS
(
ST_idle,
ST_pre_round,
ST_round_op,
ST_ready
);
--Signal for state machine
Signal state_de : StateType;
--Architecture
Begin
--Step Pre_B
b_skey1 <= b_reg - skey(1); --Subtract skey(1) from din
--Step B (B=((B-S[2*i+1])>>>A) XOR A)
ba_key <= b_reg - skey(Conv_Integer(i_cnt & '1')); --Subtract key from B
With a_reg(4 downto 0) Select --rotate B by A
b_rot <= ba_key (0) & ba_key(31 downto 1) when "00001",
ba_key(1 downto 0) & ba_key(31 downto 2) when "00010",
ba_key(2 downto 0) & ba_key(31 downto 3) when "00011",
ba_key(3 downto 0) & ba_key(31 downto 4) when "00100",
ba_key(4 downto 0) & ba_key(31 downto 5) when "00101",
ba_key(5 downto 0) & ba_key(31 downto 6) when "00110",
ba_key(6 downto 0) & ba_key(31 downto 7) when "00111",
ba_key(7 downto 0) & ba_key(31 downto 8) when "01000",
ba_key(8 downto 0) & ba_key(31 downto 9) when "01001",
ba_key(9 downto 0) & ba_key(31 downto 10) when "01010",
ba_key(10 downto 0) & ba_key(31 downto 11) when "01011",
ba_key(11 downto 0) & ba_key(31 downto 12) when "01100",
ba_key(12 downto 0) & ba_key(31 downto 13) when "01101",
ba_key(13 downto 0) & ba_key(31 downto 14) when "01110",
ba_key(14 downto 0) & ba_key(31 downto 15) when "01111",
ba_key(15 downto 0) & ba_key(31 downto 16) when "10000",
ba_key(16 downto 0) & ba_key(31 downto 17) when "10001",
ba_key(17 downto 0) & ba_key(31 downto 18) when "10010",
ba_key(18 downto 0) & ba_key(31 downto 19) when "10011",
ba_key(19 downto 0) & ba_key(31 downto 20) when "10100",
ba_key(20 downto 0) & ba_key(31 downto 21) when "10101",
ba_key(21 downto 0) & ba_key(31 downto 22) when "10110",
ba_key(22 downto 0) & ba_key(31 downto 23) when "10111",
ba_key(23 downto 0) & ba_key(31 downto 24) when "11000",
ba_key(24 downto 0) & ba_key(31 downto 25) when "11001",
ba_key(25 downto 0) & ba_key(31 downto 26) when "11010",
ba_key(26 downto 0) & ba_key(31 downto 27) when "11011",
ba_key(27 downto 0) & ba_key(31 downto 28) when "11100",
ba_key(28 downto 0) & ba_key(31 downto 29) when "11101",
ba_key(29 downto 0) & ba_key(31 downto 30) when "11110",
ba_key(30 downto 0) & ba_key(31) when "11111",
ba_key when others;
b <= b_rot XOR a_reg; --XOR with A after rotation
--Step A (A=((A-S[2*i])>>>B) XOR B)
a_skey0 <= a_reg - skey(0);
ab_key <= a_reg - skey(Conv_Integer(i_cnt & '0')); --subtract key from A
With b(4 downto 0) Select --Rotate A by result of b
a_rot <= ab_key (0) & ab_key(31 downto 1) when "00001",
ab_key(1 downto 0) & ab_key(31 downto 2) when "00010",
ab_key(2 downto 0) & ab_key(31 downto 3) when "00011",
ab_key(3 downto 0) & ab_key(31 downto 4) when "00100",
ab_key(4 downto 0) & ab_key(31 downto 5) when "00101",
ab_key(5 downto 0) & ab_key(31 downto 6) when "00110",
ab_key(6 downto 0) & ab_key(31 downto 7) when "00111",
ab_key(7 downto 0) & ab_key(31 downto 8) when "01000",
ab_key(8 downto 0) & ab_key(31 downto 9) when "01001",
ab_key(9 downto 0) & ab_key(31 downto 10) when "01010",
ab_key(10 downto 0) & ab_key(31 downto 11) when "01011",
ab_key(11 downto 0) & ab_key(31 downto 12) when "01100",
ab_key(12 downto 0) & ab_key(31 downto 13) when "01101",
ab_key(13 downto 0) & ab_key(31 downto 14) when "01110",
ab_key(14 downto 0) & ab_key(31 downto 15) when "01111",
ab_key(15 downto 0) & ab_key(31 downto 16) when "10000",
ab_key(16 downto 0) & ab_key(31 downto 17) when "10001",
ab_key(17 downto 0) & ab_key(31 downto 18) when "10010",
ab_key(18 downto 0) & ab_key(31 downto 19) when "10011",
ab_key(19 downto 0) & ab_key(31 downto 20) when "10100",
ab_key(20 downto 0) & ab_key(31 downto 21) when "10101",
ab_key(21 downto 0) & ab_key(31 downto 22) when "10110",
ab_key(22 downto 0) & ab_key(31 downto 23) when "10111",
ab_key(23 downto 0) & ab_key(31 downto 24) when "11000",
ab_key(24 downto 0) & ab_key(31 downto 25) when "11001",
ab_key(25 downto 0) & ab_key(31 downto 26) when "11010",
ab_key(26 downto 0) & ab_key(31 downto 27) when "11011",
ab_key(27 downto 0) & ab_key(31 downto 28) when "11100",
ab_key(28 downto 0) & ab_key(31 downto 29) when "11101",
ab_key(29 downto 0) & ab_key(31 downto 30) when "11110",
ab_key(30 downto 0) & ab_key(31) when "11111",
ab_key when others;
a <= a_rot XOR b; --XOR rotated A with result of b
--Register A
Process(clr, clk) Begin
If(clr='0') Then
a_reg <= din(63 downto 32);
elsif(clk'Event and clk='1') Then
If (state_de = ST_round_op) Then
a_reg <= a;
End If;
End If;
End Process;
--Register B
Process(clr, clk) Begin
If(clr='0') Then
b_reg <= din(31 downto 0);
Elsif(clk'Event and clk='1') Then
If (state_de = ST_round_op) Then
b_reg <= b;
End If;
End If;
End Process;
--State Machine Counter
Process(clr, clk) Begin
If(clr='0') Then
state_de <= ST_idle;
Elsif(clk'Event And clk='1') Then
Case state_de IS
When ST_idle => If (din_vld = '1' and key_rdy='1') Then state_de <= ST_round_op; End If;
When ST_round_op => If (i_cnt = "0001") Then state_de <= ST_pre_round; End If;
When ST_pre_round => state_de <= ST_ready;
When ST_ready => state_de <= ST_idle;
End Case;
End If;
End Process;
--Round Counter
Process(clr, clk) Begin
If(clr='0') Then
i_cnt <= "1100";
Elsif(clk'Event And clk='1') Then
If (state_de = ST_round_op) Then
If(i_cnt="0001") Then
i_cnt <= "1100";
Else
i_cnt <= i_cnt - '1';
End If;
End If;
End If;
End Process;
--Output
dout <= a_skey0 & b_skey1;
With state_de Select
dout_rdy <= '1' When ST_ready,
'0' When Others;
End rtl; |
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_dec IS
Port
( --Ports
clr : In std_logic;
clk : In std_logic;
din : In std_logic_vector(63 downto 0);
din_vld : In std_logic;
key_rdy : In std_logic;
skey : In rom;
dout : Out std_logic_vector(63 downto 0);
dout_rdy : Out std_logic
);
End rc5_dec;
Architecture rtl Of rc5_dec IS
--signals --Signals
Signal i_cnt : Std_logic_vector(3 downto 0);
Signal ab_key : Std_logic_vector(31 downto 0);
Signal a_rot : Std_logic_vector(31 downto 0);
Signal a : Std_logic_vector(31 downto 0);
Signal a_reg : Std_logic_vector(31 downto 0);
Signal a_skey0 : Std_logic_vector(31 downto 0);
Signal ba_key : Std_logic_vector(31 downto 0);
Signal b_rot : Std_logic_vector(31 downto 0);
Signal b : Std_logic_vector(31 downto 0);
Signal b_reg : Std_logic_vector(31 downto 0);
Signal b_skey1 : Std_logic_vector(31 downto 0);
--Type for state machine
Type StateType IS
(
ST_idle,
ST_pre_round,
ST_round_op,
ST_ready
);
--Signal for state machine
Signal state_de : StateType;
--Architecture
Begin
--Step Pre_B
b_skey1 <= b_reg - skey(1); --Subtract skey(1) from din
--Step B (B=((B-S[2*i+1])>>>A) XOR A)
ba_key <= b_reg - skey(Conv_Integer(i_cnt & '1')); --Subtract key from B
With a_reg(4 downto 0) Select --rotate B by A
b_rot <= ba_key (0) & ba_key(31 downto 1) when "00001",
ba_key(1 downto 0) & ba_key(31 downto 2) when "00010",
ba_key(2 downto 0) & ba_key(31 downto 3) when "00011",
ba_key(3 downto 0) & ba_key(31 downto 4) when "00100",
ba_key(4 downto 0) & ba_key(31 downto 5) when "00101",
ba_key(5 downto 0) & ba_key(31 downto 6) when "00110",
ba_key(6 downto 0) & ba_key(31 downto 7) when "00111",
ba_key(7 downto 0) & ba_key(31 downto 8) when "01000",
ba_key(8 downto 0) & ba_key(31 downto 9) when "01001",
ba_key(9 downto 0) & ba_key(31 downto 10) when "01010",
ba_key(10 downto 0) & ba_key(31 downto 11) when "01011",
ba_key(11 downto 0) & ba_key(31 downto 12) when "01100",
ba_key(12 downto 0) & ba_key(31 downto 13) when "01101",
ba_key(13 downto 0) & ba_key(31 downto 14) when "01110",
ba_key(14 downto 0) & ba_key(31 downto 15) when "01111",
ba_key(15 downto 0) & ba_key(31 downto 16) when "10000",
ba_key(16 downto 0) & ba_key(31 downto 17) when "10001",
ba_key(17 downto 0) & ba_key(31 downto 18) when "10010",
ba_key(18 downto 0) & ba_key(31 downto 19) when "10011",
ba_key(19 downto 0) & ba_key(31 downto 20) when "10100",
ba_key(20 downto 0) & ba_key(31 downto 21) when "10101",
ba_key(21 downto 0) & ba_key(31 downto 22) when "10110",
ba_key(22 downto 0) & ba_key(31 downto 23) when "10111",
ba_key(23 downto 0) & ba_key(31 downto 24) when "11000",
ba_key(24 downto 0) & ba_key(31 downto 25) when "11001",
ba_key(25 downto 0) & ba_key(31 downto 26) when "11010",
ba_key(26 downto 0) & ba_key(31 downto 27) when "11011",
ba_key(27 downto 0) & ba_key(31 downto 28) when "11100",
ba_key(28 downto 0) & ba_key(31 downto 29) when "11101",
ba_key(29 downto 0) & ba_key(31 downto 30) when "11110",
ba_key(30 downto 0) & ba_key(31) when "11111",
ba_key when others;
b <= b_rot XOR a_reg; --XOR with A after rotation
--Step A (A=((A-S[2*i])>>>B) XOR B)
a_skey0 <= a_reg - skey(0);
ab_key <= a_reg - skey(Conv_Integer(i_cnt & '0')); --subtract key from A
With b(4 downto 0) Select --Rotate A by result of b
a_rot <= ab_key (0) & ab_key(31 downto 1) when "00001",
ab_key(1 downto 0) & ab_key(31 downto 2) when "00010",
ab_key(2 downto 0) & ab_key(31 downto 3) when "00011",
ab_key(3 downto 0) & ab_key(31 downto 4) when "00100",
ab_key(4 downto 0) & ab_key(31 downto 5) when "00101",
ab_key(5 downto 0) & ab_key(31 downto 6) when "00110",
ab_key(6 downto 0) & ab_key(31 downto 7) when "00111",
ab_key(7 downto 0) & ab_key(31 downto 8) when "01000",
ab_key(8 downto 0) & ab_key(31 downto 9) when "01001",
ab_key(9 downto 0) & ab_key(31 downto 10) when "01010",
ab_key(10 downto 0) & ab_key(31 downto 11) when "01011",
ab_key(11 downto 0) & ab_key(31 downto 12) when "01100",
ab_key(12 downto 0) & ab_key(31 downto 13) when "01101",
ab_key(13 downto 0) & ab_key(31 downto 14) when "01110",
ab_key(14 downto 0) & ab_key(31 downto 15) when "01111",
ab_key(15 downto 0) & ab_key(31 downto 16) when "10000",
ab_key(16 downto 0) & ab_key(31 downto 17) when "10001",
ab_key(17 downto 0) & ab_key(31 downto 18) when "10010",
ab_key(18 downto 0) & ab_key(31 downto 19) when "10011",
ab_key(19 downto 0) & ab_key(31 downto 20) when "10100",
ab_key(20 downto 0) & ab_key(31 downto 21) when "10101",
ab_key(21 downto 0) & ab_key(31 downto 22) when "10110",
ab_key(22 downto 0) & ab_key(31 downto 23) when "10111",
ab_key(23 downto 0) & ab_key(31 downto 24) when "11000",
ab_key(24 downto 0) & ab_key(31 downto 25) when "11001",
ab_key(25 downto 0) & ab_key(31 downto 26) when "11010",
ab_key(26 downto 0) & ab_key(31 downto 27) when "11011",
ab_key(27 downto 0) & ab_key(31 downto 28) when "11100",
ab_key(28 downto 0) & ab_key(31 downto 29) when "11101",
ab_key(29 downto 0) & ab_key(31 downto 30) when "11110",
ab_key(30 downto 0) & ab_key(31) when "11111",
ab_key when others;
a <= a_rot XOR b; --XOR rotated A with result of b
--Register A
Process(clr, clk) Begin
If(clr='0') Then
a_reg <= din(63 downto 32);
elsif(clk'Event and clk='1') Then
If (state_de = ST_round_op) Then
a_reg <= a;
End If;
End If;
End Process;
--Register B
Process(clr, clk) Begin
If(clr='0') Then
b_reg <= din(31 downto 0);
Elsif(clk'Event and clk='1') Then
If (state_de = ST_round_op) Then
b_reg <= b;
End If;
End If;
End Process;
--State Machine Counter
Process(clr, clk) Begin
If(clr='0') Then
state_de <= ST_idle;
Elsif(clk'Event And clk='1') Then
Case state_de IS
When ST_idle => If (din_vld = '1' and key_rdy='1') Then state_de <= ST_round_op; End If;
When ST_round_op => If (i_cnt = "0001") Then state_de <= ST_pre_round; End If;
When ST_pre_round => state_de <= ST_ready;
When ST_ready => state_de <= ST_idle;
End Case;
End If;
End Process;
--Round Counter
Process(clr, clk) Begin
If(clr='0') Then
i_cnt <= "1100";
Elsif(clk'Event And clk='1') Then
If (state_de = ST_round_op) Then
If(i_cnt="0001") Then
i_cnt <= "1100";
Else
i_cnt <= i_cnt - '1';
End If;
End If;
End If;
End Process;
--Output
dout <= a_skey0 & b_skey1;
With state_de Select
dout_rdy <= '1' When ST_ready,
'0' When Others;
End rtl; |
-- VHDL Entity R6502_TC.Testbench.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 13:06:53 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity Testbench is
port(
IRQn : in std_logic;
NMIn : in std_logic;
RDY : in std_logic;
RSTn : in std_logic;
clk : in std_logic;
clk1 : in std_logic;
so_n_i : in std_logic;
A : out std_logic_vector (15 downto 0);
CPU_DOUT : out std_logic_vector ( 7 downto 0 );
RAM_DOUT : out std_logic_vector (7 downto 0);
RD : out std_logic;
SYNC : out std_logic;
WR : out std_logic
);
-- Declarations
end Testbench ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $log$
--
-- Title: Testbench for the 6502 Core
-- Path: R6502_TC/Testbench/struct
-- Edited: by eda on 08 Apr 2008
--
-- VHDL Architecture R6502_TC.Testbench.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 13:06:54 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library R6502_TC;
architecture struct of Testbench is
-- Architecture declarations
-- Internal signal declarations
signal dout : std_logic_vector(7 downto 0);
signal dout1 : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal CPU_DOUT_internal : std_logic_vector ( 7 downto 0 );
signal RAM_DOUT_internal : std_logic_vector (7 downto 0);
signal WR_internal : std_logic;
signal A_internal : std_logic_vector (15 downto 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_2' of 'ramsp'
type MW_U_2RAM_TYPE is array (((2**16) -1) downto 0) of std_logic_vector(7 downto 0);
signal mw_U_2ram_table : MW_U_2RAM_TYPE := (others => "00000000");
signal mw_U_2addr_reg: std_logic_vector(15 downto 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'rom'
type MW_U_3ROM_TYPE is array(65535 downto 0) of std_logic_vector(7 downto 0);
signal mw_U_3rom_table : MW_U_3ROM_TYPE;
signal mw_U_3addr_int : INTEGER := 0 ;
-- Component Declarations
component R6502_TC
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : R6502_TC use entity R6502_TC.R6502_TC;
-- pragma synthesis_on
begin
-- ModuleWare code(v1.9) for instance 'U_1' of 'mux'
u_1combo_proc: process(dout, dout1, A_internal(15))
begin
case A_internal(15) is
when '0' => RAM_DOUT_internal <= dout;
when '1' => RAM_DOUT_internal <= dout1;
when others => RAM_DOUT_internal <= (others => 'X');
end case;
end process u_1combo_proc;
-- ModuleWare code(v1.9) for instance 'U_2' of 'ramsp'
--attribute block_ram : boolean;
--attribute block_ram of mem : signal is false;
u_2ram_p_proc: process (clk1)
begin
if (clk1'event and clk1='1') then
if (WR_internal = '1') then
mw_U_2ram_table(CONV_INTEGER(unsigned(A_internal))) <= CPU_DOUT_internal;
end if;
mw_U_2addr_reg <= A_internal;
end if;
end process u_2ram_p_proc;
dout <= mw_U_2ram_table(CONV_INTEGER(unsigned(mw_U_2addr_reg)));
-- ModuleWare code(v1.9) for instance 'U_3' of 'rom'
mw_U_3addr_int <= (CONV_INTEGER(unsigned(A_internal(15 DOWNTO 0))));
u_3rom_table_proc : process ( mw_U_3addr_int )
begin
case mw_U_3addr_int is
when 32768 => mw_U_3rom_table(32768) <= "11111111";
when 32769 => mw_U_3rom_table(32769) <= "11111111";
when 32770 => mw_U_3rom_table(32770) <= "11111111";
when 32771 => mw_U_3rom_table(32771) <= "11111111";
when 32772 => mw_U_3rom_table(32772) <= "11111111";
when 32773 => mw_U_3rom_table(32773) <= "11111111";
when 32774 => mw_U_3rom_table(32774) <= "11111111";
when 32775 => mw_U_3rom_table(32775) <= "11111111";
when 32776 => mw_U_3rom_table(32776) <= "11111111";
when 32777 => mw_U_3rom_table(32777) <= "11111111";
when 32778 => mw_U_3rom_table(32778) <= "11111111";
when 32779 => mw_U_3rom_table(32779) <= "11111111";
when 32780 => mw_U_3rom_table(32780) <= "11111111";
when 32781 => mw_U_3rom_table(32781) <= "11111111";
when 32782 => mw_U_3rom_table(32782) <= "11111111";
when 32783 => mw_U_3rom_table(32783) <= "11111111";
when 32784 => mw_U_3rom_table(32784) <= "11111111";
when 32785 => mw_U_3rom_table(32785) <= "11111111";
when 32786 => mw_U_3rom_table(32786) <= "11111111";
when 32787 => mw_U_3rom_table(32787) <= "11111111";
when 32788 => mw_U_3rom_table(32788) <= "11111111";
when 32789 => mw_U_3rom_table(32789) <= "11111111";
when 32790 => mw_U_3rom_table(32790) <= "11111111";
when 32791 => mw_U_3rom_table(32791) <= "11111111";
when 32792 => mw_U_3rom_table(32792) <= "11111111";
when 32793 => mw_U_3rom_table(32793) <= "11111111";
when 32794 => mw_U_3rom_table(32794) <= "11111111";
when 32795 => mw_U_3rom_table(32795) <= "11111111";
when 32796 => mw_U_3rom_table(32796) <= "11111111";
when 32797 => mw_U_3rom_table(32797) <= "11111111";
when 32798 => mw_U_3rom_table(32798) <= "11111111";
when 32799 => mw_U_3rom_table(32799) <= "00000000";
when 57344 => mw_U_3rom_table(57344) <= "00010100";
when 57345 => mw_U_3rom_table(57345) <= "00000000";
when 57346 => mw_U_3rom_table(57346) <= "00001010";
when 57347 => mw_U_3rom_table(57347) <= "00000000";
when 57348 => mw_U_3rom_table(57348) <= "00000100";
when 57349 => mw_U_3rom_table(57349) <= "00000000";
when 57350 => mw_U_3rom_table(57350) <= "00000011";
when 57351 => mw_U_3rom_table(57351) <= "00000000";
when 57352 => mw_U_3rom_table(57352) <= "00000010";
when 57353 => mw_U_3rom_table(57353) <= "00000000";
when 57354 => mw_U_3rom_table(57354) <= "00000001";
when 57355 => mw_U_3rom_table(57355) <= "00000000";
when 57356 => mw_U_3rom_table(57356) <= "00000000";
when 57357 => mw_U_3rom_table(57357) <= "00000100";
when 57358 => mw_U_3rom_table(57358) <= "11010010";
when 57359 => mw_U_3rom_table(57359) <= "00000100";
when 57360 => mw_U_3rom_table(57360) <= "11010010";
when 57361 => mw_U_3rom_table(57361) <= "00000010";
when 57362 => mw_U_3rom_table(57362) <= "10011100";
when 57363 => mw_U_3rom_table(57363) <= "00000010";
when 57364 => mw_U_3rom_table(57364) <= "10011100";
when 57365 => mw_U_3rom_table(57365) <= "00000000";
when 57366 => mw_U_3rom_table(57366) <= "00101010";
when 57367 => mw_U_3rom_table(57367) <= "00000000";
when 57368 => mw_U_3rom_table(57368) <= "00101010";
when 57369 => mw_U_3rom_table(57369) <= "00010010";
when 57370 => mw_U_3rom_table(57370) <= "00110100";
when 57371 => mw_U_3rom_table(57371) <= "00000110";
when 57372 => mw_U_3rom_table(57372) <= "00010001";
when 57373 => mw_U_3rom_table(57373) <= "00010010";
when 57374 => mw_U_3rom_table(57374) <= "00110100";
when 57375 => mw_U_3rom_table(57375) <= "00010010";
when 57376 => mw_U_3rom_table(57376) <= "00000001";
when 57377 => mw_U_3rom_table(57377) <= "00000000";
when 57378 => mw_U_3rom_table(57378) <= "00000001";
when 57379 => mw_U_3rom_table(57379) <= "00000000";
when 57380 => mw_U_3rom_table(57380) <= "00000001";
when 57381 => mw_U_3rom_table(57381) <= "00000000";
when 57382 => mw_U_3rom_table(57382) <= "00000000";
when 57383 => mw_U_3rom_table(57383) <= "00000000";
when 57384 => mw_U_3rom_table(57384) <= "00000001";
when 57385 => mw_U_3rom_table(57385) <= "00000000";
when 57386 => mw_U_3rom_table(57386) <= "00000000";
when 57387 => mw_U_3rom_table(57387) <= "00000000";
when 57388 => mw_U_3rom_table(57388) <= "00000001";
when 57389 => mw_U_3rom_table(57389) <= "00100011";
when 57390 => mw_U_3rom_table(57390) <= "01000000";
when 57391 => mw_U_3rom_table(57391) <= "00000001";
when 57392 => mw_U_3rom_table(57392) <= "00100011";
when 57393 => mw_U_3rom_table(57393) <= "00000000";
when 57394 => mw_U_3rom_table(57394) <= "00000011";
when 57395 => mw_U_3rom_table(57395) <= "11111111";
when 57396 => mw_U_3rom_table(57396) <= "11111100";
when 57397 => mw_U_3rom_table(57397) <= "00000000";
when 57398 => mw_U_3rom_table(57398) <= "00001010";
when 57399 => mw_U_3rom_table(57399) <= "00000000";
when 57400 => mw_U_3rom_table(57400) <= "00010101";
when 57401 => mw_U_3rom_table(57401) <= "11100000";
when 57402 => mw_U_3rom_table(57402) <= "00100101";
when 57403 => mw_U_3rom_table(57403) <= "11100000";
when 57404 => mw_U_3rom_table(57404) <= "00100011";
when 57405 => mw_U_3rom_table(57405) <= "00000000";
when 57406 => mw_U_3rom_table(57406) <= "01100100";
when 57407 => mw_U_3rom_table(57407) <= "00000000";
when 57408 => mw_U_3rom_table(57408) <= "11111111";
when 57409 => mw_U_3rom_table(57409) <= "11111111";
when 57410 => mw_U_3rom_table(57410) <= "11111111";
when 57411 => mw_U_3rom_table(57411) <= "11111111";
when 57412 => mw_U_3rom_table(57412) <= "11111111";
when 57413 => mw_U_3rom_table(57413) <= "11111111";
when 57414 => mw_U_3rom_table(57414) <= "11111111";
when 57415 => mw_U_3rom_table(57415) <= "11111111";
when 57416 => mw_U_3rom_table(57416) <= "11111111";
when 57417 => mw_U_3rom_table(57417) <= "11111111";
when 57418 => mw_U_3rom_table(57418) <= "11111111";
when 57419 => mw_U_3rom_table(57419) <= "11111111";
when 57420 => mw_U_3rom_table(57420) <= "11111111";
when 57421 => mw_U_3rom_table(57421) <= "11111111";
when 57422 => mw_U_3rom_table(57422) <= "11111111";
when 57423 => mw_U_3rom_table(57423) <= "11111111";
when 57424 => mw_U_3rom_table(57424) <= "11111111";
when 57425 => mw_U_3rom_table(57425) <= "11111111";
when 57426 => mw_U_3rom_table(57426) <= "11111111";
when 57427 => mw_U_3rom_table(57427) <= "11111111";
when 57428 => mw_U_3rom_table(57428) <= "11111111";
when 57429 => mw_U_3rom_table(57429) <= "11111111";
when 57430 => mw_U_3rom_table(57430) <= "11111111";
when 57431 => mw_U_3rom_table(57431) <= "11111111";
when 57432 => mw_U_3rom_table(57432) <= "11111111";
when 57433 => mw_U_3rom_table(57433) <= "00010010";
when 57434 => mw_U_3rom_table(57434) <= "00110100";
when 57435 => mw_U_3rom_table(57435) <= "00000000";
when 57436 => mw_U_3rom_table(57436) <= "00000000";
when 57437 => mw_U_3rom_table(57437) <= "00000000";
when 57438 => mw_U_3rom_table(57438) <= "00000000";
when 57439 => mw_U_3rom_table(57439) <= "00000000";
when 61440 => mw_U_3rom_table(61440) <= "00000110";
when 61441 => mw_U_3rom_table(61441) <= "10101101";
when 61442 => mw_U_3rom_table(61442) <= "01011011";
when 61443 => mw_U_3rom_table(61443) <= "10000101";
when 61444 => mw_U_3rom_table(61444) <= "11100000";
when 61445 => mw_U_3rom_table(61445) <= "00000101";
when 61446 => mw_U_3rom_table(61446) <= "10101101";
when 61447 => mw_U_3rom_table(61447) <= "01011010";
when 61448 => mw_U_3rom_table(61448) <= "10000101";
when 61449 => mw_U_3rom_table(61449) <= "11100000";
when 61450 => mw_U_3rom_table(61450) <= "00000100";
when 61451 => mw_U_3rom_table(61451) <= "10101101";
when 61452 => mw_U_3rom_table(61452) <= "01011001";
when 61453 => mw_U_3rom_table(61453) <= "10000101";
when 61454 => mw_U_3rom_table(61454) <= "11100000";
when 61455 => mw_U_3rom_table(61455) <= "00000011";
when 61456 => mw_U_3rom_table(61456) <= "10101101";
when 61457 => mw_U_3rom_table(61457) <= "01011000";
when 61458 => mw_U_3rom_table(61458) <= "10000101";
when 61459 => mw_U_3rom_table(61459) <= "11100000";
when 61460 => mw_U_3rom_table(61460) <= "00000010";
when 61461 => mw_U_3rom_table(61461) <= "10101101";
when 61462 => mw_U_3rom_table(61462) <= "01010111";
when 61463 => mw_U_3rom_table(61463) <= "10000101";
when 61464 => mw_U_3rom_table(61464) <= "11100000";
when 61465 => mw_U_3rom_table(61465) <= "00000001";
when 61466 => mw_U_3rom_table(61466) <= "10101101";
when 61467 => mw_U_3rom_table(61467) <= "01010110";
when 61468 => mw_U_3rom_table(61468) <= "10000101";
when 61469 => mw_U_3rom_table(61469) <= "11100000";
when 61470 => mw_U_3rom_table(61470) <= "00000000";
when 61471 => mw_U_3rom_table(61471) <= "10101101";
when 61472 => mw_U_3rom_table(61472) <= "10000101";
when 61473 => mw_U_3rom_table(61473) <= "11100000";
when 61474 => mw_U_3rom_table(61474) <= "00001100";
when 61475 => mw_U_3rom_table(61475) <= "10101101";
when 61476 => mw_U_3rom_table(61476) <= "01100001";
when 61477 => mw_U_3rom_table(61477) <= "10000101";
when 61478 => mw_U_3rom_table(61478) <= "11100000";
when 61479 => mw_U_3rom_table(61479) <= "00001011";
when 61480 => mw_U_3rom_table(61480) <= "10101101";
when 61481 => mw_U_3rom_table(61481) <= "01100000";
when 61482 => mw_U_3rom_table(61482) <= "10000101";
when 61483 => mw_U_3rom_table(61483) <= "11100000";
when 61484 => mw_U_3rom_table(61484) <= "00001010";
when 61485 => mw_U_3rom_table(61485) <= "10101101";
when 61486 => mw_U_3rom_table(61486) <= "01011111";
when 61487 => mw_U_3rom_table(61487) <= "10000101";
when 61488 => mw_U_3rom_table(61488) <= "11100000";
when 61489 => mw_U_3rom_table(61489) <= "00001001";
when 61490 => mw_U_3rom_table(61490) <= "10101101";
when 61491 => mw_U_3rom_table(61491) <= "01011110";
when 61492 => mw_U_3rom_table(61492) <= "10000101";
when 61493 => mw_U_3rom_table(61493) <= "11100000";
when 61494 => mw_U_3rom_table(61494) <= "00001000";
when 61495 => mw_U_3rom_table(61495) <= "10101101";
when 61496 => mw_U_3rom_table(61496) <= "01011101";
when 61497 => mw_U_3rom_table(61497) <= "10000101";
when 61498 => mw_U_3rom_table(61498) <= "11100000";
when 61499 => mw_U_3rom_table(61499) <= "00000111";
when 61500 => mw_U_3rom_table(61500) <= "10101101";
when 61501 => mw_U_3rom_table(61501) <= "01011100";
when 61502 => mw_U_3rom_table(61502) <= "10000101";
when 61503 => mw_U_3rom_table(61503) <= "11100000";
when 61504 => mw_U_3rom_table(61504) <= "10101101";
when 61505 => mw_U_3rom_table(61505) <= "01101000";
when 61506 => mw_U_3rom_table(61506) <= "10000101";
when 61507 => mw_U_3rom_table(61507) <= "11100000";
when 61508 => mw_U_3rom_table(61508) <= "00010010";
when 61509 => mw_U_3rom_table(61509) <= "10101101";
when 61510 => mw_U_3rom_table(61510) <= "01100111";
when 61511 => mw_U_3rom_table(61511) <= "10000101";
when 61512 => mw_U_3rom_table(61512) <= "11100000";
when 61513 => mw_U_3rom_table(61513) <= "00010001";
when 61514 => mw_U_3rom_table(61514) <= "10101101";
when 61515 => mw_U_3rom_table(61515) <= "01100110";
when 61516 => mw_U_3rom_table(61516) <= "10000101";
when 61517 => mw_U_3rom_table(61517) <= "11100000";
when 61518 => mw_U_3rom_table(61518) <= "00010000";
when 61519 => mw_U_3rom_table(61519) <= "10101101";
when 61520 => mw_U_3rom_table(61520) <= "01100101";
when 61521 => mw_U_3rom_table(61521) <= "10000101";
when 61522 => mw_U_3rom_table(61522) <= "11100000";
when 61523 => mw_U_3rom_table(61523) <= "00001111";
when 61524 => mw_U_3rom_table(61524) <= "10101101";
when 61525 => mw_U_3rom_table(61525) <= "01100100";
when 61526 => mw_U_3rom_table(61526) <= "10000101";
when 61527 => mw_U_3rom_table(61527) <= "11100000";
when 61528 => mw_U_3rom_table(61528) <= "00001110";
when 61529 => mw_U_3rom_table(61529) <= "10101101";
when 61530 => mw_U_3rom_table(61530) <= "01100011";
when 61531 => mw_U_3rom_table(61531) <= "10000101";
when 61532 => mw_U_3rom_table(61532) <= "11100000";
when 61533 => mw_U_3rom_table(61533) <= "00001101";
when 61534 => mw_U_3rom_table(61534) <= "10101101";
when 61535 => mw_U_3rom_table(61535) <= "01100010";
when 61536 => mw_U_3rom_table(61536) <= "11100000";
when 61537 => mw_U_3rom_table(61537) <= "00011001";
when 61538 => mw_U_3rom_table(61538) <= "10101101";
when 61539 => mw_U_3rom_table(61539) <= "01101110";
when 61540 => mw_U_3rom_table(61540) <= "10000101";
when 61541 => mw_U_3rom_table(61541) <= "11100000";
when 61542 => mw_U_3rom_table(61542) <= "00011000";
when 61543 => mw_U_3rom_table(61543) <= "10101101";
when 61544 => mw_U_3rom_table(61544) <= "01101101";
when 61545 => mw_U_3rom_table(61545) <= "10000101";
when 61546 => mw_U_3rom_table(61546) <= "11100000";
when 61547 => mw_U_3rom_table(61547) <= "00010111";
when 61548 => mw_U_3rom_table(61548) <= "10101101";
when 61549 => mw_U_3rom_table(61549) <= "01101100";
when 61550 => mw_U_3rom_table(61550) <= "10000101";
when 61551 => mw_U_3rom_table(61551) <= "11100000";
when 61552 => mw_U_3rom_table(61552) <= "00010110";
when 61553 => mw_U_3rom_table(61553) <= "10101101";
when 61554 => mw_U_3rom_table(61554) <= "01101011";
when 61555 => mw_U_3rom_table(61555) <= "10000101";
when 61556 => mw_U_3rom_table(61556) <= "11100000";
when 61557 => mw_U_3rom_table(61557) <= "00010101";
when 61558 => mw_U_3rom_table(61558) <= "10101101";
when 61559 => mw_U_3rom_table(61559) <= "01101010";
when 61560 => mw_U_3rom_table(61560) <= "10000101";
when 61561 => mw_U_3rom_table(61561) <= "11100000";
when 61562 => mw_U_3rom_table(61562) <= "00010100";
when 61563 => mw_U_3rom_table(61563) <= "10101101";
when 61564 => mw_U_3rom_table(61564) <= "01101001";
when 61565 => mw_U_3rom_table(61565) <= "10000101";
when 61566 => mw_U_3rom_table(61566) <= "11100000";
when 61567 => mw_U_3rom_table(61567) <= "00010011";
when 61568 => mw_U_3rom_table(61568) <= "01110101";
when 61569 => mw_U_3rom_table(61569) <= "10000101";
when 61570 => mw_U_3rom_table(61570) <= "11100000";
when 61571 => mw_U_3rom_table(61571) <= "00011111";
when 61572 => mw_U_3rom_table(61572) <= "10101101";
when 61573 => mw_U_3rom_table(61573) <= "01110100";
when 61574 => mw_U_3rom_table(61574) <= "10000101";
when 61575 => mw_U_3rom_table(61575) <= "11100000";
when 61576 => mw_U_3rom_table(61576) <= "00011110";
when 61577 => mw_U_3rom_table(61577) <= "10101101";
when 61578 => mw_U_3rom_table(61578) <= "01110011";
when 61579 => mw_U_3rom_table(61579) <= "10000101";
when 61580 => mw_U_3rom_table(61580) <= "11100000";
when 61581 => mw_U_3rom_table(61581) <= "00011101";
when 61582 => mw_U_3rom_table(61582) <= "10101101";
when 61583 => mw_U_3rom_table(61583) <= "01110010";
when 61584 => mw_U_3rom_table(61584) <= "10000101";
when 61585 => mw_U_3rom_table(61585) <= "11100000";
when 61586 => mw_U_3rom_table(61586) <= "00011100";
when 61587 => mw_U_3rom_table(61587) <= "10101101";
when 61588 => mw_U_3rom_table(61588) <= "01110001";
when 61589 => mw_U_3rom_table(61589) <= "10000101";
when 61590 => mw_U_3rom_table(61590) <= "11100000";
when 61591 => mw_U_3rom_table(61591) <= "00011011";
when 61592 => mw_U_3rom_table(61592) <= "10101101";
when 61593 => mw_U_3rom_table(61593) <= "01110000";
when 61594 => mw_U_3rom_table(61594) <= "10000101";
when 61595 => mw_U_3rom_table(61595) <= "11100000";
when 61596 => mw_U_3rom_table(61596) <= "00011010";
when 61597 => mw_U_3rom_table(61597) <= "10101101";
when 61598 => mw_U_3rom_table(61598) <= "01101111";
when 61599 => mw_U_3rom_table(61599) <= "10000101";
when 61600 => mw_U_3rom_table(61600) <= "00100110";
when 61601 => mw_U_3rom_table(61601) <= "10101101";
when 61602 => mw_U_3rom_table(61602) <= "01111011";
when 61603 => mw_U_3rom_table(61603) <= "10000101";
when 61604 => mw_U_3rom_table(61604) <= "11100000";
when 61605 => mw_U_3rom_table(61605) <= "00100101";
when 61606 => mw_U_3rom_table(61606) <= "10101101";
when 61607 => mw_U_3rom_table(61607) <= "01111010";
when 61608 => mw_U_3rom_table(61608) <= "10000101";
when 61609 => mw_U_3rom_table(61609) <= "11100000";
when 61610 => mw_U_3rom_table(61610) <= "00100100";
when 61611 => mw_U_3rom_table(61611) <= "10101101";
when 61612 => mw_U_3rom_table(61612) <= "01111001";
when 61613 => mw_U_3rom_table(61613) <= "10000101";
when 61614 => mw_U_3rom_table(61614) <= "11100000";
when 61615 => mw_U_3rom_table(61615) <= "00100011";
when 61616 => mw_U_3rom_table(61616) <= "10101101";
when 61617 => mw_U_3rom_table(61617) <= "01111000";
when 61618 => mw_U_3rom_table(61618) <= "10000101";
when 61619 => mw_U_3rom_table(61619) <= "11100000";
when 61620 => mw_U_3rom_table(61620) <= "00100010";
when 61621 => mw_U_3rom_table(61621) <= "10101101";
when 61622 => mw_U_3rom_table(61622) <= "01110111";
when 61623 => mw_U_3rom_table(61623) <= "10000101";
when 61624 => mw_U_3rom_table(61624) <= "11100000";
when 61625 => mw_U_3rom_table(61625) <= "00100001";
when 61626 => mw_U_3rom_table(61626) <= "10101101";
when 61627 => mw_U_3rom_table(61627) <= "01110110";
when 61628 => mw_U_3rom_table(61628) <= "10000101";
when 61629 => mw_U_3rom_table(61629) <= "11100000";
when 61630 => mw_U_3rom_table(61630) <= "00100000";
when 61631 => mw_U_3rom_table(61631) <= "10101101";
when 61632 => mw_U_3rom_table(61632) <= "10000101";
when 61633 => mw_U_3rom_table(61633) <= "11100000";
when 61634 => mw_U_3rom_table(61634) <= "00101100";
when 61635 => mw_U_3rom_table(61635) <= "10101101";
when 61636 => mw_U_3rom_table(61636) <= "10000001";
when 61637 => mw_U_3rom_table(61637) <= "10000101";
when 61638 => mw_U_3rom_table(61638) <= "11100000";
when 61639 => mw_U_3rom_table(61639) <= "00101011";
when 61640 => mw_U_3rom_table(61640) <= "10101101";
when 61641 => mw_U_3rom_table(61641) <= "10000000";
when 61642 => mw_U_3rom_table(61642) <= "10000101";
when 61643 => mw_U_3rom_table(61643) <= "11100000";
when 61644 => mw_U_3rom_table(61644) <= "00101010";
when 61645 => mw_U_3rom_table(61645) <= "10101101";
when 61646 => mw_U_3rom_table(61646) <= "01111111";
when 61647 => mw_U_3rom_table(61647) <= "10000101";
when 61648 => mw_U_3rom_table(61648) <= "11100000";
when 61649 => mw_U_3rom_table(61649) <= "00101001";
when 61650 => mw_U_3rom_table(61650) <= "10101101";
when 61651 => mw_U_3rom_table(61651) <= "01111110";
when 61652 => mw_U_3rom_table(61652) <= "10000101";
when 61653 => mw_U_3rom_table(61653) <= "11100000";
when 61654 => mw_U_3rom_table(61654) <= "00101000";
when 61655 => mw_U_3rom_table(61655) <= "10101101";
when 61656 => mw_U_3rom_table(61656) <= "01111101";
when 61657 => mw_U_3rom_table(61657) <= "10000101";
when 61658 => mw_U_3rom_table(61658) <= "11100000";
when 61659 => mw_U_3rom_table(61659) <= "00100111";
when 61660 => mw_U_3rom_table(61660) <= "10101101";
when 61661 => mw_U_3rom_table(61661) <= "01111100";
when 61662 => mw_U_3rom_table(61662) <= "10000101";
when 61663 => mw_U_3rom_table(61663) <= "11100000";
when 61664 => mw_U_3rom_table(61664) <= "10101101";
when 61665 => mw_U_3rom_table(61665) <= "10001000";
when 61666 => mw_U_3rom_table(61666) <= "10000101";
when 61667 => mw_U_3rom_table(61667) <= "11100000";
when 61668 => mw_U_3rom_table(61668) <= "00110010";
when 61669 => mw_U_3rom_table(61669) <= "10101101";
when 61670 => mw_U_3rom_table(61670) <= "10000111";
when 61671 => mw_U_3rom_table(61671) <= "10000101";
when 61672 => mw_U_3rom_table(61672) <= "11100000";
when 61673 => mw_U_3rom_table(61673) <= "00110001";
when 61674 => mw_U_3rom_table(61674) <= "10101101";
when 61675 => mw_U_3rom_table(61675) <= "10000110";
when 61676 => mw_U_3rom_table(61676) <= "10000101";
when 61677 => mw_U_3rom_table(61677) <= "11100000";
when 61678 => mw_U_3rom_table(61678) <= "00110000";
when 61679 => mw_U_3rom_table(61679) <= "10101101";
when 61680 => mw_U_3rom_table(61680) <= "10000101";
when 61681 => mw_U_3rom_table(61681) <= "10000101";
when 61682 => mw_U_3rom_table(61682) <= "11100000";
when 61683 => mw_U_3rom_table(61683) <= "00101111";
when 61684 => mw_U_3rom_table(61684) <= "10101101";
when 61685 => mw_U_3rom_table(61685) <= "10000100";
when 61686 => mw_U_3rom_table(61686) <= "10000101";
when 61687 => mw_U_3rom_table(61687) <= "11100000";
when 61688 => mw_U_3rom_table(61688) <= "00101110";
when 61689 => mw_U_3rom_table(61689) <= "10101101";
when 61690 => mw_U_3rom_table(61690) <= "10000011";
when 61691 => mw_U_3rom_table(61691) <= "10000101";
when 61692 => mw_U_3rom_table(61692) <= "11100000";
when 61693 => mw_U_3rom_table(61693) <= "00101101";
when 61694 => mw_U_3rom_table(61694) <= "10101101";
when 61695 => mw_U_3rom_table(61695) <= "10000010";
when 61696 => mw_U_3rom_table(61696) <= "11100000";
when 61697 => mw_U_3rom_table(61697) <= "00111001";
when 61698 => mw_U_3rom_table(61698) <= "10101101";
when 61699 => mw_U_3rom_table(61699) <= "10001110";
when 61700 => mw_U_3rom_table(61700) <= "10000101";
when 61701 => mw_U_3rom_table(61701) <= "11100000";
when 61702 => mw_U_3rom_table(61702) <= "00111000";
when 61703 => mw_U_3rom_table(61703) <= "10101101";
when 61704 => mw_U_3rom_table(61704) <= "10001101";
when 61705 => mw_U_3rom_table(61705) <= "10000101";
when 61706 => mw_U_3rom_table(61706) <= "11100000";
when 61707 => mw_U_3rom_table(61707) <= "00110111";
when 61708 => mw_U_3rom_table(61708) <= "10101101";
when 61709 => mw_U_3rom_table(61709) <= "10001100";
when 61710 => mw_U_3rom_table(61710) <= "10000101";
when 61711 => mw_U_3rom_table(61711) <= "11100000";
when 61712 => mw_U_3rom_table(61712) <= "00110110";
when 61713 => mw_U_3rom_table(61713) <= "10101101";
when 61714 => mw_U_3rom_table(61714) <= "10001011";
when 61715 => mw_U_3rom_table(61715) <= "10000101";
when 61716 => mw_U_3rom_table(61716) <= "11100000";
when 61717 => mw_U_3rom_table(61717) <= "00110101";
when 61718 => mw_U_3rom_table(61718) <= "10101101";
when 61719 => mw_U_3rom_table(61719) <= "10001010";
when 61720 => mw_U_3rom_table(61720) <= "10000101";
when 61721 => mw_U_3rom_table(61721) <= "11100000";
when 61722 => mw_U_3rom_table(61722) <= "00110100";
when 61723 => mw_U_3rom_table(61723) <= "10101101";
when 61724 => mw_U_3rom_table(61724) <= "10001001";
when 61725 => mw_U_3rom_table(61725) <= "10000101";
when 61726 => mw_U_3rom_table(61726) <= "11100000";
when 61727 => mw_U_3rom_table(61727) <= "00110011";
when 61728 => mw_U_3rom_table(61728) <= "10010101";
when 61729 => mw_U_3rom_table(61729) <= "10000101";
when 61730 => mw_U_3rom_table(61730) <= "11100000";
when 61731 => mw_U_3rom_table(61731) <= "00111111";
when 61732 => mw_U_3rom_table(61732) <= "10101101";
when 61733 => mw_U_3rom_table(61733) <= "10010100";
when 61734 => mw_U_3rom_table(61734) <= "10000101";
when 61735 => mw_U_3rom_table(61735) <= "11100000";
when 61736 => mw_U_3rom_table(61736) <= "00111110";
when 61737 => mw_U_3rom_table(61737) <= "10101101";
when 61738 => mw_U_3rom_table(61738) <= "10010011";
when 61739 => mw_U_3rom_table(61739) <= "10000101";
when 61740 => mw_U_3rom_table(61740) <= "11100000";
when 61741 => mw_U_3rom_table(61741) <= "00111101";
when 61742 => mw_U_3rom_table(61742) <= "10101101";
when 61743 => mw_U_3rom_table(61743) <= "10010010";
when 61744 => mw_U_3rom_table(61744) <= "10000101";
when 61745 => mw_U_3rom_table(61745) <= "11100000";
when 61746 => mw_U_3rom_table(61746) <= "00111100";
when 61747 => mw_U_3rom_table(61747) <= "10101101";
when 61748 => mw_U_3rom_table(61748) <= "10010001";
when 61749 => mw_U_3rom_table(61749) <= "10000101";
when 61750 => mw_U_3rom_table(61750) <= "11100000";
when 61751 => mw_U_3rom_table(61751) <= "00111011";
when 61752 => mw_U_3rom_table(61752) <= "10101101";
when 61753 => mw_U_3rom_table(61753) <= "10010000";
when 61754 => mw_U_3rom_table(61754) <= "10000101";
when 61755 => mw_U_3rom_table(61755) <= "11100000";
when 61756 => mw_U_3rom_table(61756) <= "00111010";
when 61757 => mw_U_3rom_table(61757) <= "10101101";
when 61758 => mw_U_3rom_table(61758) <= "10001111";
when 61759 => mw_U_3rom_table(61759) <= "10000101";
when 61760 => mw_U_3rom_table(61760) <= "01000110";
when 61761 => mw_U_3rom_table(61761) <= "10101101";
when 61762 => mw_U_3rom_table(61762) <= "10011011";
when 61763 => mw_U_3rom_table(61763) <= "10000101";
when 61764 => mw_U_3rom_table(61764) <= "11100000";
when 61765 => mw_U_3rom_table(61765) <= "01000101";
when 61766 => mw_U_3rom_table(61766) <= "10101101";
when 61767 => mw_U_3rom_table(61767) <= "10011010";
when 61768 => mw_U_3rom_table(61768) <= "10000101";
when 61769 => mw_U_3rom_table(61769) <= "11100000";
when 61770 => mw_U_3rom_table(61770) <= "01000100";
when 61771 => mw_U_3rom_table(61771) <= "10101101";
when 61772 => mw_U_3rom_table(61772) <= "10011001";
when 61773 => mw_U_3rom_table(61773) <= "10000101";
when 61774 => mw_U_3rom_table(61774) <= "11100000";
when 61775 => mw_U_3rom_table(61775) <= "01000011";
when 61776 => mw_U_3rom_table(61776) <= "10101101";
when 61777 => mw_U_3rom_table(61777) <= "10011000";
when 61778 => mw_U_3rom_table(61778) <= "10000101";
when 61779 => mw_U_3rom_table(61779) <= "11100000";
when 61780 => mw_U_3rom_table(61780) <= "01000010";
when 61781 => mw_U_3rom_table(61781) <= "10101101";
when 61782 => mw_U_3rom_table(61782) <= "10010111";
when 61783 => mw_U_3rom_table(61783) <= "10000101";
when 61784 => mw_U_3rom_table(61784) <= "11100000";
when 61785 => mw_U_3rom_table(61785) <= "01000001";
when 61786 => mw_U_3rom_table(61786) <= "10101101";
when 61787 => mw_U_3rom_table(61787) <= "10010110";
when 61788 => mw_U_3rom_table(61788) <= "10000101";
when 61789 => mw_U_3rom_table(61789) <= "11100000";
when 61790 => mw_U_3rom_table(61790) <= "01000000";
when 61791 => mw_U_3rom_table(61791) <= "10101101";
when 61792 => mw_U_3rom_table(61792) <= "00110101";
when 61793 => mw_U_3rom_table(61793) <= "01010110";
when 61794 => mw_U_3rom_table(61794) <= "00110010";
when 61795 => mw_U_3rom_table(61795) <= "01010110";
when 61796 => mw_U_3rom_table(61796) <= "00110001";
when 61797 => mw_U_3rom_table(61797) <= "01010110";
when 61798 => mw_U_3rom_table(61798) <= "00100001";
when 61799 => mw_U_3rom_table(61799) <= "01010110";
when 61800 => mw_U_3rom_table(61800) <= "00101001";
when 61801 => mw_U_3rom_table(61801) <= "11110001";
when 61802 => mw_U_3rom_table(61802) <= "01100011";
when 61803 => mw_U_3rom_table(61803) <= "01101101";
when 61804 => mw_U_3rom_table(61804) <= "01010110";
when 61805 => mw_U_3rom_table(61805) <= "01100101";
when 61806 => mw_U_3rom_table(61806) <= "00000000";
when 61807 => mw_U_3rom_table(61807) <= "01010110";
when 61808 => mw_U_3rom_table(61808) <= "01111001";
when 61809 => mw_U_3rom_table(61809) <= "01010110";
when 61810 => mw_U_3rom_table(61810) <= "01110101";
when 61811 => mw_U_3rom_table(61811) <= "01010110";
when 61812 => mw_U_3rom_table(61812) <= "01110010";
when 61813 => mw_U_3rom_table(61813) <= "01010110";
when 61814 => mw_U_3rom_table(61814) <= "01110010";
when 61815 => mw_U_3rom_table(61815) <= "01010110";
when 61816 => mw_U_3rom_table(61816) <= "01110001";
when 61817 => mw_U_3rom_table(61817) <= "01010110";
when 61818 => mw_U_3rom_table(61818) <= "01100001";
when 61819 => mw_U_3rom_table(61819) <= "01010110";
when 61820 => mw_U_3rom_table(61820) <= "01101001";
when 61821 => mw_U_3rom_table(61821) <= "10011100";
when 61822 => mw_U_3rom_table(61822) <= "10000101";
when 61823 => mw_U_3rom_table(61823) <= "11100000";
when 61824 => mw_U_3rom_table(61824) <= "11101010";
when 61825 => mw_U_3rom_table(61825) <= "00000001";
when 61826 => mw_U_3rom_table(61826) <= "00010000";
when 61827 => mw_U_3rom_table(61827) <= "11101010";
when 61828 => mw_U_3rom_table(61828) <= "00000001";
when 61829 => mw_U_3rom_table(61829) <= "00110000";
when 61830 => mw_U_3rom_table(61830) <= "11101010";
when 61831 => mw_U_3rom_table(61831) <= "00000001";
when 61832 => mw_U_3rom_table(61832) <= "11010000";
when 61833 => mw_U_3rom_table(61833) <= "11101010";
when 61834 => mw_U_3rom_table(61834) <= "00000001";
when 61835 => mw_U_3rom_table(61835) <= "11110000";
when 61836 => mw_U_3rom_table(61836) <= "11101010";
when 61837 => mw_U_3rom_table(61837) <= "00000001";
when 61838 => mw_U_3rom_table(61838) <= "10110000";
when 61839 => mw_U_3rom_table(61839) <= "11101010";
when 61840 => mw_U_3rom_table(61840) <= "00000001";
when 61841 => mw_U_3rom_table(61841) <= "10010000";
when 61842 => mw_U_3rom_table(61842) <= "01010110";
when 61843 => mw_U_3rom_table(61843) <= "00000110";
when 61844 => mw_U_3rom_table(61844) <= "01010110";
when 61845 => mw_U_3rom_table(61845) <= "00010110";
when 61846 => mw_U_3rom_table(61846) <= "00001010";
when 61847 => mw_U_3rom_table(61847) <= "11110001";
when 61848 => mw_U_3rom_table(61848) <= "01100011";
when 61849 => mw_U_3rom_table(61849) <= "00101101";
when 61850 => mw_U_3rom_table(61850) <= "01010110";
when 61851 => mw_U_3rom_table(61851) <= "00100101";
when 61852 => mw_U_3rom_table(61852) <= "00000000";
when 61853 => mw_U_3rom_table(61853) <= "01010110";
when 61854 => mw_U_3rom_table(61854) <= "00111001";
when 61855 => mw_U_3rom_table(61855) <= "01010110";
when 61856 => mw_U_3rom_table(61856) <= "01010110";
when 61857 => mw_U_3rom_table(61857) <= "11011001";
when 61858 => mw_U_3rom_table(61858) <= "01010110";
when 61859 => mw_U_3rom_table(61859) <= "11010101";
when 61860 => mw_U_3rom_table(61860) <= "01010110";
when 61861 => mw_U_3rom_table(61861) <= "11010010";
when 61862 => mw_U_3rom_table(61862) <= "01010110";
when 61863 => mw_U_3rom_table(61863) <= "11010001";
when 61864 => mw_U_3rom_table(61864) <= "01010110";
when 61865 => mw_U_3rom_table(61865) <= "11000001";
when 61866 => mw_U_3rom_table(61866) <= "01010110";
when 61867 => mw_U_3rom_table(61867) <= "11001001";
when 61868 => mw_U_3rom_table(61868) <= "10111000";
when 61869 => mw_U_3rom_table(61869) <= "01011000";
when 61870 => mw_U_3rom_table(61870) <= "11011000";
when 61871 => mw_U_3rom_table(61871) <= "00011000";
when 61872 => mw_U_3rom_table(61872) <= "00000000";
when 61873 => mw_U_3rom_table(61873) <= "11110001";
when 61874 => mw_U_3rom_table(61874) <= "01100011";
when 61875 => mw_U_3rom_table(61875) <= "00101100";
when 61876 => mw_U_3rom_table(61876) <= "01010110";
when 61877 => mw_U_3rom_table(61877) <= "00100100";
when 61878 => mw_U_3rom_table(61878) <= "01010110";
when 61879 => mw_U_3rom_table(61879) <= "00110100";
when 61880 => mw_U_3rom_table(61880) <= "01010110";
when 61881 => mw_U_3rom_table(61881) <= "10001001";
when 61882 => mw_U_3rom_table(61882) <= "11101010";
when 61883 => mw_U_3rom_table(61883) <= "00000001";
when 61884 => mw_U_3rom_table(61884) <= "01110000";
when 61885 => mw_U_3rom_table(61885) <= "11101010";
when 61886 => mw_U_3rom_table(61886) <= "00000001";
when 61887 => mw_U_3rom_table(61887) <= "01010000";
when 61888 => mw_U_3rom_table(61888) <= "11001010";
when 61889 => mw_U_3rom_table(61889) <= "11110001";
when 61890 => mw_U_3rom_table(61890) <= "01100011";
when 61891 => mw_U_3rom_table(61891) <= "11001110";
when 61892 => mw_U_3rom_table(61892) <= "01010110";
when 61893 => mw_U_3rom_table(61893) <= "11000110";
when 61894 => mw_U_3rom_table(61894) <= "11110001";
when 61895 => mw_U_3rom_table(61895) <= "01100011";
when 61896 => mw_U_3rom_table(61896) <= "11011110";
when 61897 => mw_U_3rom_table(61897) <= "01010110";
when 61898 => mw_U_3rom_table(61898) <= "11010110";
when 61899 => mw_U_3rom_table(61899) <= "00111010";
when 61900 => mw_U_3rom_table(61900) <= "11110001";
when 61901 => mw_U_3rom_table(61901) <= "01100011";
when 61902 => mw_U_3rom_table(61902) <= "11001100";
when 61903 => mw_U_3rom_table(61903) <= "01010110";
when 61904 => mw_U_3rom_table(61904) <= "11000100";
when 61905 => mw_U_3rom_table(61905) <= "01010110";
when 61906 => mw_U_3rom_table(61906) <= "11000000";
when 61907 => mw_U_3rom_table(61907) <= "11110001";
when 61908 => mw_U_3rom_table(61908) <= "01100011";
when 61909 => mw_U_3rom_table(61909) <= "11101100";
when 61910 => mw_U_3rom_table(61910) <= "01010110";
when 61911 => mw_U_3rom_table(61911) <= "11100100";
when 61912 => mw_U_3rom_table(61912) <= "01010110";
when 61913 => mw_U_3rom_table(61913) <= "11100000";
when 61914 => mw_U_3rom_table(61914) <= "11110001";
when 61915 => mw_U_3rom_table(61915) <= "01100011";
when 61916 => mw_U_3rom_table(61916) <= "11001101";
when 61917 => mw_U_3rom_table(61917) <= "01010110";
when 61918 => mw_U_3rom_table(61918) <= "11000101";
when 61919 => mw_U_3rom_table(61919) <= "00000000";
when 61920 => mw_U_3rom_table(61920) <= "11001000";
when 61921 => mw_U_3rom_table(61921) <= "11101000";
when 61922 => mw_U_3rom_table(61922) <= "11110001";
when 61923 => mw_U_3rom_table(61923) <= "01100011";
when 61924 => mw_U_3rom_table(61924) <= "11101110";
when 61925 => mw_U_3rom_table(61925) <= "01010110";
when 61926 => mw_U_3rom_table(61926) <= "11100110";
when 61927 => mw_U_3rom_table(61927) <= "11110001";
when 61928 => mw_U_3rom_table(61928) <= "01100011";
when 61929 => mw_U_3rom_table(61929) <= "11111110";
when 61930 => mw_U_3rom_table(61930) <= "01010110";
when 61931 => mw_U_3rom_table(61931) <= "11110110";
when 61932 => mw_U_3rom_table(61932) <= "00011010";
when 61933 => mw_U_3rom_table(61933) <= "11110001";
when 61934 => mw_U_3rom_table(61934) <= "01100011";
when 61935 => mw_U_3rom_table(61935) <= "01001101";
when 61936 => mw_U_3rom_table(61936) <= "01010110";
when 61937 => mw_U_3rom_table(61937) <= "01000101";
when 61938 => mw_U_3rom_table(61938) <= "00000000";
when 61939 => mw_U_3rom_table(61939) <= "01010110";
when 61940 => mw_U_3rom_table(61940) <= "01011001";
when 61941 => mw_U_3rom_table(61941) <= "01010110";
when 61942 => mw_U_3rom_table(61942) <= "01010101";
when 61943 => mw_U_3rom_table(61943) <= "01010110";
when 61944 => mw_U_3rom_table(61944) <= "01010010";
when 61945 => mw_U_3rom_table(61945) <= "01010110";
when 61946 => mw_U_3rom_table(61946) <= "01010001";
when 61947 => mw_U_3rom_table(61947) <= "01010110";
when 61948 => mw_U_3rom_table(61948) <= "01000001";
when 61949 => mw_U_3rom_table(61949) <= "01010110";
when 61950 => mw_U_3rom_table(61950) <= "01001001";
when 61951 => mw_U_3rom_table(61951) <= "10001000";
when 61952 => mw_U_3rom_table(61952) <= "01100011";
when 61953 => mw_U_3rom_table(61953) <= "10101101";
when 61954 => mw_U_3rom_table(61954) <= "01010110";
when 61955 => mw_U_3rom_table(61955) <= "10100101";
when 61956 => mw_U_3rom_table(61956) <= "00000000";
when 61957 => mw_U_3rom_table(61957) <= "01010110";
when 61958 => mw_U_3rom_table(61958) <= "10111001";
when 61959 => mw_U_3rom_table(61959) <= "01010110";
when 61960 => mw_U_3rom_table(61960) <= "10110101";
when 61961 => mw_U_3rom_table(61961) <= "01010110";
when 61962 => mw_U_3rom_table(61962) <= "10110010";
when 61963 => mw_U_3rom_table(61963) <= "01010110";
when 61964 => mw_U_3rom_table(61964) <= "10110001";
when 61965 => mw_U_3rom_table(61965) <= "01010110";
when 61966 => mw_U_3rom_table(61966) <= "10100001";
when 61967 => mw_U_3rom_table(61967) <= "01010110";
when 61968 => mw_U_3rom_table(61968) <= "10101001";
when 61969 => mw_U_3rom_table(61969) <= "11110001";
when 61970 => mw_U_3rom_table(61970) <= "01100011";
when 61971 => mw_U_3rom_table(61971) <= "00100000";
when 61972 => mw_U_3rom_table(61972) <= "00000000";
when 61973 => mw_U_3rom_table(61973) <= "01010110";
when 61974 => mw_U_3rom_table(61974) <= "00100000";
when 61975 => mw_U_3rom_table(61975) <= "00000000";
when 61976 => mw_U_3rom_table(61976) <= "01010110";
when 61977 => mw_U_3rom_table(61977) <= "01001100";
when 61978 => mw_U_3rom_table(61978) <= "00000000";
when 61979 => mw_U_3rom_table(61979) <= "01010110";
when 61980 => mw_U_3rom_table(61980) <= "01101100";
when 61981 => mw_U_3rom_table(61981) <= "00000000";
when 61982 => mw_U_3rom_table(61982) <= "01010110";
when 61983 => mw_U_3rom_table(61983) <= "01111100";
when 61984 => mw_U_3rom_table(61984) <= "01010110";
when 61985 => mw_U_3rom_table(61985) <= "00000001";
when 61986 => mw_U_3rom_table(61986) <= "01010110";
when 61987 => mw_U_3rom_table(61987) <= "00001001";
when 61988 => mw_U_3rom_table(61988) <= "11101010";
when 61989 => mw_U_3rom_table(61989) <= "11110001";
when 61990 => mw_U_3rom_table(61990) <= "01100011";
when 61991 => mw_U_3rom_table(61991) <= "01001110";
when 61992 => mw_U_3rom_table(61992) <= "01010110";
when 61993 => mw_U_3rom_table(61993) <= "01000110";
when 61994 => mw_U_3rom_table(61994) <= "01010110";
when 61995 => mw_U_3rom_table(61995) <= "01010110";
when 61996 => mw_U_3rom_table(61996) <= "01001010";
when 61997 => mw_U_3rom_table(61997) <= "11110001";
when 61998 => mw_U_3rom_table(61998) <= "01100011";
when 61999 => mw_U_3rom_table(61999) <= "10101100";
when 62000 => mw_U_3rom_table(62000) <= "01010110";
when 62001 => mw_U_3rom_table(62001) <= "10100100";
when 62002 => mw_U_3rom_table(62002) <= "01010110";
when 62003 => mw_U_3rom_table(62003) <= "10110100";
when 62004 => mw_U_3rom_table(62004) <= "01010110";
when 62005 => mw_U_3rom_table(62005) <= "10100000";
when 62006 => mw_U_3rom_table(62006) <= "11110001";
when 62007 => mw_U_3rom_table(62007) <= "01100011";
when 62008 => mw_U_3rom_table(62008) <= "10101110";
when 62009 => mw_U_3rom_table(62009) <= "01010110";
when 62010 => mw_U_3rom_table(62010) <= "10100110";
when 62011 => mw_U_3rom_table(62011) <= "01010110";
when 62012 => mw_U_3rom_table(62012) <= "10110110";
when 62013 => mw_U_3rom_table(62013) <= "01010110";
when 62014 => mw_U_3rom_table(62014) <= "10100010";
when 62015 => mw_U_3rom_table(62015) <= "11110001";
when 62016 => mw_U_3rom_table(62016) <= "11110001";
when 62017 => mw_U_3rom_table(62017) <= "01100011";
when 62018 => mw_U_3rom_table(62018) <= "01111110";
when 62019 => mw_U_3rom_table(62019) <= "01010110";
when 62020 => mw_U_3rom_table(62020) <= "01110110";
when 62021 => mw_U_3rom_table(62021) <= "01101010";
when 62022 => mw_U_3rom_table(62022) <= "11110001";
when 62023 => mw_U_3rom_table(62023) <= "01100011";
when 62024 => mw_U_3rom_table(62024) <= "00101110";
when 62025 => mw_U_3rom_table(62025) <= "01010110";
when 62026 => mw_U_3rom_table(62026) <= "00100110";
when 62027 => mw_U_3rom_table(62027) <= "01010110";
when 62028 => mw_U_3rom_table(62028) <= "00110110";
when 62029 => mw_U_3rom_table(62029) <= "00101010";
when 62030 => mw_U_3rom_table(62030) <= "00101000";
when 62031 => mw_U_3rom_table(62031) <= "01101000";
when 62032 => mw_U_3rom_table(62032) <= "00001000";
when 62033 => mw_U_3rom_table(62033) <= "01001000";
when 62034 => mw_U_3rom_table(62034) <= "11110001";
when 62035 => mw_U_3rom_table(62035) <= "01100011";
when 62036 => mw_U_3rom_table(62036) <= "00001101";
when 62037 => mw_U_3rom_table(62037) <= "01010110";
when 62038 => mw_U_3rom_table(62038) <= "00000101";
when 62039 => mw_U_3rom_table(62039) <= "00000000";
when 62040 => mw_U_3rom_table(62040) <= "01010110";
when 62041 => mw_U_3rom_table(62041) <= "00011001";
when 62042 => mw_U_3rom_table(62042) <= "01010110";
when 62043 => mw_U_3rom_table(62043) <= "00010101";
when 62044 => mw_U_3rom_table(62044) <= "01010110";
when 62045 => mw_U_3rom_table(62045) <= "00010010";
when 62046 => mw_U_3rom_table(62046) <= "01010110";
when 62047 => mw_U_3rom_table(62047) <= "00010001";
when 62048 => mw_U_3rom_table(62048) <= "01010110";
when 62049 => mw_U_3rom_table(62049) <= "10010001";
when 62050 => mw_U_3rom_table(62050) <= "01010110";
when 62051 => mw_U_3rom_table(62051) <= "10000001";
when 62052 => mw_U_3rom_table(62052) <= "01111000";
when 62053 => mw_U_3rom_table(62053) <= "11111000";
when 62054 => mw_U_3rom_table(62054) <= "00111000";
when 62055 => mw_U_3rom_table(62055) <= "11110001";
when 62056 => mw_U_3rom_table(62056) <= "01100011";
when 62057 => mw_U_3rom_table(62057) <= "11101101";
when 62058 => mw_U_3rom_table(62058) <= "01010110";
when 62059 => mw_U_3rom_table(62059) <= "11100101";
when 62060 => mw_U_3rom_table(62060) <= "00000000";
when 62061 => mw_U_3rom_table(62061) <= "01010110";
when 62062 => mw_U_3rom_table(62062) <= "11111001";
when 62063 => mw_U_3rom_table(62063) <= "01010110";
when 62064 => mw_U_3rom_table(62064) <= "11110101";
when 62065 => mw_U_3rom_table(62065) <= "01010110";
when 62066 => mw_U_3rom_table(62066) <= "11110010";
when 62067 => mw_U_3rom_table(62067) <= "01010110";
when 62068 => mw_U_3rom_table(62068) <= "11110001";
when 62069 => mw_U_3rom_table(62069) <= "01010110";
when 62070 => mw_U_3rom_table(62070) <= "11100001";
when 62071 => mw_U_3rom_table(62071) <= "01010110";
when 62072 => mw_U_3rom_table(62072) <= "11101001";
when 62073 => mw_U_3rom_table(62073) <= "01100000";
when 62074 => mw_U_3rom_table(62074) <= "01000000";
when 62075 => mw_U_3rom_table(62075) <= "11110001";
when 62076 => mw_U_3rom_table(62076) <= "01100011";
when 62077 => mw_U_3rom_table(62077) <= "01101110";
when 62078 => mw_U_3rom_table(62078) <= "01010110";
when 62079 => mw_U_3rom_table(62079) <= "01100110";
when 62080 => mw_U_3rom_table(62080) <= "10011000";
when 62081 => mw_U_3rom_table(62081) <= "10011010";
when 62082 => mw_U_3rom_table(62082) <= "10001010";
when 62083 => mw_U_3rom_table(62083) <= "10111010";
when 62084 => mw_U_3rom_table(62084) <= "10101000";
when 62085 => mw_U_3rom_table(62085) <= "10101010";
when 62086 => mw_U_3rom_table(62086) <= "11110001";
when 62087 => mw_U_3rom_table(62087) <= "01100011";
when 62088 => mw_U_3rom_table(62088) <= "10001100";
when 62089 => mw_U_3rom_table(62089) <= "01010110";
when 62090 => mw_U_3rom_table(62090) <= "10000100";
when 62091 => mw_U_3rom_table(62091) <= "01010110";
when 62092 => mw_U_3rom_table(62092) <= "10010100";
when 62093 => mw_U_3rom_table(62093) <= "11110001";
when 62094 => mw_U_3rom_table(62094) <= "01100011";
when 62095 => mw_U_3rom_table(62095) <= "10001110";
when 62096 => mw_U_3rom_table(62096) <= "01010110";
when 62097 => mw_U_3rom_table(62097) <= "10000110";
when 62098 => mw_U_3rom_table(62098) <= "01010110";
when 62099 => mw_U_3rom_table(62099) <= "10010110";
when 62100 => mw_U_3rom_table(62100) <= "11110001";
when 62101 => mw_U_3rom_table(62101) <= "01100011";
when 62102 => mw_U_3rom_table(62102) <= "10001101";
when 62103 => mw_U_3rom_table(62103) <= "01010110";
when 62104 => mw_U_3rom_table(62104) <= "10000101";
when 62105 => mw_U_3rom_table(62105) <= "00000000";
when 62106 => mw_U_3rom_table(62106) <= "01010110";
when 62107 => mw_U_3rom_table(62107) <= "10011001";
when 62108 => mw_U_3rom_table(62108) <= "01010110";
when 62109 => mw_U_3rom_table(62109) <= "10010101";
when 62110 => mw_U_3rom_table(62110) <= "01010110";
when 62111 => mw_U_3rom_table(62111) <= "10010010";
when 62112 => mw_U_3rom_table(62112) <= "11100010";
when 62113 => mw_U_3rom_table(62113) <= "01010110";
when 62114 => mw_U_3rom_table(62114) <= "10011111";
when 62115 => mw_U_3rom_table(62115) <= "11100101";
when 62116 => mw_U_3rom_table(62116) <= "01010110";
when 62117 => mw_U_3rom_table(62117) <= "10001111";
when 62118 => mw_U_3rom_table(62118) <= "11101000";
when 62119 => mw_U_3rom_table(62119) <= "01010110";
when 62120 => mw_U_3rom_table(62120) <= "01111111";
when 62121 => mw_U_3rom_table(62121) <= "11101011";
when 62122 => mw_U_3rom_table(62122) <= "01010110";
when 62123 => mw_U_3rom_table(62123) <= "01101111";
when 62124 => mw_U_3rom_table(62124) <= "11101110";
when 62125 => mw_U_3rom_table(62125) <= "01010110";
when 62126 => mw_U_3rom_table(62126) <= "01011111";
when 62127 => mw_U_3rom_table(62127) <= "11110001";
when 62128 => mw_U_3rom_table(62128) <= "01010110";
when 62129 => mw_U_3rom_table(62129) <= "01001111";
when 62130 => mw_U_3rom_table(62130) <= "11110100";
when 62131 => mw_U_3rom_table(62131) <= "01010110";
when 62132 => mw_U_3rom_table(62132) <= "00111111";
when 62133 => mw_U_3rom_table(62133) <= "11110111";
when 62134 => mw_U_3rom_table(62134) <= "01010110";
when 62135 => mw_U_3rom_table(62135) <= "00101111";
when 62136 => mw_U_3rom_table(62136) <= "11111010";
when 62137 => mw_U_3rom_table(62137) <= "01010110";
when 62138 => mw_U_3rom_table(62138) <= "00011111";
when 62139 => mw_U_3rom_table(62139) <= "11111101";
when 62140 => mw_U_3rom_table(62140) <= "01010110";
when 62141 => mw_U_3rom_table(62141) <= "00001111";
when 62142 => mw_U_3rom_table(62142) <= "00000000";
when 62143 => mw_U_3rom_table(62143) <= "10000000";
when 62144 => mw_U_3rom_table(62144) <= "01000111";
when 62145 => mw_U_3rom_table(62145) <= "01010110";
when 62146 => mw_U_3rom_table(62146) <= "00110111";
when 62147 => mw_U_3rom_table(62147) <= "01010110";
when 62148 => mw_U_3rom_table(62148) <= "00100111";
when 62149 => mw_U_3rom_table(62149) <= "01010110";
when 62150 => mw_U_3rom_table(62150) <= "00010111";
when 62151 => mw_U_3rom_table(62151) <= "01010110";
when 62152 => mw_U_3rom_table(62152) <= "00000111";
when 62153 => mw_U_3rom_table(62153) <= "01111010";
when 62154 => mw_U_3rom_table(62154) <= "11111010";
when 62155 => mw_U_3rom_table(62155) <= "01011010";
when 62156 => mw_U_3rom_table(62156) <= "11011010";
when 62157 => mw_U_3rom_table(62157) <= "00000010";
when 62158 => mw_U_3rom_table(62158) <= "11010000";
when 62159 => mw_U_3rom_table(62159) <= "01010110";
when 62160 => mw_U_3rom_table(62160) <= "11111111";
when 62161 => mw_U_3rom_table(62161) <= "11010011";
when 62162 => mw_U_3rom_table(62162) <= "01010110";
when 62163 => mw_U_3rom_table(62163) <= "11101111";
when 62164 => mw_U_3rom_table(62164) <= "11010110";
when 62165 => mw_U_3rom_table(62165) <= "01010110";
when 62166 => mw_U_3rom_table(62166) <= "11011111";
when 62167 => mw_U_3rom_table(62167) <= "11011001";
when 62168 => mw_U_3rom_table(62168) <= "01010110";
when 62169 => mw_U_3rom_table(62169) <= "11001111";
when 62170 => mw_U_3rom_table(62170) <= "11011100";
when 62171 => mw_U_3rom_table(62171) <= "01010110";
when 62172 => mw_U_3rom_table(62172) <= "10111111";
when 62173 => mw_U_3rom_table(62173) <= "11011111";
when 62174 => mw_U_3rom_table(62174) <= "01010110";
when 62175 => mw_U_3rom_table(62175) <= "10101111";
when 62176 => mw_U_3rom_table(62176) <= "01010110";
when 62177 => mw_U_3rom_table(62177) <= "00010100";
when 62178 => mw_U_3rom_table(62178) <= "11110001";
when 62179 => mw_U_3rom_table(62179) <= "01100011";
when 62180 => mw_U_3rom_table(62180) <= "10011100";
when 62181 => mw_U_3rom_table(62181) <= "01010110";
when 62182 => mw_U_3rom_table(62182) <= "01100100";
when 62183 => mw_U_3rom_table(62183) <= "01010110";
when 62184 => mw_U_3rom_table(62184) <= "01110100";
when 62185 => mw_U_3rom_table(62185) <= "01010110";
when 62186 => mw_U_3rom_table(62186) <= "11110111";
when 62187 => mw_U_3rom_table(62187) <= "01010110";
when 62188 => mw_U_3rom_table(62188) <= "11100111";
when 62189 => mw_U_3rom_table(62189) <= "01010110";
when 62190 => mw_U_3rom_table(62190) <= "11010111";
when 62191 => mw_U_3rom_table(62191) <= "01010110";
when 62192 => mw_U_3rom_table(62192) <= "11000111";
when 62193 => mw_U_3rom_table(62193) <= "01010110";
when 62194 => mw_U_3rom_table(62194) <= "10110111";
when 62195 => mw_U_3rom_table(62195) <= "01010110";
when 62196 => mw_U_3rom_table(62196) <= "10100111";
when 62197 => mw_U_3rom_table(62197) <= "01010110";
when 62198 => mw_U_3rom_table(62198) <= "10010111";
when 62199 => mw_U_3rom_table(62199) <= "01010110";
when 62200 => mw_U_3rom_table(62200) <= "10000111";
when 62201 => mw_U_3rom_table(62201) <= "01010110";
when 62202 => mw_U_3rom_table(62202) <= "01110111";
when 62203 => mw_U_3rom_table(62203) <= "01010110";
when 62204 => mw_U_3rom_table(62204) <= "01100111";
when 62205 => mw_U_3rom_table(62205) <= "01010110";
when 62206 => mw_U_3rom_table(62206) <= "01010111";
when 62207 => mw_U_3rom_table(62207) <= "01010110";
when 62208 => mw_U_3rom_table(62208) <= "11111111";
when 62209 => mw_U_3rom_table(62209) <= "11111111";
when 62210 => mw_U_3rom_table(62210) <= "11111111";
when 62211 => mw_U_3rom_table(62211) <= "11111111";
when 62212 => mw_U_3rom_table(62212) <= "11111111";
when 62213 => mw_U_3rom_table(62213) <= "11111111";
when 62214 => mw_U_3rom_table(62214) <= "11111111";
when 62215 => mw_U_3rom_table(62215) <= "11111111";
when 62216 => mw_U_3rom_table(62216) <= "11111111";
when 62217 => mw_U_3rom_table(62217) <= "11111111";
when 62218 => mw_U_3rom_table(62218) <= "11111111";
when 62219 => mw_U_3rom_table(62219) <= "11111111";
when 62220 => mw_U_3rom_table(62220) <= "11111111";
when 62221 => mw_U_3rom_table(62221) <= "11111111";
when 62222 => mw_U_3rom_table(62222) <= "11111111";
when 62223 => mw_U_3rom_table(62223) <= "11111111";
when 62224 => mw_U_3rom_table(62224) <= "11111111";
when 62225 => mw_U_3rom_table(62225) <= "11111111";
when 62226 => mw_U_3rom_table(62226) <= "11111111";
when 62227 => mw_U_3rom_table(62227) <= "11111111";
when 62228 => mw_U_3rom_table(62228) <= "11111111";
when 62229 => mw_U_3rom_table(62229) <= "11111111";
when 62230 => mw_U_3rom_table(62230) <= "11111111";
when 62231 => mw_U_3rom_table(62231) <= "11111111";
when 62232 => mw_U_3rom_table(62232) <= "11111111";
when 62233 => mw_U_3rom_table(62233) <= "11111111";
when 62234 => mw_U_3rom_table(62234) <= "11111111";
when 62235 => mw_U_3rom_table(62235) <= "11111111";
when 62236 => mw_U_3rom_table(62236) <= "11111111";
when 62237 => mw_U_3rom_table(62237) <= "11111111";
when 62238 => mw_U_3rom_table(62238) <= "01010110";
when 62239 => mw_U_3rom_table(62239) <= "00000100";
when 65504 => mw_U_3rom_table(65504) <= "11111111";
when 65505 => mw_U_3rom_table(65505) <= "11111111";
when 65506 => mw_U_3rom_table(65506) <= "11110000";
when 65507 => mw_U_3rom_table(65507) <= "00000000";
when 65508 => mw_U_3rom_table(65508) <= "11111111";
when 65509 => mw_U_3rom_table(65509) <= "11111111";
when 65510 => mw_U_3rom_table(65510) <= "11111111";
when 65511 => mw_U_3rom_table(65511) <= "11111111";
when 65512 => mw_U_3rom_table(65512) <= "11111111";
when 65513 => mw_U_3rom_table(65513) <= "11111111";
when 65514 => mw_U_3rom_table(65514) <= "11111111";
when 65515 => mw_U_3rom_table(65515) <= "11111111";
when 65516 => mw_U_3rom_table(65516) <= "11111111";
when 65517 => mw_U_3rom_table(65517) <= "11111111";
when 65518 => mw_U_3rom_table(65518) <= "11111111";
when 65519 => mw_U_3rom_table(65519) <= "11111111";
when 65520 => mw_U_3rom_table(65520) <= "11111111";
when 65521 => mw_U_3rom_table(65521) <= "11111111";
when 65522 => mw_U_3rom_table(65522) <= "11111111";
when 65523 => mw_U_3rom_table(65523) <= "11111111";
when 65524 => mw_U_3rom_table(65524) <= "11111111";
when 65525 => mw_U_3rom_table(65525) <= "11111111";
when 65526 => mw_U_3rom_table(65526) <= "11111111";
when 65527 => mw_U_3rom_table(65527) <= "11111111";
when 65528 => mw_U_3rom_table(65528) <= "11111111";
when 65529 => mw_U_3rom_table(65529) <= "11111111";
when 65530 => mw_U_3rom_table(65530) <= "11111111";
when 65531 => mw_U_3rom_table(65531) <= "11111111";
when 65532 => mw_U_3rom_table(65532) <= "11111111";
when 65533 => mw_U_3rom_table(65533) <= "11111111";
when 65534 => mw_U_3rom_table(65534) <= "11111111";
when 65535 => mw_U_3rom_table(65535) <= "11111111";
when others => mw_U_3rom_table(mw_U_3addr_int) <= (others => 'X') ;
end case;
end process ;
u_3rom_read_proc : process ( clk1 )
begin
if (clk1'event and clk1='1') then
dout1 <= mw_U_3rom_table(mw_U_3addr_int);
end if;
end process ;
-- Instance port mappings.
U_0 : R6502_TC
port map (
clk_clk_i => clk,
d_i => RAM_DOUT_internal,
irq_n_i => IRQn,
nmi_n_i => NMIn,
rdy_i => RDY,
rst_rst_n_i => RSTn,
so_n_i => so_n_i,
a_o => A_internal,
d_o => CPU_DOUT_internal,
rd_o => RD,
sync_o => SYNC,
wr_n_o => open,
wr_o => WR_internal
);
-- Implicit buffered output assignments
CPU_DOUT <= CPU_DOUT_internal;
RAM_DOUT <= RAM_DOUT_internal;
WR <= WR_internal;
A <= A_internal;
end struct;
|
-- VHDL Entity R6502_TC.Testbench.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 13:06:53 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity Testbench is
port(
IRQn : in std_logic;
NMIn : in std_logic;
RDY : in std_logic;
RSTn : in std_logic;
clk : in std_logic;
clk1 : in std_logic;
so_n_i : in std_logic;
A : out std_logic_vector (15 downto 0);
CPU_DOUT : out std_logic_vector ( 7 downto 0 );
RAM_DOUT : out std_logic_vector (7 downto 0);
RD : out std_logic;
SYNC : out std_logic;
WR : out std_logic
);
-- Declarations
end Testbench ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $log$
--
-- Title: Testbench for the 6502 Core
-- Path: R6502_TC/Testbench/struct
-- Edited: by eda on 08 Apr 2008
--
-- VHDL Architecture R6502_TC.Testbench.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 13:06:54 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library R6502_TC;
architecture struct of Testbench is
-- Architecture declarations
-- Internal signal declarations
signal dout : std_logic_vector(7 downto 0);
signal dout1 : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal CPU_DOUT_internal : std_logic_vector ( 7 downto 0 );
signal RAM_DOUT_internal : std_logic_vector (7 downto 0);
signal WR_internal : std_logic;
signal A_internal : std_logic_vector (15 downto 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_2' of 'ramsp'
type MW_U_2RAM_TYPE is array (((2**16) -1) downto 0) of std_logic_vector(7 downto 0);
signal mw_U_2ram_table : MW_U_2RAM_TYPE := (others => "00000000");
signal mw_U_2addr_reg: std_logic_vector(15 downto 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'rom'
type MW_U_3ROM_TYPE is array(65535 downto 0) of std_logic_vector(7 downto 0);
signal mw_U_3rom_table : MW_U_3ROM_TYPE;
signal mw_U_3addr_int : INTEGER := 0 ;
-- Component Declarations
component R6502_TC
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : R6502_TC use entity R6502_TC.R6502_TC;
-- pragma synthesis_on
begin
-- ModuleWare code(v1.9) for instance 'U_1' of 'mux'
u_1combo_proc: process(dout, dout1, A_internal(15))
begin
case A_internal(15) is
when '0' => RAM_DOUT_internal <= dout;
when '1' => RAM_DOUT_internal <= dout1;
when others => RAM_DOUT_internal <= (others => 'X');
end case;
end process u_1combo_proc;
-- ModuleWare code(v1.9) for instance 'U_2' of 'ramsp'
--attribute block_ram : boolean;
--attribute block_ram of mem : signal is false;
u_2ram_p_proc: process (clk1)
begin
if (clk1'event and clk1='1') then
if (WR_internal = '1') then
mw_U_2ram_table(CONV_INTEGER(unsigned(A_internal))) <= CPU_DOUT_internal;
end if;
mw_U_2addr_reg <= A_internal;
end if;
end process u_2ram_p_proc;
dout <= mw_U_2ram_table(CONV_INTEGER(unsigned(mw_U_2addr_reg)));
-- ModuleWare code(v1.9) for instance 'U_3' of 'rom'
mw_U_3addr_int <= (CONV_INTEGER(unsigned(A_internal(15 DOWNTO 0))));
u_3rom_table_proc : process ( mw_U_3addr_int )
begin
case mw_U_3addr_int is
when 32768 => mw_U_3rom_table(32768) <= "11111111";
when 32769 => mw_U_3rom_table(32769) <= "11111111";
when 32770 => mw_U_3rom_table(32770) <= "11111111";
when 32771 => mw_U_3rom_table(32771) <= "11111111";
when 32772 => mw_U_3rom_table(32772) <= "11111111";
when 32773 => mw_U_3rom_table(32773) <= "11111111";
when 32774 => mw_U_3rom_table(32774) <= "11111111";
when 32775 => mw_U_3rom_table(32775) <= "11111111";
when 32776 => mw_U_3rom_table(32776) <= "11111111";
when 32777 => mw_U_3rom_table(32777) <= "11111111";
when 32778 => mw_U_3rom_table(32778) <= "11111111";
when 32779 => mw_U_3rom_table(32779) <= "11111111";
when 32780 => mw_U_3rom_table(32780) <= "11111111";
when 32781 => mw_U_3rom_table(32781) <= "11111111";
when 32782 => mw_U_3rom_table(32782) <= "11111111";
when 32783 => mw_U_3rom_table(32783) <= "11111111";
when 32784 => mw_U_3rom_table(32784) <= "11111111";
when 32785 => mw_U_3rom_table(32785) <= "11111111";
when 32786 => mw_U_3rom_table(32786) <= "11111111";
when 32787 => mw_U_3rom_table(32787) <= "11111111";
when 32788 => mw_U_3rom_table(32788) <= "11111111";
when 32789 => mw_U_3rom_table(32789) <= "11111111";
when 32790 => mw_U_3rom_table(32790) <= "11111111";
when 32791 => mw_U_3rom_table(32791) <= "11111111";
when 32792 => mw_U_3rom_table(32792) <= "11111111";
when 32793 => mw_U_3rom_table(32793) <= "11111111";
when 32794 => mw_U_3rom_table(32794) <= "11111111";
when 32795 => mw_U_3rom_table(32795) <= "11111111";
when 32796 => mw_U_3rom_table(32796) <= "11111111";
when 32797 => mw_U_3rom_table(32797) <= "11111111";
when 32798 => mw_U_3rom_table(32798) <= "11111111";
when 32799 => mw_U_3rom_table(32799) <= "00000000";
when 57344 => mw_U_3rom_table(57344) <= "00010100";
when 57345 => mw_U_3rom_table(57345) <= "00000000";
when 57346 => mw_U_3rom_table(57346) <= "00001010";
when 57347 => mw_U_3rom_table(57347) <= "00000000";
when 57348 => mw_U_3rom_table(57348) <= "00000100";
when 57349 => mw_U_3rom_table(57349) <= "00000000";
when 57350 => mw_U_3rom_table(57350) <= "00000011";
when 57351 => mw_U_3rom_table(57351) <= "00000000";
when 57352 => mw_U_3rom_table(57352) <= "00000010";
when 57353 => mw_U_3rom_table(57353) <= "00000000";
when 57354 => mw_U_3rom_table(57354) <= "00000001";
when 57355 => mw_U_3rom_table(57355) <= "00000000";
when 57356 => mw_U_3rom_table(57356) <= "00000000";
when 57357 => mw_U_3rom_table(57357) <= "00000100";
when 57358 => mw_U_3rom_table(57358) <= "11010010";
when 57359 => mw_U_3rom_table(57359) <= "00000100";
when 57360 => mw_U_3rom_table(57360) <= "11010010";
when 57361 => mw_U_3rom_table(57361) <= "00000010";
when 57362 => mw_U_3rom_table(57362) <= "10011100";
when 57363 => mw_U_3rom_table(57363) <= "00000010";
when 57364 => mw_U_3rom_table(57364) <= "10011100";
when 57365 => mw_U_3rom_table(57365) <= "00000000";
when 57366 => mw_U_3rom_table(57366) <= "00101010";
when 57367 => mw_U_3rom_table(57367) <= "00000000";
when 57368 => mw_U_3rom_table(57368) <= "00101010";
when 57369 => mw_U_3rom_table(57369) <= "00010010";
when 57370 => mw_U_3rom_table(57370) <= "00110100";
when 57371 => mw_U_3rom_table(57371) <= "00000110";
when 57372 => mw_U_3rom_table(57372) <= "00010001";
when 57373 => mw_U_3rom_table(57373) <= "00010010";
when 57374 => mw_U_3rom_table(57374) <= "00110100";
when 57375 => mw_U_3rom_table(57375) <= "00010010";
when 57376 => mw_U_3rom_table(57376) <= "00000001";
when 57377 => mw_U_3rom_table(57377) <= "00000000";
when 57378 => mw_U_3rom_table(57378) <= "00000001";
when 57379 => mw_U_3rom_table(57379) <= "00000000";
when 57380 => mw_U_3rom_table(57380) <= "00000001";
when 57381 => mw_U_3rom_table(57381) <= "00000000";
when 57382 => mw_U_3rom_table(57382) <= "00000000";
when 57383 => mw_U_3rom_table(57383) <= "00000000";
when 57384 => mw_U_3rom_table(57384) <= "00000001";
when 57385 => mw_U_3rom_table(57385) <= "00000000";
when 57386 => mw_U_3rom_table(57386) <= "00000000";
when 57387 => mw_U_3rom_table(57387) <= "00000000";
when 57388 => mw_U_3rom_table(57388) <= "00000001";
when 57389 => mw_U_3rom_table(57389) <= "00100011";
when 57390 => mw_U_3rom_table(57390) <= "01000000";
when 57391 => mw_U_3rom_table(57391) <= "00000001";
when 57392 => mw_U_3rom_table(57392) <= "00100011";
when 57393 => mw_U_3rom_table(57393) <= "00000000";
when 57394 => mw_U_3rom_table(57394) <= "00000011";
when 57395 => mw_U_3rom_table(57395) <= "11111111";
when 57396 => mw_U_3rom_table(57396) <= "11111100";
when 57397 => mw_U_3rom_table(57397) <= "00000000";
when 57398 => mw_U_3rom_table(57398) <= "00001010";
when 57399 => mw_U_3rom_table(57399) <= "00000000";
when 57400 => mw_U_3rom_table(57400) <= "00010101";
when 57401 => mw_U_3rom_table(57401) <= "11100000";
when 57402 => mw_U_3rom_table(57402) <= "00100101";
when 57403 => mw_U_3rom_table(57403) <= "11100000";
when 57404 => mw_U_3rom_table(57404) <= "00100011";
when 57405 => mw_U_3rom_table(57405) <= "00000000";
when 57406 => mw_U_3rom_table(57406) <= "01100100";
when 57407 => mw_U_3rom_table(57407) <= "00000000";
when 57408 => mw_U_3rom_table(57408) <= "11111111";
when 57409 => mw_U_3rom_table(57409) <= "11111111";
when 57410 => mw_U_3rom_table(57410) <= "11111111";
when 57411 => mw_U_3rom_table(57411) <= "11111111";
when 57412 => mw_U_3rom_table(57412) <= "11111111";
when 57413 => mw_U_3rom_table(57413) <= "11111111";
when 57414 => mw_U_3rom_table(57414) <= "11111111";
when 57415 => mw_U_3rom_table(57415) <= "11111111";
when 57416 => mw_U_3rom_table(57416) <= "11111111";
when 57417 => mw_U_3rom_table(57417) <= "11111111";
when 57418 => mw_U_3rom_table(57418) <= "11111111";
when 57419 => mw_U_3rom_table(57419) <= "11111111";
when 57420 => mw_U_3rom_table(57420) <= "11111111";
when 57421 => mw_U_3rom_table(57421) <= "11111111";
when 57422 => mw_U_3rom_table(57422) <= "11111111";
when 57423 => mw_U_3rom_table(57423) <= "11111111";
when 57424 => mw_U_3rom_table(57424) <= "11111111";
when 57425 => mw_U_3rom_table(57425) <= "11111111";
when 57426 => mw_U_3rom_table(57426) <= "11111111";
when 57427 => mw_U_3rom_table(57427) <= "11111111";
when 57428 => mw_U_3rom_table(57428) <= "11111111";
when 57429 => mw_U_3rom_table(57429) <= "11111111";
when 57430 => mw_U_3rom_table(57430) <= "11111111";
when 57431 => mw_U_3rom_table(57431) <= "11111111";
when 57432 => mw_U_3rom_table(57432) <= "11111111";
when 57433 => mw_U_3rom_table(57433) <= "00010010";
when 57434 => mw_U_3rom_table(57434) <= "00110100";
when 57435 => mw_U_3rom_table(57435) <= "00000000";
when 57436 => mw_U_3rom_table(57436) <= "00000000";
when 57437 => mw_U_3rom_table(57437) <= "00000000";
when 57438 => mw_U_3rom_table(57438) <= "00000000";
when 57439 => mw_U_3rom_table(57439) <= "00000000";
when 61440 => mw_U_3rom_table(61440) <= "00000110";
when 61441 => mw_U_3rom_table(61441) <= "10101101";
when 61442 => mw_U_3rom_table(61442) <= "01011011";
when 61443 => mw_U_3rom_table(61443) <= "10000101";
when 61444 => mw_U_3rom_table(61444) <= "11100000";
when 61445 => mw_U_3rom_table(61445) <= "00000101";
when 61446 => mw_U_3rom_table(61446) <= "10101101";
when 61447 => mw_U_3rom_table(61447) <= "01011010";
when 61448 => mw_U_3rom_table(61448) <= "10000101";
when 61449 => mw_U_3rom_table(61449) <= "11100000";
when 61450 => mw_U_3rom_table(61450) <= "00000100";
when 61451 => mw_U_3rom_table(61451) <= "10101101";
when 61452 => mw_U_3rom_table(61452) <= "01011001";
when 61453 => mw_U_3rom_table(61453) <= "10000101";
when 61454 => mw_U_3rom_table(61454) <= "11100000";
when 61455 => mw_U_3rom_table(61455) <= "00000011";
when 61456 => mw_U_3rom_table(61456) <= "10101101";
when 61457 => mw_U_3rom_table(61457) <= "01011000";
when 61458 => mw_U_3rom_table(61458) <= "10000101";
when 61459 => mw_U_3rom_table(61459) <= "11100000";
when 61460 => mw_U_3rom_table(61460) <= "00000010";
when 61461 => mw_U_3rom_table(61461) <= "10101101";
when 61462 => mw_U_3rom_table(61462) <= "01010111";
when 61463 => mw_U_3rom_table(61463) <= "10000101";
when 61464 => mw_U_3rom_table(61464) <= "11100000";
when 61465 => mw_U_3rom_table(61465) <= "00000001";
when 61466 => mw_U_3rom_table(61466) <= "10101101";
when 61467 => mw_U_3rom_table(61467) <= "01010110";
when 61468 => mw_U_3rom_table(61468) <= "10000101";
when 61469 => mw_U_3rom_table(61469) <= "11100000";
when 61470 => mw_U_3rom_table(61470) <= "00000000";
when 61471 => mw_U_3rom_table(61471) <= "10101101";
when 61472 => mw_U_3rom_table(61472) <= "10000101";
when 61473 => mw_U_3rom_table(61473) <= "11100000";
when 61474 => mw_U_3rom_table(61474) <= "00001100";
when 61475 => mw_U_3rom_table(61475) <= "10101101";
when 61476 => mw_U_3rom_table(61476) <= "01100001";
when 61477 => mw_U_3rom_table(61477) <= "10000101";
when 61478 => mw_U_3rom_table(61478) <= "11100000";
when 61479 => mw_U_3rom_table(61479) <= "00001011";
when 61480 => mw_U_3rom_table(61480) <= "10101101";
when 61481 => mw_U_3rom_table(61481) <= "01100000";
when 61482 => mw_U_3rom_table(61482) <= "10000101";
when 61483 => mw_U_3rom_table(61483) <= "11100000";
when 61484 => mw_U_3rom_table(61484) <= "00001010";
when 61485 => mw_U_3rom_table(61485) <= "10101101";
when 61486 => mw_U_3rom_table(61486) <= "01011111";
when 61487 => mw_U_3rom_table(61487) <= "10000101";
when 61488 => mw_U_3rom_table(61488) <= "11100000";
when 61489 => mw_U_3rom_table(61489) <= "00001001";
when 61490 => mw_U_3rom_table(61490) <= "10101101";
when 61491 => mw_U_3rom_table(61491) <= "01011110";
when 61492 => mw_U_3rom_table(61492) <= "10000101";
when 61493 => mw_U_3rom_table(61493) <= "11100000";
when 61494 => mw_U_3rom_table(61494) <= "00001000";
when 61495 => mw_U_3rom_table(61495) <= "10101101";
when 61496 => mw_U_3rom_table(61496) <= "01011101";
when 61497 => mw_U_3rom_table(61497) <= "10000101";
when 61498 => mw_U_3rom_table(61498) <= "11100000";
when 61499 => mw_U_3rom_table(61499) <= "00000111";
when 61500 => mw_U_3rom_table(61500) <= "10101101";
when 61501 => mw_U_3rom_table(61501) <= "01011100";
when 61502 => mw_U_3rom_table(61502) <= "10000101";
when 61503 => mw_U_3rom_table(61503) <= "11100000";
when 61504 => mw_U_3rom_table(61504) <= "10101101";
when 61505 => mw_U_3rom_table(61505) <= "01101000";
when 61506 => mw_U_3rom_table(61506) <= "10000101";
when 61507 => mw_U_3rom_table(61507) <= "11100000";
when 61508 => mw_U_3rom_table(61508) <= "00010010";
when 61509 => mw_U_3rom_table(61509) <= "10101101";
when 61510 => mw_U_3rom_table(61510) <= "01100111";
when 61511 => mw_U_3rom_table(61511) <= "10000101";
when 61512 => mw_U_3rom_table(61512) <= "11100000";
when 61513 => mw_U_3rom_table(61513) <= "00010001";
when 61514 => mw_U_3rom_table(61514) <= "10101101";
when 61515 => mw_U_3rom_table(61515) <= "01100110";
when 61516 => mw_U_3rom_table(61516) <= "10000101";
when 61517 => mw_U_3rom_table(61517) <= "11100000";
when 61518 => mw_U_3rom_table(61518) <= "00010000";
when 61519 => mw_U_3rom_table(61519) <= "10101101";
when 61520 => mw_U_3rom_table(61520) <= "01100101";
when 61521 => mw_U_3rom_table(61521) <= "10000101";
when 61522 => mw_U_3rom_table(61522) <= "11100000";
when 61523 => mw_U_3rom_table(61523) <= "00001111";
when 61524 => mw_U_3rom_table(61524) <= "10101101";
when 61525 => mw_U_3rom_table(61525) <= "01100100";
when 61526 => mw_U_3rom_table(61526) <= "10000101";
when 61527 => mw_U_3rom_table(61527) <= "11100000";
when 61528 => mw_U_3rom_table(61528) <= "00001110";
when 61529 => mw_U_3rom_table(61529) <= "10101101";
when 61530 => mw_U_3rom_table(61530) <= "01100011";
when 61531 => mw_U_3rom_table(61531) <= "10000101";
when 61532 => mw_U_3rom_table(61532) <= "11100000";
when 61533 => mw_U_3rom_table(61533) <= "00001101";
when 61534 => mw_U_3rom_table(61534) <= "10101101";
when 61535 => mw_U_3rom_table(61535) <= "01100010";
when 61536 => mw_U_3rom_table(61536) <= "11100000";
when 61537 => mw_U_3rom_table(61537) <= "00011001";
when 61538 => mw_U_3rom_table(61538) <= "10101101";
when 61539 => mw_U_3rom_table(61539) <= "01101110";
when 61540 => mw_U_3rom_table(61540) <= "10000101";
when 61541 => mw_U_3rom_table(61541) <= "11100000";
when 61542 => mw_U_3rom_table(61542) <= "00011000";
when 61543 => mw_U_3rom_table(61543) <= "10101101";
when 61544 => mw_U_3rom_table(61544) <= "01101101";
when 61545 => mw_U_3rom_table(61545) <= "10000101";
when 61546 => mw_U_3rom_table(61546) <= "11100000";
when 61547 => mw_U_3rom_table(61547) <= "00010111";
when 61548 => mw_U_3rom_table(61548) <= "10101101";
when 61549 => mw_U_3rom_table(61549) <= "01101100";
when 61550 => mw_U_3rom_table(61550) <= "10000101";
when 61551 => mw_U_3rom_table(61551) <= "11100000";
when 61552 => mw_U_3rom_table(61552) <= "00010110";
when 61553 => mw_U_3rom_table(61553) <= "10101101";
when 61554 => mw_U_3rom_table(61554) <= "01101011";
when 61555 => mw_U_3rom_table(61555) <= "10000101";
when 61556 => mw_U_3rom_table(61556) <= "11100000";
when 61557 => mw_U_3rom_table(61557) <= "00010101";
when 61558 => mw_U_3rom_table(61558) <= "10101101";
when 61559 => mw_U_3rom_table(61559) <= "01101010";
when 61560 => mw_U_3rom_table(61560) <= "10000101";
when 61561 => mw_U_3rom_table(61561) <= "11100000";
when 61562 => mw_U_3rom_table(61562) <= "00010100";
when 61563 => mw_U_3rom_table(61563) <= "10101101";
when 61564 => mw_U_3rom_table(61564) <= "01101001";
when 61565 => mw_U_3rom_table(61565) <= "10000101";
when 61566 => mw_U_3rom_table(61566) <= "11100000";
when 61567 => mw_U_3rom_table(61567) <= "00010011";
when 61568 => mw_U_3rom_table(61568) <= "01110101";
when 61569 => mw_U_3rom_table(61569) <= "10000101";
when 61570 => mw_U_3rom_table(61570) <= "11100000";
when 61571 => mw_U_3rom_table(61571) <= "00011111";
when 61572 => mw_U_3rom_table(61572) <= "10101101";
when 61573 => mw_U_3rom_table(61573) <= "01110100";
when 61574 => mw_U_3rom_table(61574) <= "10000101";
when 61575 => mw_U_3rom_table(61575) <= "11100000";
when 61576 => mw_U_3rom_table(61576) <= "00011110";
when 61577 => mw_U_3rom_table(61577) <= "10101101";
when 61578 => mw_U_3rom_table(61578) <= "01110011";
when 61579 => mw_U_3rom_table(61579) <= "10000101";
when 61580 => mw_U_3rom_table(61580) <= "11100000";
when 61581 => mw_U_3rom_table(61581) <= "00011101";
when 61582 => mw_U_3rom_table(61582) <= "10101101";
when 61583 => mw_U_3rom_table(61583) <= "01110010";
when 61584 => mw_U_3rom_table(61584) <= "10000101";
when 61585 => mw_U_3rom_table(61585) <= "11100000";
when 61586 => mw_U_3rom_table(61586) <= "00011100";
when 61587 => mw_U_3rom_table(61587) <= "10101101";
when 61588 => mw_U_3rom_table(61588) <= "01110001";
when 61589 => mw_U_3rom_table(61589) <= "10000101";
when 61590 => mw_U_3rom_table(61590) <= "11100000";
when 61591 => mw_U_3rom_table(61591) <= "00011011";
when 61592 => mw_U_3rom_table(61592) <= "10101101";
when 61593 => mw_U_3rom_table(61593) <= "01110000";
when 61594 => mw_U_3rom_table(61594) <= "10000101";
when 61595 => mw_U_3rom_table(61595) <= "11100000";
when 61596 => mw_U_3rom_table(61596) <= "00011010";
when 61597 => mw_U_3rom_table(61597) <= "10101101";
when 61598 => mw_U_3rom_table(61598) <= "01101111";
when 61599 => mw_U_3rom_table(61599) <= "10000101";
when 61600 => mw_U_3rom_table(61600) <= "00100110";
when 61601 => mw_U_3rom_table(61601) <= "10101101";
when 61602 => mw_U_3rom_table(61602) <= "01111011";
when 61603 => mw_U_3rom_table(61603) <= "10000101";
when 61604 => mw_U_3rom_table(61604) <= "11100000";
when 61605 => mw_U_3rom_table(61605) <= "00100101";
when 61606 => mw_U_3rom_table(61606) <= "10101101";
when 61607 => mw_U_3rom_table(61607) <= "01111010";
when 61608 => mw_U_3rom_table(61608) <= "10000101";
when 61609 => mw_U_3rom_table(61609) <= "11100000";
when 61610 => mw_U_3rom_table(61610) <= "00100100";
when 61611 => mw_U_3rom_table(61611) <= "10101101";
when 61612 => mw_U_3rom_table(61612) <= "01111001";
when 61613 => mw_U_3rom_table(61613) <= "10000101";
when 61614 => mw_U_3rom_table(61614) <= "11100000";
when 61615 => mw_U_3rom_table(61615) <= "00100011";
when 61616 => mw_U_3rom_table(61616) <= "10101101";
when 61617 => mw_U_3rom_table(61617) <= "01111000";
when 61618 => mw_U_3rom_table(61618) <= "10000101";
when 61619 => mw_U_3rom_table(61619) <= "11100000";
when 61620 => mw_U_3rom_table(61620) <= "00100010";
when 61621 => mw_U_3rom_table(61621) <= "10101101";
when 61622 => mw_U_3rom_table(61622) <= "01110111";
when 61623 => mw_U_3rom_table(61623) <= "10000101";
when 61624 => mw_U_3rom_table(61624) <= "11100000";
when 61625 => mw_U_3rom_table(61625) <= "00100001";
when 61626 => mw_U_3rom_table(61626) <= "10101101";
when 61627 => mw_U_3rom_table(61627) <= "01110110";
when 61628 => mw_U_3rom_table(61628) <= "10000101";
when 61629 => mw_U_3rom_table(61629) <= "11100000";
when 61630 => mw_U_3rom_table(61630) <= "00100000";
when 61631 => mw_U_3rom_table(61631) <= "10101101";
when 61632 => mw_U_3rom_table(61632) <= "10000101";
when 61633 => mw_U_3rom_table(61633) <= "11100000";
when 61634 => mw_U_3rom_table(61634) <= "00101100";
when 61635 => mw_U_3rom_table(61635) <= "10101101";
when 61636 => mw_U_3rom_table(61636) <= "10000001";
when 61637 => mw_U_3rom_table(61637) <= "10000101";
when 61638 => mw_U_3rom_table(61638) <= "11100000";
when 61639 => mw_U_3rom_table(61639) <= "00101011";
when 61640 => mw_U_3rom_table(61640) <= "10101101";
when 61641 => mw_U_3rom_table(61641) <= "10000000";
when 61642 => mw_U_3rom_table(61642) <= "10000101";
when 61643 => mw_U_3rom_table(61643) <= "11100000";
when 61644 => mw_U_3rom_table(61644) <= "00101010";
when 61645 => mw_U_3rom_table(61645) <= "10101101";
when 61646 => mw_U_3rom_table(61646) <= "01111111";
when 61647 => mw_U_3rom_table(61647) <= "10000101";
when 61648 => mw_U_3rom_table(61648) <= "11100000";
when 61649 => mw_U_3rom_table(61649) <= "00101001";
when 61650 => mw_U_3rom_table(61650) <= "10101101";
when 61651 => mw_U_3rom_table(61651) <= "01111110";
when 61652 => mw_U_3rom_table(61652) <= "10000101";
when 61653 => mw_U_3rom_table(61653) <= "11100000";
when 61654 => mw_U_3rom_table(61654) <= "00101000";
when 61655 => mw_U_3rom_table(61655) <= "10101101";
when 61656 => mw_U_3rom_table(61656) <= "01111101";
when 61657 => mw_U_3rom_table(61657) <= "10000101";
when 61658 => mw_U_3rom_table(61658) <= "11100000";
when 61659 => mw_U_3rom_table(61659) <= "00100111";
when 61660 => mw_U_3rom_table(61660) <= "10101101";
when 61661 => mw_U_3rom_table(61661) <= "01111100";
when 61662 => mw_U_3rom_table(61662) <= "10000101";
when 61663 => mw_U_3rom_table(61663) <= "11100000";
when 61664 => mw_U_3rom_table(61664) <= "10101101";
when 61665 => mw_U_3rom_table(61665) <= "10001000";
when 61666 => mw_U_3rom_table(61666) <= "10000101";
when 61667 => mw_U_3rom_table(61667) <= "11100000";
when 61668 => mw_U_3rom_table(61668) <= "00110010";
when 61669 => mw_U_3rom_table(61669) <= "10101101";
when 61670 => mw_U_3rom_table(61670) <= "10000111";
when 61671 => mw_U_3rom_table(61671) <= "10000101";
when 61672 => mw_U_3rom_table(61672) <= "11100000";
when 61673 => mw_U_3rom_table(61673) <= "00110001";
when 61674 => mw_U_3rom_table(61674) <= "10101101";
when 61675 => mw_U_3rom_table(61675) <= "10000110";
when 61676 => mw_U_3rom_table(61676) <= "10000101";
when 61677 => mw_U_3rom_table(61677) <= "11100000";
when 61678 => mw_U_3rom_table(61678) <= "00110000";
when 61679 => mw_U_3rom_table(61679) <= "10101101";
when 61680 => mw_U_3rom_table(61680) <= "10000101";
when 61681 => mw_U_3rom_table(61681) <= "10000101";
when 61682 => mw_U_3rom_table(61682) <= "11100000";
when 61683 => mw_U_3rom_table(61683) <= "00101111";
when 61684 => mw_U_3rom_table(61684) <= "10101101";
when 61685 => mw_U_3rom_table(61685) <= "10000100";
when 61686 => mw_U_3rom_table(61686) <= "10000101";
when 61687 => mw_U_3rom_table(61687) <= "11100000";
when 61688 => mw_U_3rom_table(61688) <= "00101110";
when 61689 => mw_U_3rom_table(61689) <= "10101101";
when 61690 => mw_U_3rom_table(61690) <= "10000011";
when 61691 => mw_U_3rom_table(61691) <= "10000101";
when 61692 => mw_U_3rom_table(61692) <= "11100000";
when 61693 => mw_U_3rom_table(61693) <= "00101101";
when 61694 => mw_U_3rom_table(61694) <= "10101101";
when 61695 => mw_U_3rom_table(61695) <= "10000010";
when 61696 => mw_U_3rom_table(61696) <= "11100000";
when 61697 => mw_U_3rom_table(61697) <= "00111001";
when 61698 => mw_U_3rom_table(61698) <= "10101101";
when 61699 => mw_U_3rom_table(61699) <= "10001110";
when 61700 => mw_U_3rom_table(61700) <= "10000101";
when 61701 => mw_U_3rom_table(61701) <= "11100000";
when 61702 => mw_U_3rom_table(61702) <= "00111000";
when 61703 => mw_U_3rom_table(61703) <= "10101101";
when 61704 => mw_U_3rom_table(61704) <= "10001101";
when 61705 => mw_U_3rom_table(61705) <= "10000101";
when 61706 => mw_U_3rom_table(61706) <= "11100000";
when 61707 => mw_U_3rom_table(61707) <= "00110111";
when 61708 => mw_U_3rom_table(61708) <= "10101101";
when 61709 => mw_U_3rom_table(61709) <= "10001100";
when 61710 => mw_U_3rom_table(61710) <= "10000101";
when 61711 => mw_U_3rom_table(61711) <= "11100000";
when 61712 => mw_U_3rom_table(61712) <= "00110110";
when 61713 => mw_U_3rom_table(61713) <= "10101101";
when 61714 => mw_U_3rom_table(61714) <= "10001011";
when 61715 => mw_U_3rom_table(61715) <= "10000101";
when 61716 => mw_U_3rom_table(61716) <= "11100000";
when 61717 => mw_U_3rom_table(61717) <= "00110101";
when 61718 => mw_U_3rom_table(61718) <= "10101101";
when 61719 => mw_U_3rom_table(61719) <= "10001010";
when 61720 => mw_U_3rom_table(61720) <= "10000101";
when 61721 => mw_U_3rom_table(61721) <= "11100000";
when 61722 => mw_U_3rom_table(61722) <= "00110100";
when 61723 => mw_U_3rom_table(61723) <= "10101101";
when 61724 => mw_U_3rom_table(61724) <= "10001001";
when 61725 => mw_U_3rom_table(61725) <= "10000101";
when 61726 => mw_U_3rom_table(61726) <= "11100000";
when 61727 => mw_U_3rom_table(61727) <= "00110011";
when 61728 => mw_U_3rom_table(61728) <= "10010101";
when 61729 => mw_U_3rom_table(61729) <= "10000101";
when 61730 => mw_U_3rom_table(61730) <= "11100000";
when 61731 => mw_U_3rom_table(61731) <= "00111111";
when 61732 => mw_U_3rom_table(61732) <= "10101101";
when 61733 => mw_U_3rom_table(61733) <= "10010100";
when 61734 => mw_U_3rom_table(61734) <= "10000101";
when 61735 => mw_U_3rom_table(61735) <= "11100000";
when 61736 => mw_U_3rom_table(61736) <= "00111110";
when 61737 => mw_U_3rom_table(61737) <= "10101101";
when 61738 => mw_U_3rom_table(61738) <= "10010011";
when 61739 => mw_U_3rom_table(61739) <= "10000101";
when 61740 => mw_U_3rom_table(61740) <= "11100000";
when 61741 => mw_U_3rom_table(61741) <= "00111101";
when 61742 => mw_U_3rom_table(61742) <= "10101101";
when 61743 => mw_U_3rom_table(61743) <= "10010010";
when 61744 => mw_U_3rom_table(61744) <= "10000101";
when 61745 => mw_U_3rom_table(61745) <= "11100000";
when 61746 => mw_U_3rom_table(61746) <= "00111100";
when 61747 => mw_U_3rom_table(61747) <= "10101101";
when 61748 => mw_U_3rom_table(61748) <= "10010001";
when 61749 => mw_U_3rom_table(61749) <= "10000101";
when 61750 => mw_U_3rom_table(61750) <= "11100000";
when 61751 => mw_U_3rom_table(61751) <= "00111011";
when 61752 => mw_U_3rom_table(61752) <= "10101101";
when 61753 => mw_U_3rom_table(61753) <= "10010000";
when 61754 => mw_U_3rom_table(61754) <= "10000101";
when 61755 => mw_U_3rom_table(61755) <= "11100000";
when 61756 => mw_U_3rom_table(61756) <= "00111010";
when 61757 => mw_U_3rom_table(61757) <= "10101101";
when 61758 => mw_U_3rom_table(61758) <= "10001111";
when 61759 => mw_U_3rom_table(61759) <= "10000101";
when 61760 => mw_U_3rom_table(61760) <= "01000110";
when 61761 => mw_U_3rom_table(61761) <= "10101101";
when 61762 => mw_U_3rom_table(61762) <= "10011011";
when 61763 => mw_U_3rom_table(61763) <= "10000101";
when 61764 => mw_U_3rom_table(61764) <= "11100000";
when 61765 => mw_U_3rom_table(61765) <= "01000101";
when 61766 => mw_U_3rom_table(61766) <= "10101101";
when 61767 => mw_U_3rom_table(61767) <= "10011010";
when 61768 => mw_U_3rom_table(61768) <= "10000101";
when 61769 => mw_U_3rom_table(61769) <= "11100000";
when 61770 => mw_U_3rom_table(61770) <= "01000100";
when 61771 => mw_U_3rom_table(61771) <= "10101101";
when 61772 => mw_U_3rom_table(61772) <= "10011001";
when 61773 => mw_U_3rom_table(61773) <= "10000101";
when 61774 => mw_U_3rom_table(61774) <= "11100000";
when 61775 => mw_U_3rom_table(61775) <= "01000011";
when 61776 => mw_U_3rom_table(61776) <= "10101101";
when 61777 => mw_U_3rom_table(61777) <= "10011000";
when 61778 => mw_U_3rom_table(61778) <= "10000101";
when 61779 => mw_U_3rom_table(61779) <= "11100000";
when 61780 => mw_U_3rom_table(61780) <= "01000010";
when 61781 => mw_U_3rom_table(61781) <= "10101101";
when 61782 => mw_U_3rom_table(61782) <= "10010111";
when 61783 => mw_U_3rom_table(61783) <= "10000101";
when 61784 => mw_U_3rom_table(61784) <= "11100000";
when 61785 => mw_U_3rom_table(61785) <= "01000001";
when 61786 => mw_U_3rom_table(61786) <= "10101101";
when 61787 => mw_U_3rom_table(61787) <= "10010110";
when 61788 => mw_U_3rom_table(61788) <= "10000101";
when 61789 => mw_U_3rom_table(61789) <= "11100000";
when 61790 => mw_U_3rom_table(61790) <= "01000000";
when 61791 => mw_U_3rom_table(61791) <= "10101101";
when 61792 => mw_U_3rom_table(61792) <= "00110101";
when 61793 => mw_U_3rom_table(61793) <= "01010110";
when 61794 => mw_U_3rom_table(61794) <= "00110010";
when 61795 => mw_U_3rom_table(61795) <= "01010110";
when 61796 => mw_U_3rom_table(61796) <= "00110001";
when 61797 => mw_U_3rom_table(61797) <= "01010110";
when 61798 => mw_U_3rom_table(61798) <= "00100001";
when 61799 => mw_U_3rom_table(61799) <= "01010110";
when 61800 => mw_U_3rom_table(61800) <= "00101001";
when 61801 => mw_U_3rom_table(61801) <= "11110001";
when 61802 => mw_U_3rom_table(61802) <= "01100011";
when 61803 => mw_U_3rom_table(61803) <= "01101101";
when 61804 => mw_U_3rom_table(61804) <= "01010110";
when 61805 => mw_U_3rom_table(61805) <= "01100101";
when 61806 => mw_U_3rom_table(61806) <= "00000000";
when 61807 => mw_U_3rom_table(61807) <= "01010110";
when 61808 => mw_U_3rom_table(61808) <= "01111001";
when 61809 => mw_U_3rom_table(61809) <= "01010110";
when 61810 => mw_U_3rom_table(61810) <= "01110101";
when 61811 => mw_U_3rom_table(61811) <= "01010110";
when 61812 => mw_U_3rom_table(61812) <= "01110010";
when 61813 => mw_U_3rom_table(61813) <= "01010110";
when 61814 => mw_U_3rom_table(61814) <= "01110010";
when 61815 => mw_U_3rom_table(61815) <= "01010110";
when 61816 => mw_U_3rom_table(61816) <= "01110001";
when 61817 => mw_U_3rom_table(61817) <= "01010110";
when 61818 => mw_U_3rom_table(61818) <= "01100001";
when 61819 => mw_U_3rom_table(61819) <= "01010110";
when 61820 => mw_U_3rom_table(61820) <= "01101001";
when 61821 => mw_U_3rom_table(61821) <= "10011100";
when 61822 => mw_U_3rom_table(61822) <= "10000101";
when 61823 => mw_U_3rom_table(61823) <= "11100000";
when 61824 => mw_U_3rom_table(61824) <= "11101010";
when 61825 => mw_U_3rom_table(61825) <= "00000001";
when 61826 => mw_U_3rom_table(61826) <= "00010000";
when 61827 => mw_U_3rom_table(61827) <= "11101010";
when 61828 => mw_U_3rom_table(61828) <= "00000001";
when 61829 => mw_U_3rom_table(61829) <= "00110000";
when 61830 => mw_U_3rom_table(61830) <= "11101010";
when 61831 => mw_U_3rom_table(61831) <= "00000001";
when 61832 => mw_U_3rom_table(61832) <= "11010000";
when 61833 => mw_U_3rom_table(61833) <= "11101010";
when 61834 => mw_U_3rom_table(61834) <= "00000001";
when 61835 => mw_U_3rom_table(61835) <= "11110000";
when 61836 => mw_U_3rom_table(61836) <= "11101010";
when 61837 => mw_U_3rom_table(61837) <= "00000001";
when 61838 => mw_U_3rom_table(61838) <= "10110000";
when 61839 => mw_U_3rom_table(61839) <= "11101010";
when 61840 => mw_U_3rom_table(61840) <= "00000001";
when 61841 => mw_U_3rom_table(61841) <= "10010000";
when 61842 => mw_U_3rom_table(61842) <= "01010110";
when 61843 => mw_U_3rom_table(61843) <= "00000110";
when 61844 => mw_U_3rom_table(61844) <= "01010110";
when 61845 => mw_U_3rom_table(61845) <= "00010110";
when 61846 => mw_U_3rom_table(61846) <= "00001010";
when 61847 => mw_U_3rom_table(61847) <= "11110001";
when 61848 => mw_U_3rom_table(61848) <= "01100011";
when 61849 => mw_U_3rom_table(61849) <= "00101101";
when 61850 => mw_U_3rom_table(61850) <= "01010110";
when 61851 => mw_U_3rom_table(61851) <= "00100101";
when 61852 => mw_U_3rom_table(61852) <= "00000000";
when 61853 => mw_U_3rom_table(61853) <= "01010110";
when 61854 => mw_U_3rom_table(61854) <= "00111001";
when 61855 => mw_U_3rom_table(61855) <= "01010110";
when 61856 => mw_U_3rom_table(61856) <= "01010110";
when 61857 => mw_U_3rom_table(61857) <= "11011001";
when 61858 => mw_U_3rom_table(61858) <= "01010110";
when 61859 => mw_U_3rom_table(61859) <= "11010101";
when 61860 => mw_U_3rom_table(61860) <= "01010110";
when 61861 => mw_U_3rom_table(61861) <= "11010010";
when 61862 => mw_U_3rom_table(61862) <= "01010110";
when 61863 => mw_U_3rom_table(61863) <= "11010001";
when 61864 => mw_U_3rom_table(61864) <= "01010110";
when 61865 => mw_U_3rom_table(61865) <= "11000001";
when 61866 => mw_U_3rom_table(61866) <= "01010110";
when 61867 => mw_U_3rom_table(61867) <= "11001001";
when 61868 => mw_U_3rom_table(61868) <= "10111000";
when 61869 => mw_U_3rom_table(61869) <= "01011000";
when 61870 => mw_U_3rom_table(61870) <= "11011000";
when 61871 => mw_U_3rom_table(61871) <= "00011000";
when 61872 => mw_U_3rom_table(61872) <= "00000000";
when 61873 => mw_U_3rom_table(61873) <= "11110001";
when 61874 => mw_U_3rom_table(61874) <= "01100011";
when 61875 => mw_U_3rom_table(61875) <= "00101100";
when 61876 => mw_U_3rom_table(61876) <= "01010110";
when 61877 => mw_U_3rom_table(61877) <= "00100100";
when 61878 => mw_U_3rom_table(61878) <= "01010110";
when 61879 => mw_U_3rom_table(61879) <= "00110100";
when 61880 => mw_U_3rom_table(61880) <= "01010110";
when 61881 => mw_U_3rom_table(61881) <= "10001001";
when 61882 => mw_U_3rom_table(61882) <= "11101010";
when 61883 => mw_U_3rom_table(61883) <= "00000001";
when 61884 => mw_U_3rom_table(61884) <= "01110000";
when 61885 => mw_U_3rom_table(61885) <= "11101010";
when 61886 => mw_U_3rom_table(61886) <= "00000001";
when 61887 => mw_U_3rom_table(61887) <= "01010000";
when 61888 => mw_U_3rom_table(61888) <= "11001010";
when 61889 => mw_U_3rom_table(61889) <= "11110001";
when 61890 => mw_U_3rom_table(61890) <= "01100011";
when 61891 => mw_U_3rom_table(61891) <= "11001110";
when 61892 => mw_U_3rom_table(61892) <= "01010110";
when 61893 => mw_U_3rom_table(61893) <= "11000110";
when 61894 => mw_U_3rom_table(61894) <= "11110001";
when 61895 => mw_U_3rom_table(61895) <= "01100011";
when 61896 => mw_U_3rom_table(61896) <= "11011110";
when 61897 => mw_U_3rom_table(61897) <= "01010110";
when 61898 => mw_U_3rom_table(61898) <= "11010110";
when 61899 => mw_U_3rom_table(61899) <= "00111010";
when 61900 => mw_U_3rom_table(61900) <= "11110001";
when 61901 => mw_U_3rom_table(61901) <= "01100011";
when 61902 => mw_U_3rom_table(61902) <= "11001100";
when 61903 => mw_U_3rom_table(61903) <= "01010110";
when 61904 => mw_U_3rom_table(61904) <= "11000100";
when 61905 => mw_U_3rom_table(61905) <= "01010110";
when 61906 => mw_U_3rom_table(61906) <= "11000000";
when 61907 => mw_U_3rom_table(61907) <= "11110001";
when 61908 => mw_U_3rom_table(61908) <= "01100011";
when 61909 => mw_U_3rom_table(61909) <= "11101100";
when 61910 => mw_U_3rom_table(61910) <= "01010110";
when 61911 => mw_U_3rom_table(61911) <= "11100100";
when 61912 => mw_U_3rom_table(61912) <= "01010110";
when 61913 => mw_U_3rom_table(61913) <= "11100000";
when 61914 => mw_U_3rom_table(61914) <= "11110001";
when 61915 => mw_U_3rom_table(61915) <= "01100011";
when 61916 => mw_U_3rom_table(61916) <= "11001101";
when 61917 => mw_U_3rom_table(61917) <= "01010110";
when 61918 => mw_U_3rom_table(61918) <= "11000101";
when 61919 => mw_U_3rom_table(61919) <= "00000000";
when 61920 => mw_U_3rom_table(61920) <= "11001000";
when 61921 => mw_U_3rom_table(61921) <= "11101000";
when 61922 => mw_U_3rom_table(61922) <= "11110001";
when 61923 => mw_U_3rom_table(61923) <= "01100011";
when 61924 => mw_U_3rom_table(61924) <= "11101110";
when 61925 => mw_U_3rom_table(61925) <= "01010110";
when 61926 => mw_U_3rom_table(61926) <= "11100110";
when 61927 => mw_U_3rom_table(61927) <= "11110001";
when 61928 => mw_U_3rom_table(61928) <= "01100011";
when 61929 => mw_U_3rom_table(61929) <= "11111110";
when 61930 => mw_U_3rom_table(61930) <= "01010110";
when 61931 => mw_U_3rom_table(61931) <= "11110110";
when 61932 => mw_U_3rom_table(61932) <= "00011010";
when 61933 => mw_U_3rom_table(61933) <= "11110001";
when 61934 => mw_U_3rom_table(61934) <= "01100011";
when 61935 => mw_U_3rom_table(61935) <= "01001101";
when 61936 => mw_U_3rom_table(61936) <= "01010110";
when 61937 => mw_U_3rom_table(61937) <= "01000101";
when 61938 => mw_U_3rom_table(61938) <= "00000000";
when 61939 => mw_U_3rom_table(61939) <= "01010110";
when 61940 => mw_U_3rom_table(61940) <= "01011001";
when 61941 => mw_U_3rom_table(61941) <= "01010110";
when 61942 => mw_U_3rom_table(61942) <= "01010101";
when 61943 => mw_U_3rom_table(61943) <= "01010110";
when 61944 => mw_U_3rom_table(61944) <= "01010010";
when 61945 => mw_U_3rom_table(61945) <= "01010110";
when 61946 => mw_U_3rom_table(61946) <= "01010001";
when 61947 => mw_U_3rom_table(61947) <= "01010110";
when 61948 => mw_U_3rom_table(61948) <= "01000001";
when 61949 => mw_U_3rom_table(61949) <= "01010110";
when 61950 => mw_U_3rom_table(61950) <= "01001001";
when 61951 => mw_U_3rom_table(61951) <= "10001000";
when 61952 => mw_U_3rom_table(61952) <= "01100011";
when 61953 => mw_U_3rom_table(61953) <= "10101101";
when 61954 => mw_U_3rom_table(61954) <= "01010110";
when 61955 => mw_U_3rom_table(61955) <= "10100101";
when 61956 => mw_U_3rom_table(61956) <= "00000000";
when 61957 => mw_U_3rom_table(61957) <= "01010110";
when 61958 => mw_U_3rom_table(61958) <= "10111001";
when 61959 => mw_U_3rom_table(61959) <= "01010110";
when 61960 => mw_U_3rom_table(61960) <= "10110101";
when 61961 => mw_U_3rom_table(61961) <= "01010110";
when 61962 => mw_U_3rom_table(61962) <= "10110010";
when 61963 => mw_U_3rom_table(61963) <= "01010110";
when 61964 => mw_U_3rom_table(61964) <= "10110001";
when 61965 => mw_U_3rom_table(61965) <= "01010110";
when 61966 => mw_U_3rom_table(61966) <= "10100001";
when 61967 => mw_U_3rom_table(61967) <= "01010110";
when 61968 => mw_U_3rom_table(61968) <= "10101001";
when 61969 => mw_U_3rom_table(61969) <= "11110001";
when 61970 => mw_U_3rom_table(61970) <= "01100011";
when 61971 => mw_U_3rom_table(61971) <= "00100000";
when 61972 => mw_U_3rom_table(61972) <= "00000000";
when 61973 => mw_U_3rom_table(61973) <= "01010110";
when 61974 => mw_U_3rom_table(61974) <= "00100000";
when 61975 => mw_U_3rom_table(61975) <= "00000000";
when 61976 => mw_U_3rom_table(61976) <= "01010110";
when 61977 => mw_U_3rom_table(61977) <= "01001100";
when 61978 => mw_U_3rom_table(61978) <= "00000000";
when 61979 => mw_U_3rom_table(61979) <= "01010110";
when 61980 => mw_U_3rom_table(61980) <= "01101100";
when 61981 => mw_U_3rom_table(61981) <= "00000000";
when 61982 => mw_U_3rom_table(61982) <= "01010110";
when 61983 => mw_U_3rom_table(61983) <= "01111100";
when 61984 => mw_U_3rom_table(61984) <= "01010110";
when 61985 => mw_U_3rom_table(61985) <= "00000001";
when 61986 => mw_U_3rom_table(61986) <= "01010110";
when 61987 => mw_U_3rom_table(61987) <= "00001001";
when 61988 => mw_U_3rom_table(61988) <= "11101010";
when 61989 => mw_U_3rom_table(61989) <= "11110001";
when 61990 => mw_U_3rom_table(61990) <= "01100011";
when 61991 => mw_U_3rom_table(61991) <= "01001110";
when 61992 => mw_U_3rom_table(61992) <= "01010110";
when 61993 => mw_U_3rom_table(61993) <= "01000110";
when 61994 => mw_U_3rom_table(61994) <= "01010110";
when 61995 => mw_U_3rom_table(61995) <= "01010110";
when 61996 => mw_U_3rom_table(61996) <= "01001010";
when 61997 => mw_U_3rom_table(61997) <= "11110001";
when 61998 => mw_U_3rom_table(61998) <= "01100011";
when 61999 => mw_U_3rom_table(61999) <= "10101100";
when 62000 => mw_U_3rom_table(62000) <= "01010110";
when 62001 => mw_U_3rom_table(62001) <= "10100100";
when 62002 => mw_U_3rom_table(62002) <= "01010110";
when 62003 => mw_U_3rom_table(62003) <= "10110100";
when 62004 => mw_U_3rom_table(62004) <= "01010110";
when 62005 => mw_U_3rom_table(62005) <= "10100000";
when 62006 => mw_U_3rom_table(62006) <= "11110001";
when 62007 => mw_U_3rom_table(62007) <= "01100011";
when 62008 => mw_U_3rom_table(62008) <= "10101110";
when 62009 => mw_U_3rom_table(62009) <= "01010110";
when 62010 => mw_U_3rom_table(62010) <= "10100110";
when 62011 => mw_U_3rom_table(62011) <= "01010110";
when 62012 => mw_U_3rom_table(62012) <= "10110110";
when 62013 => mw_U_3rom_table(62013) <= "01010110";
when 62014 => mw_U_3rom_table(62014) <= "10100010";
when 62015 => mw_U_3rom_table(62015) <= "11110001";
when 62016 => mw_U_3rom_table(62016) <= "11110001";
when 62017 => mw_U_3rom_table(62017) <= "01100011";
when 62018 => mw_U_3rom_table(62018) <= "01111110";
when 62019 => mw_U_3rom_table(62019) <= "01010110";
when 62020 => mw_U_3rom_table(62020) <= "01110110";
when 62021 => mw_U_3rom_table(62021) <= "01101010";
when 62022 => mw_U_3rom_table(62022) <= "11110001";
when 62023 => mw_U_3rom_table(62023) <= "01100011";
when 62024 => mw_U_3rom_table(62024) <= "00101110";
when 62025 => mw_U_3rom_table(62025) <= "01010110";
when 62026 => mw_U_3rom_table(62026) <= "00100110";
when 62027 => mw_U_3rom_table(62027) <= "01010110";
when 62028 => mw_U_3rom_table(62028) <= "00110110";
when 62029 => mw_U_3rom_table(62029) <= "00101010";
when 62030 => mw_U_3rom_table(62030) <= "00101000";
when 62031 => mw_U_3rom_table(62031) <= "01101000";
when 62032 => mw_U_3rom_table(62032) <= "00001000";
when 62033 => mw_U_3rom_table(62033) <= "01001000";
when 62034 => mw_U_3rom_table(62034) <= "11110001";
when 62035 => mw_U_3rom_table(62035) <= "01100011";
when 62036 => mw_U_3rom_table(62036) <= "00001101";
when 62037 => mw_U_3rom_table(62037) <= "01010110";
when 62038 => mw_U_3rom_table(62038) <= "00000101";
when 62039 => mw_U_3rom_table(62039) <= "00000000";
when 62040 => mw_U_3rom_table(62040) <= "01010110";
when 62041 => mw_U_3rom_table(62041) <= "00011001";
when 62042 => mw_U_3rom_table(62042) <= "01010110";
when 62043 => mw_U_3rom_table(62043) <= "00010101";
when 62044 => mw_U_3rom_table(62044) <= "01010110";
when 62045 => mw_U_3rom_table(62045) <= "00010010";
when 62046 => mw_U_3rom_table(62046) <= "01010110";
when 62047 => mw_U_3rom_table(62047) <= "00010001";
when 62048 => mw_U_3rom_table(62048) <= "01010110";
when 62049 => mw_U_3rom_table(62049) <= "10010001";
when 62050 => mw_U_3rom_table(62050) <= "01010110";
when 62051 => mw_U_3rom_table(62051) <= "10000001";
when 62052 => mw_U_3rom_table(62052) <= "01111000";
when 62053 => mw_U_3rom_table(62053) <= "11111000";
when 62054 => mw_U_3rom_table(62054) <= "00111000";
when 62055 => mw_U_3rom_table(62055) <= "11110001";
when 62056 => mw_U_3rom_table(62056) <= "01100011";
when 62057 => mw_U_3rom_table(62057) <= "11101101";
when 62058 => mw_U_3rom_table(62058) <= "01010110";
when 62059 => mw_U_3rom_table(62059) <= "11100101";
when 62060 => mw_U_3rom_table(62060) <= "00000000";
when 62061 => mw_U_3rom_table(62061) <= "01010110";
when 62062 => mw_U_3rom_table(62062) <= "11111001";
when 62063 => mw_U_3rom_table(62063) <= "01010110";
when 62064 => mw_U_3rom_table(62064) <= "11110101";
when 62065 => mw_U_3rom_table(62065) <= "01010110";
when 62066 => mw_U_3rom_table(62066) <= "11110010";
when 62067 => mw_U_3rom_table(62067) <= "01010110";
when 62068 => mw_U_3rom_table(62068) <= "11110001";
when 62069 => mw_U_3rom_table(62069) <= "01010110";
when 62070 => mw_U_3rom_table(62070) <= "11100001";
when 62071 => mw_U_3rom_table(62071) <= "01010110";
when 62072 => mw_U_3rom_table(62072) <= "11101001";
when 62073 => mw_U_3rom_table(62073) <= "01100000";
when 62074 => mw_U_3rom_table(62074) <= "01000000";
when 62075 => mw_U_3rom_table(62075) <= "11110001";
when 62076 => mw_U_3rom_table(62076) <= "01100011";
when 62077 => mw_U_3rom_table(62077) <= "01101110";
when 62078 => mw_U_3rom_table(62078) <= "01010110";
when 62079 => mw_U_3rom_table(62079) <= "01100110";
when 62080 => mw_U_3rom_table(62080) <= "10011000";
when 62081 => mw_U_3rom_table(62081) <= "10011010";
when 62082 => mw_U_3rom_table(62082) <= "10001010";
when 62083 => mw_U_3rom_table(62083) <= "10111010";
when 62084 => mw_U_3rom_table(62084) <= "10101000";
when 62085 => mw_U_3rom_table(62085) <= "10101010";
when 62086 => mw_U_3rom_table(62086) <= "11110001";
when 62087 => mw_U_3rom_table(62087) <= "01100011";
when 62088 => mw_U_3rom_table(62088) <= "10001100";
when 62089 => mw_U_3rom_table(62089) <= "01010110";
when 62090 => mw_U_3rom_table(62090) <= "10000100";
when 62091 => mw_U_3rom_table(62091) <= "01010110";
when 62092 => mw_U_3rom_table(62092) <= "10010100";
when 62093 => mw_U_3rom_table(62093) <= "11110001";
when 62094 => mw_U_3rom_table(62094) <= "01100011";
when 62095 => mw_U_3rom_table(62095) <= "10001110";
when 62096 => mw_U_3rom_table(62096) <= "01010110";
when 62097 => mw_U_3rom_table(62097) <= "10000110";
when 62098 => mw_U_3rom_table(62098) <= "01010110";
when 62099 => mw_U_3rom_table(62099) <= "10010110";
when 62100 => mw_U_3rom_table(62100) <= "11110001";
when 62101 => mw_U_3rom_table(62101) <= "01100011";
when 62102 => mw_U_3rom_table(62102) <= "10001101";
when 62103 => mw_U_3rom_table(62103) <= "01010110";
when 62104 => mw_U_3rom_table(62104) <= "10000101";
when 62105 => mw_U_3rom_table(62105) <= "00000000";
when 62106 => mw_U_3rom_table(62106) <= "01010110";
when 62107 => mw_U_3rom_table(62107) <= "10011001";
when 62108 => mw_U_3rom_table(62108) <= "01010110";
when 62109 => mw_U_3rom_table(62109) <= "10010101";
when 62110 => mw_U_3rom_table(62110) <= "01010110";
when 62111 => mw_U_3rom_table(62111) <= "10010010";
when 62112 => mw_U_3rom_table(62112) <= "11100010";
when 62113 => mw_U_3rom_table(62113) <= "01010110";
when 62114 => mw_U_3rom_table(62114) <= "10011111";
when 62115 => mw_U_3rom_table(62115) <= "11100101";
when 62116 => mw_U_3rom_table(62116) <= "01010110";
when 62117 => mw_U_3rom_table(62117) <= "10001111";
when 62118 => mw_U_3rom_table(62118) <= "11101000";
when 62119 => mw_U_3rom_table(62119) <= "01010110";
when 62120 => mw_U_3rom_table(62120) <= "01111111";
when 62121 => mw_U_3rom_table(62121) <= "11101011";
when 62122 => mw_U_3rom_table(62122) <= "01010110";
when 62123 => mw_U_3rom_table(62123) <= "01101111";
when 62124 => mw_U_3rom_table(62124) <= "11101110";
when 62125 => mw_U_3rom_table(62125) <= "01010110";
when 62126 => mw_U_3rom_table(62126) <= "01011111";
when 62127 => mw_U_3rom_table(62127) <= "11110001";
when 62128 => mw_U_3rom_table(62128) <= "01010110";
when 62129 => mw_U_3rom_table(62129) <= "01001111";
when 62130 => mw_U_3rom_table(62130) <= "11110100";
when 62131 => mw_U_3rom_table(62131) <= "01010110";
when 62132 => mw_U_3rom_table(62132) <= "00111111";
when 62133 => mw_U_3rom_table(62133) <= "11110111";
when 62134 => mw_U_3rom_table(62134) <= "01010110";
when 62135 => mw_U_3rom_table(62135) <= "00101111";
when 62136 => mw_U_3rom_table(62136) <= "11111010";
when 62137 => mw_U_3rom_table(62137) <= "01010110";
when 62138 => mw_U_3rom_table(62138) <= "00011111";
when 62139 => mw_U_3rom_table(62139) <= "11111101";
when 62140 => mw_U_3rom_table(62140) <= "01010110";
when 62141 => mw_U_3rom_table(62141) <= "00001111";
when 62142 => mw_U_3rom_table(62142) <= "00000000";
when 62143 => mw_U_3rom_table(62143) <= "10000000";
when 62144 => mw_U_3rom_table(62144) <= "01000111";
when 62145 => mw_U_3rom_table(62145) <= "01010110";
when 62146 => mw_U_3rom_table(62146) <= "00110111";
when 62147 => mw_U_3rom_table(62147) <= "01010110";
when 62148 => mw_U_3rom_table(62148) <= "00100111";
when 62149 => mw_U_3rom_table(62149) <= "01010110";
when 62150 => mw_U_3rom_table(62150) <= "00010111";
when 62151 => mw_U_3rom_table(62151) <= "01010110";
when 62152 => mw_U_3rom_table(62152) <= "00000111";
when 62153 => mw_U_3rom_table(62153) <= "01111010";
when 62154 => mw_U_3rom_table(62154) <= "11111010";
when 62155 => mw_U_3rom_table(62155) <= "01011010";
when 62156 => mw_U_3rom_table(62156) <= "11011010";
when 62157 => mw_U_3rom_table(62157) <= "00000010";
when 62158 => mw_U_3rom_table(62158) <= "11010000";
when 62159 => mw_U_3rom_table(62159) <= "01010110";
when 62160 => mw_U_3rom_table(62160) <= "11111111";
when 62161 => mw_U_3rom_table(62161) <= "11010011";
when 62162 => mw_U_3rom_table(62162) <= "01010110";
when 62163 => mw_U_3rom_table(62163) <= "11101111";
when 62164 => mw_U_3rom_table(62164) <= "11010110";
when 62165 => mw_U_3rom_table(62165) <= "01010110";
when 62166 => mw_U_3rom_table(62166) <= "11011111";
when 62167 => mw_U_3rom_table(62167) <= "11011001";
when 62168 => mw_U_3rom_table(62168) <= "01010110";
when 62169 => mw_U_3rom_table(62169) <= "11001111";
when 62170 => mw_U_3rom_table(62170) <= "11011100";
when 62171 => mw_U_3rom_table(62171) <= "01010110";
when 62172 => mw_U_3rom_table(62172) <= "10111111";
when 62173 => mw_U_3rom_table(62173) <= "11011111";
when 62174 => mw_U_3rom_table(62174) <= "01010110";
when 62175 => mw_U_3rom_table(62175) <= "10101111";
when 62176 => mw_U_3rom_table(62176) <= "01010110";
when 62177 => mw_U_3rom_table(62177) <= "00010100";
when 62178 => mw_U_3rom_table(62178) <= "11110001";
when 62179 => mw_U_3rom_table(62179) <= "01100011";
when 62180 => mw_U_3rom_table(62180) <= "10011100";
when 62181 => mw_U_3rom_table(62181) <= "01010110";
when 62182 => mw_U_3rom_table(62182) <= "01100100";
when 62183 => mw_U_3rom_table(62183) <= "01010110";
when 62184 => mw_U_3rom_table(62184) <= "01110100";
when 62185 => mw_U_3rom_table(62185) <= "01010110";
when 62186 => mw_U_3rom_table(62186) <= "11110111";
when 62187 => mw_U_3rom_table(62187) <= "01010110";
when 62188 => mw_U_3rom_table(62188) <= "11100111";
when 62189 => mw_U_3rom_table(62189) <= "01010110";
when 62190 => mw_U_3rom_table(62190) <= "11010111";
when 62191 => mw_U_3rom_table(62191) <= "01010110";
when 62192 => mw_U_3rom_table(62192) <= "11000111";
when 62193 => mw_U_3rom_table(62193) <= "01010110";
when 62194 => mw_U_3rom_table(62194) <= "10110111";
when 62195 => mw_U_3rom_table(62195) <= "01010110";
when 62196 => mw_U_3rom_table(62196) <= "10100111";
when 62197 => mw_U_3rom_table(62197) <= "01010110";
when 62198 => mw_U_3rom_table(62198) <= "10010111";
when 62199 => mw_U_3rom_table(62199) <= "01010110";
when 62200 => mw_U_3rom_table(62200) <= "10000111";
when 62201 => mw_U_3rom_table(62201) <= "01010110";
when 62202 => mw_U_3rom_table(62202) <= "01110111";
when 62203 => mw_U_3rom_table(62203) <= "01010110";
when 62204 => mw_U_3rom_table(62204) <= "01100111";
when 62205 => mw_U_3rom_table(62205) <= "01010110";
when 62206 => mw_U_3rom_table(62206) <= "01010111";
when 62207 => mw_U_3rom_table(62207) <= "01010110";
when 62208 => mw_U_3rom_table(62208) <= "11111111";
when 62209 => mw_U_3rom_table(62209) <= "11111111";
when 62210 => mw_U_3rom_table(62210) <= "11111111";
when 62211 => mw_U_3rom_table(62211) <= "11111111";
when 62212 => mw_U_3rom_table(62212) <= "11111111";
when 62213 => mw_U_3rom_table(62213) <= "11111111";
when 62214 => mw_U_3rom_table(62214) <= "11111111";
when 62215 => mw_U_3rom_table(62215) <= "11111111";
when 62216 => mw_U_3rom_table(62216) <= "11111111";
when 62217 => mw_U_3rom_table(62217) <= "11111111";
when 62218 => mw_U_3rom_table(62218) <= "11111111";
when 62219 => mw_U_3rom_table(62219) <= "11111111";
when 62220 => mw_U_3rom_table(62220) <= "11111111";
when 62221 => mw_U_3rom_table(62221) <= "11111111";
when 62222 => mw_U_3rom_table(62222) <= "11111111";
when 62223 => mw_U_3rom_table(62223) <= "11111111";
when 62224 => mw_U_3rom_table(62224) <= "11111111";
when 62225 => mw_U_3rom_table(62225) <= "11111111";
when 62226 => mw_U_3rom_table(62226) <= "11111111";
when 62227 => mw_U_3rom_table(62227) <= "11111111";
when 62228 => mw_U_3rom_table(62228) <= "11111111";
when 62229 => mw_U_3rom_table(62229) <= "11111111";
when 62230 => mw_U_3rom_table(62230) <= "11111111";
when 62231 => mw_U_3rom_table(62231) <= "11111111";
when 62232 => mw_U_3rom_table(62232) <= "11111111";
when 62233 => mw_U_3rom_table(62233) <= "11111111";
when 62234 => mw_U_3rom_table(62234) <= "11111111";
when 62235 => mw_U_3rom_table(62235) <= "11111111";
when 62236 => mw_U_3rom_table(62236) <= "11111111";
when 62237 => mw_U_3rom_table(62237) <= "11111111";
when 62238 => mw_U_3rom_table(62238) <= "01010110";
when 62239 => mw_U_3rom_table(62239) <= "00000100";
when 65504 => mw_U_3rom_table(65504) <= "11111111";
when 65505 => mw_U_3rom_table(65505) <= "11111111";
when 65506 => mw_U_3rom_table(65506) <= "11110000";
when 65507 => mw_U_3rom_table(65507) <= "00000000";
when 65508 => mw_U_3rom_table(65508) <= "11111111";
when 65509 => mw_U_3rom_table(65509) <= "11111111";
when 65510 => mw_U_3rom_table(65510) <= "11111111";
when 65511 => mw_U_3rom_table(65511) <= "11111111";
when 65512 => mw_U_3rom_table(65512) <= "11111111";
when 65513 => mw_U_3rom_table(65513) <= "11111111";
when 65514 => mw_U_3rom_table(65514) <= "11111111";
when 65515 => mw_U_3rom_table(65515) <= "11111111";
when 65516 => mw_U_3rom_table(65516) <= "11111111";
when 65517 => mw_U_3rom_table(65517) <= "11111111";
when 65518 => mw_U_3rom_table(65518) <= "11111111";
when 65519 => mw_U_3rom_table(65519) <= "11111111";
when 65520 => mw_U_3rom_table(65520) <= "11111111";
when 65521 => mw_U_3rom_table(65521) <= "11111111";
when 65522 => mw_U_3rom_table(65522) <= "11111111";
when 65523 => mw_U_3rom_table(65523) <= "11111111";
when 65524 => mw_U_3rom_table(65524) <= "11111111";
when 65525 => mw_U_3rom_table(65525) <= "11111111";
when 65526 => mw_U_3rom_table(65526) <= "11111111";
when 65527 => mw_U_3rom_table(65527) <= "11111111";
when 65528 => mw_U_3rom_table(65528) <= "11111111";
when 65529 => mw_U_3rom_table(65529) <= "11111111";
when 65530 => mw_U_3rom_table(65530) <= "11111111";
when 65531 => mw_U_3rom_table(65531) <= "11111111";
when 65532 => mw_U_3rom_table(65532) <= "11111111";
when 65533 => mw_U_3rom_table(65533) <= "11111111";
when 65534 => mw_U_3rom_table(65534) <= "11111111";
when 65535 => mw_U_3rom_table(65535) <= "11111111";
when others => mw_U_3rom_table(mw_U_3addr_int) <= (others => 'X') ;
end case;
end process ;
u_3rom_read_proc : process ( clk1 )
begin
if (clk1'event and clk1='1') then
dout1 <= mw_U_3rom_table(mw_U_3addr_int);
end if;
end process ;
-- Instance port mappings.
U_0 : R6502_TC
port map (
clk_clk_i => clk,
d_i => RAM_DOUT_internal,
irq_n_i => IRQn,
nmi_n_i => NMIn,
rdy_i => RDY,
rst_rst_n_i => RSTn,
so_n_i => so_n_i,
a_o => A_internal,
d_o => CPU_DOUT_internal,
rd_o => RD,
sync_o => SYNC,
wr_n_o => open,
wr_o => WR_internal
);
-- Implicit buffered output assignments
CPU_DOUT <= CPU_DOUT_internal;
RAM_DOUT <= RAM_DOUT_internal;
WR <= WR_internal;
A <= A_internal;
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.reu_pkg.all;
entity reu_tc_1 is
end reu_tc_1;
architecture testcase of reu_tc_1 is
shared variable errors : integer := 0;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_reu_base : unsigned := X"DF00";
constant c_read_after_reset : t_byte_array(0 to 15) := (
X"10", -- status: version 0, no irq pending, done flag not set, no verify error, 256K or bigger.
X"10", -- command: only ff00 flag set
X"00", X"00", -- c64 base / addr
X"00", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"FF", X"FF", -- trans length
X"1F", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_1 : t_byte_array(0 to 15) := (
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask (all 3 bits set, other bits unused, thus 1)
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_2 : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"B0", -- status: version 0, irq pending, done flag NOT set, verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"10", X"00", -- trans length = 0x10 (error after 16 bytes, 16 to go)
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_swap : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"12", -- command: ff00 flag set, mode is swap
X"A0", X"30", -- c64 base / addr 3080+20
X"20", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
procedure check(a,b : std_logic_vector; d: unsigned; s : string) is
begin
if a /= b then
print("ERROR: " & s & ": " & hstr(a) & "/=" & hstr(b) & " on addr " & hstr(d));
errors := errors + 1;
end if;
-- assert a = b report s severity error;
end procedure;
begin
i_harness: entity work.harness_reu
;
p_test: process
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable addr : unsigned(15 downto 0);
variable c64_mem : h_mem_object;
variable reu_mem : h_mem_object;
--variable datas : t_byte_array(0 to 15);
procedure reu_operation(op : std_logic_vector;
c64_addr : unsigned(15 downto 0);
reu_addr : unsigned(23 downto 0);
len : unsigned(15 downto 0) ) is
variable cmd : std_logic_vector(7 downto 0);
begin
cmd := X"90";
cmd(op'length-1 downto 0) := op;
slot_io_write(slot, c_reu_base + c_c64base_l, std_logic_vector(c64_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_c64base_h, std_logic_vector(c64_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_l, std_logic_vector(reu_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_reubase_m, std_logic_vector(reu_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_h, std_logic_vector(reu_addr(23 downto 16)));
slot_io_write(slot, c_reu_base + c_translen_l, std_logic_vector(len( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_translen_h, std_logic_vector(len(15 downto 8)));
slot_io_write(slot, c_reu_base + c_command, cmd);
end procedure;
begin
wait for 150 ns;
bind_slot_bus_master_bfm("slot master", slot);
bind_mem_model("c64_memory", c64_mem);
bind_mem_model("reu_memory", reu_mem);
for i in c_read_after_reset'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_reset(i), addr, "Register read after reset not as expected.");
end loop;
for i in 0 to 255 loop
write_memory_8(c64_mem, std_logic_vector(to_unsigned(16#3000# + i, 32)),
std_logic_vector(to_unsigned(99+i*37, 8)));
end loop;
-- enable IRQ on done (and verify error for later), so that we can wait for it
slot_io_write(slot, c_reu_base + c_irqmask, X"E0");
-- try to copy something (16 bytes) from c64 to reu
reu_operation(c_mode_toreu, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
slot_io_read(slot, c_reu_base + c_status, data);
-- Verify the copied data
reu_operation(c_mode_verify, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
for i in c_read_after_verify_1'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_1(i), addr, "Register read after verify 1 not as expected.");
end loop;
-- Verify operation 2: verify 32 bytes, of course this will fail, since we only copied 16 bytes
reu_operation(c_mode_verify, X"3000", X"012345", X"0020");
slot_wait_irq(slot);
for i in c_read_after_verify_2'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_2(i), addr, "Register read after verify 2 not as expected.");
end loop;
-- Swap operation
reu_operation(c_mode_swap, X"3080", X"000000", X"0020");
slot_wait_irq(slot);
for i in c_read_after_swap'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_swap(i), addr, "Register read after swap not as expected.");
end loop;
assert errors = 0 report "Errors encounted" severity failure;
wait;
end process;
end testcase;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.reu_pkg.all;
entity reu_tc_1 is
end reu_tc_1;
architecture testcase of reu_tc_1 is
shared variable errors : integer := 0;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_reu_base : unsigned := X"DF00";
constant c_read_after_reset : t_byte_array(0 to 15) := (
X"10", -- status: version 0, no irq pending, done flag not set, no verify error, 256K or bigger.
X"10", -- command: only ff00 flag set
X"00", X"00", -- c64 base / addr
X"00", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"FF", X"FF", -- trans length
X"1F", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_1 : t_byte_array(0 to 15) := (
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask (all 3 bits set, other bits unused, thus 1)
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_2 : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"B0", -- status: version 0, irq pending, done flag NOT set, verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"10", X"00", -- trans length = 0x10 (error after 16 bytes, 16 to go)
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_swap : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"12", -- command: ff00 flag set, mode is swap
X"A0", X"30", -- c64 base / addr 3080+20
X"20", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
procedure check(a,b : std_logic_vector; d: unsigned; s : string) is
begin
if a /= b then
print("ERROR: " & s & ": " & hstr(a) & "/=" & hstr(b) & " on addr " & hstr(d));
errors := errors + 1;
end if;
-- assert a = b report s severity error;
end procedure;
begin
i_harness: entity work.harness_reu
;
p_test: process
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable addr : unsigned(15 downto 0);
variable c64_mem : h_mem_object;
variable reu_mem : h_mem_object;
--variable datas : t_byte_array(0 to 15);
procedure reu_operation(op : std_logic_vector;
c64_addr : unsigned(15 downto 0);
reu_addr : unsigned(23 downto 0);
len : unsigned(15 downto 0) ) is
variable cmd : std_logic_vector(7 downto 0);
begin
cmd := X"90";
cmd(op'length-1 downto 0) := op;
slot_io_write(slot, c_reu_base + c_c64base_l, std_logic_vector(c64_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_c64base_h, std_logic_vector(c64_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_l, std_logic_vector(reu_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_reubase_m, std_logic_vector(reu_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_h, std_logic_vector(reu_addr(23 downto 16)));
slot_io_write(slot, c_reu_base + c_translen_l, std_logic_vector(len( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_translen_h, std_logic_vector(len(15 downto 8)));
slot_io_write(slot, c_reu_base + c_command, cmd);
end procedure;
begin
wait for 150 ns;
bind_slot_bus_master_bfm("slot master", slot);
bind_mem_model("c64_memory", c64_mem);
bind_mem_model("reu_memory", reu_mem);
for i in c_read_after_reset'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_reset(i), addr, "Register read after reset not as expected.");
end loop;
for i in 0 to 255 loop
write_memory_8(c64_mem, std_logic_vector(to_unsigned(16#3000# + i, 32)),
std_logic_vector(to_unsigned(99+i*37, 8)));
end loop;
-- enable IRQ on done (and verify error for later), so that we can wait for it
slot_io_write(slot, c_reu_base + c_irqmask, X"E0");
-- try to copy something (16 bytes) from c64 to reu
reu_operation(c_mode_toreu, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
slot_io_read(slot, c_reu_base + c_status, data);
-- Verify the copied data
reu_operation(c_mode_verify, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
for i in c_read_after_verify_1'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_1(i), addr, "Register read after verify 1 not as expected.");
end loop;
-- Verify operation 2: verify 32 bytes, of course this will fail, since we only copied 16 bytes
reu_operation(c_mode_verify, X"3000", X"012345", X"0020");
slot_wait_irq(slot);
for i in c_read_after_verify_2'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_2(i), addr, "Register read after verify 2 not as expected.");
end loop;
-- Swap operation
reu_operation(c_mode_swap, X"3080", X"000000", X"0020");
slot_wait_irq(slot);
for i in c_read_after_swap'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_swap(i), addr, "Register read after swap not as expected.");
end loop;
assert errors = 0 report "Errors encounted" severity failure;
wait;
end process;
end testcase;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.reu_pkg.all;
entity reu_tc_1 is
end reu_tc_1;
architecture testcase of reu_tc_1 is
shared variable errors : integer := 0;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_reu_base : unsigned := X"DF00";
constant c_read_after_reset : t_byte_array(0 to 15) := (
X"10", -- status: version 0, no irq pending, done flag not set, no verify error, 256K or bigger.
X"10", -- command: only ff00 flag set
X"00", X"00", -- c64 base / addr
X"00", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"FF", X"FF", -- trans length
X"1F", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_1 : t_byte_array(0 to 15) := (
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask (all 3 bits set, other bits unused, thus 1)
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_2 : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"B0", -- status: version 0, irq pending, done flag NOT set, verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"10", X"00", -- trans length = 0x10 (error after 16 bytes, 16 to go)
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_swap : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"12", -- command: ff00 flag set, mode is swap
X"A0", X"30", -- c64 base / addr 3080+20
X"20", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
procedure check(a,b : std_logic_vector; d: unsigned; s : string) is
begin
if a /= b then
print("ERROR: " & s & ": " & hstr(a) & "/=" & hstr(b) & " on addr " & hstr(d));
errors := errors + 1;
end if;
-- assert a = b report s severity error;
end procedure;
begin
i_harness: entity work.harness_reu
;
p_test: process
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable addr : unsigned(15 downto 0);
variable c64_mem : h_mem_object;
variable reu_mem : h_mem_object;
--variable datas : t_byte_array(0 to 15);
procedure reu_operation(op : std_logic_vector;
c64_addr : unsigned(15 downto 0);
reu_addr : unsigned(23 downto 0);
len : unsigned(15 downto 0) ) is
variable cmd : std_logic_vector(7 downto 0);
begin
cmd := X"90";
cmd(op'length-1 downto 0) := op;
slot_io_write(slot, c_reu_base + c_c64base_l, std_logic_vector(c64_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_c64base_h, std_logic_vector(c64_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_l, std_logic_vector(reu_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_reubase_m, std_logic_vector(reu_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_h, std_logic_vector(reu_addr(23 downto 16)));
slot_io_write(slot, c_reu_base + c_translen_l, std_logic_vector(len( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_translen_h, std_logic_vector(len(15 downto 8)));
slot_io_write(slot, c_reu_base + c_command, cmd);
end procedure;
begin
wait for 150 ns;
bind_slot_bus_master_bfm("slot master", slot);
bind_mem_model("c64_memory", c64_mem);
bind_mem_model("reu_memory", reu_mem);
for i in c_read_after_reset'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_reset(i), addr, "Register read after reset not as expected.");
end loop;
for i in 0 to 255 loop
write_memory_8(c64_mem, std_logic_vector(to_unsigned(16#3000# + i, 32)),
std_logic_vector(to_unsigned(99+i*37, 8)));
end loop;
-- enable IRQ on done (and verify error for later), so that we can wait for it
slot_io_write(slot, c_reu_base + c_irqmask, X"E0");
-- try to copy something (16 bytes) from c64 to reu
reu_operation(c_mode_toreu, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
slot_io_read(slot, c_reu_base + c_status, data);
-- Verify the copied data
reu_operation(c_mode_verify, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
for i in c_read_after_verify_1'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_1(i), addr, "Register read after verify 1 not as expected.");
end loop;
-- Verify operation 2: verify 32 bytes, of course this will fail, since we only copied 16 bytes
reu_operation(c_mode_verify, X"3000", X"012345", X"0020");
slot_wait_irq(slot);
for i in c_read_after_verify_2'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_2(i), addr, "Register read after verify 2 not as expected.");
end loop;
-- Swap operation
reu_operation(c_mode_swap, X"3080", X"000000", X"0020");
slot_wait_irq(slot);
for i in c_read_after_swap'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_swap(i), addr, "Register read after swap not as expected.");
end loop;
assert errors = 0 report "Errors encounted" severity failure;
wait;
end process;
end testcase;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.reu_pkg.all;
entity reu_tc_1 is
end reu_tc_1;
architecture testcase of reu_tc_1 is
shared variable errors : integer := 0;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_reu_base : unsigned := X"DF00";
constant c_read_after_reset : t_byte_array(0 to 15) := (
X"10", -- status: version 0, no irq pending, done flag not set, no verify error, 256K or bigger.
X"10", -- command: only ff00 flag set
X"00", X"00", -- c64 base / addr
X"00", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"FF", X"FF", -- trans length
X"1F", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_1 : t_byte_array(0 to 15) := (
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask (all 3 bits set, other bits unused, thus 1)
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_2 : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"B0", -- status: version 0, irq pending, done flag NOT set, verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"10", X"00", -- trans length = 0x10 (error after 16 bytes, 16 to go)
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_swap : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"12", -- command: ff00 flag set, mode is swap
X"A0", X"30", -- c64 base / addr 3080+20
X"20", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
procedure check(a,b : std_logic_vector; d: unsigned; s : string) is
begin
if a /= b then
print("ERROR: " & s & ": " & hstr(a) & "/=" & hstr(b) & " on addr " & hstr(d));
errors := errors + 1;
end if;
-- assert a = b report s severity error;
end procedure;
begin
i_harness: entity work.harness_reu
;
p_test: process
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable addr : unsigned(15 downto 0);
variable c64_mem : h_mem_object;
variable reu_mem : h_mem_object;
--variable datas : t_byte_array(0 to 15);
procedure reu_operation(op : std_logic_vector;
c64_addr : unsigned(15 downto 0);
reu_addr : unsigned(23 downto 0);
len : unsigned(15 downto 0) ) is
variable cmd : std_logic_vector(7 downto 0);
begin
cmd := X"90";
cmd(op'length-1 downto 0) := op;
slot_io_write(slot, c_reu_base + c_c64base_l, std_logic_vector(c64_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_c64base_h, std_logic_vector(c64_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_l, std_logic_vector(reu_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_reubase_m, std_logic_vector(reu_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_h, std_logic_vector(reu_addr(23 downto 16)));
slot_io_write(slot, c_reu_base + c_translen_l, std_logic_vector(len( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_translen_h, std_logic_vector(len(15 downto 8)));
slot_io_write(slot, c_reu_base + c_command, cmd);
end procedure;
begin
wait for 150 ns;
bind_slot_bus_master_bfm("slot master", slot);
bind_mem_model("c64_memory", c64_mem);
bind_mem_model("reu_memory", reu_mem);
for i in c_read_after_reset'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_reset(i), addr, "Register read after reset not as expected.");
end loop;
for i in 0 to 255 loop
write_memory_8(c64_mem, std_logic_vector(to_unsigned(16#3000# + i, 32)),
std_logic_vector(to_unsigned(99+i*37, 8)));
end loop;
-- enable IRQ on done (and verify error for later), so that we can wait for it
slot_io_write(slot, c_reu_base + c_irqmask, X"E0");
-- try to copy something (16 bytes) from c64 to reu
reu_operation(c_mode_toreu, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
slot_io_read(slot, c_reu_base + c_status, data);
-- Verify the copied data
reu_operation(c_mode_verify, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
for i in c_read_after_verify_1'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_1(i), addr, "Register read after verify 1 not as expected.");
end loop;
-- Verify operation 2: verify 32 bytes, of course this will fail, since we only copied 16 bytes
reu_operation(c_mode_verify, X"3000", X"012345", X"0020");
slot_wait_irq(slot);
for i in c_read_after_verify_2'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_2(i), addr, "Register read after verify 2 not as expected.");
end loop;
-- Swap operation
reu_operation(c_mode_swap, X"3080", X"000000", X"0020");
slot_wait_irq(slot);
for i in c_read_after_swap'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_swap(i), addr, "Register read after swap not as expected.");
end loop;
assert errors = 0 report "Errors encounted" severity failure;
wait;
end process;
end testcase;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.reu_pkg.all;
entity reu_tc_1 is
end reu_tc_1;
architecture testcase of reu_tc_1 is
shared variable errors : integer := 0;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_reu_base : unsigned := X"DF00";
constant c_read_after_reset : t_byte_array(0 to 15) := (
X"10", -- status: version 0, no irq pending, done flag not set, no verify error, 256K or bigger.
X"10", -- command: only ff00 flag set
X"00", X"00", -- c64 base / addr
X"00", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"FF", X"FF", -- trans length
X"1F", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_1 : t_byte_array(0 to 15) := (
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask (all 3 bits set, other bits unused, thus 1)
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_2 : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"B0", -- status: version 0, irq pending, done flag NOT set, verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"10", X"00", -- trans length = 0x10 (error after 16 bytes, 16 to go)
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_swap : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"12", -- command: ff00 flag set, mode is swap
X"A0", X"30", -- c64 base / addr 3080+20
X"20", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
procedure check(a,b : std_logic_vector; d: unsigned; s : string) is
begin
if a /= b then
print("ERROR: " & s & ": " & hstr(a) & "/=" & hstr(b) & " on addr " & hstr(d));
errors := errors + 1;
end if;
-- assert a = b report s severity error;
end procedure;
begin
i_harness: entity work.harness_reu
;
p_test: process
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable addr : unsigned(15 downto 0);
variable c64_mem : h_mem_object;
variable reu_mem : h_mem_object;
--variable datas : t_byte_array(0 to 15);
procedure reu_operation(op : std_logic_vector;
c64_addr : unsigned(15 downto 0);
reu_addr : unsigned(23 downto 0);
len : unsigned(15 downto 0) ) is
variable cmd : std_logic_vector(7 downto 0);
begin
cmd := X"90";
cmd(op'length-1 downto 0) := op;
slot_io_write(slot, c_reu_base + c_c64base_l, std_logic_vector(c64_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_c64base_h, std_logic_vector(c64_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_l, std_logic_vector(reu_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_reubase_m, std_logic_vector(reu_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_h, std_logic_vector(reu_addr(23 downto 16)));
slot_io_write(slot, c_reu_base + c_translen_l, std_logic_vector(len( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_translen_h, std_logic_vector(len(15 downto 8)));
slot_io_write(slot, c_reu_base + c_command, cmd);
end procedure;
begin
wait for 150 ns;
bind_slot_bus_master_bfm("slot master", slot);
bind_mem_model("c64_memory", c64_mem);
bind_mem_model("reu_memory", reu_mem);
for i in c_read_after_reset'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_reset(i), addr, "Register read after reset not as expected.");
end loop;
for i in 0 to 255 loop
write_memory_8(c64_mem, std_logic_vector(to_unsigned(16#3000# + i, 32)),
std_logic_vector(to_unsigned(99+i*37, 8)));
end loop;
-- enable IRQ on done (and verify error for later), so that we can wait for it
slot_io_write(slot, c_reu_base + c_irqmask, X"E0");
-- try to copy something (16 bytes) from c64 to reu
reu_operation(c_mode_toreu, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
slot_io_read(slot, c_reu_base + c_status, data);
-- Verify the copied data
reu_operation(c_mode_verify, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
for i in c_read_after_verify_1'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_1(i), addr, "Register read after verify 1 not as expected.");
end loop;
-- Verify operation 2: verify 32 bytes, of course this will fail, since we only copied 16 bytes
reu_operation(c_mode_verify, X"3000", X"012345", X"0020");
slot_wait_irq(slot);
for i in c_read_after_verify_2'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_2(i), addr, "Register read after verify 2 not as expected.");
end loop;
-- Swap operation
reu_operation(c_mode_swap, X"3080", X"000000", X"0020");
slot_wait_irq(slot);
for i in c_read_after_swap'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_swap(i), addr, "Register read after swap not as expected.");
end loop;
assert errors = 0 report "Errors encounted" severity failure;
wait;
end process;
end testcase;
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
check_en : out std_logic; -- check_en.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ready : in std_logic := '0'; -- ready.wire
data_en : out std_logic; -- data_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_en : out std_logic -- ctrl_en.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component StateMachineEditor is
port (
clock : in std_logic := 'X'; -- clk
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_end : in std_logic := 'X'; -- wire
ready : in std_logic := 'X'; -- wire
reset : in std_logic := 'X'; -- wire
state : out std_logic_vector(2 downto 0) -- wire
);
end component StateMachineEditor;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GN4KF5KLTA is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic; -- wire
r2 : out std_logic; -- wire
r3 : out std_logic; -- wire
r4 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GN4KF5KLTA;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GN5P6ORZXA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN5P6ORZXA;
component alt_dspbuilder_cast_GNLWRZWTQF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLWRZWTQF;
signal pipelined_adder1user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder1user_aclrGND:output -> Pipelined_Adder1:user_aclr
signal pipelined_adder1enavcc_output_wire : std_logic; -- Pipelined_Adder1enaVCC:output -> Pipelined_Adder1:ena
signal single_pulsesclrgnd_output_wire : std_logic; -- Single_PulsesclrGND:output -> Single_Pulse:sclr
signal single_pulseenavcc_output_wire : std_logic; -- Single_PulseenaVCC:output -> Single_Pulse:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [If_Statement6:a, cast27:input]
signal constant15_output_wire : std_logic_vector(23 downto 0); -- Constant15:output -> Pipelined_Adder1:datab
signal pipelined_adder1_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder1:result -> If_Statement6:b
signal single_pulse_result_wire : std_logic; -- Single_Pulse:result -> State_Machine_Editor:reset
signal ready_0_output_wire : std_logic; -- ready_0:output -> State_Machine_Editor:ready
signal if_statement6_true_wire : std_logic; -- If_Statement6:true -> State_Machine_Editor:data_end
signal case_statement_r1_wire : std_logic; -- Case_Statement:r1 -> ctrl_en_0:input
signal case_statement_r2_wire : std_logic; -- Case_Statement:r2 -> data_en_0:input
signal case_statement_r3_wire : std_logic; -- Case_Statement:r3 -> check_en_0:input
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast26:input
signal cast26_output_wire : std_logic_vector(23 downto 0); -- cast26:output -> Pipelined_Adder1:dataa
signal cast27_output_wire : std_logic_vector(23 downto 0); -- cast27:output -> State_Machine_Editor:counter
signal state_machine_editor_state_wire : std_logic_vector(2 downto 0); -- State_Machine_Editor:state -> cast28:input
signal cast28_output_wire : std_logic_vector(2 downto 0); -- cast28:output -> Case_Statement:input
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Case_Statement:clock, Pipelined_Adder1:clock, Single_Pulse:clock, State_Machine_Editor:clock]
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Case_Statement:aclr, Pipelined_Adder1:aclr, Single_Pulse:aclr]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r1_wire, -- input.wire
output => ctrl_en -- output.wire
);
state_machine_editor : component StateMachineEditor
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse_result_wire, -- reset.wire
ready => ready_0_output_wire, -- ready.wire
counter => cast27_output_wire, -- counter.wire
data_end => if_statement6_true_wire, -- data_end.wire
state => state_machine_editor_state_wire -- state.wire
);
pipelined_adder1 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast26_output_wire, -- dataa.wire
datab => constant15_output_wire, -- datab.wire
result => pipelined_adder1_result_wire, -- result.wire
user_aclr => pipelined_adder1user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder1enavcc_output_wire -- ena.wire
);
pipelined_adder1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder1user_aclrgnd_output_wire -- output.wire
);
pipelined_adder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder1enavcc_output_wire -- output.wire
);
case_statement : component alt_dspbuilder_case_statement_GN4KF5KLTA
generic map (
number_outputs => 5,
hasDefault => 1,
pipeline => 0,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast28_output_wire, -- input.wire
r0 => open, -- r0.wire
r1 => case_statement_r1_wire, -- r1.wire
r2 => case_statement_r2_wire, -- r2.wire
r3 => case_statement_r3_wire, -- r3.wire
r4 => open -- r4.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r2_wire, -- input.wire
output => data_en -- output.wire
);
if_statement6 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement6_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => pipelined_adder1_result_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
single_pulse : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse_result_wire, -- result.wire
sclr => single_pulsesclrgnd_output_wire, -- sclr.wire
ena => single_pulseenavcc_output_wire -- ena.wire
);
single_pulsesclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulsesclrgnd_output_wire -- output.wire
);
single_pulseenavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulseenavcc_output_wire -- output.wire
);
constant15 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant15_output_wire -- output.wire
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r3_wire, -- input.wire
output => check_en -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
cast26 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast26_output_wire -- output.wire
);
cast27 : component alt_dspbuilder_cast_GN5P6ORZXA
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast27_output_wire -- output.wire
);
cast28 : component alt_dspbuilder_cast_GNLWRZWTQF
generic map (
round => 0,
saturate => 0
)
port map (
input => state_machine_editor_state_wire, -- input.wire
output => cast28_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
check_en : out std_logic; -- check_en.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ready : in std_logic := '0'; -- ready.wire
data_en : out std_logic; -- data_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_en : out std_logic -- ctrl_en.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component StateMachineEditor is
port (
clock : in std_logic := 'X'; -- clk
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_end : in std_logic := 'X'; -- wire
ready : in std_logic := 'X'; -- wire
reset : in std_logic := 'X'; -- wire
state : out std_logic_vector(2 downto 0) -- wire
);
end component StateMachineEditor;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GN4KF5KLTA is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic; -- wire
r2 : out std_logic; -- wire
r3 : out std_logic; -- wire
r4 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GN4KF5KLTA;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GN5P6ORZXA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN5P6ORZXA;
component alt_dspbuilder_cast_GNLWRZWTQF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLWRZWTQF;
signal pipelined_adder1user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder1user_aclrGND:output -> Pipelined_Adder1:user_aclr
signal pipelined_adder1enavcc_output_wire : std_logic; -- Pipelined_Adder1enaVCC:output -> Pipelined_Adder1:ena
signal single_pulsesclrgnd_output_wire : std_logic; -- Single_PulsesclrGND:output -> Single_Pulse:sclr
signal single_pulseenavcc_output_wire : std_logic; -- Single_PulseenaVCC:output -> Single_Pulse:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [If_Statement6:a, cast27:input]
signal constant15_output_wire : std_logic_vector(23 downto 0); -- Constant15:output -> Pipelined_Adder1:datab
signal pipelined_adder1_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder1:result -> If_Statement6:b
signal single_pulse_result_wire : std_logic; -- Single_Pulse:result -> State_Machine_Editor:reset
signal ready_0_output_wire : std_logic; -- ready_0:output -> State_Machine_Editor:ready
signal if_statement6_true_wire : std_logic; -- If_Statement6:true -> State_Machine_Editor:data_end
signal case_statement_r1_wire : std_logic; -- Case_Statement:r1 -> ctrl_en_0:input
signal case_statement_r2_wire : std_logic; -- Case_Statement:r2 -> data_en_0:input
signal case_statement_r3_wire : std_logic; -- Case_Statement:r3 -> check_en_0:input
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast26:input
signal cast26_output_wire : std_logic_vector(23 downto 0); -- cast26:output -> Pipelined_Adder1:dataa
signal cast27_output_wire : std_logic_vector(23 downto 0); -- cast27:output -> State_Machine_Editor:counter
signal state_machine_editor_state_wire : std_logic_vector(2 downto 0); -- State_Machine_Editor:state -> cast28:input
signal cast28_output_wire : std_logic_vector(2 downto 0); -- cast28:output -> Case_Statement:input
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Case_Statement:clock, Pipelined_Adder1:clock, Single_Pulse:clock, State_Machine_Editor:clock]
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Case_Statement:aclr, Pipelined_Adder1:aclr, Single_Pulse:aclr]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r1_wire, -- input.wire
output => ctrl_en -- output.wire
);
state_machine_editor : component StateMachineEditor
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse_result_wire, -- reset.wire
ready => ready_0_output_wire, -- ready.wire
counter => cast27_output_wire, -- counter.wire
data_end => if_statement6_true_wire, -- data_end.wire
state => state_machine_editor_state_wire -- state.wire
);
pipelined_adder1 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast26_output_wire, -- dataa.wire
datab => constant15_output_wire, -- datab.wire
result => pipelined_adder1_result_wire, -- result.wire
user_aclr => pipelined_adder1user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder1enavcc_output_wire -- ena.wire
);
pipelined_adder1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder1user_aclrgnd_output_wire -- output.wire
);
pipelined_adder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder1enavcc_output_wire -- output.wire
);
case_statement : component alt_dspbuilder_case_statement_GN4KF5KLTA
generic map (
number_outputs => 5,
hasDefault => 1,
pipeline => 0,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast28_output_wire, -- input.wire
r0 => open, -- r0.wire
r1 => case_statement_r1_wire, -- r1.wire
r2 => case_statement_r2_wire, -- r2.wire
r3 => case_statement_r3_wire, -- r3.wire
r4 => open -- r4.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r2_wire, -- input.wire
output => data_en -- output.wire
);
if_statement6 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement6_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => pipelined_adder1_result_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
single_pulse : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse_result_wire, -- result.wire
sclr => single_pulsesclrgnd_output_wire, -- sclr.wire
ena => single_pulseenavcc_output_wire -- ena.wire
);
single_pulsesclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulsesclrgnd_output_wire -- output.wire
);
single_pulseenavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulseenavcc_output_wire -- output.wire
);
constant15 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant15_output_wire -- output.wire
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r3_wire, -- input.wire
output => check_en -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
cast26 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast26_output_wire -- output.wire
);
cast27 : component alt_dspbuilder_cast_GN5P6ORZXA
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast27_output_wire -- output.wire
);
cast28 : component alt_dspbuilder_cast_GNLWRZWTQF
generic map (
round => 0,
saturate => 0
)
port map (
input => state_machine_editor_state_wire, -- input.wire
output => cast28_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:31:18 11/23/2016
-- Design Name:
-- Module Name: Z:/Documents/COP/COPproject/project/controltester.vhd
-- Project Name: project
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY controltester IS
END controltester;
ARCHITECTURE behavior OF controltester IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control
PORT(
Inst : IN std_logic_vector(15 downto 0);
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
Imm : IN std_logic_vector(15 downto 0);
T : IN std_logic;
OP : OUT std_logic_vector(3 downto 0);
Wctrl : OUT std_logic_vector(3 downto 0);
PCctrl : OUT std_logic_vector(1 downto 0);
RFctrl : OUT std_logic_vector(2 downto 0);
Immctrl : OUT std_logic_vector(3 downto 0);
Rs : OUT std_logic_vector(3 downto 0);
Rt : OUT std_logic_vector(3 downto 0);
Rd : OUT std_logic_vector(3 downto 0);
ctrl1 : OUT std_logic;
ctrl2 : OUT std_logic;
AccMEM : OUT std_logic;
memWE : OUT std_logic;
regWE : OUT std_logic;
DataIN : OUT std_logic_vector(15 downto 0);
newT : OUT std_logic
);
END COMPONENT;
--Inputs
signal Inst : std_logic_vector(15 downto 0) := (others => '0');
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
signal Imm : std_logic_vector(15 downto 0) := (others => '0');
signal T : std_logic := '0';
--Outputs
signal OP : std_logic_vector(3 downto 0);
signal Wctrl : std_logic_vector(3 downto 0);
signal PCctrl : std_logic_vector(1 downto 0);
signal RFctrl : std_logic_vector(2 downto 0);
signal Immctrl : std_logic_vector(3 downto 0);
signal Rs : std_logic_vector(3 downto 0);
signal Rt : std_logic_vector(3 downto 0);
signal Rd : std_logic_vector(3 downto 0);
signal ctrl1 : std_logic;
signal ctrl2 : std_logic;
signal AccMEM : std_logic;
signal memWE : std_logic;
signal regWE : std_logic;
signal DataIN : std_logic_vector(15 downto 0);
signal newT : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control PORT MAP (
Inst => Inst,
A => A,
B => B,
Imm => Imm,
T => T,
OP => OP,
Wctrl => Wctrl,
PCctrl => PCctrl,
RFctrl => RFctrl,
Immctrl => Immctrl,
Rs => Rs,
Rt => Rt,
Rd => Rd,
ctrl1 => ctrl1,
ctrl2 => ctrl2,
AccMEM => AccMEM,
memWE => memWE,
regWE => regWE,
DataIN => DataIN,
newT => newT
);
END;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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`protect end_protected
|
`protect begin_protected
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`protect end_protected
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`protect end_protected
|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect end_protected
|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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`protect end_protected
|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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`protect end_protected
|
`protect begin_protected
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b8aZHDlGNKPn9JHE8vO10WyixEfUqg6jh+I4dT5bQ/6/8iY+j28VrEcJhi5xNLLn0CNSFF0Zlu7l
GYYVFsn22OGF0ckn+xSYlp/fUX0CPYnfq/V1qUMWDUqlC7ElFF7DlR+eoS1tNB6uW3KvegVNUkCd
tFR2txgIhzoJ/ii0LBYEpGF210/a0UITlvNTQrRLbIAvke2BSLaKdOT5yKXMdLb6zFIbYK3JOjbr
jXHa+xLbgL3g5o1OMGMnHI5rhqeJcH/wXtXcoN+c/gNI4fYgQu72ngzgTYPeDwInApfTQ09aQ939
JpxAbJpYcBk1OUqSzhIyPMsyKijKNsyVJVLRkOnd21no8VQ2JwvJYEUPP1VjOqKeoJxSrAF5MJ9g
qSbmkiRQSc5SU7lkI9+ImXgCmi/e1YZeLz8JJA60feHUOqnpoATVKiZuW/Vtp5zHP+vw3A3VvefP
fmOK0e+0GorLviE0lrHVzZnA+czWyuhSJ5p4wONFNgmD+qd/mOQMHxXQO/hvNW+d8EH0nfHg0lnt
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OGohheBDKQpwVrlhmdHB1zJGENUnjsajs8Ya9OcCd848Lg8yiDKOMMYOiThI81cRnx2xV4KHB3qD
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k3KDypbNdyGrp7YeVFSs59TiQ+uU8zUoeSnh9TJDv8L/iEqDxbqJfV0IaI0728wihOijm8CPqi5b
eRublhhQXYp75ypTFtFd6GlDuRfoTpbN6iCGEFi1fVg6Y/31ieyDCNshWtCx5aFHLpXg2QXQmkCC
HdKkIbzQai4yVKXTy8Y5N5mNjAx2cclLbs363EZRZSopzfxah+OPlGztYmYePVCzLaw3FusZP+Iz
FeVUX9SYCMgWtowfSTxEWRnK37bm3alk3mygCSYW/X9uyPsgUIYDpz3NUs2pWN6m6L0e0UjZFafI
V+Fh/F4XRA3rscQqZKaOnxPNZfig93nchFCMUmV4l/1evB6KNf7jqFPdyS00G8192cZCHxXx0mcX
lBYkFo+eBvF8pZvR10IyDH08O/8F3irfkUjGQBHNHsVD4C0jXv694YD5HVyEXRBhJnBTWCTSytOw
V/1cDsI=
`protect end_protected
|
-------------------------------------------------------------------------------
-- Title : UART Receiver (Odd-Parity)
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
--
-- Data is received with LSB (Least Significat Bit) first.
-- The receiver uses 5x oversampling, therefore clk_rx_en needs to be five times
-- higher than the desired bitrate.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_rx is
port (
rxd_p : in std_logic;
disable_p : in std_logic;
data_p : out std_logic_vector(7 downto 0);
we_p : out std_logic;
error_p : out std_logic;
full_p : in std_logic;
clk_rx_en : in std_logic;
clk : in std_logic);
end uart_rx;
-------------------------------------------------------------------------------
architecture behavioural of uart_rx is
type receive_states is (IDLE, START, DATA);
type uart_rx_type is record
state : receive_states;
bitcount : integer range 0 to 10;
samplecount : integer range 0 to 4;
samples : std_logic_vector(4 downto 0);
parity : std_logic;
-- is set when the reception has been
-- disabled during the last byte
disabled : std_logic;
shift_reg : std_logic_vector(9 downto 0);
-- Output FIFO
fifo_data : std_logic_vector(7 downto 0);
fifo_we : std_logic;
fifo_error : std_logic; -- parity of framing error
end record;
signal r, rin : uart_rx_type := (
state => IDLE,
bitcount => 0,
samplecount => 0,
samples => (others => '0'),
parity => '0',
disabled => '0',
shift_reg => (others => '0'),
fifo_data => (others => '0'),
fifo_we => '0',
fifo_error => '0');
signal voter_output : std_logic := '0';
-- Five bit majority voter.
--
-- Returns '1' if more than two bits in the input vector are set, and
-- '0' otherwise.
function voter(samples : in std_logic_vector(4 downto 0)) return std_logic is
variable cnt : integer range 0 to 5 := 0;
begin
for c in 1 to 3 loop
if samples(c) = '1' then
cnt := cnt + 1;
end if;
end loop;
if cnt >= 2 then
return '1';
else
return '0';
end if;
end voter;
begin
-- Connections between ports and signals
data_p <= r.fifo_data;
we_p <= r.fifo_we;
error_p <= r.fifo_error;
-- Sequential part of finite state machine (FSM)
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-- Combinatorial part of FSM
comb_proc : process(clk_rx_en, disable_p, r, rxd_p, voter_output)
variable v : uart_rx_type;
begin
v := r;
v.fifo_we := '0';
v.fifo_error := '0';
v.fifo_data := (others => '0');
-- RXD line is constantly sampled.
if clk_rx_en = '1' then
v.samples := r.samples(3 downto 0) & rxd_p;
voter_output <= voter(r.samples);
end if;
if disable_p = '1' then
v.disabled := '1';
end if;
case r.state is
when IDLE =>
if clk_rx_en = '1' then
if rxd_p = '0' then
v.state := START;
v.samplecount := 0;
end if;
end if;
when START =>
if clk_rx_en = '1' then
if r.samplecount = 3 then
if voter_output = '0' then
v.state := DATA;
v.samplecount := 0;
v.bitcount := 0;
v.parity := '0';
else
v.state := IDLE;
end if;
else
v.samplecount := r.samplecount + 1;
end if;
end if;
when DATA =>
if clk_rx_en = '1' then
if r.samplecount = 4 then
v.samplecount := 0;
v.shift_reg := voter_output & r.shift_reg(9 downto 1);
v.parity := r.parity xor voter_output;
if r.bitcount = 9 then
v.state := IDLE;
v.disabled := '0';
-- Only forward the received data if the receiver
-- wasn't disabled during the receiption.
if r.disabled = '0' then
v.fifo_we := '1';
end if;
-- Check for framing errors (= no stop bit) or parity errors
if v.shift_reg(9) = '0' or v.parity = '1' then
v.fifo_error := '1';
end if;
v.fifo_data := v.shift_reg(7 downto 0);
else
v.bitcount := r.bitcount + 1;
end if;
else
v.samplecount := r.samplecount + 1;
end if;
end if;
end case;
rin <= v;
end process comb_proc;
-- Component instantiations
end behavioural;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: MemoryBlock
-- Date:2011-11-14
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.utilPkg.all;
use work.helperComponents.all;
entity MemoryBlock is
port (
reset : in std_logic;
clk : in std_logic;
-------------------------------------------------
p1_addr : in std_logic_vector(10 downto 0);
p1_data_in : in std_logic_vector(7 downto 0);
p1_strobe : in std_logic;
p1_data_out : out std_logic_vector(7 downto 0);
-------------------------------------------------
p2_addr : in std_logic_vector(10 downto 0);
p2_data_in : in std_logic_vector(7 downto 0);
p2_strobe : in std_logic;
p2_data_out : out std_logic_vector(7 downto 0)
);
end MemoryBlock;
architecture arch of MemoryBlock is
type mem is array(0 to 31) of std_logic_vector(7 downto 0);
signal memory : mem;
signal addrP1, addrP2 : integer range 0 to 31;
begin
addrP1 <= conv_integer(UNSIGNED(p1_addr));
addrP2 <= conv_integer(UNSIGNED(p2_addr));
process(reset, clk) begin
if reset = '1' then
elsif rising_edge(clk) then
p1_data_out <= memory(addrP1);
p2_data_out <= memory(addrP2);
if p1_strobe = '1' then
memory(addrP1) <= p1_data_in;
end if;
if p2_strobe = '1' then
memory(addrP2) <= p2_data_in;
end if;
end if;
end process;
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
port(
op_1_in: in std_logic_vector(31 downto 0) := (others => '0');
op_2_in: in std_logic_vector(31 downto 0) := (others => '0');
result_out: out std_logic_vector(63 downto 0) := (others => '0')
);
end multiplier;
architecture multiplier_arq of multiplier is
begin
process(op_1_in, op_2_in)
variable op_1_h : unsigned(15 downto 0) := (others => '0');
variable op_1_l : unsigned(15 downto 0) := (others => '0');
variable op_2_h : unsigned(15 downto 0) := (others => '0');
variable op_2_l : unsigned(15 downto 0) := (others => '0');
variable result_ll : unsigned(63 downto 0) := (others => '0');
variable result_lh : unsigned(63 downto 0) := (others => '0');
variable result_hl : unsigned(63 downto 0) := (others => '0');
variable result_hh : unsigned(63 downto 0) := (others => '0');
begin
op_1_l := unsigned(op_1_in(15 downto 0));
op_1_h := unsigned(op_1_in(31 downto 16));
op_2_l := unsigned(op_2_in(15 downto 0));
op_2_h := unsigned(op_2_in(31 downto 16));
--report "OP1L: " & integer'image(to_integer(op_1_l));
--report "OP1H: " & integer'image(to_integer(op_1_h));
--report "OP2L: " & integer'image(to_integer(op_2_l));
--report "OP2H: " & integer'image(to_integer(op_2_h));
result_ll := "00000000000000000000000000000000" & (op_1_l * op_2_l);
result_lh := shift_left("00000000000000000000000000000000" & (op_1_l * op_2_h), 16);
result_hl := shift_left("00000000000000000000000000000000" & (op_1_h * op_2_l), 16);
result_hh := shift_left("00000000000000000000000000000000" & (op_1_h * op_2_h), 32);
--report "LL: " & integer'image(to_integer(result_ll));
--report "LH: " & integer'image(to_integer(result_lh));
--report "HL: " & integer'image(to_integer(result_hl));
--report "HH: " & integer'image(to_integer(result_hh));
result_out <= std_logic_vector(result_ll + result_lh + result_hl + result_hh);
end process;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
entity dff01 is
port (q : out std_logic_vector (3 downto 0);
d : std_logic_vector (3 downto 0);
en : std_logic;
rst : std_logic;
clk : std_logic);
end dff01;
architecture behav of dff01 is
signal t : std_logic_vector (7 downto 0);
signal a : std_logic_vector (3 downto 0);
begin
a <= d xor b"0101";
process (clk) is
begin
if rst = '1' then
q <= x"0";
elsif rising_edge (clk) then
if en = '1' then
q <= d;
t (7 downto 4) <= a;
end if;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff01 is
port (q : out std_logic_vector (3 downto 0);
d : std_logic_vector (3 downto 0);
en : std_logic;
rst : std_logic;
clk : std_logic);
end dff01;
architecture behav of dff01 is
signal t : std_logic_vector (7 downto 0);
signal a : std_logic_vector (3 downto 0);
begin
a <= d xor b"0101";
process (clk) is
begin
if rst = '1' then
q <= x"0";
elsif rising_edge (clk) then
if en = '1' then
q <= d;
t (7 downto 4) <= a;
end if;
end if;
end process;
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
ENTITY colision IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10);
PORT (snake_body : IN int_array;
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
reset : IN STD_LOGIC;
gmap : OUT STD_LOGIC_VECTOR(0 to N*M-1);
lost : OUT STD_LOGIC);
END colision;
ARCHITECTURE Behavior OF colision IS
BEGIN
PROCESS(snake_body(0),reset)
variable i : integer range 0 to 255;
variable index : integer range 0 to M*N;
variable outl : STD_LOGIC;
BEGIN
IF (reset = '1') THEN
outl := '0';
ELSE
i := 1;
outl := '0';
WHILE (i < N*M and not(snake_body(i) = -1) and outl = '0') LOOP
IF (snake_body(0) = snake_body(i)) THEN
outl := '1';
END IF;
i := i + 1;
END LOOP;
IF (outl = '0') THEN
IF (dir = "00") THEN
IF (snake_body(0) > M*N-1) THEN
outl := '1';
END IF;
ELSIF (dir = "01") THEN
IF (snake_body(0) mod M = 0 and snake_body(1) mod M = (M-1)) THEN
outl := '1';
END IF;
ELSIF (dir = "10") THEN
IF (snake_body(0) mod M = (M-1) and snake_body(1) mod M = 0) THEN
outl := '1';
END IF;
ELSE
IF (snake_body(0) < 0) THEN
outl := '1';
END IF;
END IF;
END IF;
END IF;
IF (outl = '0') THEN
i := 0;
WHILE (i < M*N and not(snake_body(i) = -1)) LOOP
index := snake_body(i);
gmap(index) <= '1';
i := i + 1;
END LOOP;
END IF;
lost <= outl;
END PROCESS;
END Behavior;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 25 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clkout : out std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
iosn : out std_ulogic;
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal lclk, lclkout : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal dsubre : std_ulogic;
component clkgen_ep1c20board is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
freq : integer := 50000);
port (
clkin : in std_logic;
clkout : out std_logic;
clk : out std_logic;
clkn : out std_logic;
sdclk : out std_logic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; --cgi.pllref <= lclk; --pllref; -- clk; --'0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkout_pad : outpad generic map (tech => padtech, slew => 1) port map (clkout, lclkout);
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clkgen0 : clkgen_ep1c20board
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN, CFG_CLK_NOFB)
port map (lclk, lclkout, clkm, open, sdclkl, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo2.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo2.sdcsn(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
----
----
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP1C20 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_registers is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF" );
port (
clock : in std_logic;
clock_en : in std_logic;
ready : in std_logic;
reset : in std_logic;
-- package pins
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
so_n : in std_logic := '1';
-- data from "data_oper"
alu_data : in std_logic_vector(7 downto 0);
mem_data : in std_logic_vector(7 downto 0);
new_flags : in std_logic_vector(7 downto 0);
-- from implied handler
set_a : in std_logic;
set_x : in std_logic;
set_y : in std_logic;
set_s : in std_logic;
set_data : in std_logic_vector(7 downto 0);
-- interrupt pins
interrupt : in std_logic;
vect_addr : in std_logic_vector(3 downto 0);
-- from processor state machine and decoder
sync : in std_logic; -- latch ireg
rwn : in std_logic;
latch_dreg : in std_logic;
irq_done : in std_logic;
vectoring : in std_logic;
reg_update : in std_logic;
copy_d2p : in std_logic;
a_mux : in t_amux;
dout_mux : in t_dout_mux;
pc_oper : in t_pc_oper;
s_oper : in t_sp_oper;
adl_oper : in t_adl_oper;
adh_oper : in t_adh_oper;
-- outputs to processor state machine
i_reg : out std_logic_vector(7 downto 0) := X"00";
index_carry : out std_logic;
pc_carry : out std_logic;
branch_taken : out boolean;
-- register outputs
addr_out : out std_logic_vector(15 downto 0) := X"FFFF";
d_reg : out std_logic_vector(7 downto 0) := X"00";
a_reg : out std_logic_vector(7 downto 0) := X"00";
x_reg : out std_logic_vector(7 downto 0) := X"00";
y_reg : out std_logic_vector(7 downto 0) := X"00";
s_reg : out std_logic_vector(7 downto 0) := X"00";
p_reg : out std_logic_vector(7 downto 0) := X"00";
pc_out : out std_logic_vector(15 downto 0) );
end proc_registers;
architecture gideon of proc_registers is
-- signal a_reg : std_logic_vector(7 downto 0);
signal dreg : std_logic_vector(7 downto 0) := X"00";
signal a_reg_i : std_logic_vector(7 downto 0) := X"00";
signal x_reg_i : std_logic_vector(7 downto 0) := X"00";
signal y_reg_i : std_logic_vector(7 downto 0) := X"00";
signal selected_idx : std_logic_vector(7 downto 0) := X"00";
signal i_reg_i : std_logic_vector(7 downto 0) := X"00";
signal s_reg_i : std_logic_vector(7 downto 0) := X"00";
signal p_reg_i : std_logic_vector(7 downto 0) := X"30";
signal pcl, pch : std_logic_vector(7 downto 0) := X"FF";
signal adl, adh : std_logic_vector(7 downto 0) := X"00";
signal pc_carry_i : std_logic;
signal pc_carry_d : std_logic;
signal branch_flag : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal vect : std_logic_vector(3 downto 0) := "1111";
signal dreg_zero : std_logic;
alias C_flag : std_logic is p_reg_i(0);
alias Z_flag : std_logic is p_reg_i(1);
alias I_flag : std_logic is p_reg_i(2);
alias D_flag : std_logic is p_reg_i(3);
alias B_flag : std_logic is p_reg_i(4);
alias V_flag : std_logic is p_reg_i(6);
alias N_flag : std_logic is p_reg_i(7);
signal p_reg_push : std_logic_vector(7 downto 0);
begin
dreg_zero <= '1' when dreg=X"00" else '0';
p_reg_push <= p_reg_i(7 downto 6) & '1' & not vectoring & p_reg_i(3 downto 0);
process(clock)
variable pcl_t : std_logic_vector(8 downto 0);
variable adl_t : std_logic_vector(8 downto 0);
begin
if rising_edge(clock) then
-- if reg_update='1' and I_flag /= new_flags(2) then
-- p_reg_i(2) <= '0'; -- set/clear I outside ready
-- end if;
if clock_en='1' then
if ready='1' or rwn='0' then
-- Data Register
if latch_dreg='1' then
dreg <= data_in;
end if;
-- Flags Register
if copy_d2p = '1' then
p_reg_i <= dreg;
elsif reg_update='1' then
p_reg_i <= new_flags;
end if;
if irq_done='1' then
I_flag <= '1';
end if;
if so_n='0' then -- only 1 bit is affected, so no syncronization needed
V_flag <= '1';
end if;
-- Instruction Register
if sync='1' then
i_reg_i <= data_in;
end if;
-- Logic for the Program Counter
pc_carry_i <= '0';
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= dreg;
pch <= data_in;
when from_alu =>
pcl_t := ('0' & pcl) + (dreg(7) & dreg); -- sign extended 1 bit
pcl <= pcl_t(7 downto 0);
pc_carry_i <= pcl_t(8);
pc_carry_d <= dreg(7);
when others => -- keep (and fix)
if pc_carry_i='1' then
if pc_carry_d='1' then
pch <= pch - 1;
else
pch <= pch + 1;
end if;
end if;
end case;
-- Logic for the Address register
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl_t := ('0' & dreg) + ('0' & selected_idx);
adl <= adl_t(7 downto 0);
index_carry <= adl_t(8);
when load_bus =>
adl <= data_in;
when copy_dreg =>
adl <= dreg;
when others =>
null;
end case;
case adh_oper is
when increment =>
adh <= adh + 1;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= data_in;
when others =>
null;
end case;
-- Logic for ALU register
if reg_update='1' then
if set_a='1' then
a_reg_i <= set_data;
elsif store_a_from_alu(i_reg_i) then
a_reg_i <= alu_data;
end if;
end if;
-- Logic for Index registers
if reg_update='1' then
if set_x='1' then
x_reg_i <= set_data;
elsif load_x(i_reg_i) then
x_reg_i <= alu_data; --dreg; -- alu is okay, too (they should be the same)
end if;
end if;
if reg_update='1' then
if set_y='1' then
y_reg_i <= set_data;
elsif load_y(i_reg_i) then
y_reg_i <= dreg;
end if;
end if;
-- Logic for the Stack Pointer
if set_s='1' then
s_reg_i <= set_data;
else
case s_oper is
when increment =>
s_reg_i <= s_reg_i + 1;
when decrement =>
s_reg_i <= s_reg_i - 1;
when others =>
null;
end case;
end if;
end if;
end if;
-- Reset
if reset='1' then
p_reg_i <= X"34"; -- I=1
index_carry <= '0';
end if;
end if;
end process;
with i_reg_i(7 downto 6) select branch_flag <=
N_flag when "00",
V_flag when "01",
C_flag when "10",
Z_flag when "11",
'0' when others;
branch_taken <= (branch_flag xor not i_reg_i(5))='1';
with a_mux select addr_out <=
vector_page & vect_addr when 0,
adh & adl when 1,
X"01" & s_reg_i when 2,
pch & pcl when 3;
with i_reg_i(1 downto 0) select reg_out <=
y_reg_i when "00",
a_reg_i when "01",
x_reg_i when "10",
a_reg_i and x_reg_i when others;
with dout_mux select data_out <=
dreg when reg_d,
a_reg_i when reg_accu,
reg_out when reg_axy,
p_reg_push when reg_flags,
pcl when reg_pcl,
pch when reg_pch,
mem_data when shift_res,
X"FF" when others;
selected_idx <= y_reg_i when select_index_y(i_reg_i) else x_reg_i;
pc_carry <= pc_carry_i;
s_reg <= s_reg_i;
p_reg <= p_reg_i;
i_reg <= i_reg_i;
a_reg <= a_reg_i;
x_reg <= x_reg_i;
y_reg <= y_reg_i;
d_reg <= dreg;
pc_out <= pch & pcl;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_registers is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF" );
port (
clock : in std_logic;
clock_en : in std_logic;
ready : in std_logic;
reset : in std_logic;
-- package pins
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
so_n : in std_logic := '1';
-- data from "data_oper"
alu_data : in std_logic_vector(7 downto 0);
mem_data : in std_logic_vector(7 downto 0);
new_flags : in std_logic_vector(7 downto 0);
-- from implied handler
set_a : in std_logic;
set_x : in std_logic;
set_y : in std_logic;
set_s : in std_logic;
set_data : in std_logic_vector(7 downto 0);
-- interrupt pins
interrupt : in std_logic;
vect_addr : in std_logic_vector(3 downto 0);
-- from processor state machine and decoder
sync : in std_logic; -- latch ireg
rwn : in std_logic;
latch_dreg : in std_logic;
irq_done : in std_logic;
vectoring : in std_logic;
reg_update : in std_logic;
copy_d2p : in std_logic;
a_mux : in t_amux;
dout_mux : in t_dout_mux;
pc_oper : in t_pc_oper;
s_oper : in t_sp_oper;
adl_oper : in t_adl_oper;
adh_oper : in t_adh_oper;
-- outputs to processor state machine
i_reg : out std_logic_vector(7 downto 0) := X"00";
index_carry : out std_logic;
pc_carry : out std_logic;
branch_taken : out boolean;
-- register outputs
addr_out : out std_logic_vector(15 downto 0) := X"FFFF";
d_reg : out std_logic_vector(7 downto 0) := X"00";
a_reg : out std_logic_vector(7 downto 0) := X"00";
x_reg : out std_logic_vector(7 downto 0) := X"00";
y_reg : out std_logic_vector(7 downto 0) := X"00";
s_reg : out std_logic_vector(7 downto 0) := X"00";
p_reg : out std_logic_vector(7 downto 0) := X"00";
pc_out : out std_logic_vector(15 downto 0) );
end proc_registers;
architecture gideon of proc_registers is
-- signal a_reg : std_logic_vector(7 downto 0);
signal dreg : std_logic_vector(7 downto 0) := X"00";
signal a_reg_i : std_logic_vector(7 downto 0) := X"00";
signal x_reg_i : std_logic_vector(7 downto 0) := X"00";
signal y_reg_i : std_logic_vector(7 downto 0) := X"00";
signal selected_idx : std_logic_vector(7 downto 0) := X"00";
signal i_reg_i : std_logic_vector(7 downto 0) := X"00";
signal s_reg_i : std_logic_vector(7 downto 0) := X"00";
signal p_reg_i : std_logic_vector(7 downto 0) := X"30";
signal pcl, pch : std_logic_vector(7 downto 0) := X"FF";
signal adl, adh : std_logic_vector(7 downto 0) := X"00";
signal pc_carry_i : std_logic;
signal pc_carry_d : std_logic;
signal branch_flag : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal vect : std_logic_vector(3 downto 0) := "1111";
signal dreg_zero : std_logic;
alias C_flag : std_logic is p_reg_i(0);
alias Z_flag : std_logic is p_reg_i(1);
alias I_flag : std_logic is p_reg_i(2);
alias D_flag : std_logic is p_reg_i(3);
alias B_flag : std_logic is p_reg_i(4);
alias V_flag : std_logic is p_reg_i(6);
alias N_flag : std_logic is p_reg_i(7);
signal p_reg_push : std_logic_vector(7 downto 0);
begin
dreg_zero <= '1' when dreg=X"00" else '0';
p_reg_push <= p_reg_i(7 downto 6) & '1' & not vectoring & p_reg_i(3 downto 0);
process(clock)
variable pcl_t : std_logic_vector(8 downto 0);
variable adl_t : std_logic_vector(8 downto 0);
begin
if rising_edge(clock) then
-- if reg_update='1' and I_flag /= new_flags(2) then
-- p_reg_i(2) <= '0'; -- set/clear I outside ready
-- end if;
if clock_en='1' then
if ready='1' or rwn='0' then
-- Data Register
if latch_dreg='1' then
dreg <= data_in;
end if;
-- Flags Register
if copy_d2p = '1' then
p_reg_i <= dreg;
elsif reg_update='1' then
p_reg_i <= new_flags;
end if;
if irq_done='1' then
I_flag <= '1';
end if;
if so_n='0' then -- only 1 bit is affected, so no syncronization needed
V_flag <= '1';
end if;
-- Instruction Register
if sync='1' then
i_reg_i <= data_in;
end if;
-- Logic for the Program Counter
pc_carry_i <= '0';
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= dreg;
pch <= data_in;
when from_alu =>
pcl_t := ('0' & pcl) + (dreg(7) & dreg); -- sign extended 1 bit
pcl <= pcl_t(7 downto 0);
pc_carry_i <= pcl_t(8);
pc_carry_d <= dreg(7);
when others => -- keep (and fix)
if pc_carry_i='1' then
if pc_carry_d='1' then
pch <= pch - 1;
else
pch <= pch + 1;
end if;
end if;
end case;
-- Logic for the Address register
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl_t := ('0' & dreg) + ('0' & selected_idx);
adl <= adl_t(7 downto 0);
index_carry <= adl_t(8);
when load_bus =>
adl <= data_in;
when copy_dreg =>
adl <= dreg;
when others =>
null;
end case;
case adh_oper is
when increment =>
adh <= adh + 1;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= data_in;
when others =>
null;
end case;
-- Logic for ALU register
if reg_update='1' then
if set_a='1' then
a_reg_i <= set_data;
elsif store_a_from_alu(i_reg_i) then
a_reg_i <= alu_data;
end if;
end if;
-- Logic for Index registers
if reg_update='1' then
if set_x='1' then
x_reg_i <= set_data;
elsif load_x(i_reg_i) then
x_reg_i <= alu_data; --dreg; -- alu is okay, too (they should be the same)
end if;
end if;
if reg_update='1' then
if set_y='1' then
y_reg_i <= set_data;
elsif load_y(i_reg_i) then
y_reg_i <= dreg;
end if;
end if;
-- Logic for the Stack Pointer
if set_s='1' then
s_reg_i <= set_data;
else
case s_oper is
when increment =>
s_reg_i <= s_reg_i + 1;
when decrement =>
s_reg_i <= s_reg_i - 1;
when others =>
null;
end case;
end if;
end if;
end if;
-- Reset
if reset='1' then
p_reg_i <= X"34"; -- I=1
index_carry <= '0';
end if;
end if;
end process;
with i_reg_i(7 downto 6) select branch_flag <=
N_flag when "00",
V_flag when "01",
C_flag when "10",
Z_flag when "11",
'0' when others;
branch_taken <= (branch_flag xor not i_reg_i(5))='1';
with a_mux select addr_out <=
vector_page & vect_addr when 0,
adh & adl when 1,
X"01" & s_reg_i when 2,
pch & pcl when 3;
with i_reg_i(1 downto 0) select reg_out <=
y_reg_i when "00",
a_reg_i when "01",
x_reg_i when "10",
a_reg_i and x_reg_i when others;
with dout_mux select data_out <=
dreg when reg_d,
a_reg_i when reg_accu,
reg_out when reg_axy,
p_reg_push when reg_flags,
pcl when reg_pcl,
pch when reg_pch,
mem_data when shift_res,
X"FF" when others;
selected_idx <= y_reg_i when select_index_y(i_reg_i) else x_reg_i;
pc_carry <= pc_carry_i;
s_reg <= s_reg_i;
p_reg <= p_reg_i;
i_reg <= i_reg_i;
a_reg <= a_reg_i;
x_reg <= x_reg_i;
y_reg <= y_reg_i;
d_reg <= dreg;
pc_out <= pch & pcl;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_Pofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end kn_kalman_Pofkplusone;
architecture struct of kn_kalman_Pofkplusone is
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_mult port map (clock => clock, dataa => Pdashofkplusone, datab => Kofkplusone, result => Z);
M2 : kn_kalman_sub port map (clock => clock, dataa => Pdashofkplusone, datab => Z, result => Pofkplusone);
end struct;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity gates is
port( A,B,C,D : in std_logic;
O : out std_logic);
end gates;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity gates is
port( A,B,C,D : in std_logic;
O : out std_logic);
end gates;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.counter_f;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v2_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.counter_f;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v2_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.counter_f;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v2_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.counter_f;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v2_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.counter_f;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v2_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.counter_f;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v2_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.counter_f;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v2_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_hot;
architecture behaviour of ex3_hot is
constant s1: std_logic_vector(9 downto 0) := "1000000000";
constant s2: std_logic_vector(9 downto 0) := "0100000000";
constant s4: std_logic_vector(9 downto 0) := "0010000000";
constant s3: std_logic_vector(9 downto 0) := "0001000000";
constant s0: std_logic_vector(9 downto 0) := "0000100000";
constant s7: std_logic_vector(9 downto 0) := "0000010000";
constant s8: std_logic_vector(9 downto 0) := "0000001000";
constant s6: std_logic_vector(9 downto 0) := "0000000100";
constant s5: std_logic_vector(9 downto 0) := "0000000010";
constant s9: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "01";
elsif std_match(input, "10") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "10";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "--";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----------"; output <= "--";
end case;
end process;
end behaviour;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Pointer is
Generic (initX : STD_LOGIC_VECTOR (9 downto 0);
initY : STD_LOGIC_VECTOR (8 downto 0));
Port ( MoveUp : in STD_LOGIC;
MoveDown : in STD_LOGIC;
MoveLeft : in STD_LOGIC;
MoveRight : in STD_LOGIC;
Move : in STD_LOGIC;
Clk : in STD_LOGIC;
Here : out STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0);
Y : out STD_LOGIC_VECTOR (8 downto 0);
syncX : in STD_LOGIC_VECTOR (9 downto 0);
syncY : in STD_LOGIC_VECTOR (8 downto 0));
end Pointer;
architecture Behavioral of Pointer is
signal rX : STD_LOGIC_VECTOR (9 downto 0) := initX;
signal rY : STD_LOGIC_VECTOR (8 downto 0) := initY;
begin
Here <= '1' when syncX(9 downto 3)=rX(9 downto 3) and
syncY(8 downto 3)=rY(8 downto 3) else '0';
X <= rX;
Y <= rY;
process (Clk) begin
if (rising_edge(Clk)) then
if (Move = '1') then
if (MoveLeft = '1' and MoveRight = '0') then
if not (rX = "0000000000") then
rX <= rX - 1;
end if;
elsif (MoveLeft = '0' and MoveRight = '1') then
if not (rX = "1001111111") then
rX <= rX + 1;
end if;
end if;
if (MoveUp = '1' and MoveDown = '0') then
if not (rY = "000000000") then
rY <= rY - 1;
end if;
elsif (MoveUp = '0' and MoveDown = '1') then
if not (rY = "111011111") then
rY <= rY + 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Composite Function Block for FlexPRET
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FlexPRET is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--special emitted internal variables for child I/O
UART_TX : out unsigned(7 downto 0); --type was BYTE
UART_TX_READY : in std_logic; --type was BOOL
UART_TX_SEND : out std_logic; --type was BOOL
--for done signal
done : out std_logic
);
end entity;
architecture rtl of FlexPRET is
-- Signals needed for event connections
signal IO_InjectorArmFinishMovement_conn : std_logic;
signal IO_EmergencyStopChanged_conn : std_logic;
signal IO_CanisterPressureChanged_conn : std_logic;
signal IO_FillContentsAvailableChanged_conn : std_logic;
signal IO_LasersChanged_conn : std_logic;
signal IO_DoorOverride_conn : std_logic;
signal IO_VacuumTimerElapsed_conn : std_logic;
signal CCounter_CanisterCountChanged_conn : std_logic;
signal Door_DoorReleaseCanister_conn : std_logic;
signal Conveyor_ConveyorChanged_conn : std_logic;
signal Conveyor_ConveyorStoppedForInject_conn : std_logic;
signal RejectArm_GoRejectArm_conn : std_logic;
signal Pumps_PumpFinished_conn : std_logic;
signal Pumps_RejectCanister_conn : std_logic;
signal Pumps_InjectorControlsChanged_conn : std_logic;
signal Pumps_FillContentsChanged_conn : std_logic;
signal Pumps_StartVacuumTimer_conn : std_logic;
signal Motor_StartPump_conn : std_logic;
signal Motor_InjectDone_conn : std_logic;
signal Motor_InjectorPositionChanged_conn : std_logic;
-- Signals needed for data connections
signal IO_EmergencyStop_conn : std_logic; --type was BOOL
signal IO_CanisterPressure_conn : unsigned(7 downto 0); --type was BYTE
signal IO_FillContentsAvailable_conn : unsigned(7 downto 0); --type was BYTE
signal IO_DoorSiteLaser_conn : std_logic; --type was BOOL
signal IO_InjectSiteLaser_conn : std_logic; --type was BOOL
signal IO_RejectSiteLaser_conn : std_logic; --type was BOOL
signal IO_RejectBinLaser_conn : std_logic; --type was BOOL
signal IO_AcceptBinLaser_conn : std_logic; --type was BOOL
signal CCounter_CanisterCount_conn : unsigned(7 downto 0); --type was BYTE
signal Conveyor_ConveyorSpeed_conn : unsigned(7 downto 0); --type was BYTE
signal Pumps_InjectorContentsValveOpen_conn : std_logic; --type was BOOL
signal Pumps_InjectorVacuumRun_conn : std_logic; --type was BOOL
signal Pumps_InjectorPressurePumpRun_conn : std_logic; --type was BOOL
signal Pumps_FillContents_conn : std_logic; --type was BOOL
signal Motor_InjectorPosition_conn : unsigned(7 downto 0); --type was BYTE
-- Signals needed for the done signals
signal IO_done : std_logic;
signal CCounter_done : std_logic;
signal Door_done : std_logic;
signal Conveyor_done : std_logic;
signal RejectArm_done : std_logic;
signal Pumps_done : std_logic;
signal Motor_done : std_logic;
begin
--top level I/O to signals
-- child I/O to signals
IO : entity work.IOManager port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
InjectorArmFinishMovement => IO_InjectorArmFinishMovement_conn,
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
CanisterPressureChanged => IO_CanisterPressureChanged_conn,
FillContentsAvailableChanged => IO_FillContentsAvailableChanged_conn,
LasersChanged => IO_LasersChanged_conn,
DoorOverride => IO_DoorOverride_conn,
VacuumTimerElapsed => IO_VacuumTimerElapsed_conn,
--event inputs
CanisterCountChanged => CCounter_CanisterCountChanged_conn,
DoorReleaseCanister => Door_DoorReleaseCanister_conn,
ConveyorChanged => Conveyor_ConveyorChanged_conn,
GoRejectArm => RejectArm_GoRejectArm_conn,
InjectorControlsChanged => Pumps_InjectorControlsChanged_conn,
FillContentsChanged => Pumps_FillContentsChanged_conn,
StartVacuumTimer => Pumps_StartVacuumTimer_conn,
InjectDone => Motor_InjectDone_conn,
InjectorPositionChanged => Motor_InjectorPositionChanged_conn,
--data outputs
EmergencyStop_O => IO_EmergencyStop_conn,
CanisterPressure_O => IO_CanisterPressure_conn,
FillContentsAvailable_O => IO_FillContentsAvailable_conn,
DoorSiteLaser_O => IO_DoorSiteLaser_conn,
InjectSiteLaser_O => IO_InjectSiteLaser_conn,
RejectSiteLaser_O => IO_RejectSiteLaser_conn,
RejectBinLaser_O => IO_RejectBinLaser_conn,
AcceptBinLaser_O => IO_AcceptBinLaser_conn,
--data inputs
CanisterCount_I => CCounter_CanisterCount_conn,
ConveyorSpeed_I => Conveyor_ConveyorSpeed_conn,
InjectorContentsValveOpen_I => Pumps_InjectorContentsValveOpen_conn,
InjectorVacuumRun_I => Pumps_InjectorVacuumRun_conn,
InjectorPressurePumpRun_I => Pumps_InjectorPressurePumpRun_conn,
FillContents_I => Pumps_FillContents_conn,
InjectorPosition_I => Motor_InjectorPosition_conn,
--specials
UART_TX => UART_TX, --output
UART_TX_READY => UART_TX_READY, --input
UART_TX_SEND => UART_TX_SEND, --output
done => IO_done
);
CCounter : entity work.CanisterCounter port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
CanisterCountChanged => CCounter_CanisterCountChanged_conn,
--event inputs
LasersChanged => IO_LasersChanged_conn,
--data outputs
CanisterCount_O => CCounter_CanisterCount_conn,
--data inputs
DoorSiteLaser_I => IO_DoorSiteLaser_conn,
RejectBinLaser_I => IO_RejectBinLaser_conn,
AcceptBinLaser_I => IO_AcceptBinLaser_conn,
done => CCounter_done
);
Door : entity work.DoorController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
DoorReleaseCanister => Door_DoorReleaseCanister_conn,
--event inputs
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
ReleaseDoorOverride => IO_DoorOverride_conn,
BottlingDone => Motor_InjectDone_conn,
--data outputs
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
done => Door_done
);
Conveyor : entity work.ConveyorController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
ConveyorChanged => Conveyor_ConveyorChanged_conn,
ConveyorStoppedForInject => Conveyor_ConveyorStoppedForInject_conn,
--event inputs
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
LasersChanged => IO_LasersChanged_conn,
InjectDone => Motor_InjectDone_conn,
--data outputs
ConveyorSpeed_O => Conveyor_ConveyorSpeed_conn,
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
InjectSiteLaser_I => IO_InjectSiteLaser_conn,
done => Conveyor_done
);
RejectArm : entity work.RejectArmController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
GoRejectArm => RejectArm_GoRejectArm_conn,
--event inputs
LasersChanged => IO_LasersChanged_conn,
RejectCanister => Pumps_RejectCanister_conn,
--data outputs
--data inputs
RejectSiteLaser_I => IO_RejectSiteLaser_conn,
done => RejectArm_done
);
Pumps : entity work.InjectorPumpsController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
PumpFinished => Pumps_PumpFinished_conn,
RejectCanister => Pumps_RejectCanister_conn,
InjectorControlsChanged => Pumps_InjectorControlsChanged_conn,
FillContentsChanged => Pumps_FillContentsChanged_conn,
StartVacuumTimer => Pumps_StartVacuumTimer_conn,
--event inputs
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
CanisterPressureChanged => IO_CanisterPressureChanged_conn,
FillContentsAvailableChanged => IO_FillContentsAvailableChanged_conn,
VacuumTimerElapsed => IO_VacuumTimerElapsed_conn,
StartPump => Motor_StartPump_conn,
--data outputs
InjectorContentsValveOpen_O => Pumps_InjectorContentsValveOpen_conn,
InjectorVacuumRun_O => Pumps_InjectorVacuumRun_conn,
InjectorPressurePumpRun_O => Pumps_InjectorPressurePumpRun_conn,
FillContents_O => Pumps_FillContents_conn,
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
CanisterPressure_I => IO_CanisterPressure_conn,
FillContentsAvailable_I => IO_FillContentsAvailable_conn,
done => Pumps_done
);
Motor : entity work.InjectorMotorController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
StartPump => Motor_StartPump_conn,
InjectDone => Motor_InjectDone_conn,
InjectorPositionChanged => Motor_InjectorPositionChanged_conn,
--event inputs
InjectorArmFinishedMovement => IO_InjectorArmFinishMovement_conn,
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
ConveyorStoppedForInject => Conveyor_ConveyorStoppedForInject_conn,
PumpFinished => Pumps_PumpFinished_conn,
--data outputs
InjectorPosition_O => Motor_InjectorPosition_conn,
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
done => Motor_done
);
-- done signal
done <= IO_done and CCounter_done and Door_done and Conveyor_done and RejectArm_done and Pumps_done and Motor_done;
end rtl;
|
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Composite Function Block for FlexPRET
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FlexPRET is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--special emitted internal variables for child I/O
UART_TX : out unsigned(7 downto 0); --type was BYTE
UART_TX_READY : in std_logic; --type was BOOL
UART_TX_SEND : out std_logic; --type was BOOL
--for done signal
done : out std_logic
);
end entity;
architecture rtl of FlexPRET is
-- Signals needed for event connections
signal IO_InjectorArmFinishMovement_conn : std_logic;
signal IO_EmergencyStopChanged_conn : std_logic;
signal IO_CanisterPressureChanged_conn : std_logic;
signal IO_FillContentsAvailableChanged_conn : std_logic;
signal IO_LasersChanged_conn : std_logic;
signal IO_DoorOverride_conn : std_logic;
signal IO_VacuumTimerElapsed_conn : std_logic;
signal CCounter_CanisterCountChanged_conn : std_logic;
signal Door_DoorReleaseCanister_conn : std_logic;
signal Conveyor_ConveyorChanged_conn : std_logic;
signal Conveyor_ConveyorStoppedForInject_conn : std_logic;
signal RejectArm_GoRejectArm_conn : std_logic;
signal Pumps_PumpFinished_conn : std_logic;
signal Pumps_RejectCanister_conn : std_logic;
signal Pumps_InjectorControlsChanged_conn : std_logic;
signal Pumps_FillContentsChanged_conn : std_logic;
signal Pumps_StartVacuumTimer_conn : std_logic;
signal Motor_StartPump_conn : std_logic;
signal Motor_InjectDone_conn : std_logic;
signal Motor_InjectorPositionChanged_conn : std_logic;
-- Signals needed for data connections
signal IO_EmergencyStop_conn : std_logic; --type was BOOL
signal IO_CanisterPressure_conn : unsigned(7 downto 0); --type was BYTE
signal IO_FillContentsAvailable_conn : unsigned(7 downto 0); --type was BYTE
signal IO_DoorSiteLaser_conn : std_logic; --type was BOOL
signal IO_InjectSiteLaser_conn : std_logic; --type was BOOL
signal IO_RejectSiteLaser_conn : std_logic; --type was BOOL
signal IO_RejectBinLaser_conn : std_logic; --type was BOOL
signal IO_AcceptBinLaser_conn : std_logic; --type was BOOL
signal CCounter_CanisterCount_conn : unsigned(7 downto 0); --type was BYTE
signal Conveyor_ConveyorSpeed_conn : unsigned(7 downto 0); --type was BYTE
signal Pumps_InjectorContentsValveOpen_conn : std_logic; --type was BOOL
signal Pumps_InjectorVacuumRun_conn : std_logic; --type was BOOL
signal Pumps_InjectorPressurePumpRun_conn : std_logic; --type was BOOL
signal Pumps_FillContents_conn : std_logic; --type was BOOL
signal Motor_InjectorPosition_conn : unsigned(7 downto 0); --type was BYTE
-- Signals needed for the done signals
signal IO_done : std_logic;
signal CCounter_done : std_logic;
signal Door_done : std_logic;
signal Conveyor_done : std_logic;
signal RejectArm_done : std_logic;
signal Pumps_done : std_logic;
signal Motor_done : std_logic;
begin
--top level I/O to signals
-- child I/O to signals
IO : entity work.IOManager port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
InjectorArmFinishMovement => IO_InjectorArmFinishMovement_conn,
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
CanisterPressureChanged => IO_CanisterPressureChanged_conn,
FillContentsAvailableChanged => IO_FillContentsAvailableChanged_conn,
LasersChanged => IO_LasersChanged_conn,
DoorOverride => IO_DoorOverride_conn,
VacuumTimerElapsed => IO_VacuumTimerElapsed_conn,
--event inputs
CanisterCountChanged => CCounter_CanisterCountChanged_conn,
DoorReleaseCanister => Door_DoorReleaseCanister_conn,
ConveyorChanged => Conveyor_ConveyorChanged_conn,
GoRejectArm => RejectArm_GoRejectArm_conn,
InjectorControlsChanged => Pumps_InjectorControlsChanged_conn,
FillContentsChanged => Pumps_FillContentsChanged_conn,
StartVacuumTimer => Pumps_StartVacuumTimer_conn,
InjectDone => Motor_InjectDone_conn,
InjectorPositionChanged => Motor_InjectorPositionChanged_conn,
--data outputs
EmergencyStop_O => IO_EmergencyStop_conn,
CanisterPressure_O => IO_CanisterPressure_conn,
FillContentsAvailable_O => IO_FillContentsAvailable_conn,
DoorSiteLaser_O => IO_DoorSiteLaser_conn,
InjectSiteLaser_O => IO_InjectSiteLaser_conn,
RejectSiteLaser_O => IO_RejectSiteLaser_conn,
RejectBinLaser_O => IO_RejectBinLaser_conn,
AcceptBinLaser_O => IO_AcceptBinLaser_conn,
--data inputs
CanisterCount_I => CCounter_CanisterCount_conn,
ConveyorSpeed_I => Conveyor_ConveyorSpeed_conn,
InjectorContentsValveOpen_I => Pumps_InjectorContentsValveOpen_conn,
InjectorVacuumRun_I => Pumps_InjectorVacuumRun_conn,
InjectorPressurePumpRun_I => Pumps_InjectorPressurePumpRun_conn,
FillContents_I => Pumps_FillContents_conn,
InjectorPosition_I => Motor_InjectorPosition_conn,
--specials
UART_TX => UART_TX, --output
UART_TX_READY => UART_TX_READY, --input
UART_TX_SEND => UART_TX_SEND, --output
done => IO_done
);
CCounter : entity work.CanisterCounter port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
CanisterCountChanged => CCounter_CanisterCountChanged_conn,
--event inputs
LasersChanged => IO_LasersChanged_conn,
--data outputs
CanisterCount_O => CCounter_CanisterCount_conn,
--data inputs
DoorSiteLaser_I => IO_DoorSiteLaser_conn,
RejectBinLaser_I => IO_RejectBinLaser_conn,
AcceptBinLaser_I => IO_AcceptBinLaser_conn,
done => CCounter_done
);
Door : entity work.DoorController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
DoorReleaseCanister => Door_DoorReleaseCanister_conn,
--event inputs
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
ReleaseDoorOverride => IO_DoorOverride_conn,
BottlingDone => Motor_InjectDone_conn,
--data outputs
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
done => Door_done
);
Conveyor : entity work.ConveyorController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
ConveyorChanged => Conveyor_ConveyorChanged_conn,
ConveyorStoppedForInject => Conveyor_ConveyorStoppedForInject_conn,
--event inputs
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
LasersChanged => IO_LasersChanged_conn,
InjectDone => Motor_InjectDone_conn,
--data outputs
ConveyorSpeed_O => Conveyor_ConveyorSpeed_conn,
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
InjectSiteLaser_I => IO_InjectSiteLaser_conn,
done => Conveyor_done
);
RejectArm : entity work.RejectArmController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
GoRejectArm => RejectArm_GoRejectArm_conn,
--event inputs
LasersChanged => IO_LasersChanged_conn,
RejectCanister => Pumps_RejectCanister_conn,
--data outputs
--data inputs
RejectSiteLaser_I => IO_RejectSiteLaser_conn,
done => RejectArm_done
);
Pumps : entity work.InjectorPumpsController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
PumpFinished => Pumps_PumpFinished_conn,
RejectCanister => Pumps_RejectCanister_conn,
InjectorControlsChanged => Pumps_InjectorControlsChanged_conn,
FillContentsChanged => Pumps_FillContentsChanged_conn,
StartVacuumTimer => Pumps_StartVacuumTimer_conn,
--event inputs
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
CanisterPressureChanged => IO_CanisterPressureChanged_conn,
FillContentsAvailableChanged => IO_FillContentsAvailableChanged_conn,
VacuumTimerElapsed => IO_VacuumTimerElapsed_conn,
StartPump => Motor_StartPump_conn,
--data outputs
InjectorContentsValveOpen_O => Pumps_InjectorContentsValveOpen_conn,
InjectorVacuumRun_O => Pumps_InjectorVacuumRun_conn,
InjectorPressurePumpRun_O => Pumps_InjectorPressurePumpRun_conn,
FillContents_O => Pumps_FillContents_conn,
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
CanisterPressure_I => IO_CanisterPressure_conn,
FillContentsAvailable_I => IO_FillContentsAvailable_conn,
done => Pumps_done
);
Motor : entity work.InjectorMotorController port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
StartPump => Motor_StartPump_conn,
InjectDone => Motor_InjectDone_conn,
InjectorPositionChanged => Motor_InjectorPositionChanged_conn,
--event inputs
InjectorArmFinishedMovement => IO_InjectorArmFinishMovement_conn,
EmergencyStopChanged => IO_EmergencyStopChanged_conn,
ConveyorStoppedForInject => Conveyor_ConveyorStoppedForInject_conn,
PumpFinished => Pumps_PumpFinished_conn,
--data outputs
InjectorPosition_O => Motor_InjectorPosition_conn,
--data inputs
EmergencyStop_I => IO_EmergencyStop_conn,
done => Motor_done
);
-- done signal
done <= IO_done and CCounter_done and Door_done and Conveyor_done and RejectArm_done and Pumps_done and Motor_done;
end rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_stub.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_reset_0_0 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_reset_0_0;
architecture stub of system_vga_sync_reset_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync_reset,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1090.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01090ent IS
END c06s05b00x00p02n01i01090ent;
ARCHITECTURE c06s05b00x00p02n01i01090arch OF c06s05b00x00p02n01i01090ent IS
BEGIN
TESTING: PROCESS
type I1 is range 0 to 11;
type ABASE is array (I1 range <>) of BOOLEAN;
subtype A1 is ABASE(I1);
variable V1 : A1 ; -- := A1'(others=>TRUE);
BEGIN
V1(5 to 6) := V1(1 to 10)(2 to 9)(3 to 8)(4 to 7)(5 to 6);
assert NOT(V1(5 to 6)=(false,false))
report "***PASSED TEST: c06s05b00x00p02n01i01090"
severity NOTE;
assert (V1(5 to 6)=(false,false))
report "***FAILED TEST: c06s05b00x00p02n01i01090 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01090arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1090.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01090ent IS
END c06s05b00x00p02n01i01090ent;
ARCHITECTURE c06s05b00x00p02n01i01090arch OF c06s05b00x00p02n01i01090ent IS
BEGIN
TESTING: PROCESS
type I1 is range 0 to 11;
type ABASE is array (I1 range <>) of BOOLEAN;
subtype A1 is ABASE(I1);
variable V1 : A1 ; -- := A1'(others=>TRUE);
BEGIN
V1(5 to 6) := V1(1 to 10)(2 to 9)(3 to 8)(4 to 7)(5 to 6);
assert NOT(V1(5 to 6)=(false,false))
report "***PASSED TEST: c06s05b00x00p02n01i01090"
severity NOTE;
assert (V1(5 to 6)=(false,false))
report "***FAILED TEST: c06s05b00x00p02n01i01090 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01090arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1090.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01090ent IS
END c06s05b00x00p02n01i01090ent;
ARCHITECTURE c06s05b00x00p02n01i01090arch OF c06s05b00x00p02n01i01090ent IS
BEGIN
TESTING: PROCESS
type I1 is range 0 to 11;
type ABASE is array (I1 range <>) of BOOLEAN;
subtype A1 is ABASE(I1);
variable V1 : A1 ; -- := A1'(others=>TRUE);
BEGIN
V1(5 to 6) := V1(1 to 10)(2 to 9)(3 to 8)(4 to 7)(5 to 6);
assert NOT(V1(5 to 6)=(false,false))
report "***PASSED TEST: c06s05b00x00p02n01i01090"
severity NOTE;
assert (V1(5 to 6)=(false,false))
report "***FAILED TEST: c06s05b00x00p02n01i01090 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01090arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_3_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_3_max_dsp_32_arch OF convolve_kernel_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_3_max_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_3_max_dsp_32_arch;
|
-- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- $File: //acds/rel/13.1/ip/sopc/components/verification/lib/altera_avalon_components_pkg.vhd $
-- $Revision: #1 $
-- $Date: 2013/08/11 $
-- $Author: swbranch $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.all;
package altera_avalon_components_pkg is
-----------------------------------------------------------------------------
-- Avalon Interrupt Source
-----------------------------------------------------------------------------
type irq_source_method_id is (IRQ_SRC_SET_IRQ,
IRQ_SRC_CLEAR_IRQ);
function conv_std_logic (
method : irq_source_method_id
) return std_logic;
component altera_avalon_interrupt_source_api_wrapper
generic (AV_DATA_W : integer := 32;
AV_ADDR_W : integer := 8
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic;
api_call_data : in std_logic;
api_call_valid : in std_logic;
api_return_method : out std_logic;
api_return_data : out std_logic;
api_return_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
avs_waitrequest : out std_logic;
avs_readdatavalid : out std_logic;
avs_readdata : out std_logic_vector(AV_DATA_W-1 downto 0);
avs_write : in std_logic;
avs_read : in std_logic;
avs_address : in std_logic_vector(AV_ADDR_W-1 downto 0);
avs_writedata : in std_logic_vector(AV_DATA_W-1 downto 0);
irq : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Avalon Interrupt Sink
-----------------------------------------------------------------------------
type irq_sink_method_id is (IRQ_SINK_GET_IRQ,
IRQ_SINK_CLEAR_IRQ);
function conv_std_logic (
method : irq_sink_method_id
) return std_logic;
component altera_avalon_interrupt_sink_api_wrapper
generic (AV_DATA_W : integer := 32;
AV_ADDR_W : integer := 8;
AV_IRQ_W : integer := 1
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic;
api_call_data : in std_logic;
api_call_valid : in std_logic;
api_return_method : out std_logic;
api_return_data : out std_logic_vector(AV_IRQ_W-1 downto 0);
api_return_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
avm_waitrequest : in std_logic;
avm_readdatavalid : in std_logic;
avm_readdata : in std_logic_vector(AV_DATA_W-1 downto 0);
avm_write : out std_logic;
avm_read : out std_logic;
avm_address : out std_logic_vector(AV_ADDR_W-1 downto 0);
avm_writedata : out std_logic_vector(AV_DATA_W-1 downto 0);
irq : in std_logic_vector(AV_IRQ_W-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- Avalon Streaming Source API Wrapper
-----------------------------------------------------------------------------
type st_source_signal_index is (
ST_SRC_SIGNAL_READY,
ST_SRC_SIGNAL_NOT_READY,
ST_SRC_SIGNAL_TRANS_COMPLETE,
ST_SRC_SIGNAL_DRIVING_TRANS,
ST_SRC_SIGNAL_RESERVED_4,
ST_SRC_SIGNAL_RESERVED_5,
ST_SRC_SIGNAL_RESERVED_6,
ST_SRC_SIGNAL_RESERVED_7);
type st_source_method_id is (
ST_SRC_INIT,
ST_SRC_SET_RESP_TIMEOUT,
ST_SRC_PUSH_TRANS,
ST_SRC_GET_TRANS_QUEUE_SIZE,
ST_SRC_GET_RESP_QUEUE_SIZE,
ST_SRC_SET_TRANS_DATA,
ST_SRC_SET_TRANS_CHANNEL,
ST_SRC_SET_TRANS_IDLES,
ST_SRC_SET_TRANS_SOP,
ST_SRC_SET_TRANS_EOP,
ST_SRC_SET_TRANS_ERROR,
ST_SRC_SET_TRANS_EMPTY,
ST_SRC_POP_RESP,
ST_SRC_GET_RESP_LATENCY,
ST_SRC_GET_SRC_READY,
ST_SRC_GET_SRC_TRANS_COMPLETE);
function conv_integer (
sig : st_source_signal_index
) return integer;
function conv_std_logic (
method : st_source_method_id
) return std_logic_vector;
component altera_avalon_st_source_api_wrapper
generic (
ST_SYMBOL_W : integer := 8;
ST_NUMSYMBOLS : integer := 4;
ST_CHANNEL_W : integer := 0;
ST_ERROR_W : integer := 0;
ST_EMPTY_W : integer := 0;
ST_READY_LATENCY: integer := 0;
ST_MAX_CHANNELS : integer := 1;
USE_PACKET : integer := 1;
USE_CHANNEL : integer := 1;
USE_ERROR : integer := 1;
USE_READY : integer := 1;
USE_VALID : integer := 1;
USE_EMPTY : integer := 1;
API_CALL_DATA_W : integer := 32;
API_RETURN_DATA_W : integer := 32
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(API_CALL_DATA_W-1 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(31 downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
src_data : out std_logic_vector(
ST_SYMBOL_W*ST_NUMSYMBOLS-1 downto 0);
src_channel : out std_logic_vector(ST_CHANNEL_W-1 downto 0);
src_valid : out std_logic;
src_startofpacket : out std_logic;
src_endofpacket : out std_logic;
src_error : out std_logic_vector(ST_ERROR_W-1 downto 0);
src_empty : out std_logic_vector(ST_EMPTY_W-1 downto 0);
src_ready : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Avalon Streaming Sink
-----------------------------------------------------------------------------
type st_sink_signal_index is (
ST_SINK_SIGNAL_TRANS_RECEIVED,
ST_SINK_SIGNAL_READY_ASSERT,
ST_SINK_SIGNAL_READY_DEASSERT,
ST_SINK_SIGNAL_RESERVED_3,
ST_SINK_SIGNAL_RESERVED_4,
ST_SINK_SIGNAL_RESERVED_5,
ST_SINK_SIGNAL_RESERVED_6,
ST_SINK_SIGNAL_RESERVED_7
);
type st_sink_method_id is (
ST_SINK_INIT,
ST_SINK_SET_READY,
ST_SINK_POP_TRANS,
ST_SINK_GET_TRANS_IDLES,
ST_SINK_GET_TRANS_DATA,
ST_SINK_GET_TRANS_CHANNEL,
ST_SINK_GET_TRANS_SOP,
ST_SINK_GET_TRANS_EOP,
ST_SINK_GET_TRANS_ERROR,
ST_SINK_GET_TRANS_EMPTY,
ST_SINK_GET_TRANS_QUEUE_SIZE
);
function conv_integer (
sig : st_sink_signal_index
) return integer;
function conv_std_logic (
method : st_sink_method_id
) return std_logic_vector;
component altera_avalon_st_sink_api_wrapper
generic (
ST_SYMBOL_W : integer := 8;
ST_NUMSYMBOLS : integer := 4;
ST_CHANNEL_W : integer := 0;
ST_ERROR_W : integer := 0;
ST_EMPTY_W : integer := 0;
ST_READY_LATENCY: integer := 0;
ST_MAX_CHANNELS : integer := 1;
USE_PACKET : integer := 1;
USE_CHANNEL : integer := 1;
USE_ERROR : integer := 1;
USE_READY : integer := 1;
USE_VALID : integer := 1;
USE_EMPTY : integer := 1;
API_CALL_DATA_W : integer := 32;
API_RETURN_DATA_W : integer := 32
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(31 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(API_RETURN_DATA_W downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
sink_data : in std_logic_vector(
ST_SYMBOL_W*ST_NUMSYMBOLS-1 downto 0);
sink_channel : in std_logic_vector(ST_CHANNEL_W-1 downto 0);
sink_valid : in std_logic;
sink_startofpacket : in std_logic;
sink_endofpacket : in std_logic;
sink_error : in std_logic_vector(ST_ERROR_W-1 downto 0);
sink_empty : in std_logic_vector(ST_EMPTY_W-1 downto 0);
sink_ready : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Avalon MM Master
-----------------------------------------------------------------------------
type mm_mstr_signal_index is (
MM_MSTR_SIGNAL_FATAL_ERROR ,
MM_MSTR_SIGNAL_RESPONSE_COMPLETE ,
MM_MSTR_SIGNAL_COMMAND_ISSUED ,
MM_MSTR_SIGNAL_ALL_TRANS_COMPLETE ,
MM_MSTR_SIGNAL_RESERVED_4 ,
MM_MSTR_SIGNAL_RESERVED_5 ,
MM_MSTR_SIGNAL_RESERVED_6 ,
MM_MSTR_SIGNAL_RESERVED_7
);
type mm_mstr_method_id is (
MM_MSTR_INIT ,
MM_MSTR_SET_RESP_TIMEOUT ,
MM_MSTR_SET_CMD_TIMEOUT ,
MM_MSTR_ALL_TRANS_COMPLETE ,
MM_MSTR_GET_CMD_ISSUE_QUEUE_SIZE ,
MM_MSTR_GET_CMD_PEND_QUEUE_SIZE ,
MM_MSTR_GET_RESP_QUEUE_SIZE ,
MM_MSTR_PUSH_CMD ,
MM_MSTR_POP_RESP ,
MM_MSTR_SET_CMD_DATA ,
MM_MSTR_SET_CMD_ADDRESS ,
MM_MSTR_SET_CMD_BYTE_ENABLE ,
MM_MSTR_SET_CMD_BURST_COUNT ,
MM_MSTR_SET_CMD_IDLE ,
MM_MSTR_SET_CMD_REQUEST ,
MM_MSTR_SET_CMD_RESERVED_1 ,
MM_MSTR_GET_RESP_REQUEST ,
MM_MSTR_GET_RESP_DATA ,
MM_MSTR_GET_RESP_ADDRESS ,
MM_MSTR_GET_RESP_BYTE_ENABLE ,
MM_MSTR_GET_RESP_BURST_SIZE ,
MM_MSTR_GET_RESP_LATENCY ,
MM_MSTR_GET_RESP_WAIT_TIME ,
MM_MSTR_SET_CMD_INIT_LATENCY ,
MM_MSTR_SET_CMD_BURST_SIZE
);
function conv_integer (
sig : mm_mstr_signal_index
) return integer;
function conv_std_logic (
method : mm_mstr_method_id
) return std_logic_vector;
component altera_avalon_mm_master_bfm_api_wrapper
generic (
AV_ADDRESS_W : integer := 32;
AV_SYMBOL_W : integer := 8;
AV_NUMSYMBOLS : integer := 4;
AV_BURSTCOUNT_W : integer := 3;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_ADDRESS : integer := 1;
USE_BYTE_ENABLE : integer := 1;
USE_BURSTCOUNT : integer := 1;
USE_READ_DATA : integer := 1;
USE_READ_DATA_VALID : integer := 1;
USE_WRITE_DATA : integer := 1;
USE_BEGIN_TRANSFER : integer := 1;
USE_BEGIN_BURST_TRANSFER : integer := 1;
USE_WAIT_REQUEST : integer := 1;
AV_FIX_READ_LATENCY : integer := 0;
AV_MAX_PENDING_READS : integer := 1;
AV_BURST_LINEWRAP : integer := 0;
AV_BURST_BNDR_ONLY : integer := 0;
API_CALL_DATA_W : integer := 64;
API_RETURN_DATA_W : integer := 64
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(API_CALL_DATA_W-1 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(API_RETURN_DATA_W-1 downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
avm_clk : in std_logic;
avm_reset : in std_logic;
avm_waitrequest : in std_logic;
avm_readdatavalid : in std_logic;
avm_readdata : in std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0);
avm_write : out std_logic;
avm_read : out std_logic;
avm_address : out std_logic_vector(AV_ADDRESS_W-1 downto 0);
avm_byteenable : out std_logic_vector(AV_NUMSYMBOLS-1 downto 0);
avm_burstcount : out std_logic_vector(AV_BURSTCOUNT_W-1 downto 0);
avm_beginbursttransfer : out std_logic;
avm_begintransfer : out std_logic;
avm_writedata : out std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- Avalon MM Slave
-----------------------------------------------------------------------------
type mm_slv_signal_index is (
MM_SLV_SIGNAL_FATAL_ERROR ,
MM_SLV_SIGNAL_ERROR_EXCEED_MAX_PENDING_READS,
MM_SLV_SIGNAL_COMMAND_RECEIVED ,
MM_SLV_SIGNAL_RESP_ISSUED ,
MM_SLV_SIGNAL_RESERVED_4 ,
MM_SLV_SIGNAL_RESERVED_5 ,
MM_SLV_SIGNAL_RESERVED_6 ,
MM_SLV_SIGNAL_RESERVED_7
);
type mm_slv_method_id is (
MM_SLV_INIT ,
MM_SLV_SET_RESP_TIMEOUT ,
MM_SLV_GET_CMD_QUEUE_SIZE ,
MM_SLV_GET_RESP_QUEUE_SIZE ,
MM_SLV_PUSH_RESP ,
MM_SLV_POP_CMD ,
MM_SLV_SET_RESP_DATA ,
MM_SLV_SET_RESP_BURST_SIZE ,
MM_SLV_SET_RESP_LATENCY ,
MM_SLV_SET_INTERFACE_WAIT_TIME ,
MM_SLV_GET_CMD_REQUEST ,
MM_SLV_GET_CMD_DATA ,
MM_SLV_GET_CMD_ADDRESS ,
MM_SLV_GET_CMD_BYTE_ENABLE ,
MM_SLV_GET_CMD_BURST_COUNT ,
MM_SLV_GET_CMD_BURST_CYCLE
);
function conv_integer (
sig : mm_slv_signal_index
) return integer;
function conv_std_logic (
method : mm_slv_method_id
) return std_logic_vector;
component altera_avalon_mm_slave_bfm_api_wrapper
generic (
AV_ADDRESS_W : integer := 32;
AV_SYMBOL_W : integer := 8;
AV_NUMSYMBOLS : integer := 4;
AV_BURSTCOUNT_W : integer := 3;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_ADDRESS : integer := 1;
USE_BYTE_ENABLE : integer := 1;
USE_BURSTCOUNT : integer := 1;
USE_READ_DATA : integer := 1;
USE_READ_DATA_VALID : integer := 1;
USE_WRITE_DATA : integer := 1;
USE_BEGIN_TRANSFER : integer := 1;
USE_BEGIN_BURST_TRANSFER : integer := 1;
USE_WAIT_REQUEST : integer := 1;
AV_FIX_READ_LATENCY : integer := 0;
AV_MAX_PENDING_READS : integer := 1;
AV_BURST_LINEWRAP : integer := 0;
AV_BURST_BNDR_ONLY : integer := 0;
AV_READ_WAIT_TIME : integer := 0;
AV_WRITE_WAIT_TIME : integer := 0;
API_CALL_DATA_W : integer := 64;
API_RETURN_DATA_W : integer := 64
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(API_CALL_DATA_W-1 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(API_RETURN_DATA_W-1 downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
avs_clk : in std_logic;
avs_reset : in std_logic;
avs_waitrequest : out std_logic;
avs_readdatavalid : out std_logic;
avs_readdata : out std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0);
avs_write : in std_logic;
avs_read : in std_logic;
avs_address : in std_logic_vector(AV_ADDRESS_W-1 downto 0);
avs_byteenable : in std_logic_vector(AV_NUMSYMBOLS-1 downto 0);
avs_burstcount : in std_logic_vector(AV_BURSTCOUNT_W-1 downto 0);
avs_beginbursttransfer : in std_logic;
avs_begintransfer : in std_logic;
avs_writedata : in std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0)
);
end component;
end altera_avalon_components_pkg;
package body altera_avalon_components_pkg is
-----------------------------------------------------------------------------
-- Avalon Interrupt Source
-----------------------------------------------------------------------------
function conv_std_logic (
method : irq_source_method_id
) return std_logic is
begin
case method is
when IRQ_SRC_SET_IRQ => return '0';
when IRQ_SRC_CLEAR_IRQ => return '1';
when others => return 'X';
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon Interrupt Sink
-----------------------------------------------------------------------------
function conv_std_logic (
method : irq_sink_method_id
) return std_logic is
begin
case method is
when IRQ_SINK_GET_IRQ => return '0';
when IRQ_SINK_CLEAR_IRQ => return '1';
when others => return 'X';
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon ST Source
-----------------------------------------------------------------------------
function conv_integer (
sig : st_source_signal_index
) return integer is
begin
case sig is
when ST_SRC_SIGNAL_READY => return 0;
when ST_SRC_SIGNAL_NOT_READY => return 1;
when ST_SRC_SIGNAL_TRANS_COMPLETE => return 2;
when ST_SRC_SIGNAL_DRIVING_TRANS => return 3;
when ST_SRC_SIGNAL_RESERVED_4 => return 4;
when ST_SRC_SIGNAL_RESERVED_5 => return 5;
when ST_SRC_SIGNAL_RESERVED_6 => return 6;
when ST_SRC_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : st_source_method_id
) return std_logic_vector is
begin
case method is
when ST_SRC_INIT => return X"00";
when ST_SRC_SET_RESP_TIMEOUT => return X"01";
when ST_SRC_PUSH_TRANS => return X"02";
when ST_SRC_GET_TRANS_QUEUE_SIZE => return X"03";
when ST_SRC_GET_RESP_QUEUE_SIZE => return X"04";
when ST_SRC_SET_TRANS_DATA => return X"05";
when ST_SRC_SET_TRANS_CHANNEL => return X"06";
when ST_SRC_SET_TRANS_IDLES => return X"07";
when ST_SRC_SET_TRANS_SOP => return X"08";
when ST_SRC_SET_TRANS_EOP => return X"09";
when ST_SRC_SET_TRANS_ERROR => return X"0A";
when ST_SRC_SET_TRANS_EMPTY => return X"0B";
when ST_SRC_POP_RESP => return X"0C";
when ST_SRC_GET_RESP_LATENCY => return X"0D";
when ST_SRC_GET_SRC_READY => return X"0E";
when ST_SRC_GET_SRC_TRANS_COMPLETE => return X"0F";
when others => return X"FF";
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon ST Sink
-----------------------------------------------------------------------------
function conv_integer (
sig : st_sink_signal_index
) return integer is
begin
case sig is
when ST_SINK_SIGNAL_TRANS_RECEIVED => return 0;
when ST_SINK_SIGNAL_READY_ASSERT => return 1;
when ST_SINK_SIGNAL_READY_DEASSERT => return 2;
when ST_SINK_SIGNAL_RESERVED_3 => return 3;
when ST_SINK_SIGNAL_RESERVED_4 => return 4;
when ST_SINK_SIGNAL_RESERVED_5 => return 5;
when ST_SINK_SIGNAL_RESERVED_6 => return 6;
when ST_SINK_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : st_sink_method_id
) return std_logic_vector is
begin
case method is
when ST_SINK_INIT => return X"00";
when ST_SINK_SET_READY => return X"01";
when ST_SINK_POP_TRANS => return X"02";
when ST_SINK_GET_TRANS_IDLES => return X"03";
when ST_SINK_GET_TRANS_DATA => return X"04";
when ST_SINK_GET_TRANS_CHANNEL => return X"05";
when ST_SINK_GET_TRANS_SOP => return X"06";
when ST_SINK_GET_TRANS_EOP => return X"07";
when ST_SINK_GET_TRANS_ERROR => return X"08";
when ST_SINK_GET_TRANS_EMPTY => return X"09";
when ST_SINK_GET_TRANS_QUEUE_SIZE => return X"0A";
when others => return X"FF";
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon MM Master
-----------------------------------------------------------------------------
function conv_integer (
sig : mm_mstr_signal_index
) return integer is
begin
case sig is
when MM_MSTR_SIGNAL_FATAL_ERROR => return 0;
when MM_MSTR_SIGNAL_RESPONSE_COMPLETE => return 1;
when MM_MSTR_SIGNAL_COMMAND_ISSUED => return 2;
when MM_MSTR_SIGNAL_ALL_TRANS_COMPLETE => return 3;
when MM_MSTR_SIGNAL_RESERVED_4 => return 4;
when MM_MSTR_SIGNAL_RESERVED_5 => return 5;
when MM_MSTR_SIGNAL_RESERVED_6 => return 6;
when MM_MSTR_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : mm_mstr_method_id
) return std_logic_vector is
begin
case method is
when MM_MSTR_INIT => return X"00";
when MM_MSTR_SET_RESP_TIMEOUT => return X"01";
when MM_MSTR_SET_CMD_TIMEOUT => return X"02";
when MM_MSTR_ALL_TRANS_COMPLETE => return X"03";
when MM_MSTR_GET_CMD_ISSUE_QUEUE_SIZE => return X"04";
when MM_MSTR_GET_CMD_PEND_QUEUE_SIZE => return X"05";
when MM_MSTR_GET_RESP_QUEUE_SIZE => return X"06";
when MM_MSTR_PUSH_CMD => return X"07";
when MM_MSTR_POP_RESP => return X"08";
when MM_MSTR_SET_CMD_DATA => return X"09";
when MM_MSTR_SET_CMD_ADDRESS => return X"0A";
when MM_MSTR_SET_CMD_BYTE_ENABLE => return X"0B";
when MM_MSTR_SET_CMD_BURST_COUNT => return X"0C";
when MM_MSTR_SET_CMD_IDLE => return X"0D";
when MM_MSTR_SET_CMD_REQUEST => return X"0E";
when MM_MSTR_SET_CMD_RESERVED_1 => return X"0F";
when MM_MSTR_GET_RESP_REQUEST => return X"10";
when MM_MSTR_GET_RESP_DATA => return X"11";
when MM_MSTR_GET_RESP_ADDRESS => return X"12";
when MM_MSTR_GET_RESP_BYTE_ENABLE => return X"13";
when MM_MSTR_GET_RESP_BURST_SIZE => return X"14";
when MM_MSTR_GET_RESP_LATENCY => return X"15";
when MM_MSTR_GET_RESP_WAIT_TIME => return X"16";
when MM_MSTR_SET_CMD_INIT_LATENCY => return X"17";
when MM_MSTR_SET_CMD_BURST_SIZE => return X"18";
when others => return X"FF";
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon MM Slave
-----------------------------------------------------------------------------
function conv_integer (
sig : mm_slv_signal_index
) return integer is
begin
case sig is
when MM_SLV_SIGNAL_FATAL_ERROR => return 0;
when MM_SLV_SIGNAL_ERROR_EXCEED_MAX_PENDING_READS => return 1;
when MM_SLV_SIGNAL_COMMAND_RECEIVED => return 2;
when MM_SLV_SIGNAL_RESP_ISSUED => return 3;
when MM_SLV_SIGNAL_RESERVED_4 => return 4;
when MM_SLV_SIGNAL_RESERVED_5 => return 5;
when MM_SLV_SIGNAL_RESERVED_6 => return 6;
when MM_SLV_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : mm_slv_method_id
) return std_logic_vector is
begin
case method is
when MM_SLV_INIT => return X"00";
when MM_SLV_SET_RESP_TIMEOUT => return X"01";
when MM_SLV_GET_CMD_QUEUE_SIZE => return X"02";
when MM_SLV_GET_RESP_QUEUE_SIZE => return X"03";
when MM_SLV_PUSH_RESP => return X"04";
when MM_SLV_POP_CMD => return X"05";
when MM_SLV_SET_RESP_DATA => return X"06";
when MM_SLV_SET_RESP_BURST_SIZE => return X"07";
when MM_SLV_SET_RESP_LATENCY => return X"08";
when MM_SLV_SET_INTERFACE_WAIT_TIME => return X"09";
when MM_SLV_GET_CMD_REQUEST => return X"0A";
when MM_SLV_GET_CMD_DATA => return X"0B";
when MM_SLV_GET_CMD_ADDRESS => return X"0C";
when MM_SLV_GET_CMD_BYTE_ENABLE => return X"0D";
when MM_SLV_GET_CMD_BURST_COUNT => return X"0E";
when MM_SLV_GET_CMD_BURST_CYCLE => return X"0F";
when others => return X"FF";
end case;
end function conv_std_logic;
end package body altera_avalon_components_pkg;
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-14T16:53:23+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.enforcement_types_WaterBoilerEnforcer.all;
entity enforcer_WaterBoilerEnforcer_P1 is
port
(
clk : in std_logic;
reset : in std_logic;
t : in unsigned(63 downto 0); --current time in nanoseconds
e : out std_logic; --if enforcement occured
--the input signals
--the enforce signals
q : in enforced_signals_WaterBoilerEnforcer;
q_prime : out enforced_signals_WaterBoilerEnforcer
);
end entity;
architecture behaviour of enforcer_WaterBoilerEnforcer_P1 is
signal trigger_Top : std_logic := '0';
signal trigger_Top_time : unsigned(63 downto 0) := (others => '0');
begin
--trigger process
process(reset, clk, q, t)
variable q_enf: enforced_signals_WaterBoilerEnforcer;
begin
if(rising_edge(clk)) then
--default values
q_enf := q;
e <= '0';
--policies begin
if((trigger_Top = '1') and not((q_enf.Vop = to_unsigned(255, 8))) and (t > (to_unsigned(10000000, 64) + trigger_Top_time)) ) then
e <= '1';
--recover
q_enf.Vop := to_unsigned(255, 8);
end if;
--Triggers begin (triggers are after policies because a policy might edit a value that a trigger depends on)
if(trigger_Top = '0' and ((q_enf.Pboiler >= to_unsigned(100, 8)))) then
trigger_Top <= '1';
trigger_Top_time <= t;
end if;
if(trigger_Top = '1' and ((q_enf.Pboiler < to_unsigned(100, 8)))) then
trigger_Top <= '0';
end if;
q_prime <= q_enf;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_reset_sync is
generic (
INITIALISE : bit := '1';
DEPTH : integer := 5
);
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
attribute dont_touch : string;
attribute dont_touch of tri_mode_ethernet_mac_0_reset_sync : entity is "yes";
end tri_mode_ethernet_mac_0_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of tri_mode_ethernet_mac_0_reset_sync is
signal reset_sync_reg0 : std_logic;
signal reset_sync_reg1 : std_logic;
signal reset_sync_reg2 : std_logic;
signal reset_sync_reg3 : std_logic;
signal reset_sync_reg4 : std_logic;
attribute async_reg : string;
attribute async_reg of reset_sync0 : label is "true";
attribute async_reg of reset_sync1 : label is "true";
attribute async_reg of reset_sync2 : label is "true";
attribute async_reg of reset_sync3 : label is "true";
attribute async_reg of reset_sync4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of reset_sync0 : label is "no";
attribute shreg_extract of reset_sync1 : label is "no";
attribute shreg_extract of reset_sync2 : label is "no";
attribute shreg_extract of reset_sync3 : label is "no";
attribute shreg_extract of reset_sync4 : label is "no";
begin
reset_sync0 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg0
);
reset_sync1 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg0,
Q => reset_sync_reg1
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg1,
Q => reset_sync_reg2
);
reset_sync3 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg2,
Q => reset_sync_reg3
);
reset_sync4 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg3,
Q => reset_sync_reg4
);
reset_out <= reset_sync_reg4;
end rtl;
|
--------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_reset_sync is
generic (
INITIALISE : bit := '1';
DEPTH : integer := 5
);
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
attribute dont_touch : string;
attribute dont_touch of tri_mode_ethernet_mac_0_reset_sync : entity is "yes";
end tri_mode_ethernet_mac_0_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of tri_mode_ethernet_mac_0_reset_sync is
signal reset_sync_reg0 : std_logic;
signal reset_sync_reg1 : std_logic;
signal reset_sync_reg2 : std_logic;
signal reset_sync_reg3 : std_logic;
signal reset_sync_reg4 : std_logic;
attribute async_reg : string;
attribute async_reg of reset_sync0 : label is "true";
attribute async_reg of reset_sync1 : label is "true";
attribute async_reg of reset_sync2 : label is "true";
attribute async_reg of reset_sync3 : label is "true";
attribute async_reg of reset_sync4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of reset_sync0 : label is "no";
attribute shreg_extract of reset_sync1 : label is "no";
attribute shreg_extract of reset_sync2 : label is "no";
attribute shreg_extract of reset_sync3 : label is "no";
attribute shreg_extract of reset_sync4 : label is "no";
begin
reset_sync0 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg0
);
reset_sync1 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg0,
Q => reset_sync_reg1
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg1,
Q => reset_sync_reg2
);
reset_sync3 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg2,
Q => reset_sync_reg3
);
reset_sync4 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg3,
Q => reset_sync_reg4
);
reset_out <= reset_sync_reg4;
end rtl;
|
--------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_reset_sync is
generic (
INITIALISE : bit := '1';
DEPTH : integer := 5
);
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
attribute dont_touch : string;
attribute dont_touch of tri_mode_ethernet_mac_0_reset_sync : entity is "yes";
end tri_mode_ethernet_mac_0_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of tri_mode_ethernet_mac_0_reset_sync is
signal reset_sync_reg0 : std_logic;
signal reset_sync_reg1 : std_logic;
signal reset_sync_reg2 : std_logic;
signal reset_sync_reg3 : std_logic;
signal reset_sync_reg4 : std_logic;
attribute async_reg : string;
attribute async_reg of reset_sync0 : label is "true";
attribute async_reg of reset_sync1 : label is "true";
attribute async_reg of reset_sync2 : label is "true";
attribute async_reg of reset_sync3 : label is "true";
attribute async_reg of reset_sync4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of reset_sync0 : label is "no";
attribute shreg_extract of reset_sync1 : label is "no";
attribute shreg_extract of reset_sync2 : label is "no";
attribute shreg_extract of reset_sync3 : label is "no";
attribute shreg_extract of reset_sync4 : label is "no";
begin
reset_sync0 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg0
);
reset_sync1 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg0,
Q => reset_sync_reg1
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg1,
Q => reset_sync_reg2
);
reset_sync3 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg2,
Q => reset_sync_reg3
);
reset_sync4 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg3,
Q => reset_sync_reg4
);
reset_out <= reset_sync_reg4;
end rtl;
|
--------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_reset_sync is
generic (
INITIALISE : bit := '1';
DEPTH : integer := 5
);
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
attribute dont_touch : string;
attribute dont_touch of tri_mode_ethernet_mac_0_reset_sync : entity is "yes";
end tri_mode_ethernet_mac_0_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of tri_mode_ethernet_mac_0_reset_sync is
signal reset_sync_reg0 : std_logic;
signal reset_sync_reg1 : std_logic;
signal reset_sync_reg2 : std_logic;
signal reset_sync_reg3 : std_logic;
signal reset_sync_reg4 : std_logic;
attribute async_reg : string;
attribute async_reg of reset_sync0 : label is "true";
attribute async_reg of reset_sync1 : label is "true";
attribute async_reg of reset_sync2 : label is "true";
attribute async_reg of reset_sync3 : label is "true";
attribute async_reg of reset_sync4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of reset_sync0 : label is "no";
attribute shreg_extract of reset_sync1 : label is "no";
attribute shreg_extract of reset_sync2 : label is "no";
attribute shreg_extract of reset_sync3 : label is "no";
attribute shreg_extract of reset_sync4 : label is "no";
begin
reset_sync0 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg0
);
reset_sync1 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg0,
Q => reset_sync_reg1
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg1,
Q => reset_sync_reg2
);
reset_sync3 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg2,
Q => reset_sync_reg3
);
reset_sync4 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg3,
Q => reset_sync_reg4
);
reset_out <= reset_sync_reg4;
end rtl;
|
--
-- FFZ - Find first (least-significant) zero bit
--
-- Custom instruction for Nios II
--
-- Copyright (C) 2012 Tobias Klauser <tklauser@distanz.ch>
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ffz is
port(
signal dataa : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(31 downto 0)
);
end entity ffz;
architecture rtl of ffz is
begin
process(dataa)
variable word : unsigned(result'range);
variable ret : unsigned(result'range);
begin
ret := to_unsigned(0, ret'length);
for i in dataa'range loop
if dataa(i) = '0' then
ret := to_unsigned(i + 1, ret'length);
end if;
end loop;
result <= std_logic_vector(ret);
end process;
end architecture rtl;
|
--
-- FFZ - Find first (least-significant) zero bit
--
-- Custom instruction for Nios II
--
-- Copyright (C) 2012 Tobias Klauser <tklauser@distanz.ch>
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ffz is
port(
signal dataa : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(31 downto 0)
);
end entity ffz;
architecture rtl of ffz is
begin
process(dataa)
variable word : unsigned(result'range);
variable ret : unsigned(result'range);
begin
ret := to_unsigned(0, ret'length);
for i in dataa'range loop
if dataa(i) = '0' then
ret := to_unsigned(i + 1, ret'length);
end if;
end loop;
result <= std_logic_vector(ret);
end process;
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fifo_buffer is
generic(
BUFFER_DEPTH : positive;
BUFFER_WIDTH : positive
);
port(
reset : in std_logic;
clock : in std_logic;
head: out std_logic_vector(BUFFER_WIDTH-1 downto 0);
tail : in std_logic_vector(BUFFER_WIDTH-1 downto 0);
push : in std_logic;
pull : in std_logic;
counter : out natural
);
end;
architecture circular_fifo_buffer of fifo_buffer is
type buff is array(0 to BUFFER_DEPTH - 1) of std_logic_vector(BUFFER_WIDTH-1 downto 0);
subtype pointer is natural range 0 to BUFFER_DEPTH - 1;
procedure increment_pointer(p: inout pointer) is
begin
if p = BUFFER_DEPTH - 1 then
p := 0;
else
p := p + 1;
end if;
end increment_pointer;
signal buf: buff := (others=>(others=>'0'));
signal is_full : boolean;
signal first: pointer;
signal last: pointer;
begin
head <= buf(first);
counter <= BUFFER_DEPTH when is_full else
last - first when (last >= first) else
BUFFER_DEPTH - (first - last);
process(reset, clock)
variable aux_first, aux_last: pointer;
variable aux_is_full, is_empty : boolean;
begin
if reset = '1' then
last <= 0;
first <= 0;
is_full <= false;
is_empty := true;
elsif rising_edge(clock) then
aux_is_full := is_full;
aux_last := last;
aux_first := first;
-- remove data
if not is_empty and pull = '1' then
increment_pointer(aux_first);
aux_is_full := false;
is_empty := (aux_first = aux_last);
end if;
-- append data
if not aux_is_full and push = '1' then
buf(aux_last) <= tail;
increment_pointer(aux_last);
is_empty := false;
aux_is_full := (aux_last = aux_first);
end if;
is_full <= aux_is_full;
last <= aux_last;
first <= aux_first;
end if;
end process;
end circular_fifo_buffer;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_fetch is
port (pc : in std_logic_vector(31 downto 0);
pcbranch : in std_logic_vector(31 downto 0);
pcsrc : in std_logic;
instr_n : out std_logic_vector(31 downto 0);
pcplus4_n : out std_logic_vector(31 downto 0);
pc_n : out std_logic_vector(31 downto 0);
imem_addr : out std_logic_vector(31 downto 0);
imem_data : in std_logic_vector(31 downto 0));
end entity cpu_fetch;
architecture rtl of cpu_fetch is
signal pcplus4 : std_logic_vector(31 downto 0);
begin
pcplus4 <= pc + 4;
instr_n <= imem_data;
imem_addr <= pc;
pcplus4_n <= pcplus4;
pc_n <= pcbranch when pcsrc = '1' else
pcplus4;
end architecture rtl;
|
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