content stringlengths 1 1.04M ⌀ |
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library ieee;
use ieee.std_logic_1164.all;
entity concat is
port (a: in std_ulogic_vector (3 downto 0);
b: in std_ulogic_vector (3 downto 0);
q1: out std_ulogic_vector (7 downto 0);
q2: out std_ulogic_vector (7 downto 0);
q3: out std_ulogic_vector (7 downto 0));
end concat;
architecture rtl of concat is
begin
as_q1: q1 <= "0000" & b;
as_q2: q2 <= a & "0000";
as_q3: q3 <= a & b;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity concat is
port (a: in std_ulogic_vector (3 downto 0);
b: in std_ulogic_vector (3 downto 0);
q1: out std_ulogic_vector (7 downto 0);
q2: out std_ulogic_vector (7 downto 0);
q3: out std_ulogic_vector (7 downto 0));
end concat;
architecture rtl of concat is
begin
as_q1: q1 <= "0000" & b;
as_q2: q2 <= a & "0000";
as_q3: q3 <= a & b;
end rtl;
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dypiioUitRnvRaIey0cwToWp69VPoPtGjE7wiYdwdwzeUr+Lfib2Tjhm1xNT5rdPkHL9+wmwzVru
9Hd+TxPrmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NUfD/GHJrOd/qogedfzQcxTc/0SdKSS5HBngy204ApFhdH8woOp/E/qkABUhWf6vrahUSE/GLxf2
9+LkE7kJHeallsm8o06h7coNJh6nasWRkAhabrfcqod+H0gmcR7Zs1ev2MVdWZGq+wpdDmlDN8Yk
pUyMkK2FSkmhtqdVYG8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pQ9i4QJszZqJppmBNAqd6CSjK0Asd4msEXepT1olDANWpYn1q+Fj+vBsOQ+/m0uKOgfIPRrLcULj
Bw2QEphZAoTYB5XZBGMt//xJ5Cg9oBYjJQyfoOdAQXMAlGmSvlkfc5iICKdJvi9pPIWWuhnEaKFd
p3vZfLYHw+tz5nHjTU4RE2JbmUjG9HA0i+n8DO08xR+DE6cJ1HydUs0EV1gD1V47eCFFecLL31Yi
BPJEm7MV+V6OPNADBAY8NQ0vn4EIcXNAKPjW46qak3xcz7Cqoxb6m0ewElsoucbEMhN3PL9LhxoT
5Yf+E8Sm9UamnqgPJo3P1UgV/jSkyErAokFHtg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D3a3L/ompCyxvtFucUYeEOQF82K/G7ZZQsbx1izGkgPenK/ThZujqCVGI6CgkUBDQPl9dX+foVHQ
B0XpFUjt+fISZ4RgCml+u3UkBlgZWO1a/OqtnfbIrL7BT7PGBvz/D3Nf7zJxbN/NCeA66CShuiLX
/sQCxKcJ8vskxBTZISc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eKnWiEl6O78YHFK4iUzw/hrir/bRXNbeFOxW2qnHYtzi16COF6eNDiq/09Kf8lTKaML0j906jpbR
PwVy5eU0MbqqrwouD6tUY5Ocz/lkLrr3LN19zfk7xXbOGZf0IONM3Yb3VjtngaJBjKkBtaPPt49C
/oJTNU9ejs1d0sD4rJyWxBPJl3l8fA2OdFhJI2oO42MPaUpj2jK5yazqqslPOqbwMRdipsNsL4Re
92C2ED31fF1FpR/+CmmqplMxuuvOmb6QBLiyWt7cDvwfcg40tzl/xz3lC3cq8Sp2YIlM1iORQbcF
eo4fjEZGTDjou8Dbqb8TfP9NjRG4P4BHE1obwg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23424)
`protect data_block
9CTNH+3CVHu5IbxE+xMlVC6Z8JqR4usxETAwZc4uryWDUglhYyHxjPl2V70XuUHtsrFd+RrBt+8r
2IP378pDJYHindp51fQYwiN6m8u+KIe7GmtnnGn6PPvKdhgdOqXD5c1p9R0jxwII7CTU6klJFaUE
nPAe6hzj7BNlX7VWNKdvr3gvRM8BAHDCt4jiHwSJegqE0NY9lk3CmljW96XG7zXvC0PkB5nf6fO0
vSlTXIcWO16IBW/rsSn8GkLjxX02myBriEaxazu3oFOsr7Yi/9ndAnWmUTVvB4qngKPDM+xke0W5
T3MKsbDDdO5JBYVwDeH0CsbNkidySlZ2Ylod+cPrwlxYPO3hDTTmKhBi0yRxbH5sP9UcyCciW+SM
J4wvFxzba3Uxjf8J5xl3gCCNgUo6+4FGVkN5zmXEe2nDJF9DP9JHcQMRwceIEFm23CFeOCBVlbkp
mPI0Tj049aaHjp35aUCuJtyukygUDjpp3b+qXTCprCwkFSlApL3xZX+JiBPuOE8P5OFCA4poV+Ix
YxOKbQyLfktuPFDyQYfiAEoAxnXhnYaHsHlZTWd9RD27DcXn+nrWr/Ssw6RkoPSjpwYwV10fMigQ
OcDfKNatHTD83Sd2xtiJRMEDpAFtHXnMRW0+8CrMG29uXL5now7ImQ9lBkDXOEnBVgEaNvmPnTzP
Kmz2/N21NJlZZdOfjYigfKESfBPcdyOjw7xTiQkwj1qQtfEZcC+qpndG9ri0dFw0Cp94ukRYFmAs
7CynrOk+nfOrj2dIEUjkAVQyGDEMucVvx4uwNhTthaUtilsOzng47UpNfbTw4OrBH5UwJEIdxoz9
X2gzqboYdJAtyG1eD5jiJh1ciUKVpa6EpXvng2LRmagqU7eETsT2x4dM7xokfias22pbRyIcaga/
7jw1hE+o6HqLk8L8ISmhEA2ODQNpJBt6+kPJKJh8sq6DOIiuKb0ug74KviTYMcDlK1oEnhwGhufa
6Nq6214q+XZYHExZjMhJwREHgIHv62emTUyvuwM9OC/vFxLoT4dNuUILiB8esyoSEmh6sbT1mwGJ
kUToCq7nCyTbY2HTqBtr0NyaAGAd3v5DC1QogAEeDRLnbz+qs4/qgR3c3u+JAlyq15lOEJFBEdMv
WIA/ZK9tYKPQJN9RRBED2eYQENG6M1AgTX7ElgDKyYlS7Wk6galjjCOgOUbFHdvneuSqPUYXQItH
V/rMQBA5FgcXrEXOCWv65RXWq7aLfAadQyIndJIxUDnv9QTz91N7pgP63uZ5BUHFN6p1ck7M706z
7spFEFvXmATbOsvmdX0mbuTcUVwpQA/QN9FDL8kidr79hjPRUo6zWmsXiK5jn4N/beeXRI3UPBf4
OwmQ+ahteeOtca38wBnogVu3x7ngixNxfkXiZ+3S3nQUr3OaJVwKW/RCh/3DmcNs4/PSJ9tykN4x
l7SiteA57QmxFtR5FlaG10as3ChaRZJUgSZRIA4HI2nxuhNcr24OIT7uWO0kxAjSRvPanu6o+kQj
MIQVriQdR7pkAkLngsyHYuoUwiNZNVIslVyK61Qit2eDwnmyb70015x6sq3gQt05FpCv9kV3kd7B
Jd3TZZX84UygSdiI674tMiwhhoYgJQI8HCYLuv3g9tlkr4X7f5iFcobyYx+IkORh6oncFlUxS0hj
WuBh4xymBws2jJE6DIKOcSVaQLZU0PkO5S19gBZaDkMSuaN3S8e9OK9ZAkLrhrX7uGiBU3mWFkU+
EB5O4vydnelMOBT/IdWfM8E8kEvJm/zYY65iu+R+84Z7+Ol7uEhOSjZW+IeYPMQCJEQtjn6OlAxW
u692Emp0Abejp7mLk00yc09OFJFZO3aMD8uTDRz123/15H+Lbn6zfsuCVPz4jBAvqacR9ORWQzxw
xfg3Y+CcF4qVIQNFZzkE+BDX/DZELYmvDOG5YaPR4ycAShGk1QvQeXZlRpbhNRyIYoMbz9asM4ZC
WUYA7dzKHjjHBdhK6NoRWa2f6f01K6rkoOeAPvnL2gvjaHFiT/O/D7h0pIwW+ZI0dYr+YK4iD1th
Fvryq6NXNnlJk7ngTWrhEPvB7OVvqyAW9BtZJolVxxyKvJz4+0T+gQJi44yUT02qLwb2VjabiCAn
G1HrU9ExKVekzdlsPzCXkGoUe3BAW3oO0BIpa+c/7JWCFG9fARdXj1KvXAVWgiKxpSWxGCAyeRce
S7oOzlHdpDInPCJHd0J0luH/HJlVzi2Ay9u/p0CHfCn4C5j4PsiOTIrWkwYdU3azACloceM47gfW
5SAfitLw453fqe3h2imqq/p3tm8HCxOA/GbzTCRQdZ1u4vBI6/vSmVvFXAeRQMHZyymkOK7AEFiQ
eZZbXPGF1xLbUdFTxxD9fGjgTupYJHuAEp7wOI9Bnti9OmMOFxukx6HeQKLKoQ0Q33epYSdiOoOP
R4Fnv4i7Eqpd6m9rVE0Qjzz850D5kUgQvEhrdMADG3IMj7zrmofwoGEHtZS3fXEYGAUxGa71bWff
UropSKY6vxNgkhNn1mudX7ePqJ7RYDjIRWo5wdQIXyGOeaTKCQxaLD6r3Qa0ZnygVupTjlF5DGwy
GzP+R49tpwXUyXI2n3A4DItgSyrICqXd29ZhU0ZJpKaEkhuNVerFoEgQUk5x8XLr7wRy7W4bI/UV
ui5Iiq5/pbq/vEVRNllxZZC19uwzR4ACYOcLSoomZHcCtfhOaRupkGop+0Liu21RSkfqJvhZwITo
4+lDw3O+iymbijlE2qAvk+V27S9ItfLlrYp2fGHp9jotl+6A7nHakIgfT9juC1hplT/DGp84bo41
+XTF6gM2K3tDlMc42Dl36yEj/nBAuEvvEiWhRPMBAICVw4KPggb/FCYIlARvUhukGDNVlpAiBypJ
fqNr1CsvgH6p1kvE+DII1IMFBfLJz/3rfNzEmhuxHt6YT92ZfmHtgAFU8t8tVh9aNMhVgjUkC4n2
mAc9CCUfBcnQigErfehjJdRMYKfIi1vIAs0o9lf1zm7CFKt+Y7iCxUAD2u/mIqbJ3RnsW/28UABP
zYhj0wcQ4Xz2R7wnCov/Tbo7n5fDs/kKYUYXbc//0UZJr7w4W3c9Z4jEHgTAbG2kXT4LeoTgARQw
8zVSqF1yGzrMaA127RDHl45DYLLII4DwYKkTt1c8uJ/qVIo7dryez+OTPiWVqu30o6L/2N+/ygna
1Vh01LstXKWW2IL2A9YhuBYgDsecVK7c+eYJ5GXjkdk9QO4EBnFku56akmiNL5L9W2BmzSH/z90f
3mqXnzW8du1G1TRX49EyNVW391s9Q7orLIRF0jQJ13mbNCm3kd6PT57YlB0VBS0ujrOXrcjNlazQ
Tt1f44qV7T4F/gR17Hj+oyLmCLhpEpp5rk0pRLMDpgXknSdT4ONjeC998U6+0TrYDnDcfwbsL97D
QNB5/55h9rXOdSylY4z37c5Bi8GwG1Cc5clNWYwMutGFi326EqwMQxUt1p6gTKQH4l5WCBPt5WTB
fAe6G+DPJw9TsA35bp6ypPKwT7gdF/l+lxF5pr06b8udPbaxIpBONjt2hKhnfTUMsHab3odITyN7
wSNyWSNlR2fBLtB+2/VhlgsUziAk1F1ncsjbusf6Lsx5fTPHAN8rumCFKOE9jyf4AbfHrfAAuvrh
BeLLrQuidSzX0JPqOY1ll+SKGufvbUxghhBtgCy++YQdHQHEH1ECng0GfFTrBUKMXB+Ufrma9B+o
AmJ6yhlmmzc7FpBeswYIb6xg9JSeZGeWp2xMyH3hwRwqBlpeDOPdWnVABb75sBp59bcLG4bD5gpk
FN+brZVTNxNv6AGz6UyGvzFHK/N+A6YkC3zqdqxPQJe6plKhMFCZJhuEeW1mxcEmwXA96VjZxH+z
4zpZ5tuNdmVmveQx3hlZW0NAdjHOJg2bgkQjhFTAVfYdC/XyXDWGH4bDwXkel9XB2Hhzsdp8S9Ww
wQ1sSIO9z/x9UR5lF+GWteSrXLVl8A/VkZu08j0DNT2zmocJmOCzNzW1R5YCnyMav2OId3hjWjuv
z31ngS3F5/s08FvBdiiLmk+fIJm7tBoF8OeZVMeQD4E5cJGImuEN+Hem2VCEI4HEQzyrnHBEtTCA
fWhCxLW3cXyEXcEoHFekKuGsxxdLAqXpJYzauGEoclND9iF+XxB2RbEx/LiIPx2OA3IQppetQ8jt
xw7paI0B0PtJF8Q+cPAyDfLsN6pZuwYBkB45T02n3tZsfiHfzpE8UP9gHxYswGh7OYw13+TG5bsi
uojooPk9FUToLHxBHcyfFnxv3Pse3RTzaq1AMmC+LkUpELDXKiA71akQY16Rc8yWTIIpNm/s/Gbz
d3nT4uDDWy9/KNb76/d890j06302K2JrAWCFpgUK0ZyEq9auG9q0JhW+E3VhNPgSKAEyxs39s4lO
NGxcgdCXt01kGXtBsPNGCXwMruob0PrdfgDebb+qRiUoyuSZafit1pr6tsfEZlteFw/JX94WjEf6
uaqhvQ9R5KumXb3lh0WjGbONJT5YJaLjadI3pro803ElAr20jReLGhQ0UcfWuWVwKXkeNqy/bJIR
pVklChBo/F05+oGLLUEvEaQO1cSoTltXGOREOFelLdg9KWAIezm13HImsR2/+UZfZp4HZUbFOrwe
Dv4YbkphWE18HMK6y/SFJVvl+Zqh3ZtXYtFQDsQkpdk9xLCztoTVn3qgg6sN4se+T+ZC1RYPwoDh
6bZd5dELLmWhTthJczWi0/waYEl20adcpkOichNnMMCiPfyS9WE5WOHcYoaLsY3DT/JjqLCQJqaS
qKNIo52bebaNhD1elf92waG4HhwpWrQXmb8fg8zGCPI1Ss/7NLwStAR6KVoFedMBQ62yEgVJO/4s
+prBnGIc7dRvsfPulIW62rwVxGy2lY1gplaLthNqM22jbUKzy404vjNA8b+himtyemeWP9Y6NUhd
LsAVvIQZr4HnMQb/CRE0dhxolRXnYlP3OsHQL3PKyqaYnWwEPLiuh7PJ0comrLBwHm347KX6hdUl
5dxUgRIS04kKo34WRhNW756hUF1CSeVfC4OYehqIEfutkE/pC88CoyxeO+nCfu1N3oN7W4rA+4ad
fxAPEt96sfUpqbsCnaPnPU9awoKTys5gSRbzHJuQ5Ne/36j/Hf8Q+LWqpqVu4ldzGX2IF7KADDpL
5EvkG0DjNoETal/gdxzVmYIWBY6VWemeaDkqcKner0VIRh7NPS241bWTkQEWAwCr5454kFdjOo6X
SZntNOllif2A4KWSqL1KSGc/rlqaXGdShydyGDQy1j05ypAZcazJlcJ5jUfghawpm7HFvJBQoxWp
C4jZmIWMlCGM2ohWqWAunU3F91QPA83+c2hD56kJkwGcVRBkclmltmhC5thvYoTUUcPFquL+VtEI
KDK1om4iDffuWmZ8hOZEpZNdpXZUZPSG0ebvs76qAHjao/viqv45l/Ma/lx3wD8ZdpBVchefq/Fj
yJXnpUqIIP1t1w+Pb6CIxg5ebfOCYM9DVP+NAd4RGGmu566u1P+3RC/1g6xH5Ldk6PCCpCp14kJv
bVsg99yBLJx7YGYLXZ1IutiRcBjCNoIlrfZc+6P4VKCIBy+fekN8kGR6aGH3lfCzgpgtg4HtIkXN
dK4FOmgdQkWzpHK1gee0Z96KBDyN4SNlPjdZzG7lscikyQtoqHYyNZP0JSZruMhFy96xhxmpNqJy
qUqTnqOcMuaOuJgYXZ12SQVSRh8ps/XxNdnCKwL2yKuWjg7gFhkD+5B35i4wyUrsLhH0T2FNWP0R
bU0HlEJ8I1uguehEAZ2Z7KQ4lvWhpVHAHLLP9J0P3UPBPNI1ad3yiwaPQPfVVWX+CptqYGxHVYY8
Sw1y5yj78rAOve0dcnB1Oh5V/xn88fWyqEJ4NWEHxHltam5veI/AefZ20rWFeDUQBWghLLE0CDHj
ggA/1d+QltYR84g0GLAZ3nllpsOlFFa3mOtyKbfMfpjm/swNGycxx3WX2e+6gKSYDI9tdXfXmMxv
Nw2hfTLnM421/Ljq2zZnJTYBsgwtgNuhcZfPaZsC/UFgD9fi3l1bXD0d4Em/C1W9TyI6m6jp0zJo
052xScfWhvA7pr5ObP8UgpVw+8uAhk+5iN3TFC03ipoNOKKtPB5ZAx7CvO/X3rRxIxGhevDRtV43
M8RaVK8S3eE+y+g4op/aKlkpmfn+Zudus1YyBds5PLHY45lkjC54JIAuw85sIrvG/DJvETERbiBh
8hK7+iPSijKXzfW/8XuNAUybFFvOw8aOvS6EkNFgMfuNbg9LqYL5VtAPYvOlWiHeYE9XG5Lf1fmo
uX+oC1BMPSv/vFF7pWMgRYzbZt9qiq9eZw61jFA4IXPDMAKsM+PAQQPNgwEpIrq9scCsX3Jr5uwm
ajKImIxEGRJVrdfjfGnNdZjYLEc0aYZ8b3RZTtQlIRoYhnjtS/Vm2L1M76EiFQCEq4V/DpsknqU2
Yt2SWcHpZki/4GSw4MnVFuwfFKXducN8G3pSeZjo0qVDuma50sY1PZVuQqu75+T4JAKM5uVKwfO1
YM31SzBZHYYcjpPUpGgdYjq/Q/G/Nha753vJ+sF64ruhT2azwScdFmsR22U1sf0nngb5pyPAn8/x
IWS3TNpJq8y2evrln2wQ9nysQ3PqYSlXVIw9Yz4onMVMEgqhjgYOcboKEKr+OjI843txb5dlvsf5
jBL2Ejlrz13JvfSntLXzGk1BbWbJJjQfLARTNZO72T+miiNJxBJq+AJOqwKlHxjLp/m2z5jFBmXn
q1sDw1s98O65B5rgfTGtFGdsyC7Yd+Be8Cc8EvQx9s1Lt0gRwVTB0WsOhxgfcI41DHmJBl9cstmu
njAVe78IQENDuCDnLSOashiOP+PZmJVWDE7k+v1dsVRqZGmzgujBbe3F4qjZhcAM6QKiUEXqIm0D
i5ZADbxOrFuDVjoIjg06WDVg5yffOm1MttrEterixiXlIjvtrGgS3qGyy55W+419cwu0dJ6A5d5b
BWq19lamfe5X9pKbepoe4FNR7MHfCIMks0pswvTN4GNLfIRrqYP2agItp0glayRmSObIvP9Jgawo
rCdYXRrvJH12aP7NpbJCYqIU2U9MRdVP0BGwES1DNVZY3IG8B7gSq+10lbuyt1B8rVGxnLWjUAWC
yt3jVVPd9h8q6QthcxPKxbjDDKkGo4OFOCdvfKxGKnpjpsP4OfYdA76WNhzwq9Up9WAXTT6Ruqiv
F5A/GV3f7EVluscUgdlBlf00Co3KmQ1BKLnBkzEl41ozLyF4jT9OX3iBjfPHt2BJi5a5X/7nzdYA
RIYXhqG6Xa4FSQLW4A0BV403dKFn9QJzuTaUOnp7l1JfbpdI49z2Xxw4CLWclX9BLUxou+i2fnhM
9qOJZO9ipHx1zv+WsuXmqaWEFO2HzTcKpEenUzktM7ScUuxoDbAo8hPceRK2n55/WR/yPa9k3Jls
4Roxo6N8xq/WnIRmhM21ONO3UVIQec4J4XXFV4kwyDSePP3QxKa2KZWtDEpZZrO+axv0rF17l1od
0k0xlGLZxtEE29yrkIDzmIjvB38fSGWY7YeXgqxsa8CV1axl++Yg1yiOdCrmaX+Vo8bbhwEV/7nz
MlIiAQSiRpeKpqlZPTLqlFfiLAL6KJ52SMrs79IHKiZuYWwcBRHIpEi9KT00Ntoth1Vop2qQjpr5
lg7OeuIpJF0sSTxupa8NwIfC4jh90NsJG6n9MkRcSD1SFeHQUewtVgKkmGa+WSMjcocJWMyV3vAd
azc2yPylcmiK2i6xCUfAU4otsvHAotnAXHpZGaWEEG8LUI3j+IGNUZ4+mr5OpEez0UBOF4qYHpFN
TV6gXgRAgTtlZHNONMtl0QO6PI0kwLPqEXFVRKOwMFQZWcY9J8WK2ks4ASZ0OHPh+DR7wy0mUW1m
Qaz7YKKch6PlNr9VY2jlwbZRkxbMeX2YblewfIpeb+VFEe5ptgYdaAmpmlbBfivjaWH2v/XlM0eX
NBzoo6Y28Z35L89OsoUnGSpzhiSmybsE+w4qMGtURV1q/Ul3scR8QYwubbYOy7s71RydDdLkVKAd
pAWGSGXVGDBqhY0qIrDl2CV6IAFJ33QGndJAK2yBCUg7TG9NB9mgPu05uO5aYVC//EcOxVhTPnyv
ek8mdu7duW/B4xJBuDxHFvh4BwnxXad2g8/PHFbcUiMTpNJmu8ub6p3vfFJiFL5GvSv7lxMuF1JI
vLZRWraSYAxceAOD0V6jsxsP14edLABZt7sE42ZLzVeh6bxZOrcmNeAJyCRrawA1WHFDNeWscn8u
yZTu4SIlWylr8UBlpzXRvT334HmtXX2Xq54ZR+/3wHRkFsSBOGJIFV8CK+XoSHEHJxn1ICeTx6Fz
5uPM7W6fWrXkwZtt4C4WwkCmanQ3FDKJoH/zGHVjAg8ZVOlhourcpIOyNuF8JPZzq6CjDOqg/9BB
6Bw+VHvzGx2wQacaiNr+tbEePKA+I6X8hdKkKXx7BgLhywruFESrHSuwvxt0ZTaCNuMVAxa1dcW2
5TGD5GV0q1XAU5pd01hSUsnzaGtXdFUkpu1OQEbMUGLnaSQgtDTq0x5xSfV2VweEs+/WpvFLvOuz
lAeTqKjVlDtkrZ2sOlCpu/L7ZdntQSN/zJFNh6f/OLOYMjq+QCPJaDpGfXTIuJ9KO22UbFVoKQ6N
bqxzroEEPxGIr5jtuBM8PP4Fg5e2d0lHEVCE6KKUq1x52gQJxl0tF27gxJtDWplLD36zYGmkxRkG
csS0L7G/nm3e/UPDHbMcGbWA6NOSnmpixO1p0fxUbxjisCwTUISSWMwUmalBfjFHWKVfbc4wyB4N
E+jUiKwMFnB1+vhnOYy3dSId/HNzNQdZeVVajl5VIsLvLLzcCDkT32pwzmi1f3iLDZ+T7FJdj+js
mbmY9T67T5NBjF/jDwA+gTmtSmm+GlTOcZYtgalyhBjLwFxAEXSVfAFakwPOHVgP5pqqoc7oigb7
BOwtEE6IOZ1gQ32JjGNNSxKd1ZFdNGxMQ4fZB97MDeNKhgX7oUHqtcYOzjnduDC5Sm7ZbVpBSU3d
I6m4xeYzsxddCDQOdC5/HeB25gpl6v+jY1m3oByUepxMq/NchHHhc7rmnQOYBKzcFkqIL1C1caEg
++mZikESZ3zfgpANfAPNPeOW1AHarhzZ+5mlGLc3337CqN7GNUjcmn3hTYg29WDzl29Y/EGtebqU
YsbfbXurT0bjVeKHfMKmKqsHbjKVwfXDtmmAPlDfcqrwIW0D/JsMtcJ/3sEgqcBHLBPTIT9gDtOA
SJYRfznrVR8U2KmUUUV7j7FZconaDshz9xgJgnuOcEQtVLBzJim3v2VS6khMEPBYP7Nvu0xMPI7n
9i39FoSi/TU1u7v1leK/99TVT0l91xlVfmOCBmcnjatQ+/olPpcYcHBxSqCJvNmic+22O09m8hLj
GuhRsC74KjrBNZkgpO/iLd/+2KzzbLmg+7NQ2BfQo4QUTXstzGLNa9PMbE32BvPcMnO/Nx4p6NO/
2I73QAIwnUl8CTcAG6fUmewpTIul6aAzOPzhB06kboArxniCWOf2OPBMffYEcUu8D6S9MGxQw2La
p7dfL+Ynt4fseaxM4B0yxe+pLksWjriYMYXExi9AjsA0PbFAv+oxN8+a3T5l8DCLTzokvL08mLrp
9QIB2WVlz21LFpS06wIWAamGQ3FNkyR/Of7F1t0TsRhO2NITjSdzl6FxXdGAAks2/7Njwux8g44+
Q8Ww/cvPwGrMoFX4PzPqs8dhFIB/PhbxkmTcU6zMDmXCIeA7J2wo7ZqHDRE3JOSrUbvVUtfqzbxX
Ltn9doyqyt8LnzMIg3G5GAKCYdSQPcoe5t8j/rv81xP/Dd3kRpCYLHoIXpZ9+enxhqHgJqO/xnJ0
EXsUj9dVrGbnR/anEdGCNDEbnB/lOfoN+nF5TwVzX9SgRoBX7sf2mHmo3Y6ImufAkjb5KjW8cLOJ
X1Iz3wC33zNI3LLfTzaz1f1CXD303mq4ve9EDHyMZTWHZeJBZbXjr4PvXSjWC5R8LixCf8hOvxUq
molLIQq4W/jeUq1LJ9HLzLrUsuwI9XTVx11EkZ7+Z/UxxWRkV+nrQ/yOQmbhMr99MZ61IC/5+tyy
GwtA55EAilAF4tB6Eq5WQymppicga0Fl2wc7hYiZBwWy9wu0j/k+DBIePcrBPWyU2E8dFPSm+EIX
ugZeB8upicXOYfqI861qwsS135YZsOlHJqMAfXLoaETT42GJxyi/xP/6J/spKz23d0XXFGPIeyDZ
pNrJT45l0Zqt0TnWQOXmWwzWe8m0h8bycT6pHb7+pCUDpXRU5XVV6aC2ByUuIWxjRIapHuEUeXVx
Sui0Bni9q2h37gD8Q7P7PJxvxs/SclijxdI5CbaFAH2kJhSLdX7qSD9YQCHLs85N13QVstMl0giD
A3l1YYUZudHSUviPTqgXzFW9bVX/FJmpg44s2oCRIOYDGgVAILzu4NiWhBmWoEvBqHDc15NqEbhe
/VgPQnrXCHwUZnaKIdmnoI3F+ia4ezRDOlDRVKLC/65xPepeXgFjdhxjaiRLBT4Rx8bMfOJiWl+P
7H9fgTJRMcjFvu1vcpFnQZSwska3AZe46/VMetwxx2lhQCagzPLB3qM9WfwS6KfOIZqlMupurosz
sHI+QzQ/8Iq6DIy9WzmEZkoVh0Q7uMZvZiwLPIxDuMFq39uUwFUTOLCfLuLh54B4xrXK1RYG7wld
SV+zaqToaKnILvQcVnpXJtiKnFCxmvPbGgHQzt1UUvZQDYiv2oS5R78LyZFqZWL+m/RVFd7Jymiz
h8hDzOMFeEX2pVCv4V4GMDyey9zfo83qIT589uCxUfMguuO6zecRba7EHmyY54IC8hFLBi/1Wq9T
HP7onrDNp6hKld6rzFWtoRy4l4sVrmfn/EuNl/PbZinaZ9pA9Kv8TTiC72gSCooxfxUsLYjdP26L
AaNp9UdU8ZZDTrPTgzPudKHPaG/01nyDVR2CP4G9jq+8fLBeDy0X5tMl0mh9Voy2wiNi2MhwH49v
Qavn+r9i8APuMH+9E8bF/C4DbmsgNQfSJW/3nr2V1ZgJpf4/2iVXYHgovUnyVblioqRSCYiDcw6W
6dP8btA5akCA9dhAHPLyVaO2pdhoqVng6XfTOtGjiST4I9NrvF1bmBU+Mz3goUijZDvFsZJKkqKr
ebynDxeCKT/6clHLQc5hjmgVy2uBQG5Dot3ugny1/6bvXWX0x290CaxvkCVDVhWbIX1WH1cxIBEA
FKfy2VJ+A/1I16pKiuFg3VZETk68K4+sywHXAySd2NTOjryelN98Tr1/cplzZIQkBnKcRhARKDdG
06eL5gZ9e8NqixbGHPsUX+vzFqQcDEo5kBb+PxzEUonDg9dJK1baHwiQoq9mxnosMlLgEkp6vbeH
fZCjbSn+ZQSvJISfkHq86cMJW8LGiZ8mHOto098aRVuh0FaO9lDLK3JNDS1qCUIpVA/cjhqmty3y
E55TEHnxqAvsTvxmtLsczx+++Gl1At1lyGaT5ChYP2hJcfzmN8MvRBB9JsJLywuDnlYtZqGMfN0X
8nuZEcqWSz2okRyM07/UfV4JHfqe0EWQ9bXjAKmkxSkqBdks1cV+W2A6UdKhuKIwZds7CbFd2v8p
N3GbIH0Di245k7PvxRDA92Ss0sLa1dP45eErjnoivfi6wZJQWonLLxmbji799ijtQMqpkSgKDsDo
35G1ETZsGIxFHnA20Enx2LzUsY4a0Xt8OX1ZXIzozibhMeRsce61P0aXI57AyruQQ222esCY9bJi
JMMsS+P2UTJ2iSSZiZcS+TLOUiNMpiw+1mykfBjCLyMDO5G9CtlJA7a8Ez8OA6a89Mu5pNS2ydxw
WQi72dCCxWEHxwjyAkZP2UVIc9FtKze7yIQsIQpIPr/bFZ7Iyf4I1hjxIxLmuGkwO2Hka3VOMlSU
34oP7oA0kz8xe2zWghp/ntkRVVMr20mA5H70fHRVOXQSwreVk0AtoyxsW7no7a+v5EBnrzMapAcz
hu2KHJ1NLd4QBv6B9gCJLA6GXDYzcY9OhuSiqhXfjPivgn9tMZSm8/LLR8dbuF7951bFN2qIf6Eh
Qh3hy02fzPBFidFscaQIVuPUjygv1hu2ymIJ4/cY9zOWnXwzxHu3XaULHkku0bS1/2WDu3rCscNg
BDNnkQPPrsfWItSC9s5WHkGSn44R49avpxzq4dmwnt48O2TNriGXLb4uXmiYdHOYrqSX0w0zXNjj
BLxsp/m2G4tuuqG0zwUKuu5pTQrSDWYgMOhgSbswtlKlvLzoWXSG2Ew0heJzpbANmEx7Zxfqff1W
R6MR+AjnimWnO5xB05o4SNdHRNpOAcAXcQUe1SPeZtyEQyuRjngx7ccTC9s62H2TMrogFW2WnTHm
mF/VRdx0adghzwRlCz2qVuIBCORpFHwsuOQwXMboWiAq9DtHaFVmJriJXoTWiqEZyQ/wZNbGWlmq
acSTi4AOi4I4TPw7gVnMjQddISYY1m+fyggxe8lMKfTz6EmUzzuFlGOoHgIc9oMxHP1U2wSDs6p8
jEYj94EaP/pR4INn1s5vpPTemOtvcUiNjC1a7MH4JCxJp96LhzvBMzTnTcjbkj9i/fUWuu/zsIRa
0Rf8Xk5w6hS20XuGbxJdrPOl+Jt0tGA4hMEU1BV5JKixTkW5aDHM7eWLfkxOL3jM+1gY4EhZqhVQ
WdNeWRWHSDaEACsZG4LGqm985NOeYR2++KfSWmRY5lWAA+Lw18x4cbHAtajo5MxcJLcPUWctfEp+
5hZepmfIR0Me14HvI1w5zA6atSmP5YIZOaK365SVZAZZRJ38KnorpePWs/6dBzuWhJWEJNnQZ0ig
AUfETiA9IjGEVMbjuLcGxR6gxfRx/SVBj8x9A3QkVvUg0R06Q0dl9f0uVikioQmrIOyJc2GN4baS
x/NzpqHvj90hsi0vnvrrbsoTrh11Wu5GCTARZJR09lonXhVYVbu0FisESVHIGj9PwVQMwPy6LZ/l
0YrHm+yHalhIMoRR7YArAHGcBCK6v/WiVFH2Lc/kzbcgTdiFgGmzdzC12FH3IQ45A6P2YiUvQrr7
hwoKBIGRDrmez9/+qHcOKtmlvLAf7HDgwRlayr4IzWgX5XnTANko9kJPk3qVh1Oy8Cdhu/AJ7idg
mbbQhzSn/zG+NDC2XJLJJaseiL2050IAWgAhNUmB1IPC7AIIQ+S38gQTyUW70jWUYmF9VQPCvJpO
tr4aECKd275KLRCxNoWPNsjbH6FsmFecgeTCSWiUBX0xgzAEs08GJ7NkJBX6Z08+19Wb7hUtE5In
7cpYxV+r0jz6fna76jUBgM+IpetUyVLc8moUz9ktLJu+xKZMh8Woc0hE922sx/bGyk2Itgv7rCH6
Qr6yaHW36F2MDkQXlAz1WpmoWCTR6dwul2hAEdP08AdVz7AM0v40QXFEZ8bkfG5Eu88zFDwa1Cve
xVU50FIVWxXUO6cNDZiBY3zFOw5MIkREA/UHlneVtxtRL06rfXgMQLPWVwVp3zu9FPoYz+xon8UQ
Wfla9hAjU2NIwW9kaac0Y6LJfWqN9orOUtnP1n7WAzmPpYCysfp3vMAF3bkiCx0TKRaxltO0Lq1c
DYniKbSPMCTYggaTaoVrUDxI1p4AtSaZa+ZOgCBKKePxHNZSaKv5YgZlCilz2Ro0SBGy9dW37TFG
JDrnKmPVhiq4x1/OwE6L9EE99E+wNRw6ipIuilM5DQ/M8Gakp61IVv2REJ9qme1HIW8O7w3MWLdw
zOIp388PCIAHDuGORZbE7z4A1r4jy2dsl5O429B0PpELjE13qugf7C2OL/xoHK4C/Qy4Co7RNPPm
hr6eEX1rAP3RBy42V5hSSVJzI+6ABC4BqcoKzdJFRxnRIQmP7dtu4C6r6tOsbAR9HYKLxJJH6jnB
eFHn0+oheCwOlg5cDGRKxiCSh9Jbnc6n2N0L7qF4uAZaKk9+sYY/qMGBA1qLz/09Fjjr2iIOj5PK
zHgPZ6v2qily15J4Z3wmx0NBcaOGq5Z6nB+QpKpY9AkIknny5kJHkFf9TPgVgLqu3ZuvTm1Icmrz
rei7IlKDGf5eOxbwI74v+uX9AB24vpy9hDmSknYfSHeYF/nwppHSHkfiY5E411TjTLK09MGhhQiI
N+yEwpGUHpEDzf33vA8hhs6IrjNY/ArmarhEM2f/9Irh+2TYH1ycV3goDK/W+clfBFjABDAU36r+
RJ+of+4NFEU/1pQwRF9e9VujYAg3ChjemrRgsKaO5L/Gm+47IdOq5OE2Xxgl98Pv1Z8AxZroaBkl
nXd7iGN+am2d21BfNP5slcuMS98Ou3zPVEc2RO/vv94fvsoGfAnfxmb0CGtqo+6NdXtCZaDc11oc
01vzGynmFvWIxxDPxa1tTJXqF13xCcveSSKN0N5cVqnkQfmyKfHi9JJdUUFTtUv4pMy7n/mKZxhw
xgp5nDgDfVfIe82scfWGIb3JXASXfmwGh0mPsK208bIhjur/2JvbcbL3pKjLsIw7w13rHl0dv5OO
SfNl/n3FwmI/SSfvKhHpKkQWZ1IsfHGPseA1wSyxcBZvSbn3XaZYx9Y2cnS6iLGAo4kO4Vq8GgaV
KKjN8R29zh+0a+TE/IbHC0xe1w6zMGe3zHjLfeEDWlDCofq6HxG+6TKZTDyd/ZQ9l0A/DkiKjADs
ymh7tKcJajUZLo4tUFtZBzoNCb72+qvBkr9EQly3QGqLAdzzSp6NhEHxokSXJhacMh5SWdUCNWyY
hTSE2xCRDVpFYBkib8/lfGyLqNs26gdcOaklK/lZQrvjKmfLfxSg09Allgq1DRgGPea/2umbTvX7
fgsGTpVq16T8E27NmX5UOrBS3BWPPJ2/TfdWB0F7i81LD9xWgR4TI+109kDJZzjvcDGecvdyo2TU
/33RCjpJMbhacukH5dxQjBUwgtQk4p4rIjGFCA/NQluJj3JhO9KYXTKLAF0xX0d5em3rcA5dqrRU
Or+YheU9/4jneUTQ20wCx1xk7EyiIqCCiJzegKPsLNP8p6G7xbQm1Qp4pUqrwf5QsS0GphVNi4aV
5dpnLcaipOslHsDLG5mOl9s5a3WnHxmDrOtd0mu0sjG7ugF9guTpRYArjY7V9IpZDeHLNnR2xvO6
sqkZNBxKFRzP/D68/npVRS4XS5e2MkGpsdp6oUQKIP55Xo3hoxkRZn3L50rCxvquBaYWbxeBMYfK
QE9s43VcvmQiiP5XWW32H0OfrE7dFMOhZD9uQ/xX5nqBkyRXIiElRxILPwL1YjiazVwOLoJZQS6K
KW8MdFPKVgidPUCMsYPNecFrH9FZNpn+VzU4JNCsTLooszK9f+nlMASQ8B1sjfkIqvAIU8Wnd64l
lo85lxVIiZyeEaiigHCRNqoyslcs+y8RwuR9RhCqY1Vl3pxA7ye1/nP6OflfqQAoN6GcwA9vOBFW
HMy7gbD3hOVys1Y/F4WpE8Qf9ZJimDzwpnMqKgD8lnfAL+1ev62Nk0by8oJqctIvJ502zEUY/xmb
mJ/RZWNbxG15CSsxeRVYgkxls2gt3iVDCHv1hSliQ9zLO1HGN1zDzDD4b5xS/QqlucIhgAuPm8Ou
07Re2WuY05ocPTGDhB349U6pzBH7/ozErBKPGc2B8YbE/jBZEN9TMYu22n0xomzqQsdJycYiWMF9
oL5cOHZQtuN6ZT0SEaO7kPfGy8SnjohNEj5FxfRH0vp7Qat0pswHR7fqw2axcgCei2afIeTBo1Mf
WpYqR41qA4EOZPLHSP6+lewSGyci65EOpiOaqjvIHmByYlnBTJstj3IlKMD4dHfeJ6XTj9MDv4x5
JdBXNzWh5+/gATi/DoJmdNXSD1NZjZkr1YwfF1rHC9Olr0qN+hlMe1d/9LDZb3rg3EtBslsj2xDI
Ugu4WblEgHtLLmNbeKf/zI95gkwHZi/gorJ08oM7qXUHlh9pkwZ2JP6Y9s50nsWNoiJMe0gT/Lqz
57HZvkfYx9Or3bLt/obXaPO8okOh7cf+7JzcEfzynRx81X1QdjfTY6+SjYMpVseGdvZfnHKo/ZRD
lgcWgp4aAh2XsUKUKTU672EgjUN2i0kD/Ub+ev4TXMAFkXzDCMJPSiRe9rJtA3SXHKnTEy2smnj4
d9jXqsipBeJD7cJAD27wuRLnw9sxsOEURdjCpg5TcHiBlFZYVg4hDtBIWd51Xfb8N4g4j7MVLWXs
FQS98gH41coiYUCu8ILDDdo9ZsWRg70M8tygryWJafrecnfSwLtqYa6rej1UxIRA3MjO959PMjfe
Sl8t5qtK7+WuAcqkYucks/zXAGGq44ez8q1HyGqVwMa0ymV5qsmZr4YtamyvnZvJ+8IxlyB0poaf
KjDwT/omqf5dOjHXnMK7i9YqzmM8nUIIiavE+BZm6VEgfBa0vCr9TOP+m/vAk3Rp8Yr/vBzMlVZZ
evsHxKkeFE+24/An3oo+ptb3IFFVUvIvqrSmECKhCQh9qpEiViIN2u0WbgGuI1Iiq3man3vwZfUT
CtepwbQ8UjDmJjx8sLVvqB0QFMSXlO1VjOrZlJ4vPYlllJ2SgTSEdQR0qx9Itx7VVptzrSFnWP4/
RThIWIc6md2CNIjDM3l/w3CCtJtJqaINzDf0z1nIh6Y3Iotv0cNbWqLzTTBtsG0k8QyrLrBr+Oc7
rQZsixDc1l+3FSK1y6IPMsPXZS9bEWtW30Tt1LkmqPlXeX44v+y4ud0RrDQ7zD5AYculLi6pEVEF
KCIdlZXdk5KMW0xNJZ8912uL+4o6Z5ZXiu/eLBmS6PqPZSxnMrmSBSBs2MNDIFfMuX448FE+tf7r
m8q/KrdflpVCuacnZoXdQU+150x1nOTnuRkohIADzKcW1GH7OJzUWRq8p1Tgw75wCy1MilMJmpw+
q9F0ZixftQcWDthaqOpkcUVj6G5F+bqHR1OYuLxRHNA9oC++yEx8+hWm9og739M4b6Sb/mbiey6W
st4P5+h11VjtSirn9ZPzbVuBBpDPEZlaCR5P/6HlO7DKxZDU8UDg7h2dDZ5cm/JK5p/8wcpgngmu
wslpSTwk896Sb+JNjtBfLpE2n+MwB0EIFPxTRRYbFkSl3fGsNYe7DYwM+3Y+V/Nftm8oJ03V7c6v
0nesCwmmXOhb0SD9FFEnRJMVmAaIy/zHEsM+QiOJHdhcs1dHCsVGPEr1ITZ0z5v4qaaFW9jCslQT
HyqdAgUVgOSXenBofN/P+v0UofARpY5rsLBpi9TojLeMKpOKbpdz0PS3yT1e7gUMgCOODAXghfRw
JjBQnqcYqtSvlJeK0BdN2x2pD7evv0sddQBWmIaxbm/aqz2MsrI5JYh6Ej9He63GWYEFk3e361TW
5wDJDIGjASRBMW7k9z6QdEIXacLbph+FHIcEaWnaFdOMiqEC/8Dq9vj25AeBeg9jbWbUNxZ7Lvrd
r7XWa+SFvRLpZfx+xEoOzmCMQEsMeQ+sHic86/VPPytLt4pQLohhjqXUNxuBCxi40EvRxAnlK4T7
/NRKXVYrLtqOMGrkJcj3F/pUo+NSCzPGucS1HEXxNVefk6++EK5nawz05VYkhYzAhFzx9hLRq11T
YyQTkwePGJF49QHTrqEW6v27/9m98VXzpEYPNBv01TTqHQOZTRQJQ8eWcamZ4SkHG2xntD5rZgxA
UhcYzpCXeZq3Q6oF5yHFC0AOdBGTEDzUD4HAo7GR1ZeGptAWjgKvoa2E/H55AquhlzSAYHNNMeRA
d16yj2unmBc8SdmEPq9GXpOdVIf63qWixAKd5swk6oiOLE6ohfXWwMJUys9Xl46xYe6wPFMngPGQ
KMxbEn3XFL4hfMfrYTuzZl+r9CBTUSOLGG2PQXr+sXOIonKBwi2ryuZPI5mbej2HJpzh/F78WAjp
h6KuJM3sqK6xDH63h1i2AGeLnOiLmVC2YreUWMwzM9wa5pnbu+PGtE/oTXl9/XjkHGO05E1/RzuR
7oveuHUdkrVyNfx1+J/3BLL7O9hgHuXrEEuavtnb2t+bAgwmiyy9BoptMTUALw8b/CpE445Wi5Qk
J8GT58GHgih55JAQDR1kfwLorc+YnXnPPRwSan94g0lVaW/l4mdRwTPh/PCqUovx+6FlpPImt7MB
XhqVK4gaG7xfV2AmIWXznrjdrm6HAgQqcmKxkHSK+aLyrdRNHyW9MIRx/MkUBDTbWbZtUNDyzDbi
q4pSDzboikJP26fM7+N3WhJS1JpLmfiPKvGbB4W5gdYa7niAegysxx6UeS3phsp2m0PsThX1M197
mslolZLAB/zvKFYKE0++mWjphS5G6w+cyO/ir04n0Xmz5Dc9ysYs5he1H4HS5IV/4cwkeyWLjkbr
MTx1X6I/UXAthS1iCJnzYsO4fLYdGSAwHW5JqTAagm8qGRAZS3QVpVOAk6UKMN/dt+WHFu+XKu1k
CtVMtX0TEReAhlD6HarznIKSQNbQYUink+0jaGOVjMWoZw91JaEiZua5G/cUH0rVNlmt9wlczOnm
ZiMKRM7bcDrPZDbbLwUmHLa6ij6ZCzOeLMaO99i0HPEdr4trmXP15UxDYJwHr0SirlCbGv+n0+z1
F4Wz6peC4uRJxLRaXiskMj1WFHAmZS5e9P8S4lQr7lr5+fMDideHeb9yAYcnBGB24F3iqEO/HDEW
hN5c6RF/4GfvWCGJakXJQ58uB6jmqyyal6DwvifpnKc3o/x9WB7PtFkRMCHZZt4bqswLm79xg6no
z0if/97bN5NHex+oDY6Pz5Pp3U7RsakryFzMQoR6r8paAEP25V6MY56i4N8BI7+Q5xJedQW7nqHw
3ls45OvAvfrqNIGsJlESWzV/chtFeBDynfPqEnMfbnTodeU/67RKGUOB76wbFsR1zOtFiHMREvfA
H4aBXXOMIBCTqUJZYVZ/ebJ453godHlQsXpEPMVR8yuvux+ObCuRPm9xHjBAnJEgIKUvR1US9zNA
wEVyXxL9sdOzwHhb8ZXsewzV80wgcr/xSVgoVqwxAs83AwMu6YTMD2k0rTfm5PPez69bLvqhuqOJ
gV9TdPoadRxSCkUaphpWvVBPR1LYn++Mn1iVB/I1dIUjW2E4BDK3o30hJQ10/AD/T+bIAj2vM/jU
gBQXpK50UKBrq7CL56O4PgCQkVENYBbrOLJfZajkS3VRbFHNZ2hJcvvqiOx13ddzu6TtlfO06TEE
wz4yKASzqzZlB9pBUVlz2iuPWOjmvmfArjNE2bjak0i68nqmmfbGhhfaikfTrcC0C13lXkb5mopF
ad3O8sZ/LIZeFCuo4htjX3drGIvbNU+520StQqG6smxOZ3jkGGMKhrsuiRHpYzD/HgwT1svW6UEZ
uz1rkIAIbFarSzS0MxOXxGdkQXg9kTv1FM7ApH0cMh3IDOWCSkGwkJNzx+Ip6olB6LWrXH/Tj8Mw
yDNmydfwOnEgNo7XXFiTk+WCVQxDk5v7ZpniBbCJvuxj0S/qQoB9v7GAUW1wh9JKuy+blGHcOLFx
no3VYfDB/c0sEC+TUYsmzTCTWDPc5aBaq1NN5F6OvcCFIkCWrQirVLdVn1cOFizwHzM2xiK2PSMK
Rj0eWGMWIU9GsAi4z2+QuWCGuubHqp/uC0DZNmN4wz73xqbKRTL6vHE2MklkfGAgmI6mpjeHgTPI
NfyzsgOo9IJFl4Ybbmy8sjvhPF4CRzOm4W5dXbCENDDNGCby9BC2zy/tZ22ptW07QPEOIzdrJZ4D
nGa6NKkbFqHzQzvDSMRh9XaMzUJviRQcxRSo6D4NSVkiQH8ofjDZkbPnIXJTBVFn+r/892AnKkVn
XVUxQq6fGx1qIPUfX3XYRmmCPlfhZQawLyqLxxqwyPrFJCUIoPFKHRsKdm2Vtg1kr09HWqqBkJp8
bG22T3y9xCLPksFbcyLYbGJDavF8midXcUqgQourAjyCRACMJMcGhxf2nttDGVKLQ6tOzDAydMO3
8rOlyLX0/F/BZYmGs0aM38iB+WZhqWwY/LQriHDs4TFWwVbMQyas+XzS8qovB0bMkJtZDqYKadJI
ufsdijpxHvXl5+nDz7YBQl5h5aMoiA/efix4lduJt6cQpJu5CoJElBI2n1aJNMyrQZuZGSd11q4A
NROZiJqVYW1Je21yW1GZqtMQyknpvNJ+SBnb/7QSRLaRMIXHAVskRDKNkUlPjUT2LMeK7aV3MmMT
RgxkQ0lsb7qkt85rmbMBkVQLNsLnT7yW7haSIY4rtWBWl07tyibzYQzcEI85e8kwkfnoWKIbS7ow
r+nUac4cSO6D5qw3hcC+2qMrsK7VL3Gcv7qSsZsJoNzD4gsgRbUSWzLbX2nR0BxRNGGWjdexuRPm
Q1sH44qlbQwlEReI6+gEw8rc2C3FDXMAtCNXAStRWMu9xkCRX/Plq58NjoNrvO/s6+g8vXiN+tWr
ZvLlBPbdw3UIqAhA+ga+DSmYu5Hvaf7SR6IzEwX/HCnqGdZqPIE2wDoS4KjrZwMRXOmOwYNT2tuB
iJ3sOGr4U0WKdOXSbVoBcXhGFplcXetFUhe1SEO2AUBg/WeR+vvFGoNp2yM6DEDSEGJTLWN8gZ1u
1lz0p1LxqPMHB37CT3IuyBj4Eryut/9h6Kh4QLL6Cu0Ds1bhzOK4B4WQ71+Hd3iJwLuCfWMaImnW
TF0pFx+0gayHwS1657b0wv3b8cz4tHuN3No0JG7nE0jK41cfeYY43jNkGjciXM6FpKwCW9MK+OyF
AePtaPVEjc/Vsv0QszMUXgDLvskDTFUZcQEHrZYIzdLIq70cY7/d7gbMO2jY4xTNosAjh/SsCBse
qsYiNAsae5YisMsBPgxl4tDm8/ZPpb1oY8l9lfwZ9QdGQuHQtX/8UBEmF8DaLvFgNN7sX2lQirj2
cx2uxLeL0olnQUarrvarVCAeb+RZS5nda9e/O8mRt04KZj0a9HCl2dAbJydJ30T7NejUlxZhui6G
2J5ewTsImUeYI7rZmWWbQLqLVdt/IPTbdkT2BJbww6Bq6CA1nW16MYdjgbHu4KjAhGwiMsRUMwjS
hme6L62221l3mE8aGuX8zRpsTfIJPVbc6C+Mcb3IVgWxXkJK3c7Z1n1/IKBgMzHo9BNbqlZBLmC/
b6F18X2msSP6DF/K/5Os0vm8yFSUFwawPQzJN2go9vuEIudBZTy8JQ5jWbcL2C2XGlOD9aQJd1Ap
QTh4cHwG2p+GsMzazTK53deSJGhfrYd31pOSgxa7Q0mse7aSRt3HqZCZaPx4MxIsUdnyutjgWh6h
rxZLwNhW5S/70S6psMrs0XPdFtnEgqecyXp5aW51OwYb/9dr/MH17XbPyZeLAOaBADYh5y+zBzx8
rLen9JrNA9CEPQXMFTDTcLVjLC9whaPJTKklBeb5PTsm/wqWJ8BETQDvoYKfKxXKz8Wbf/qzYRcp
Q345mIg0495PEtj2mKO/XFJK4F6AJxyiupWMHOlNk8GZfXYK9YIMv2Q1DklQK2+tYi8HZEZhZhhM
NP+bJLbDe4YRMGl2EeTBrwEVwSM9O9/xPKaoI9Fvm13Jux0rGJuSBQRB1ACAyQ6AmeGbipwvT36g
hqIXnjQ2la0quJt/ss0EYItla7YKQQcZPcizoi9SpIWMotkJXjc6Fbw65xnh3P5YEzfc+YT/WsrO
AYT2T9Uwa57NvA45RSSWzUEUB6TwI+57KBaq5Nsl4VlQCHPSAhQsRtDJ/xkhKNumxdRMP+l8kQWC
MyZnNlAIlqNqHtf5deSMUHLYCMjMQj4JdB2CAJ9taeAdUFqMfxHFkAdK3nPWtcR8lJZmsHdzCK2c
nWN/9/09/kjcDxjORGG1Hl8wAbzlFlZ1doj+3tzL0t9HPK/zXmaNSl4ez6w1VWDCgob1D8q57iUI
lZMlVl7dB45qoeWK08FzG8Kl+Rw1s2x+COPxLzObLvkRCUjRuPLDln06jbisK6vXht638IhrrkzS
hCplvQr3a3MfYibEr2AEIQ0MMMunOisIl8/JBE7oh8CN9lpCeEECQ9jdAGLPKpEvF+KfWnIRbdq5
FPD5VM7hwBmS4f1AqnQbeGSpttJFTKpN2xutJsS1PTJA5NuFhOzNE9SDIrZR2g+Z5o4FMGKnSY9N
qXAElF6UWSRle3qwjCMRgkgj5uBeDsTCKf4OIaVUypL4mf4dIAk/TYRYm5HAE088urGuYVERt8lZ
W73pbGEJBuyUksZBG5rA9gjqR1pdDkxE+zpGyw61E1iiGreOWwTl1lx/BvUuFyTFQvGZjxXa09pr
DOaSrw1ss793geZiXSpkX2GRMBbO4+YPQFaKJqC/iIooWxjpwIZHBCQidpzCx4bKZ+2ufTOIVRTI
UhE+9F/kRGpigbNt2L4hiSScqUK1j0HMwN+7uPLrJs5jVg5WmCczeKIUBjQlM+mKWybvpluso+XS
0mfByhyunDhjAIv9DyYgfv30aPkvSTvcE3fg9U+X1S7Dnr/S/qM7diXpaI7UsP7vd9hBshMt5Kk4
B0dTMW9sJAi/8pFuwtYD2O8tP2ku5D7tC0jQaE1nK0N+CBiY/3F0v1RYhHZR89T/ZWfTW6+ZOkke
fNXOefpdlLaVwA1IaqCyHu70xlF9X+rxM15MbthF1+YHb4vJvQrxdBVxUpqrlQQR0CL0KOhZh43Q
vXNh/rjV4PAw+Tg2pTcwvZvvv6Zw1H0kesbSKI8aOC2V8tHzE5mlzVxS0KhMF/ppbVq2KeTplqPS
r+tsiWXurpG3gvna4eYVcUNOuJbgWM4CCJZpymoqCmU8Dhhb7DEjQl62hC/LLdvuSUIMxixtOOaY
BI5K3JdiIdOjFPP5+BZ4WVIuSulVQuVdP8o18oNF/3cXIo35TzRwVgHgf1YzAueFKWoYTwYizWWH
v40uSFz2UcTsXwVCRBONFl33WisU7qu6diIeApeizplwg/VouP0LyciomLs72MaoJ2p5vGGEQ1J0
+g2wN3IxdLOCRX9r9lCFiKmQxqKxRg3LWRBwc5zilSXuBpNdZfdYkkmvpPbdSIEF5N34uFRF8KXm
PjRMjCVU8KqFh1rnUemWZ3Q5W4JIPmVge8ACGGWhz1ZauJ3CEIFmHy69loz8w/BnnHIuLRz+4hmw
SwUMOOFzYHl7KEbwsSGDpbvOfHizK/7FYapdQHqq1mwD9cnLTeOddE9p19FVKXyEQF9uPpiOdtdK
Rg/Un30VyPKqUoHUncZZIJL0bqLsqTW9lQhFsW+1hP+KPLeoWMYRnndpqbrg9TdC2I4ISLLvMjGs
/VGshDmmbAQfdni1jBbzHqESuXuwzYnI3h7diO7JAhF3gxEiQL6saAxTXRv00yx6AWF/ZNChU3mN
H5B5wbo444Zz8ToXJR3NB/H96+Mo9VPqvVuL0FeamHPWqbaXewKqihGiAmjxw4F7gVOPbnGzvDY+
B7ieYMZ9S0ewA/OPJ2SKo/kt1G/PF20IWGQhsn9kMF6HNwZKwoGEtSlxr+8FoxXORzkHpsegXce+
nhjteRMrnTOcy0Rnp+Pj1Jc8su00TFPSaB9Fo3jgccYL2jl3GlcLhksHnoF85TnOro/14kwWwrEr
+cijdK8b+ILXnGrXgFdrHe7KhwnM2akScZRLh+3PSvB0WkRgeELZm21IonDZaXUKPOgF00N0QUBV
KhKp8Z/hw+2aUrdm0s+hcqIpAmV/mc+y483n7A4njPkZnOoc2Tgq/ItEX5mYxLS+q7M3TvfiWwGE
b+t4VHzl5dvWKxFqaB+/t2DaEBVtlYa+Ma1TPqG/XO3eVvo8qwihF/qNV//VSmx4jzDzUkXiDlag
SkhXVhtzHpjvhib2BO572ywjs+EPrMYrtreSqPed92feJoOTIwmOcvt7x3gbRgzjLv1NGRajQ9Pa
mI7CPr2KZJz/G8Y9a0UxUqnq4b7mKMhdfZoK8+rlp5G6Kv6wTQjVJCuZBioAdrRYKV+L1zauTSTL
Zt7mdUCoyoNCvoGmo+uUh0QtS4w/30AeOv284x3ijrDDdpEwzkDeKcda17E/4CNTTQzmZQ73A7nz
nE9PC+znNpQ0qOXPkJa7VSb8XtnZUTCynQYNDS2Kys3iaJWQzc37PwY0xrIGxe6xL/AzGHtuwXj6
aYED7MuzYYe5inK+R2ojXUd3Ys7ZGOLZlt8Ebn5jFj5Kaf0sqWwZgSkrrMhemr0edh8VzQgeKMDx
/1nZQPxb09Q87u0bf8IZx22YI7tUl1IALIodY5rA0qAzoQan9cRUqLv/rERGbZq69kzNCQ8k9W1Z
EoQwLKerp4mwhvMjLwZQSPfM9qKtWqzGjSVtumLgrqTOKqH8COcCkLLD4YPQ7VU9swQRIsdUx6EH
2NNYfbHEKiVfdxS6mGqvZo+P+B86tnOM6oTWqiHaJgd++ngkO+htC6+1RuxnSq0T5VTyJ9LhqECi
B6FmR3s2ITzi0TrLmautQruSDAJSWnND12b9nFti+eyHHtA83o8EjIShGv0aL5o0Qw4sXql1GORm
2FkMC9OgYfROlshRftA4Mux3WBASw2HVm63xIvRz0pUihsZhpDesH8wvEDOMKhb0Y7AOzEITHrBQ
Yw2U8sZZLikMLmRZ1fLjHJMPbLl1edz1u5HHAJpNnLpMuHfz10S4qcU2XJhx/+/gmr5BQp/BHTXX
9QwjcjumRhNFL1u/t41ESl02Mr3yTug8btz2yatGBzgo6he3JJPmTpZno6MhFGHkhYYTTbaUfyH6
8WjTfCj9fiVGQgfm+gAyuAWy9eJCegZVFfWBfEjifkbeHr7jP3SKjuZ3vyQzmanuBzv9CIGkhm8n
fN08LWc+O8UhXIVAa1EPxiL0C/pbG27iTkWns7Y6FsZ+NgOzMYtLZcdfzfoRiG1Lu/Z9c37xQbCB
9wmakXzaHiLfA5SQvYr3n5/FV2cMbs1+cpVp3DKMC60CZyw/Nn5TERHQfXu24EA3nYBhQl4LSoUK
GuGiidcnu6d28KPQ74uMql9GTBlj4UmsLPOPlTZMc+HjVtUNKQaWZfZ7JFVrlbIKKUr1hU+KQ0pq
SN3InBuYE6HcYxu7yO0NQvJOArrMUX5pOYgSOXNGNA8mQ27nME+PECK7yO2TfDnJaC5zZJ42lzKU
LAxyOvofxVAy0ybl9R6MQ+MnGKk5RWdmq8tUz5L0xfZE2Vorkj0pRl+3u2KNgA20c70hxgL8SSS4
J6Az+gPxjBy9PVo2oEoacdbBCv2+w/XaM4kjMefw2+wjdxCjvCO5kxcDR+CoQ96dG9EN0rXIBh8s
Ksar5FNuetAsoGk4lenpr5EysN3jjgVDMDyqYl8hVYAYzTwwCQD6hxKW+5JNLUe2sZGChXJgZQJm
J05y3hg53M9+55yKYG3DkhauBbp/hOb6XgwagX/ZVO+qMVHRI6schwbDsgK6+yFhb/o5OPt3H1kd
pGaYhmRNbhwbvi7EwA/NYqLjcGxVBzHWEgiNuJIilg/0PHmcJhrrjGeiLHaoP/vElTlGYLshelQA
c2FNRKxKzwj76+TB2oXsx1ynMopzsHBMQ+cdCboBu+8q9MaUZxYtASXjL9muhpR+CS2LqgUi+EmN
nMGVfF64S+e2WZ5qQYcwt3a0f3Ua/ONjeN0xYsLIsfSZv92lvYnJm2nVS47rzQNBaBF6yLGM5aSn
Z7nhQbN2iaMUo+kpmR4g3t3eWLipuDf8GePQy2E9tMoS9Xiq8AmRikLhmg/lRv0dFEbZNWxf7yV1
udvFBJ1ne1ltbaR8+j4awA85PNA1tTT3lTGGLW7OCWElrYewb+0i4oeFfrPSlaij29NOFwmnggzv
M2oqvFQSeDpHX4sXwyHaxv02fXSH41Ao9LNtcI/A0OIbd/zyAyYCPJZQdMXL7woWXyeLIpdgriq3
oqrtHpGT/Il1SfUJ6H5nXgmF9boUUzdeVweusJpON8TMlCeHapTNWfPOHWuatyVMwm42DlSZ4837
/mbqmSmWvbsSAQKBYoAKMQl2fX6OFJIRSaI+BKVeVR+Tx94Jyrg4NSw8B7qwWwgh+WfiU1lvR9WV
SeH9FwQqYqKh77pIerxVKD7DHE9rLWjsx0nlXod9CkYTHROK4jFpZEeJpeNhKuzMlOUdXcRNlQy5
ytJ16fEDeybqoaQEXMdWDg1THXdt5oJnWORlw6xWaJk/vYZXpwVyjh+n9TWoR+AbKcaiW5PwTAMl
gs8lmvZui+C+HRKKeIgSis+1naT5qmpZQ1TQeKnNpTkqcUqWJ0x2pqwl/XnqRIqvaevd0WU3sOUT
oh7H8KT3B19u96rjdfQevoBwe43sB6mVG3n+If2fyB3MQaxf4TJobnJbEE3ZLZULfqZZYGnpQDRG
3yeoA73SSrb2G/xY65Ozof4kvbGyKW1JvrXvFpShsjF0iX9IDZfMGi8Hf5N+Eanr1KBORKjJCiuu
snlvuyY8i07SJfnq47VkBVbKkGSxGHKfV35pTshMnBDh8j5jb/Bd3vgYG3oJGbVZA96e2vgyhHjs
5X0EGPM1IIUQExtEAv0gWLZ8rJVh1Ujq2UpRsndgbvHXyilhP2GGeJgLPY4tDhEbj35ZE5nrsPPI
0+97JN6bgHdiHhJrukV+asPxsVPX2M7DtGC2xO9WQ+5D0oLXF/dXqM1LbTmG6gAkfAp94TKcWwAJ
JyRCiQe6ETaaPgBQoQOwd1A8+nMc3dyejKN75LlOdK60eRgXLv9W4pJE+C+Ps/r/AS3RTnoDGfuW
UtB3LkVStqO/GO06Jz4dx2R+NL78FUVx8KFx4CYVmduZW0sT3X56BDK9IVZxOrgRr1d3ExO5/HjS
R6y4BjMBluw1+NjjL0NuDG8k5FNU+8ksehgQjIJjQUufyVB1H8p/A3eBKFxuwJChXif5yE4pCaYB
Zgp3E3kkzYFMFmd3sFCyBFDZp8ikE9jreBik3MwtoCfjE7NUiL4Df4A31+RHOauGnKf04vX6FnOb
3FcGKe7ZX3hSkVr0WLSDWZTC7INzFRSPfAG9U762KIt7B3+bLe7434yUG+Y5alSEwKJrVSJvMwjF
7Y+lNfrmaj+nVGxDQMbF77pXGRLH40LOeHrJGDhRzR7zJsfgWT+HzIcu7kZv2XlhDbyNKzliPzwY
+voncYJCgqt6TpiFZk33FhauK6jrGa2gMcjqO6mRDKkj+rdASAdpUkGMsrfr5keeiCoMeA6ECw13
pHPveF+wE8hCHQ9T0W68AAEPON8EP79qn/iUx+5Mln+RogU7vsS6niphAh/nv1X4lOpalYrnUApy
PydbSf5woV3ivXXlDzSBe2b1TUiVJ5/1N8BIPrap0iwEy1fNAE6vJ+Q5qDB5JTY12pfBt6rKGMUr
kN4RlujoztfOrZeUJUuesRnWea5LHozRltO/gYyYB2l/18XEZWKaNxuV0akPD06ltAAbc+js/4L0
dgVg49MRk7IkyKmrW7HHBf+INVpTJZnh1bHwOD2KMtHjI/v9bUF9mwybauHV8agYKZ3hXWy/qaEn
ZTpcJyyqUNOH3rCy4Bq3ZRu0amz4yYMbryY3iKf6+eLVHoCzFDnCYpaaR/4uzTjSRArh4sjC18dv
WAl/TQmTUHc52vO8HjdhV24VDIJIs2M1rIP9WqwLDKoCAVkcvnlbMnx1iDmluoSw14S2Q5HkjeBn
dWQ3Q+9XIAMfMT0u6qGFelJ0q97D3yfYwZ1fNvSC90GcRNKwJLU8t8wwBTAnAuJN6VGLTFq7mAAA
sZI4BzsM/ZOoZmHw02gOVrIZyW93Am8Il9IYecYRTvCvr8jgAQ7AruNDE8VSbNGqi1A+YZv7Gkl9
ktVrjhLbJOsIZZKWJkrN2qs/skXGyT3wmZ+lKLEKGnMEuGlTfLnIGX+XSX56OlL+W2rz1A4WqHML
GsgZu4RpCkP2pTjT74yA1RAoAqCERI3bvwwUA0f0dpMrf4bDBX474XI0IvuOfv6aiNxHEAXuRUc1
J3i15zKLjRiZUr4bSu95qjN0jURU0qreCKNO5JlzxL/Y92zw9DQfd4ljE/IBpVkO2Vz8vCsnhLv+
2tWyh1DEj1ouGjapASQbjx1F/BW+F/GzK10rvs1rKKujCzVwxXoQ0sb5oXdz3hywRmubx9KjqiCb
6gO7agjC27lKXiHH6tvA/Jmdf/PtiyWEHSLpe59+tjNmh+BJfdEX0TzOR2F1+U/vhTS1N//nW8yW
Pwf1kvQh6vEjeF5xB+/DdEe1Xd+3FZIHfkAlTYyvQzTQPM3NGnIZSpwCOTwpHtylh9aGyIHcUTRl
vtc+7eVEXhMfd0Fcq/i7+ZS4Maoe8VXrhjSn73MP4N4TPSq6dV07Sr8nSTuTNvHkQhqOBA2VnDLh
ryVyLqcCSdTz3ACSD7alIhRU/Bm+43MfJ8DCbDFy5NVgjwpBq5RyP3RF71UdO8ZwdE/JGhLPATbs
aeGHyT+iGvXkFA3ZyxjCOxY93vK0NXn71FJhm8bqdsJlq6FCQDKLBc92A6OyRXcHTC8Y3kS+CKCS
Vz9H0f1dP7aB+GqI+wNWXZcF9ebAcB9+hzn7G8qXPKbv2FtTmXw4qcMLnMAoK4GMMKXyyKorY9bV
0wnwtWqXqhylxvwW7xbGB+Gjnrpy9Sl04Hd0heBFZ8MlWxHUinOsb9YVk1AIwm7grGbzenhwPOEe
YWloiZwskQs+JjOpuYARMipzMF1u4QG8LlZqPYsx2QuAs2Xuw4TNoc/uNOJGdppRNuZ6Fp/VCCJA
6wnmkcd8LHLnadq/OqH1bvtmvW4TaNr3rMpmj7IlwgxJf4OtZyHfHXGIFRRZmWCdLCY2NSqx3Epy
ujmjmwqxTEk6Hdv7HiXAnPR1J9h7BrPDAOol3TLhTn2xeplhepxSPxfhfHotM+uDFmwulshhpZy6
CQA0y+HFa8dZYP/CbHICo6i2abm+yeUK0YZC82ITvmNxHysoIByv+JAwxPpkFtgESWwKYGeguK5m
pOJow+h2sPpIR5TbF07LBw0KYWTL1UgVOaViEJbNAp5b/L0AiDjqClmyZ2kYphxmdWiRlCNSFCib
h8awDuSkzsJUT0IdxA53ymZ8zZHkQjsZV/le6T2Qkdyv9uRzKFetxEgA3/BUMMksoz0oxqLBLVoq
aUSq0SkSZK2VjR+mdKzg27jXSRzevVzvdFoQO3xkQ8Ya4nwBmdwK2N0XW0JThw9nnLUgD2p8lIYk
PZCbeUD2ZTcoS77OnhHx62ZuMiqitvWl0LlZM7QeuvkZO09+Ervl+C29raIupGbiWj97PT4ySpGr
gjfudvAFZAUnnB8ougIkn8DgsQETkvbuDsSqqUSbDpOxQstlrSeRwFOWf1hvd6ACan2iy0b6qM1r
LlJ4RD6XhYW2rMZYFKvqjORwHSn8hXM4oM9kwHLKOYSENgoIrzlKEN0Z0acrgiDieiI1qVfaa5Bz
wJoF4AuHJGrLDuj3z3ZXc5EILJLBOO9+tSfqOfwv4CY2T7cK6TGh+OoKzP34WbaW0GgIhiuOpxF7
8BzlzxqnJOOFifDdx1g5bzNvTe2q8G96Y5sNBNiWO7JfayUOWETYXqzcXl4SclyIb8Xgxb+71SDn
DQ7hPyEMEfULc0EbqYi55/PiLwvkGGOnbLx/SE260lkU1u313Elf5AaJR99ZZyZEC1Wr3ZMj3ifG
mLyzXDMPm0BsEu/81YKdGwBwKE9m9IIEdX+krXuIbFeLoXv8j/gAb7JPLGoEs5RFXQGGCQHI4H1L
z6q2KsEzOZ3rWTZmC4c8i+6IndxymrLXqPx06rV4lraoTWw5PfBugeUm+pJ3ydZH1bnjgBEkJc6B
ElZuCmtzjFSDVZFfNJCG2DzW+J52hFDTewQL2gcJNszLKHXA8lbrYSZ85VK/2gye961a8RLqmfEJ
6Pupm0I6og2I6Y4OlzakAQn3Qd1OeqX1PTBW96FwuxPFT0MC1G1HW1AGGZ3SgV81Y0fGuDReuNCo
8wIeUPUqPcX/iS3CX/qcxW5+kqKiUoTpZNd+kXZoZglXaM4CCvLHEEbES2UhoflAJJ9u6nwmxXJt
l1BPpn/l3gp1XBwA//dFuOGXqht7V6ZYL1mMPQrH8m6rD0KdjGF+/RYT3WnVaBwbIUEdCJCUvSBL
CtC3q/PUgSITYYsY0sa912aaOKfH8n9L5F2TmkyQgNbAD5HDICnZZNeN3gUOk5g4Uz8ehqYAIK9b
brvJeTjovR4XbevLQGqYgNQ+E4eNzyEduD6HHVYTTBmWWx4adQ9KxNKp1A5Sli8IvIkzmtb53vH7
SUSHGYPDznAeRDZEWQ44i4fazvibstJpbv/qgeCq8E6dVRdz1d3HT/h4MDpJALiRsBRxRQ95o+9Y
7tlXhDGSt1rKVMdIdcWyHHgLfgCk2JLpUVX3M7ejg8/8Qwd8K4OAuC80sy++e2MvDSqaQUbpUtdh
LUGTAZ1WZBz6HnSoYc95Uml8YboICsEKDN3YiyhO8hgYOHLkoDH5n7QEGrzBZr1CoDIr91lhqy/Y
DuRJX0EfmVRBVIlUwp9C6ilTbJ0/FEbOZBkLetLnXR3mL6HQzHaxcObW+cXsYAQtVgn0qIy9Kvy9
JIYOnUaa89kzV9DuylgH92gK4rwcaTO2zh2mA1Ek7ZPBwnT4M2ieY+BeEl6TJTX6b0bVWlYfbMuc
0pAJ9TrwZ4Nnn1W53pLpvI2twSanR6qZ6XM1H2IDlZOc8msmlniqA8vqz7Vzw3yfml/+vUsie9P7
+7A5EZaUIHJtj7JWj4F9f3GMrIdI2h92eXKLvaSRl5CaBtC1ABWeJ6ZP7f1q1QhsgeZrZjGtXfco
90Z9jwhvAR4MBaa6V3n9lF2M06kypDXmFqjns5gnmAlbMnMjX7kZlz6GQkcDglCA0h2qS0QbTir5
OKdZgHMXNt/gnIArLDLaDkx1zHYCqAe0sAP88EoMMbmQ+ekZis1UkDxpT+5biK9Ketk/So+YE03k
kIx0TLgP83kkCbFgk7xzvFJgFZ1nT0osF696qzJjNT/AkhY+tsCSqLQY/OJb/RH3979SgjsH/BMl
GNup9MknMraWAWQVtWoOU2sgj4fbObP9ULKCBZelXCzuU/8lY2E5t2xHaHcz9Aew4pE6oOQAAM6D
QLPH+fe6fzTCxZp0RfQWSJT2RLI7Xh2u++M2BH84LU7M/rIoTP1fCrkqZ42uc+lppQLapdvXR5vq
FsnO9KAWageY0m6uU8FrG1Gln2u+RoRLkYRP3ovLMvfTiFgKhd4bW3TmLa36FiIFVAG7B8XixeRp
Au887sK9eF5eHrbDeTgkoar4jMHfJSTmzrh5XBKdX15ILQFgkpxxu0Uwkc56wN775hgpAOhNQnxR
/htKW8urRyLLvhH3ElJiRJ5+11lxqKhWPb6eYyXE8PZ/U/KYv13gJVO30FnqR9DFBVWQiUSJ
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
entity key_permutation_1 is
port( key: in std_logic_vector(0 to 63);
permuted_left_key: out std_logic_vector(0 to 27);
permuted_right_key: out std_logic_vector(0 to 27));
end key_permutation_1;
architecture behavior of key_permutation_1 is
begin
permuted_left_key(0)<=key(56);
permuted_left_key(1)<=key(48);
permuted_left_key(2)<=key(40);
permuted_left_key(3)<=key(32);
permuted_left_key(4)<=key(24);
permuted_left_key(5)<=key(16);
permuted_left_key(6)<=key(8);
permuted_left_key(7)<=key(0);
permuted_left_key(8)<=key(57);
permuted_left_key(9)<=key(49);
permuted_left_key(10)<=key(41);
permuted_left_key(11)<=key(33);
permuted_left_key(12)<=key(25);
permuted_left_key(13)<=key(17);
permuted_left_key(14)<=key(9);
permuted_left_key(15)<=key(1);
permuted_left_key(16)<=key(58);
permuted_left_key(17)<=key(50);
permuted_left_key(18)<=key(42);
permuted_left_key(19)<=key(34);
permuted_left_key(20)<=key(26);
permuted_left_key(21)<=key(18);
permuted_left_key(22)<=key(10);
permuted_left_key(23)<=key(2);
permuted_left_key(24)<=key(59);
permuted_left_key(25)<=key(51);
permuted_left_key(26)<=key(43);
permuted_left_key(27)<=key(35);
permuted_right_key(0)<=key(62);
permuted_right_key(1)<=key(54);
permuted_right_key(2)<=key(46);
permuted_right_key(3)<=key(38);
permuted_right_key(4)<=key(30);
permuted_right_key(5)<=key(22);
permuted_right_key(6)<=key(14);
permuted_right_key(7)<=key(6);
permuted_right_key(8)<=key(61);
permuted_right_key(9)<=key(53);
permuted_right_key(10)<=key(45);
permuted_right_key(11)<=key(37);
permuted_right_key(12)<=key(29);
permuted_right_key(13)<=key(21);
permuted_right_key(14)<=key(13);
permuted_right_key(15)<=key(5);
permuted_right_key(16)<=key(60);
permuted_right_key(17)<=key(52);
permuted_right_key(18)<=key(44);
permuted_right_key(19)<=key(36);
permuted_right_key(20)<=key(28);
permuted_right_key(21)<=key(20);
permuted_right_key(22)<=key(12);
permuted_right_key(23)<=key(4);
permuted_right_key(24)<=key(27);
permuted_right_key(25)<=key(19);
permuted_right_key(26)<=key(11);
permuted_right_key(27)<=key(3);
end behavior;
|
library ieee, base;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use base.base.all;
entity LeftShiftTests is
end entity LeftShiftTests;
architecture TB of LeftShiftTests is
component LeftShift
port(c_in : in unsigned(3 downto 0) := "0001";
c_out : out unsigned(3 downto 0);
data_in : in unsigned(3 downto 0);
data_out : out unsigned(3 downto 0));
end component LeftShift;
for uut : LeftShift use entity work.LeftShift
port map(c_in => c_in,
c_out => c_out,
data_in => data_in,
data_out => data_out);
signal c_in : unsigned(3 downto 0) := "0000";
signal c_out : unsigned(3 downto 0) := "0000";
signal data_in : unsigned(3 downto 0) := "0000";
signal data_out : unsigned(3 downto 0) := "0000";
begin
-- Unit under test
uut : LeftShift
port map(c_in => c_in,
c_out => c_out,
data_in => data_in,
data_out => data_out);
test : process
begin
c_in <= "0011";
wait for 10 ns;
assert_equal(c_out, "0011");
c_in <= "0001";
data_in <= "0001";
wait for 10 ns;
assert_equal(data_out, "0010");
c_in <= "0001";
data_in <= "0010";
wait for 10 ns;
assert_equal(data_out, "0100");
c_in <= "0100";
data_in <= "0010";
wait for 10 ns;
assert_equal(data_out, "0010");
report "Test complete";
wait;
end process;
end architecture TB;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: 64-bit SDRAM memory controller.
-- Supports HSIZE_DWORD AMBA accesses when connected to
-- AHB data bus wider than 32 bits.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl64 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl64 is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant REVISION : integer := 0;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL64, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(3 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 1); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec0 : std_ulogic;
variable adec1 : std_ulogic;
variable rams : std_logic_vector(3 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(63 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(63 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(63 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
-- lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
lline := '1' & not r.cfg.casdel & '1';
v.hrdata(63 downto 0) := sdi.data(63 downto 0);
-- Select input data depending on AHB DW and AMBA data mux settings
if AHBDW = 32 then
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
else
hwdata := ahbreaddword(ahbsi.hwdata, r.haddr(4 downto 2));
end if;
v.hwdata := hwdata;
-- AHB access
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr;
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(2 downto 0) is
when "000" => dqm := "01111111";
when "001" => dqm := "10111111";
when "010" => dqm := "11011111";
when "011" => dqm := "11101111";
when "100" => dqm := "11110111";
when "101" => dqm := "11111011";
when "110" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
case r.haddr(2 downto 1) is
when "00" => dqm := "00111111";
when "01" => dqm := "11001111";
when "10" => dqm := "11110011";
when others => dqm := "11111100";
end case;
when "10" =>
if r.hwrite = '0' then dqm := "00000000";
elsif r.haddr(2) = '0' then dqm := "00001111";
else dqm := "11110000"; end if;
when others => dqm := "00000000";
end case;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 11);
when "01" => raddr := haddr(24 downto 12);
when "10" => raddr := haddr(25 downto 13);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(27 downto 15);
else raddr := haddr(26 downto 14); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 21)) &
genmux(r.cfg.bsize, haddr(28 downto 20));
-- generate chip select
adec0 := genmux(r.cfg.bsize, haddr(29 downto 22));
adec1 := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := (adec1 and adec0) & (adec1 and not adec0) & (not adec1 and adec0) & (not adec1 and not adec0);
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 1) := ba & raddr & '0';
v.sdcsn := not rams(3 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 1) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.dqm := dqm;
v.address(14 downto 2) := r.haddr(14 downto 13) & '0' & r.haddr(12 downto 3);
if ((((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))) then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "1111"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "1111"; v.dqm := (others => '1');
else
if (ahbsi.htrans = "11") then
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "1111") or
((r.haddr(5 downto 2) = ("111" & not r.size(0))) and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "1111") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
else
if r.size = "11" then v.address(9 downto 1) := r.address(9 downto 1) + 2;
else v.address(9 downto 1) := r.address(9 downto 1) + 1; end if;
v.casn := '0';
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0000";
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
regsd(16) := r.cfg.mobileen(1);
regsd(15) := '1'; -- 64-bit support
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd & regsd;
else
dout := r.hrdata;
-- Possibly duplicate data for reads < HSIZE_DWORD since the system may
-- not be fully AMBA compliant and other cores may expect that the valid
-- WORD is present on 31:0 of AMBA HRDATA.
if andv(r.size) /= '1' and r.haddr(2) = '0' then
dout(31 downto 0) := r.hrdata(63 downto 32);
if r.hready = '1' then v.hrdata := r.hrdata; end if;
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
sdo.cb <= (others => '0'); sdo.ba <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.oct <= '0';
sdo.qdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
sdo.dqs_gate <= '0';
sdo.nbdrive <= '0';
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address(16 downto 2);
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data <= zero64 & r.hwdata;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address(16 downto 2);
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn(1 downto 0);
sdo.xsdcsn <= "1111" & r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data(63 downto 0) <= r.hwdata;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl64" & tost(hindex) &
": 64-bit PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity debayer33_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
bayer_code : out std_logic_vector(1 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end debayer33_slave;
architecture rtl of debayer33_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant BAYER_CODE_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal bayer_code_reg : std_logic_vector (1 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
bayer_code_reg <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(BAYER_CODE_REG_REG_ADDR, 4))=>
bayer_code_reg <= datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= (0 => status_reg_enable_bit_reg, others => '0');
when std_logic_vector(to_unsigned(BAYER_CODE_REG_REG_ADDR, 4))=>
datard_o <= (1 => bayer_code_reg(1), 0 => bayer_code_reg(0), others => '0');
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
bayer_code <= bayer_code_reg;
end rtl;
|
------------------------------------------------------------------------------
-- Title : Top FMC516 design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the FMC516
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-25 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_fmc130m_4ch is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
rs232_txd_o : out std_logic;
rs232_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------------------
-- General board status
-----------------------------------------
fmc_mmcm_lock_led_o : out std_logic;
fmc_pll_status_led_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
-- Directional leds
--led_south_o : out std_logic;
--led_east_o : out std_logic;
--led_north_o : out std_logic;
-- GPIO leds
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_fmc130m_4ch;
architecture rtl of dbe_bpm_fmc130m_4ch is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 9;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
--constant c_masters : natural := 9; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon
constant c_masters : natural := 7; -- RS232-Syscon,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
--constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- FMC130m_4ch
constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"30010000"), -- FMC130m_4ch control port
8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
signal rs232_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC130m_4ch Signals
signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc_mmcm_lock_int : std_logic;
signal fmc_pll_status_int : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
-- fmc130m_4ch Debug
signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
--clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n and rs232_rstn;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
cmp_xwb_rs232_syscon : xwb_rs232_syscon
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rstn_i => '1', -- No need for resetting the controller
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rs232_rstn,
-- WISHBONE master
wb_master_i => cbar_slave_o(0),
wb_master_o => cbar_slave_i(0)
);
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(1),
r_master_o => cbar_slave_i(1),
w_master_i => cbar_slave_o(2),
w_master_o => cbar_slave_i(2),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
--g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
--g_must_have_init_file => true,
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(3),
wb_master_out => cbar_slave_i(3),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
-- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
-- The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(4),
tx_ram_i => cbar_slave_o(4),
rx_ram_o => cbar_slave_i(5),
rx_ram_i => cbar_slave_o(5),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(6) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(6);
-- The FMC130M_4CH is slave 7
cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_int,
fmc_led2_o => fmc_led2_int,
fmc_led3_o => fmc_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0', -- Unused
fmc_ext_ref_clk2x_i => '0', -- Unused
fmc_ext_ref_mmcm_locked_i => '0', -- Unused
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc_130m_4ch_clk,
adc_clk2x_o => fmc_130m_4ch_clk2x,
adc_rst_n_o => fmc_130m_4ch_rst_n,
adc_data_o => fmc_130m_4ch_data,
adc_data_valid_o => fmc_130m_4ch_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_int,
fmc_pll_status_o => fmc_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc130m_4ch_in_array,
wbs_source_o => wbs_fmc130m_4ch_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc130m_4ch_debug_valid_int,
fifo_debug_full_o => fmc130m_4ch_debug_full_int,
fifo_debug_empty_o => fmc130m_4ch_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int;
fmc_pll_status_led_o <= fmc_pll_status_int;
fmc_led1_o <= fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
--led_south_o <= fmc_led1_int;
--led_east_o <= fmc_led2_int;
--led_north_o <= fmc_led3_int;
-- The board peripherals components is slave 8
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => '0',
uart_txd_o => open,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(8),
slave_o => cbar_master_i(8)
);
leds_o <= gpio_leds_int;
---- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_4_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3
);
cmp_chipscope_ila_0_fmc130m_4ch_clk0 : chipscope_ila
port map (
CONTROL => CONTROL0,
--CLK => clk_sys,
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- fmc130m_4ch WBS master output data
--TRIG_ILA0_0 <= wbs_fmc130m_4ch_out_array(3).dat &
-- wbs_fmc130m_4ch_out_array(2).dat;
TRIG_ILA0_0 <= fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(47 downto 32);
-- fmc130m_4ch WBS master output data
--TRIG_ILA0_1 <= wbs_fmc130m_4ch_out_array(1).dat &
-- wbs_fmc130m_4ch_out_array(0).dat;
--TRIG_ILA0_1 <= fmc130m_4ch_adc_data(15 downto 0) &
-- fmc130m_4ch_adc_data(47 downto 32);
TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse &
adc_dly_debug_int(1).data_chain.idelay.pulse &
adc_dly_debug_int(1).clk_chain.idelay.val &
adc_dly_debug_int(1).data_chain.idelay.val;
TRIG_ILA0_1(31 downto 12) <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA0_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc &
wbs_fmc130m_4ch_out_array(1).stb &
wbs_fmc130m_4ch_out_array(1).adr &
wbs_fmc130m_4ch_out_array(1).sel &
wbs_fmc130m_4ch_out_array(1).we &
wbs_fmc130m_4ch_out_array(2).cyc &
wbs_fmc130m_4ch_out_array(2).stb &
wbs_fmc130m_4ch_out_array(2).adr &
wbs_fmc130m_4ch_out_array(2).sel &
wbs_fmc130m_4ch_out_array(2).we;
TRIG_ILA0_2(18) <= '0';
TRIG_ILA0_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA0_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA0_2(24) <= fmc_pll_status_int;
TRIG_ILA0_2(25) <= fmc130m_4ch_debug_valid_int(1);
TRIG_ILA0_2(26) <= fmc130m_4ch_debug_full_int(1);
TRIG_ILA0_2(27) <= fmc130m_4ch_debug_empty_int(1);
TRIG_ILA0_2(31 downto 28) <= (others => '0');
-- fmc130m_4ch WBS master output control signals
--TRIG_ILA0_3(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc &
-- wbs_fmc130m_4ch_out_array(1).stb &
-- wbs_fmc130m_4ch_out_array(1).adr &
-- wbs_fmc130m_4ch_out_array(1).sel &
-- wbs_fmc130m_4ch_out_array(1).we &
-- wbs_fmc130m_4ch_out_array(0).cyc &
-- wbs_fmc130m_4ch_out_array(0).stb &
-- wbs_fmc130m_4ch_out_array(0).adr &
-- wbs_fmc130m_4ch_out_array(0).sel &
-- wbs_fmc130m_4ch_out_array(0).we;
--TRIG_ILA0_3(18) <= fmc_reset_adcs_n_out;
--TRIG_ILA0_3(22 downto 19) <= fmc130m_4ch_adc_valid;
--TRIG_ILA0_3(23) <= fmc130m_4ch_mmcm_lock_int;
--TRIG_ILA0_3(24) <= fmc130m_4ch_lmk_lock_int;
--TRIG_ILA0_3(25) <= fmc130m_4ch_debug_valid_int(1);
--TRIG_ILA0_3(26) <= fmc130m_4ch_debug_full_int(1);
--TRIG_ILA0_3(27) <= fmc130m_4ch_debug_empty_int(1);
--TRIG_ILA0_3(31 downto 28) <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
-- Etherbone debuging signals
--cmp_chipscope_ila_1_etherbone : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--TRIG_ILA1_0 <= wb_ebone_out.dat;
--TRIG_ILA1_1 <= wb_ebone_in.dat;
--TRIG_ILA1_2 <= wb_ebone_out.adr;
--TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc &
-- wb_ebone_out.stb &
-- wb_ebone_out.sel &
-- wb_ebone_out.we;
--TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack &
-- wb_ebone_in.err &
-- wb_ebone_in.rty &
-- wb_ebone_in.stall &
-- wb_ebone_in.int;
--TRIG_ILA1_3(31 downto 12) <= (others => '0');
--cmp_chipscope_ila_1_ethmac_rx : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => mrx_clk_pad_i,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--
--TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i &
-- mrxdv_pad_i &
-- mrxerr_pad_i &
-- mcoll_pad_i &
-- mcrs_pad_i;
--
--TRIG_ILA1_0(31 downto 8) <= (others => '0');
--TRIG_ILA1_1 <= (others => '0');
--TRIG_ILA1_2 <= (others => '0');
--TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_1_fmc130m_4ch_clk1 : chipscope_ila
port map (
CONTROL => CONTROL1,
--CLK => fmc_130m_4ch_clk(1),
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_0 <= fmc_130m_4ch_data(15 downto 0) &
fmc_130m_4ch_data(63 downto 48);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_1 <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA1_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(0).cyc &
wbs_fmc130m_4ch_out_array(0).stb &
wbs_fmc130m_4ch_out_array(0).adr &
wbs_fmc130m_4ch_out_array(0).sel &
wbs_fmc130m_4ch_out_array(0).we &
wbs_fmc130m_4ch_out_array(3).cyc &
wbs_fmc130m_4ch_out_array(3).stb &
wbs_fmc130m_4ch_out_array(3).adr &
wbs_fmc130m_4ch_out_array(3).sel &
wbs_fmc130m_4ch_out_array(3).we;
TRIG_ILA1_2(18) <= '0';
TRIG_ILA1_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA1_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA1_2(24) <= fmc_pll_status_int;
TRIG_ILA1_2(25) <= fmc130m_4ch_debug_valid_int(0);
TRIG_ILA1_2(26) <= fmc130m_4ch_debug_full_int(0);
TRIG_ILA1_2(27) <= fmc130m_4ch_debug_empty_int(0);
TRIG_ILA1_2(31 downto 28) <= (others => '0');
TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_2_ethmac_tx : chipscope_ila
port map (
CONTROL => CONTROL2,
CLK => mtx_clk_pad_i,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3
);
TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int &
mtxen_pad_int &
mtxerr_pad_int;
TRIG_ILA2_0(31 downto 6) <= (others => '0');
TRIG_ILA2_1 <= (others => '0');
TRIG_ILA2_2 <= (others => '0');
TRIG_ILA2_3 <= (others => '0');
--cmp_chipscope_ila_3_ethmac_miim : chipscope_ila
--port map (
-- CONTROL => CONTROL3,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA3_0,
-- TRIG1 => TRIG_ILA3_1,
-- TRIG2 => TRIG_ILA3_2,
-- TRIG3 => TRIG_ILA3_3
--);
--
--TRIG_ILA3_0(4 downto 0) <= mdc_pad_int &
-- ethmac_md_in &
-- ethmac_md_out &
-- ethmac_md_oe &
-- ethmac_int;
--
--TRIG_ILA3_0(31 downto 6) <= (others => '0');
--TRIG_ILA3_1 <= (others => '0');
--TRIG_ILA3_2 <= (others => '0');
--TRIG_ILA3_3 <= (others => '0');
-- The clocks to/from peripherals are derived from the bus clock.
-- Therefore we don't have to worry about synchronization here, just
-- keep in mind that the data/ss lines will appear longer than normal
cmp_chipscope_ila_3_fmc130m_4ch_periph : chipscope_ila
port map (
CONTROL => CONTROL3,
CLK => clk_sys,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3
);
TRIG_ILA3_0(7 downto 0) <= (others => '0');
TRIG_ILA3_0(31 downto 8) <= (others => '0');
TRIG_ILA3_1(4 downto 0) <= (others => '0');
TRIG_ILA3_1(31 downto 5) <= (others => '0');
TRIG_ILA3_2 <= (others => '0');
TRIG_ILA3_3 <= (others => '0');
end rtl;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
signal data_in_toggle_sync_vec : std_logic_vector(0 downto 0);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
SYNC_DATA_OUT => data_in_toggle_sync_vec
);
data_in_toggle_sync <= data_in_toggle_sync_vec(0);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
signal data_in_toggle_sync_vec : std_logic_vector(0 downto 0);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
SYNC_DATA_OUT => data_in_toggle_sync_vec
);
data_in_toggle_sync <= data_in_toggle_sync_vec(0);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
signal data_in_toggle_sync_vec : std_logic_vector(0 downto 0);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
SYNC_DATA_OUT => data_in_toggle_sync_vec
);
data_in_toggle_sync <= data_in_toggle_sync_vec(0);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
signal data_in_toggle_sync_vec : std_logic_vector(0 downto 0);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
SYNC_DATA_OUT => data_in_toggle_sync_vec
);
data_in_toggle_sync <= data_in_toggle_sync_vec(0);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_64i_16o_v6_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(16-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(14-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_64i_16o_v6_top;
architecture xilinx of afifo_64i_16o_v6_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_64i_16o_v6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_64i_16o_v6
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package MathHelpers is
function log2(A : integer) return integer;
function isPow2(A : integer) return boolean;
function max(A, B : integer) return integer;
function max(A, B : std_logic_vector) return std_logic_vector;
function min(A, B : integer) return integer;
function min(A, B : std_logic_vector) return std_logic_vector;
function abs_std_logic_vector(arg: std_logic_vector) return std_logic_vector;
end package MathHelpers;
package body MathHelpers is
function log2(A : integer) return integer is
begin
for I in 1 to 30 loop
if (2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
-------------------------------------------------------------------------------
-- return true if an integer nuber is a power of 2
function isPow2(x : integer) return boolean is
begin
-- Works for up to 32 bit integers
if
x = 1 or x = 2 or x = 4 or x = 8 or x = 16 or x = 32 or
x = 64 or x = 128 or x = 256 or x = 512 or x = 1024 or
x = 2048 or x = 4096 or x = 8192 or x = 16384 or
x = 32768 or x = 65536 or x = 131072 or x = 262144 or
x = 524288 or x = 1048576 or x = 2097152 or
x = 4194304 or x = 8388608 or x = 16777216 or
x = 33554432 or x = 67108864 or x = 134217728 or
x = 268435456 or x = 536870912 or x = 1073741824
then
report "Argument is a power of 2" severity NOTE;
return true;
else
report "Argument is not a power of 2" severity NOTE;
return false;
end if;
end function isPow2;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function max(A, B : integer) return integer is
begin
if B > A then
return B;
end if;
return A;
end function max;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function max(A, B : std_logic_vector) return std_logic_vector is
begin
if B > A then
return B;
end if;
return A;
end function max;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function min(A, B : integer) return integer is
begin
if B > A then
return A;
end if;
return B;
end function min;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function min(A, B : std_logic_vector) return std_logic_vector is
begin
if B > A then
return A;
end if;
return B;
end function min;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function abs_std_logic_vector(arg: std_logic_vector) return std_logic_vector is
variable Result: signed(arg'length-1 downto 0);
begin
Result := signed(arg);
if Result(Result'left) = '1' then
Result := -Result;
end if;
return std_logic_vector(Result);
end function;
end package body MathHelpers; |
--------------------------------------------------------------------------------
-- FILE: BoothMul
-- DESC: Booth's Multiplier
--
-- Author:
-- Create: 2015-08-16
-- Update: 2015-08-16
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity AddSub is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
as: in std_logic; -- Add(Active High)/Sub(Active Low)
a, b: in std_logic_vector(DATA_SIZE-1 downto 0); -- Operands
re: out std_logic_vector(DATA_SIZE-1 downto 0); -- Return value
cout: out std_logic -- Carry
);
end AddSub;
--------------------------------------------------------------------------------
-- ARCHITECURE
--------------------------------------------------------------------------------
architecture add_sub_arch of AddSub is
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin: in std_logic;
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout: out std_logic
);
end component;
signal b_new : std_logic_vector(DATA_SIZE-1 downto 0);
signal as_arr: std_logic_vector(DATA_SIZE-1 downto 0);
begin
as_arr <= (others=>as);
b_new <= b xor as_arr;
ADDER0: Adder
generic map(DATA_SIZE)
port map(as, a, b_new, re, cout);
end add_sub_arch;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:37 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : zybo_zynq_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zybo_zynq_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zybo_zynq_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zybo_zynq_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of SDIO0_WP : signal is "xilinx.com:interface:sdio:1.0 SDIO_0 WP";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => IRQ_F2P(0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc594.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:17 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00594ent IS
END c03s04b01x00p01n01i00594ent;
ARCHITECTURE c03s04b01x00p01n01i00594arch OF c03s04b01x00p01n01i00594ent IS
type integer_vector is array (natural range <>) of integer;
type integer_vector_file is file of integer_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_vector_file open read_mode is "iofile.25";
variable v : integer_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00594"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00594 - File reading operation (integer_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00594arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc594.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:17 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00594ent IS
END c03s04b01x00p01n01i00594ent;
ARCHITECTURE c03s04b01x00p01n01i00594arch OF c03s04b01x00p01n01i00594ent IS
type integer_vector is array (natural range <>) of integer;
type integer_vector_file is file of integer_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_vector_file open read_mode is "iofile.25";
variable v : integer_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00594"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00594 - File reading operation (integer_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00594arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc594.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:39 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:56 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:17 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00594ent IS
END c03s04b01x00p01n01i00594ent;
ARCHITECTURE c03s04b01x00p01n01i00594arch OF c03s04b01x00p01n01i00594ent IS
type integer_vector is array (natural range <>) of integer;
type integer_vector_file is file of integer_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_vector_file open read_mode is "iofile.25";
variable v : integer_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00594"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00594 - File reading operation (integer_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00594arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc320.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p03n01i00320ent IS
END c03s02b01x00p03n01i00320ent;
ARCHITECTURE c03s02b01x00p03n01i00320arch OF c03s02b01x00p03n01i00320ent IS
type matrix1 is array (integer range <>, integer range <>) of real;
type matrix2 is array (integer range <>, positive range <>) of real;
type matrix4 is array (bit range <>, bit range <>) of TIME;
BEGIN
TESTING: PROCESS
subtype kk is matrix1(0 to 6,0 to 6);
variable k : kk;
BEGIN
k(5,5) := 0.1;
assert NOT(k(5,5)=0.1)
report "***PASSED TEST: c03s02b01x00p03n01i00320"
severity NOTE;
assert (k(5,5)=0.1)
report "***FAILED TEST: c03s02b01x00p03n01i00320 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p03n01i00320arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc320.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p03n01i00320ent IS
END c03s02b01x00p03n01i00320ent;
ARCHITECTURE c03s02b01x00p03n01i00320arch OF c03s02b01x00p03n01i00320ent IS
type matrix1 is array (integer range <>, integer range <>) of real;
type matrix2 is array (integer range <>, positive range <>) of real;
type matrix4 is array (bit range <>, bit range <>) of TIME;
BEGIN
TESTING: PROCESS
subtype kk is matrix1(0 to 6,0 to 6);
variable k : kk;
BEGIN
k(5,5) := 0.1;
assert NOT(k(5,5)=0.1)
report "***PASSED TEST: c03s02b01x00p03n01i00320"
severity NOTE;
assert (k(5,5)=0.1)
report "***FAILED TEST: c03s02b01x00p03n01i00320 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p03n01i00320arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc320.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p03n01i00320ent IS
END c03s02b01x00p03n01i00320ent;
ARCHITECTURE c03s02b01x00p03n01i00320arch OF c03s02b01x00p03n01i00320ent IS
type matrix1 is array (integer range <>, integer range <>) of real;
type matrix2 is array (integer range <>, positive range <>) of real;
type matrix4 is array (bit range <>, bit range <>) of TIME;
BEGIN
TESTING: PROCESS
subtype kk is matrix1(0 to 6,0 to 6);
variable k : kk;
BEGIN
k(5,5) := 0.1;
assert NOT(k(5,5)=0.1)
report "***PASSED TEST: c03s02b01x00p03n01i00320"
severity NOTE;
assert (k(5,5)=0.1)
report "***FAILED TEST: c03s02b01x00p03n01i00320 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p03n01i00320arch;
|
package fifo_pkg is
end package;
package fifo_pkg is
end package;
package fifo_pkg is
end;
|
-- $Id: serport_xonrx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx - syn
-- Description: serial port: xon/xoff logic rx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx;
architecture syn of serport_xonrx is
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
n.rxovr := '0'; -- ensure single clock pulse
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
else
if r.escseen = '1' then
n.escseen := '0';
end if;
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
end syn;
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library fp_lib;
use fp_lib.float_pkg.all;
entity rnd_norm_wrapper is
Generic
(
exp_bits : integer := 8;
man_bits_in : integer := 57;
man_bits_out : integer := 32
);
Port
(
CLK : in std_logic;
RESET : in std_logic;
STALL : in std_logic;
ROUND : in std_logic;
READY : in std_logic;
OP : in std_logic_vector(exp_bits+man_bits_in downto 0);
EXCEPTION_IN : in std_logic;
DONE : out std_logic;
RESULT : out std_logic_vector(exp_bits+man_bits_out downto 0);
EXCEPTION_OUT : out std_logic
);
end rnd_norm_wrapper;
architecture Behavioral of rnd_norm_wrapper is
-- Signal definitions
signal operand : std_logic_vector(exp_bits+man_bits_in+1 downto 0);
signal rnd_done : std_logic;
signal rnd_result : std_logic_vector(exp_bits+man_bits_out downto 0);
signal rnd_exception : std_logic;
begin
operand <= OP & '0';
IF_RND_NORM_INST: if (man_bits_in = man_bits_out) generate
RND_NORM_IF_INST:rnd_norm
generic map
(
exp_bits => exp_bits,
man_bits_in => man_bits_in+1,
man_bits_out => man_bits_out
)
port map
(
CLK => CLK,
RESET => RESET,
STALL => STALL,
IN1 => operand,
READY => READY,
ROUND => ROUND,
EXCEPTION_IN => EXCEPTION_IN,
OUT1 => rnd_result,
DONE => rnd_done,
EXCEPTION_OUT => rnd_exception
);
end generate;
ELSE_RND_NORM_INST: if (man_bits_in /= man_bits_out) generate
RND_NORM_ELSE_INST:rnd_norm
generic map
(
exp_bits => exp_bits,
man_bits_in => man_bits_in,
man_bits_out => man_bits_out
)
port map
(
CLK => CLK,
RESET => RESET,
STALL => STALL,
IN1 => operand(exp_bits+man_bits_in+1 downto 1),
READY => READY,
ROUND => ROUND,
EXCEPTION_IN => EXCEPTION_IN,
OUT1 => rnd_result,
DONE => rnd_done,
EXCEPTION_OUT => rnd_exception
);
end generate;
DONE <= rnd_done;
RESULT <= rnd_result;
EXCEPTION_OUT <= rnd_exception;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT DMA_READ_QUEUE_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
-------------------------------------------------------------------------------
-- $Id: t400_por-c.vhd,v 1.1 2006-05-07 01:47:51 arniml Exp $
-------------------------------------------------------------------------------
configuration t400_por_rtl_c0 of t400_por is
for spartan
end for;
end t400_por_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.if_pkg.all;
entity instruction_fetch is
port (clk : in std_logic;
rst_n : in std_logic;
d : in if_in;
q : out if_out);
end entity instruction_fetch;
architecture Behavioral of instruction_fetch is
-------------------------------------------------
-- Types
-------------------------------------------------
type registers is record
pc : unsigned(word'range);
npc : unsigned(word'range);
end record registers;
-------------------------------------------------
-- Signals
-------------------------------------------------
signal r, rin : registers;
signal zero : std_logic := '1';
-------------------------------------------------
-- Constants
-------------------------------------------------
constant c_four : unsigned(2 downto 0) := to_unsigned(4, 3);
begin -- architecture Behavioral
-------------------------------------------------
-- assign outputs
-------------------------------------------------
q.fetch_addr <= std_logic_vector(rin.pc);
q.pc <= std_logic_vector(r.pc);
-------------------------------------------------
-- PC mux
-------------------------------------------------
pc_next_proc : process (d, r, zero) is
variable v : registers;
begin -- process pc_next_proc
-- defaults
v := r;
if (zero = '1') then
v.pc := (others => '0');
elsif (d.irq = '1') then
v.pc := IRQ_VECTOR_ADDRESS;
elsif (d.load_pc = '1') then
v.pc := unsigned(d.next_pc);
elsif (d.stall = '1') then
v.pc := r.pc;
else
v.pc := r.pc + c_four;
end if;
rin <= v;
end process pc_next_proc;
-------------------------------------------------
-- create the Program Counter register
-------------------------------------------------
pc_reg_proc : process (clk, rst_n) is
begin -- process pc_reg
if (rst_n = '0') then
r.pc <= (others => '0');
zero <= '1';
elsif (rising_edge(clk)) then
r <= rin;
zero <= '0';
end if;
end process pc_reg_proc;
end architecture Behavioral;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_data_queue_pkg.all;
package ti_data_fifo_pkg is
shared variable shared_data_fifo : t_data_queue;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the FIFO.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
-- - Returns: The index of the initiated FIFO (natural).
-- Returns 0 on error.
--
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_fifo_put
------------------------------------------
-- This procedure puts data into a FIFO with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the FIFO size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_fifo_get
------------------------------------------
-- This function returns the data from the FIFO
-- and removes the returned data from the FIFO.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to get() from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to get() a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_flush
------------------------------------------
-- This procedure empties the FIFO given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be flushed.
--
procedure uvvm_fifo_flush(
buffer_idx : natural
);
------------------------------------------
-- uvvm_fifo_peek
------------------------------------------
-- This function returns the data from the FIFO
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The number of elements occupying the FIFO (natural).
--
--
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_fifo_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the FIFO (natural).
--
--
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural;
end package ti_data_fifo_pkg;
package body ti_data_fifo_pkg is
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_fifo.init_queue(buffer_size_in_bits, "UVVM_FIFO");
end function;
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_fifo.init_queue(buffer_idx, buffer_size_in_bits, "UVVM_FIFO");
end procedure;
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
) is
begin
shared_data_fifo.push_back(buffer_idx, data);
end procedure;
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.pop_front(buffer_idx, entry_size_in_bits);
end function;
procedure uvvm_fifo_flush(
buffer_idx : natural
) is
begin
shared_data_fifo.flush(buffer_idx);
end procedure;
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.peek_front(buffer_idx, entry_size_in_bits);
end function;
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_count(buffer_idx);
end function;
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_queue_count_max(buffer_idx);
end function;
end package body ti_data_fifo_pkg;
|
-- EULER module for Betty SDR
-- implements a rectangle to polar conversion
-- file: euler.vhd
-- author: Sebastian Weiss DL3YC <dl3yc@darc.de>
-- version: 1.0
-- depends on: vcordic.vhd
--
-- change log:
-- - release implementation 1.0
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity euler is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of euler is
signal cordic_i : signed(A-1 downto 0);
signal cordic_q : signed(A-1 downto 0);
signal cordic_phi : signed(P-1 downto 0);
alias i_sign : std_logic is i(i'high);
alias q_sign : std_logic is q(q'high);
type quadrant_t is array(N+1 downto 0) of bit_vector(1 downto 0);
signal quadrant : quadrant_t;
alias actual_quadrant : bit_vector(1 downto 0) is quadrant(0);
alias last_quadrant : bit_vector(1 downto 0) is quadrant(N+1);
begin
cordic : entity work.vcordic
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => cordic_i,
q => cordic_q,
amp => amp,
phi => cordic_phi
);
process
begin
wait until rising_edge(clk);
quadrant(N+1 downto 1) <= quadrant(N downto 0);
end process;
quadrant(0) <= to_bit(i_sign) & to_bit(q_sign);
process
begin
wait until rising_edge(clk);
case actual_quadrant is
when "11" => -- 1st quadrant
cordic_i <= i;
cordic_q <= q;
when "10" => -- 2nd quadrant
cordic_i <= i;
cordic_q <= -q;
when "00" => -- 3rd quadrant
cordic_i <= -i;
cordic_q <= -q;
when "01" => -- 4th quadrant
cordic_i <= -i;
cordic_q <= q;
end case;
end process;
process
begin
wait until rising_edge(clk);
case last_quadrant is
when "11" => phi <= cordic_phi; -- 1st quadrant
when "10" => phi <= 2**(P-1) - cordic_phi; -- 2nd quadrant
when "00" => phi <= 2**(P-1) + cordic_phi; -- 3rd quadrant
when "01" => phi <= -cordic_phi; -- 4th quadrant
end case;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 21:17:00 11/15/2015
-- Design Name:
-- Module Name: DataMemoryControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataMemoryControl is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
MemRead : in STD_LOGIC;
MemWrite: in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
MemData : in STD_LOGIC_VECTOR (15 downto 0);
MemOut : out STD_LOGIC_VECTOR (15 downto 0);
SerialFinish : out STD_LOGIC;
RAM1Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1RW : out STD_LOGIC;
Serial_dataready : in STD_LOGIC;
Serial_rdn : out STD_LOGIC;
Serial_tbre : in STD_LOGIC;
Serial_tsre : in STD_LOGIC;
Serial_wrn : out STD_LOGIC;
DLED_Right : out STD_LOGIC_VECTOR (6 downto 0)
);
end DataMemoryControl;
architecture Behavioral of DataMemoryControl is
type state_type is (s0, s1, s2, s3, sr0, sr1, sr2, sr3, sr4, sr5, sr6, sr7, sr8, sr9, sr10, sr11); -- sr1 - sr11 is state for serial write. 50 MHz is too fast for serial port.
signal state : state_type;
begin
RAM1Addr(17 downto 16) <= (others => '0');
RAM1Addr(15 downto 0) <= MemAddr - x"8000";
RAM1Data <=
(others => 'Z') when MemRead = '1' else
MemData when MemWrite = '1' else
(others => 'Z');
process (clk, reset)
begin
if (reset = '0') then
state <= s0;
elsif (clk'event and clk = '1') then
case state is
when s0 => state <= s1;
when s1 => state <= s2;
when s2 => state <= s3;
when s3 =>
if (MemAddr = x"BF00" and MemWrite = '1') then
state <= sr0;
else
state <= s0;
end if;
when sr0 => state <= sr1;
when sr1 => state <= sr2;
when sr2 => state <= sr3;
when sr3 => state <= sr4;
when sr4 => state <= sr5;
when sr5 => state <= sr6;
when sr6 => state <= sr7;
when sr7 => state <= sr8;
when sr8 => state <= sr9;
when sr9 => state <= sr10;
when sr10 => state <= sr11;
when sr11 =>
if (Serial_tbre = '1' and Serial_tsre = '1') then
state <= s0;
else
state <= sr0;
end if;
when others => state <= s0;
end case;
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
RAM1EN <= '1';
RAM1OE <= '1';
RAM1RW <= '1';
Serial_rdn <= '1';
Serial_wrn <= '1';
SerialFinish <= '1';
elsif (clk'event and clk = '1' and MemAddr >= x"8000" and MemAddr <= x"FFFF") then
case state is
when s0 =>
-- prepare for the control, data and address
RAM1EN <= '1';
RAM1OE <= '1';
RAM1RW <= '1';
SerialFinish <= '1';
Serial_rdn <= '1';
Serial_wrn <= '1';
when s1 =>
if (MemRead = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0';
Serial_rdn <= '0';
Serial_wrn <= '1';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0';
Serial_wrn <= '1';
Serial_rdn <= '1';
when others =>
RAM1EN <= '0';
RAM1OE <= '0';
RAM1RW <= '1';
SerialFinish <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1';
end case;
end if;
if (MemWrite = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0';
Serial_rdn <= '1';
Serial_wrn <= '0';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0'; Serial_wrn <= '1'; Serial_rdn <= '1';
when others =>
RAM1EN <= '0';
RAM1OE <= '1';
RAM1RW <= '0';
SerialFinish <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1';
end case;
end if;
when s2 =>
if (MemRead = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0'; Serial_rdn <= '1'; Serial_wrn <= '1';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
MemOut <= (1 => Serial_dataready, 0 => (Serial_tsre and Serial_tbre), others => '0');
SerialFinish <= '1';
when others =>
RAM1EN <= '0';
RAM1OE <= '0';
RAM1RW <= '1';
SerialFinish <= '1';
MemOut <= RAM1Data;
end case;
end if;
if (MemWrite = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '0'; Serial_rdn <= '1'; Serial_wrn <= '1';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '1'; Serial_wrn <= '1'; Serial_rdn <= '1';
when others =>
RAM1EN <= '0'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '1'; Serial_wrn <= '1'; Serial_rdn <= '1';
end case;
end if;
when s3 =>
if (MemRead = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
MemOut <= RAM1Data;
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
SerialFinish <= '1';
MemOut <= (1 => Serial_dataready, 0 => (Serial_tsre and Serial_tbre), others => '0');
when others =>
RAM1EN <= '0'; RAM1OE <= '0'; RAM1RW <= '1';
SerialFinish <= '1';
MemOut <= RAM1Data;
end case;
end if;
if (MemWrite = '1') then
case MemAddr is
when x"BF00" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when x"BF01" =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
when others =>
RAM1EN <= '0'; RAM1OE <= '1'; RAM1RW <= '1'; Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
end case;
end if;
when sr0 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr1 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr2 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr3 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr4 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr5 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr6 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr7 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr8 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr9 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '0';
when sr10 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
when sr11 =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';
Serial_rdn <= '1'; Serial_wrn <= '1';
if (Serial_tsre = '1' and Serial_tbre = '1') then
SerialFinish <= '1';
else
SerialFinish <= '0';
end if;
when others =>
RAM1EN <= '1'; RAM1OE <= '1'; RAM1RW <= '1';Serial_rdn <= '1'; Serial_wrn <= '1'; SerialFinish <= '1';
end case;
end if;
end process;
DLED_Right <=
"1111110" when state = s0 else
"0110000" when state = s1 else
"1101101" when state = s2 else
"1111001" when state = s3 else
"0110011" when state = sr0 else
"1011011" when state = sr1 else
"0000000";
end Behavioral;
|
--------------------------------------------------------------------------------
-- obj_code_pkg.vhdl -- Application object code in vhdl constant string format.
--------------------------------------------------------------------------------
-- Built for project '@project_name@'.
--------------------------------------------------------------------------------
-- This file contains object code in the form of a VHDL byte table constant.
-- This constant can be used to initialize FPGA memories for synthesis or
-- simulation.
-- Note that the object code is stored as a plain byte table in byte address
-- order. This table knows nothing of data endianess and can be used to
-- initialize 32-, 16- or 8-bit-wide memory -- memory initialization functions
-- can be found in package mips_pkg.
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
package @obj_pkg_name@ is
-- Simulation or synthesis parameters ------------------------------------------
@constants@
-- Memory initialization data --------------------------------------------------
@obj_tables@
end package @obj_pkg_name@;
|
-- niosii_system_timer_0_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_timer_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 3;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(2 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_timer_0_s1_translator;
architecture rtl of niosii_system_timer_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(2 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
timer_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_timer_0_s1_translator
|
library verilog;
use verilog.vl_types.all;
entity IR is
port(
clk : in vl_logic;
rst : in vl_logic;
aluLeftCondition: in vl_logic_vector(16 downto 0);
rg_wrt_enable : in vl_logic;
rg_wrt_dest : in vl_logic_vector(2 downto 0);
rg_wrt_data : in vl_logic_vector(15 downto 0);
rg_rd_addr1 : in vl_logic_vector(2 downto 0);
rg_rd_data1 : out vl_logic_vector(15 downto 0);
rg_rd_addr2 : in vl_logic_vector(2 downto 0);
rg_rd_data2 : out vl_logic_vector(15 downto 0)
);
end IR;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: cache_types.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 21:40:49 $
--
--------------------------------------------------------------------------
--
-- Package spec defining types for cache.
--
package cache_types is
type strategy_type is (write_through, copy_back);
end cache_types;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY shd_pe_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END shd_pe_fifo;
ARCHITECTURE shd_pe_fifo_arch OF shd_pe_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF shd_pe_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF shd_pe_fifo_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF shd_pe_fifo_arch : ARCHITECTURE IS "shd_pe_fifo,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF shd_pe_fifo_arch: ARCHITECTURE IS "shd_pe_fifo,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4095,C_PROG_FULL_THRESH_NEGATE_VAL=4094,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=12,C_RD_DEPTH=4096,C_RD_FREQ=1,C_RD_PNTR_WIDTH=12,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4095,
C_PROG_FULL_THRESH_NEGATE_VAL => 4094,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 12,
C_RD_DEPTH => 4096,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 12,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END shd_pe_fifo_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc878.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s01b00x00p03n01i00878pkg is
constant UNIT_DELAY: TIME := 1 ns;
end c10s01b00x00p03n01i00878pkg;
-- a nand gate
entity ENT1 is
port ( BITIN1, BITIN2 : in BIT;
BITOUT: out BIT );
end ENT1;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
architecture ARC1 of ENT1 is
begin
BITOUT <= ( BITIN1 nand BITIN2 ) after UNIT_DELAY;
end ARC1;
configuration CON1 of ENT1 is
for ARC1
end for;
end CON1;
-- build an inverter from nand-nand logic
entity ENT2 is
port ( GOING_IN: in BIT;
COMING_OUT: out BIT );
end ENT2;
architecture ARC2 of ENT2 is
component NAND_BOX
port ( IN1, IN2: in BIT; OUT1: out BIT );
end component;
signal STUCKAT_HIGH: BIT := '1';
begin
NAND_COMP: NAND_BOX port map ( GOING_IN, STUCKAT_HIGH, COMING_OUT );
end ARC2;
use WORK.CON1;
configuration CON2 of ENT2 is
for ARC2
for NAND_COMP: NAND_BOX
use configuration CON1
port map ( IN1, IN2, OUT1 );
end for;
end for;
end CON2;
-- declare a test bench
ENTITY c10s01b00x00p03n01i00878ent IS
END c10s01b00x00p03n01i00878ent;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
ARCHITECTURE c10s01b00x00p03n01i00878arch OF c10s01b00x00p03n01i00878ent IS
component INV
port ( ENTRA: in BIT; SALE: out BIT );
end component;
signal SIGIN, SIGOUT: BIT;
BEGIN
INVERTER: INV port map ( SIGIN, SIGOUT );
TESTING: PROCESS
variable k : integer := 0;
BEGIN
SIGIN <= '0';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '1') then
k := 1;
end if;
assert ( SIGOUT = '1' )
report "didn't invert low to high" severity FAILURE;
wait for ( 3 * UNIT_DELAY );
SIGIN <= '1';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '0') then
k := 1;
end if;
assert ( SIGOUT = '0' )
report "didn't invert high to low" severity FAILURE;
assert NOT( k=0 )
report "***PASSED TEST: c10s01b00x00p03n01i00878"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c10s01b00x00p03n01i00878 - A declartive region is formed by the text of a configuration declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p03n01i00878arch;
use WORK.CON2;
configuration c10s01b00x00p03n01i00878cfg of c10s01b00x00p03n01i00878ent is
for c10s01b00x00p03n01i00878arch
for INVERTER: INV
use configuration CON2
port map ( ENTRA, SALE );
end for;
end for;
end c10s01b00x00p03n01i00878cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc878.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s01b00x00p03n01i00878pkg is
constant UNIT_DELAY: TIME := 1 ns;
end c10s01b00x00p03n01i00878pkg;
-- a nand gate
entity ENT1 is
port ( BITIN1, BITIN2 : in BIT;
BITOUT: out BIT );
end ENT1;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
architecture ARC1 of ENT1 is
begin
BITOUT <= ( BITIN1 nand BITIN2 ) after UNIT_DELAY;
end ARC1;
configuration CON1 of ENT1 is
for ARC1
end for;
end CON1;
-- build an inverter from nand-nand logic
entity ENT2 is
port ( GOING_IN: in BIT;
COMING_OUT: out BIT );
end ENT2;
architecture ARC2 of ENT2 is
component NAND_BOX
port ( IN1, IN2: in BIT; OUT1: out BIT );
end component;
signal STUCKAT_HIGH: BIT := '1';
begin
NAND_COMP: NAND_BOX port map ( GOING_IN, STUCKAT_HIGH, COMING_OUT );
end ARC2;
use WORK.CON1;
configuration CON2 of ENT2 is
for ARC2
for NAND_COMP: NAND_BOX
use configuration CON1
port map ( IN1, IN2, OUT1 );
end for;
end for;
end CON2;
-- declare a test bench
ENTITY c10s01b00x00p03n01i00878ent IS
END c10s01b00x00p03n01i00878ent;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
ARCHITECTURE c10s01b00x00p03n01i00878arch OF c10s01b00x00p03n01i00878ent IS
component INV
port ( ENTRA: in BIT; SALE: out BIT );
end component;
signal SIGIN, SIGOUT: BIT;
BEGIN
INVERTER: INV port map ( SIGIN, SIGOUT );
TESTING: PROCESS
variable k : integer := 0;
BEGIN
SIGIN <= '0';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '1') then
k := 1;
end if;
assert ( SIGOUT = '1' )
report "didn't invert low to high" severity FAILURE;
wait for ( 3 * UNIT_DELAY );
SIGIN <= '1';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '0') then
k := 1;
end if;
assert ( SIGOUT = '0' )
report "didn't invert high to low" severity FAILURE;
assert NOT( k=0 )
report "***PASSED TEST: c10s01b00x00p03n01i00878"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c10s01b00x00p03n01i00878 - A declartive region is formed by the text of a configuration declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p03n01i00878arch;
use WORK.CON2;
configuration c10s01b00x00p03n01i00878cfg of c10s01b00x00p03n01i00878ent is
for c10s01b00x00p03n01i00878arch
for INVERTER: INV
use configuration CON2
port map ( ENTRA, SALE );
end for;
end for;
end c10s01b00x00p03n01i00878cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc878.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s01b00x00p03n01i00878pkg is
constant UNIT_DELAY: TIME := 1 ns;
end c10s01b00x00p03n01i00878pkg;
-- a nand gate
entity ENT1 is
port ( BITIN1, BITIN2 : in BIT;
BITOUT: out BIT );
end ENT1;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
architecture ARC1 of ENT1 is
begin
BITOUT <= ( BITIN1 nand BITIN2 ) after UNIT_DELAY;
end ARC1;
configuration CON1 of ENT1 is
for ARC1
end for;
end CON1;
-- build an inverter from nand-nand logic
entity ENT2 is
port ( GOING_IN: in BIT;
COMING_OUT: out BIT );
end ENT2;
architecture ARC2 of ENT2 is
component NAND_BOX
port ( IN1, IN2: in BIT; OUT1: out BIT );
end component;
signal STUCKAT_HIGH: BIT := '1';
begin
NAND_COMP: NAND_BOX port map ( GOING_IN, STUCKAT_HIGH, COMING_OUT );
end ARC2;
use WORK.CON1;
configuration CON2 of ENT2 is
for ARC2
for NAND_COMP: NAND_BOX
use configuration CON1
port map ( IN1, IN2, OUT1 );
end for;
end for;
end CON2;
-- declare a test bench
ENTITY c10s01b00x00p03n01i00878ent IS
END c10s01b00x00p03n01i00878ent;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
ARCHITECTURE c10s01b00x00p03n01i00878arch OF c10s01b00x00p03n01i00878ent IS
component INV
port ( ENTRA: in BIT; SALE: out BIT );
end component;
signal SIGIN, SIGOUT: BIT;
BEGIN
INVERTER: INV port map ( SIGIN, SIGOUT );
TESTING: PROCESS
variable k : integer := 0;
BEGIN
SIGIN <= '0';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '1') then
k := 1;
end if;
assert ( SIGOUT = '1' )
report "didn't invert low to high" severity FAILURE;
wait for ( 3 * UNIT_DELAY );
SIGIN <= '1';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '0') then
k := 1;
end if;
assert ( SIGOUT = '0' )
report "didn't invert high to low" severity FAILURE;
assert NOT( k=0 )
report "***PASSED TEST: c10s01b00x00p03n01i00878"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c10s01b00x00p03n01i00878 - A declartive region is formed by the text of a configuration declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p03n01i00878arch;
use WORK.CON2;
configuration c10s01b00x00p03n01i00878cfg of c10s01b00x00p03n01i00878ent is
for c10s01b00x00p03n01i00878arch
for INVERTER: INV
use configuration CON2
port map ( ENTRA, SALE );
end for;
end for;
end c10s01b00x00p03n01i00878cfg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cia_pkg is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
type timer_t is
record
run : std_logic;
pbon : std_logic;
outmode : std_logic;
runmode : std_logic;
load : std_logic;
inmode : std_logic_vector(1 downto 0);
end record;
constant timer_default : timer_t := (
run => '0',
pbon => '0',
outmode => '0',
runmode => '0',
load => '0',
inmode => "00" );
type time_t is
record
pm : std_logic;
hr : unsigned(4 downto 0);
minh : unsigned(2 downto 0);
minl : unsigned(3 downto 0);
sech : unsigned(2 downto 0);
secl : unsigned(3 downto 0);
tenths : unsigned(3 downto 0);
end record;
constant time_default : time_t := ('1', "10001", "000", X"0", "000", X"0", X"0");
constant alarm_default : time_t := ('0', "00000", "000", X"0", "000", X"0", X"0");
type tod_t is
record
alarm_set : std_logic;
freq_sel : std_logic;
tod : time_t;
alarm : time_t;
end record;
constant tod_default : tod_t := (
alarm_set => '0',
freq_sel => '0',
tod => time_default,
alarm => alarm_default );
procedure do_tod_tick(signal t : inout time_t);
end;
package body cia_pkg is
procedure do_tod_tick(signal t : inout time_t) is
begin
if t.tenths=X"9" then
t.tenths <= X"0";
if t.secl=X"9" then
t.secl <= X"0";
if t.sech="101" then
t.sech <= "000";
if t.minl=X"9" then
t.minl <= X"0";
if t.minh="101" then
t.minh <= "000";
if t.hr="01001" then
t.hr <= "10000";
elsif t.hr="01111" then
t.hr <= "00000";
elsif t.hr="11111" then
t.hr <= "10000";
elsif t.hr="10010" then
t.hr <= "00001";
elsif t.hr="10001" then
t.hr <= "10010";
t.pm <= not t.pm;
else
t.hr <= t.hr + 1;
end if;
else
t.minh <= t.minh + 1;
end if;
else
t.minl <= t.minl + 1;
end if;
else
t.sech <= t.sech + 1;
end if;
else
t.secl <= t.secl + 1;
end if;
else
t.tenths <= t.tenths + 1;
end if;
end procedure do_tod_tick;
end; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1875.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01875ent IS
END c07s01b00x00p08n01i01875ent;
ARCHITECTURE c07s01b00x00p08n01i01875arch OF c07s01b00x00p08n01i01875ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable car : small_int;
BEGIN
car := c07s01b00x00p08n01i01875arch; --architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01875 - Architecture body names are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01875arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1875.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01875ent IS
END c07s01b00x00p08n01i01875ent;
ARCHITECTURE c07s01b00x00p08n01i01875arch OF c07s01b00x00p08n01i01875ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable car : small_int;
BEGIN
car := c07s01b00x00p08n01i01875arch; --architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01875 - Architecture body names are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01875arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1875.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01875ent IS
END c07s01b00x00p08n01i01875ent;
ARCHITECTURE c07s01b00x00p08n01i01875arch OF c07s01b00x00p08n01i01875ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable car : small_int;
BEGIN
car := c07s01b00x00p08n01i01875arch; --architecture body name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01875 - Architecture body names are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01875arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spimaster_tb is
end spimaster_tb;
architecture Behavior of spimaster_tb is
constant I_clk_period: time := 10 ns;
signal I_clk: std_logic := '0';
signal I_tx_data: std_logic_vector(7 downto 0) := X"00";
signal I_tx_start: boolean := false;
signal I_spi_miso: std_logic := '0';
signal O_spi_clk: std_logic := '0';
signal O_spi_mosi: std_logic := '0';
signal O_rx_data: std_logic_vector(7 downto 0) := X"00";
signal O_busy: boolean := false;
begin
-- instantiate unit under test
uut: entity work.spimaster port map(
I_clk => I_clk,
I_tx_data => I_tx_data,
I_tx_start => I_tx_start,
I_spi_miso => I_spi_miso,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi,
O_rx_data => O_rx_data,
O_busy => O_busy
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
stimuli: process
begin
wait until falling_edge(I_clk);
I_spi_miso <= '1';
I_tx_data <= "10101010";
I_tx_start <= true;
wait until O_busy = true;
I_tx_start <= false;
wait until O_busy = false;
I_tx_data <= X"00";
I_spi_miso <= '0';
I_tx_start <= true;
wait until O_busy = true;
I_tx_start <= false;
wait until O_busy = false;
wait for 10*I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end Behavior; |
--
-- * pipelined synchronous pulse counter *
-- pdchain -- multi-bit counter top-level entity
--
-- fast counter for slow-carry architectures
-- non-monotonic counting, value calculable by HDL/CPU
--
-- idea&code by Marek Peca <mp@duch.cz> 08/2012
-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/
-- thanks to Michael Vacek <michael.vacek@vzlu.cz> for testing
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdchain is
generic (
n: natural := 32
);
port (
clock: in std_logic;
en: in std_logic;
q: out std_logic_vector (n-1 downto 0)
);
end pdchain;
architecture behavioral of pdchain is
component pdivtwo
port (
clock: in std_logic;
en: in std_logic;
q, p: out std_logic
);
end component;
--
signal b: std_logic_vector (q'range);
begin
q0: pdivtwo
port map (
clock => clock, en => en, p => b(0), q => q(0)
);
ch: for k in 1 to b'high generate
qk: pdivtwo
port map (
clock => clock, en => b(k-1), p => b(k), q => q(k)
);
end generate;
end behavioral;
|
----------------------------------------------------------------------------------
--
-- Lab session #2: spaceship control
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spaceship is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
left : in STD_LOGIC;
right : in STD_LOGIC;
enable : in STD_LOGIC;
posH : out STD_LOGIC_VECTOR (4 downto 0));
end spaceship;
architecture Behavioral of spaceship is
begin
process( reset, clk )
variable posHAux: integer range 0 to 19; -- To be able to update the ship position
begin
-- High level reset
if reset = '1' then
posHAux := 9;
posH <= std_logic_vector( to_unsigned( posHAux, 5) ); --"00111"; -- Center the ship
-- Synchronous behaviour
elsif clk'Event and clk = '1' then
-- Clear
if Clear = '1' then
posHAux := 9;
posH <= std_logic_vector( to_unsigned( posHAux, 5) ); --"00111"; -- Center the ship
-- When enabled...
elsif enable = '1' then
-- Move left/right if possible
if left = '1' and posHAux /= 0 then
posHAux := posHAux - 1;
elsif right = '1' and posHAux /= 19 then
posHAux := posHAux + 1;
end if;
end if;
end if;
-- Update the position
posH <= std_logic_vector( to_unsigned( posHAux, 5) );
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: chip-full-c.vhd,v 1.1 2005-02-08 20:41:31 arniml Exp $
--
-------------------------------------------------------------------------------
configuration chip_full_c0 of chip is
for full
for spi_boot_b : spi_boot
use configuration work.spi_boot_rtl_c0;
end for;
end for;
end chip_full_c0;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZDYLcnShrheQ0JiTnSwllCV52mSqEuAdRVCjFB+9rWIpP+oEVlUuxAxij0s9yf316jhqbj0jv+D3
X/XbbgeYBA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pbDHrD9fb9BUcHi2dUqDoZW5VMcYJA8iZ7sLts++DTaTiLZw65o6mkwVRpsC65gySNnYe7e8JkEz
jG9SZGMqzvKQinXbi73ZVluJpOvFHrUZoKX98aTHOpKbeWfgXZCv00zkrF2Dn9hOcgIpprEe7H1e
d2Hrhdf914wUXf7288w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JLcFhvKfxO0Dj64uZjuCsMnjjtaY0MgXgNvHjRsG65tf1vhokFjJzprOY3HaUcXmUQiQjUbD7YBF
3s3+tuwKEDe0BAZGVYA/LJwle/QabbBFIh5i3lS0sv2e+WYRncpxGxqW0sKSG0boSe3iW54hAq4s
Ol7L0T5Smz0SviEBpBZYnLRmAiiv/QjzCXuyrwPcxj3nFqaKDO1HBec1iF+o4ytlkHTvcGcnhWfR
DDZUo+YSsQKHM5+Eci2jOvqzXbmmDWpdQU9/4GY9acykwixiL1FzfZ+xVDU5vDJDx9IozkSAGzd0
wPS7tZxqVsC8P01tN0v0yvzM6Dx43iO+jMIydQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
buIBqF/XoB4m9PyOb/71RRqS9VV/is0sE9Pw4UMmsJ81/8rMUDTR9ARRIpe3WupIpGPKcGlP51DY
CQAKUlwBe89ngbuYJyYJC2jUt2HFOXHMS+AD45kM236hMbUJU4CDeES73p6t7wTF+xtOxXsnxhrb
egOrCpLgJe1g08wMmQo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hu8CDwpFPxciClS2knQ69Xq7bILdQf1kDhjmbck0g5f65WqiPZ2UejHP8LLexEto+BwykQvfXcGK
7xxhFwLh6rtHzvRjx3v+EI7Ykev3ANtA+3j7eRWRUOqM1ZrevIAyJGNgdmX+YlHjhTypBDq+0bS9
T8k1vq2DBXQsHxE29pmLTZMTNxrYJ/+R8ojQwtTUlubQD+9IReBPgnsdfwv2DpSVy3thoqwQiXAG
Vg7TBLZRTMsx0pB2J/WssF4LaeMrdtxRC+vgCrYvq3iQwhPoEtE2jgoKxNBSFa65AaykcnPWratP
4jGA8soI+pAcKd/aurj204agjTC+Vqpyd3Gxjw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8080)
`protect data_block
bCeor17v4t2OiF+SFgu5qNIHB+CaogOm7C6MhUP8okA9dmyWJDFKiXQW2wK15hCVl6VBXJIamL+f
zL9dIcMmlrj5hmZHzRI7qlPKm9geqntq6jrP6hohVVxiqjzU7j1FePGXIGp+golymca3uFDep2GI
fJaC9adwSS1oQp3a+XFiTOC+JF0cuY0qWdRsmETe0/8ljZpteQlHCqhnVuxfam9oAnqESLHOyPnA
+WyaWcH1EtPWcnPWM32n0poonW0Tetvc7J24xLXMOnme9dFxFsADrTGgvY/lt4r9QjbXY4R6SX5r
OjP7b1F/OOG71F2udzwK/Z3NVKKvLlAnePaqNoLikzQu+jim95iqGzO626CtZdhgFszVy/BVkMkG
S26OuFyd5G71bWBO4iasZ/MrK7/dtSe3kMJ7oqiKqe+JAoDbQbyXwP3eDp4UInfKIr6/4ttZsZwi
JJWNI5JyPOt9NZJc74ITjHxZxpI78u4YRYvJ5/7SBitmN0oSyHAVEonPUL0TVM1JIkG1HbMgNBGH
2V+iHJ8rKYNV8qH6MKGP0Nxa5FtfzyLgwZBfIvQAZRrJuPZf8/6j9xBtXrgcPQl7vd2dqqSngUaE
ycMgWl5TMlrNuyDHMrsYRqptquUbpNLu/CHEzosBcevrET1cED4bN0+xLocUa6Iq/Nz2C6woM8CM
r3h41EwjsfCp1J8g6H+vF2bgWbEu7CpL/LiwBh1j3r1vikK7u/mPWyGAUYMMR8I35gxJijqb+VNa
tJWrC1h58b13IlERaDgASLujP5tsu+aCjqkjdDMw+wqCgtxQSi/0CaXnI5vhvM//oudc0tgEdnGK
y8V2HbaBThyv5mxJop7kYsEvrXWm08ADLoExV0WSTuVArFgTZQk38wavOKjIH7zxtj8vHxmIEbzQ
CgtoftxztQ/Qt5eDk27DjNyHVua5BmpvgERK5V5saz2DFwBXoXX2Bi+BwV/IlwbZnnPvnxrxQNs9
uMuw5/z3mqvAy02+wq6nMwG/OIFqc7iCQd4JibxcoF6uEhjXEeRhJ6XuxXF35TJBcupKYuRth5Ou
QWH5CqMlW0ZYLlIarZivgVXtvutXbt3KXv1tZJcieB95xjGK5q9sFWTDZS1+kjRyPEwu5gdI4YMR
Tt/YtihO394G5kacZJSkOT4lK9ROWijBa1YH3YUdFXJICt+2duDrgc8FtLB6pCMDy6Egz0+UFKyh
sVhfHFSykfWl3CUJhRisY6E36OuLGXvAptg1uNpaQXfnL+p7TclX0ViKV7HZs+0BXoFG/uzCNE7W
2GA2oLg5lLg6p3Nghi3BF2qMHuTEw8j15XJ/xzqOtO3BaV2Wk0UDxGQcTteksqu9U7jSRTKBnn/D
15CRifp/C9CyyjQ/yqjXCs3YR4spfUEaobZOkWnbIT/tj/Pt2qLyhxyNijvQvwU20dmeeY/UVgV2
vCgYqizWls96383z5PipgtnGl4GataGGG8YcK1tV5+4qyCRyQuNBIaoYZosNKNxN8AZ4B76Ib5MT
njZbJmGTtTQVDbi9XHhVuTx2PgPwe6bVJcD1WHNdHPWZuP7oImQuT1hyXdZ2eSkD98jW6cyL4KYa
o7U0gE4TpTeX/A81mgMWpEezLcedQXCzn7wrrIMCQ2r2O3QgNMak7JWpFVW+tDxiLEK0xmIuegv4
8U00+7eQnxeiCjDvoX/uxqMQTkf5Hwhq6y0HKM9cIbzDhJkVH9h+dWbBuhMlMGoLO4s8K1TctXQz
Oyz4Z07pYOnyeexL98wOiZBSe/yDluAWTom1pfJeCBIza+W8O3r+AGgTbM3niU0RKcmABtLL2D4h
6Vo26U0fNv+/yW1K1nBghPowyVetffDnqvlffUvgUefqNCRGdoM5s0BjR6YneH1IGp+jUeD61VXC
CFEYe/uFchE/Hfffl6kJAYSymjoBCh+Or0xv8CT4g1nJtvjlGf7picL72lWACyfS3zJgjxnNmtj4
C2htZSwEKj3TQTOwF+nkJeco4ojsGIYtz//zkhOFqCa3x7C/HGJgcancPB/gUG5WP3rH4XqhCp3c
TqngJq+QdEeZ6xKf2tuHjcO6wFrcTFbvy7ff1eoszasxtAo2gm91k/FXQfk2rPc49Iho+o/Df0Tn
XC+CxcEpjDuc6tol92USI9Ku8s4VIl1nKEJV9+jLlxjml+JzsA8tn5Mby9zkHsoK1UOuxV92n3um
YD6WmhYU4mtGhXCLAvJER80L99a6orWeBR3iE9uoxV77xk/L4La/qm58IXEKw3mYXxlZ9/FmSvWc
a/h9Dh8ArHH/vD/QKz4oNZkcIZ3v5O6phZJpT1N1sqocsRbv0EHkILkvzvjlvvpAPlhfdt5QXTU+
QdmmlkfljA6MlHJm9IOBO9eQwWPtxqN38526Hq/Dr8fVg1WVg4Cv6dNL1tw8iBKNgbFntrg0xIkJ
BuxZ0mjyS8onHlEhVAggFcLKIIIl+YK3aNEqgyZga+kxII9HIBuLmasCnwLvkqinS1oAH4YCfn+H
jHYzB9L2i3jd+gNQzHbfLDNbhwNGsshunZXHxiSDVr+WGWaJCHLdDRi5kXHzkKGmNzX4fESi067e
JQw4iiaZcrm5tcEsFuafPPhnPOT/hOL/b8i1+tosTByT08jQiv3p5zFvR8SIZcisFcSWbwb75Tbe
cxKPiSfyGyZY59CxMHqijOCtNOSkWJM8I09o0b53bq2NfxuyY5+IK4azheXRyViPlAyHN+JjSEXF
miqfzQiR6tavV9n68+2vAL3rn5NOmSh5LgSvZnFXMAeiN8HHh2W3ahbsdrCIgFGW1ZFGfcJMJMAs
HEeb1mfdq6BhqRpASY+BGx7k1akRqPywRW9Tok+Gl5Lpe3kEJWdgN0OF9uVBkAsIsYYYeENN4xPz
pxlqz3d6lAj4CkohuO8rweAEHzeczP4UXIO/f4XNc19DsmackHBv2R1dgm2mbpj7kqIyuBgPZa6M
wLdsFhMsfVIcV2w2XVRkvqNhnkSu/vLFHy8VTZjJ6xHDfN+EFoE6jD/dUsAQUOn/mXB+A8OLokTA
w8djOj9korZHkpJ42NliueT8Fi+8Na8MZzuwRMWezaD+QAv661R8eHGgwa9xop1LbRU/hZpFhXJB
4mXasZNvOF+nhKOjMAUnz/toeJZdWnur6DOhjmMNgteMBtxQhTwQtZbMF2FLICdkJ7QlSZOSqQW7
aMrmxF0kWZoIWDT3QWZ566STtHV4W7vTDjxdfahkSaMgiqi1KrVBJE4/7MzqIq4SNkrysDVG5J9N
xmqIY+DJtvAIkCVhN2nL1V7Z2ieQcpjU4Fo3uQqs5BiJO7V2JeavZwvr+G5aYYAtFkobb/3rcC01
OwO5QQxOlhaGEtW/TYaCffa5dTM45Vdgp2zqcSieclX5Atx3b2uzV0fMh4orOGzBI2Uwc9RuKhvP
zXYviodGJ6V9JJYCWPVnvvfhC39CMV+tDlHIzHhxKlRbTERJrCYtc4NLLu5MeIO7ePypRlUJSQTb
RQ4TSKozhDrcUcWoYFhLqLTyaA1QaKyfJHXOvDg0ZjMXyAJOct35zLoW6f2jvlbn9dTfd1O8WnBD
GOLA2fKqy9fZ1MetVuIsQ1Y7ZnGNdrIKKP2xwA+gcsR9wy3tOSR59SlODY5MEHzwsGXpSsgFBkFn
CPnU4PoqgQogEoHbVMCqivYPRQ8IEMgfs5IUZOhlQsFxcZyzO5LRQz9v7v4nZ1YSI+QKgbBdCyN4
11Z/EaoZmmJMRZGFLFKdlV99lz6Mc+DdbVKJ2VXGy9in+LAXA99tkCJz3E9swq5wpXGsXzEe10Lj
h2SquI1+SKTO9yMUhCfipyJPlHmBIWLIoM/LxL3E5dxMQ5ZPFW2m5yMj/KwFYnB1xWK5Zf13ctac
UvfJpWlOsDSo1QZEDCfLcXGJzI+lAKdyxgYVuvNcNwMseZd7ND6ODnILRsIkdfIcqTLhVTWBod0z
gAEl/ppwiloIdN7bMf8uJNXWGJWzFbVa8SsgEy8cGZRU+3KuMhHtQ9x8Jd31WqceF6+N+nXJrP5B
7iSzgtjDlAoIu1KYOwyCAdPWBNDYbdzGI8Jw20CoH/KY1IEF6OSfGcP8BzedFyZ0thG+oaNjBObL
RhVpkE/fHbO+91kde3MlU1i1+FFihIiW0PZ3hbnVGdJZQY73sZGKABVCaGHuKis+EEF9dz8BintM
uVYTm105c1U6U/4ZWJq0FtUjOfB3ny8Cs+BW8Q60fS69bc9jYISZtJ5rv6zjJAqK7ZMNqgorwM4R
N8zfhJWNOxDNZTY37j+HIlW5LVizsb0vYWwUtdTGVe92UFuetfc4su2sM5q+pPalMSxcmCY5i0VV
5GxTAkSf1nceZ1JZ0qdAtlpFIv8KLJgw0IjfrSh6iPu1NDfv1y0exhAdEhOYwtp22aCHgWvH3p8P
YxZMe9rUTskmIVGlin6za1By2pqgY0VdTMWIfhpRuExQiywPuZx0q4XfTyJcRXD7b/Np/nygrle2
tXZEOIHaRt8q88G6SMPuW2YxYnTCchfJCRDY838H4NaabPtTMGgpnregO33apM22iho7509NFNfd
yRq8Av4pFJ1y5SVIwSyfdqlRauhTI6yOcJw9ib795QVtUu2zLEzQ2+95rywZ/ZKW9H3jm5yAOsKX
t91BedzGOl1CY56BYASBikKyocVTUaoVYAIenAsWrfLj8ctOxsT9AyfpUkQcRVsfltm/S7C0QwF+
+ebpuLAsAm/yfh5FgX6TBrQskCboaYBthWvw7EnC6hQek4b60tytWRvFT2qVPNrNqkoow9eRcxSn
3g5uXcXGz00sjgKGUeTl4zg2UpnaThQe8Ko219Dss1Ol6b5BJRNvMXM9BQR25MVfPBrQo15aQr84
Lfj8kzP0QKwP1IrH5LeyL/nxk2RUgLjeqsbbF0D44XZGyxntLVjMbdxm6znCo547hI3b0ySPJPRz
7/uanMkVVH3ZVoNFknMQRfVr1i7qV+9S2MzybE+Z7quYmu24pPHpDYUjhPtd0adyY2eJIL9pXvhx
eUWAN3UIAeOkzPHYO+MVfakjquvrQDCTChLcRnRwjhcNiTxUYvhkXgqMYOXl3s8yd+N1LFzehLCT
i9Rn3Eb0Q/RBJwQGnFOS24U/sr7HHAhqYQXCNhsufhwZHv6k2ppo5Qm4vbdU7+2/gTUvNtG+SSe7
cjHbBM6pZWwGtmg0t+CNAIKv2H+ovrbXHWDnjTesbh9BTZgpsPCa7W3er7X2o8VUhgmpLlUiRvLw
QaMnGaxiMaWaLdGJ7xeYAnUm7KDkPvP+r+0k5urM9vnImB2tG3OjxOpL1bUIFPZC2+kzRZ2mm1E+
DLx5pqhpXVeK5KSMv7hhyTfZEfSyn0fJkjuhPrU2oeNowA+R0qD9msWlmyF4qD1/ZRRz8ouM8kEW
4LMbcFnxSB5kNKmGhLKs6U7ORLEGyinDoHF2gKIK/11XW4Qh/CJpkBD4DanbXmGQWpVOOhnvSOUe
4rSeDd2BlgZoajnztTmOJcvRd/LUAM6ka+QOYF2r6xyUalOMbf2L+MPWGZn9QuRDHgxcOyX2bT5P
DhSb7ATqR155xsPtrykQGLd095q2T8Fu0gqbdRTnU0ZxUgI5EyDQxVLGcCan8AoMtVjiKs/5OFNx
YtnAjSAint0pTb3g+9IsW3DVFX07i5fxQCGhS6qIXbtj1N/r6Zz/HUJFbcOca7AzCvQJSFjZdqRp
5Gzme2LU4fT8I9rn5tLBfiFQdnfOKc4q6Lav9PcWHlRF6y2MJKR/I7wcFIbGqnVk8D7oaZM8eyTY
9jmnJA0JAZ7keLv1rI7q3OQy2kTccer+DRDTRwdAOLdHZGd70oSMkW3ZguhMnroje8OBC97tSSU+
lDzT5iV+thLSxemv4yAV7maQrtUQYTNoC41KgTOW2FFwt/09zpaRgw8WGN0RQZbMSb9HfdBhuVB4
SRzBfx6jEySdUOJTkphi60Mek5jttDxti34cmHXWbK7oXAgesWSEVqwxv6TnWbKFLZphp/zP3GeU
kvR5wFLop81KlvVBgJ37XzsKb422Fid+MnyInvpCiWCPM1gHAaYRjqFK7dvgCWv4h682cwwhT+lU
QiE0FM6JiqpATqygCElcFcQFP3SJonIiqKSWYpdS1xf6xLbQH7PfVbfrLpD6Ux7fXO9LN10y7NZb
846IR1VbG2r1mdBSY1OdgEp2x9xPFQvU1zFdV5xQAtUNvp6RJKaFO5bKwTm10N7yAQIVZUOtcB4Y
NXBAIhcinsXhatyN5MBJK26oGeqMmIAED6UiXMPmGC/TMUJpARwxG54TrvEB8xcNvoy/ugwWVlfA
IhZE0w7NoxVvEu3f5p9jyL+Us1AXntXT2YTrrUxPuGGjsbeXm83CTAjgWOQ/YvuYDBjJdglERy/Z
DTFbFA//Ih7adIj1EZW3At5+hHqo7rhfGtvjpDv3weGaoE+hlT/9giB1+exOwEjxa//CgA45n+OS
DaxrwXtxX694c/akblU56V8BknahTS2hWbUg6S46rxJenDgM7k8fqUlymfyzqv2HDz/jgSEoVlL2
+3veUq638iKyDFhzrKgr7GwqWfjBSuMRrd2vOt7Nd5JoPRqm18HFjo9+JWfgG/DpZKpteOItElMS
7wvEFIvEW+UnXxmH/93wOqKedc1jVFonBFwaM8ve3kNCYTSf5sBrFLFeZrr0SsMKvup3u5I7DP1R
p/mvG3NdC729YkDPVuWZHZeRCCvs2s7o/Jn3JaLTtsSZ9Sg0iJzE3Yd9s3jNKN0VkD39KxMswurk
zX5AiSTyz+5CLqWZwfc3XpQdrWURlD6VOgi1IqJqi8uaCWuzb7W3brGTLK+kj2Md7kW2PgpRZ0v5
Lypkveub2586LELcFoRjo2t8D9wbTVSLJuxYCaYMPozf/fMy5NX0hridX5wsf3h0LGxrV+QaiOck
j/Tc4CFrfMrj+PmZB/zwL1QZSXt3AKanPq2wsJloFcNrqhuI1ZXbU2ZCLTnfZFO4lzf1Sl/iULRu
HPKyDAMiAOU4ZMGPnW/1IG02u48xAGCi3nGxXWxOrq6SgezRb/iME8w0su2LoyobPD/2MUtVowIQ
cwaIAJwNMbrzIJn1bB5UZqe+lxoRBMzy5cSV81BmZGRsOvFLgTZefELuJzxPDcGln31aykC1lvBy
p8pfoVLnqG0ozpYE+Lv+cLOzjmyubYcCltMLwKKnitD6UY9PJFVtTMyP29GUBmUcoQnK0bizm+UF
N0zUpPYt37T6/+spPVUVxQqQh6fDylPBzwWZttGn2WcwnA4Gqp+1MovObOuAZBrFR9xg4EjBNYUp
9Jc2f0ulQI6+bl4iSrbZ9QxKWcrQR5Thy61aGatDBonJkRDmUQQspV45no0wiCWMjRgGDgSr61jQ
CWhHzwRc6xFtmIg5WkZeB1nIrpLpeXACJBvok0nSh3D/yIdd0qhuS7bFcxcLamhPAP/NsoR6QtSc
rvH5qcvKcT0/VJgyefvxT0O41ZjxBq4GUritCSycwWLOS84XqvV701gGSLoGKmSu7+NGEPIGVAil
0LDK21lrks56IAFc6b5uG0ILkjtiizRAI4upKpJakwKv+3JRm2P0lorpc2dby+39qv6XV8+F6KFM
URoXImUAKKL9rd9N5uiUJ5sgpq3qpdSLBWtdOE8+dId/Uq5O1/ZN3WzTAoU0UK1jhOkCUUFEN8dO
yV6NbkrxMTviASurW3JpaulX21ZcanpPKE00omsWmN74DCy3LNWcSzshjPmcoKX0jIqB0e63fmCq
R8JJG4D9K/s2E/I08cIv0jXF22eF2I3wPbE9HZrwNWlHMGR9I4AQaogHQFaEQ0MbSns86R4CKxBT
NJ3bpy13SGEswXchvM/EUKukSs4lDU7mbrbOMeBuaWMl58RHn+nNHlS0CkvOa+Pj2D0WTAiks+tE
0oByKMtl6JDEYdZK6PF3YuRwH/AnZ/WfzN7aVSSu+B4RteFvAnZFo8bGvJKGgXUbmehotZe9dYR3
57+KRbbBw//6qbhCRPAfSTA2rEBKjRrptKpJECue1/1d57h2ngyIPdtLLTW5yMtVXvSEGb+G6gEs
zWc1SJewNmbHTHMAT3qZBaUREMzbwRptVHVpFA+LNZBZSuYVCBvUp1OlaVO+R/WCfoz3flrY8L/0
27rZlHlZx5FMiB/YnlCpscHbIgPpOmzyCzbKfS0OzGT0PsVUoudTYqhj9Wun4xgM3x0GstPl8zSG
2KU1Wfq2sLdKiVs5uB1eZib6p35op8Qd0LHWS7ks0DPE2hOYL8/8qqM1ordvVpv2/FbJkYA7ZiBe
8GEIauLTeuYR7fpSnQjXv1Dm8JaRNjp1ViDjtKQIqdvgxBq4XKEEBk4R8e2rkJJp7WoxBBMpDAKc
THJDp/U5moR6UADYw+c1O9HbXWAugDxavUCHqdflougQJbeQ4um0CbOxlCpsjCVA6E49M+Ku1OqU
C5GLR+J8QL4zLNYQCL2xRmlw+B7eeAn8HYG4qECOEazpDGS+ftV1vjy0tm6GQu+Rct2OzfUY/uvg
5aGgORdeeR1MU9m6DXxttSxw0wvvijM+xSxdFkJLsmUT35wzxpu+7SboWs5fk7+bf/U6ZWzWQa+s
+hcHnqYZR2ddl/TvFN6rOMXBhJrv5i6//Ct8pEDFSsFckawvyTxEuTyeMUbNArF4CaG/+k91PA77
BIwx1EdXjGKzWFlEnxeYgXAfbMEOqPGTaiS/GOsTfomKQgVBl559KLYW7oMBBRXRxenoiwA9uH4F
E1DzjlWfnaKSa6EbjXoHAo00gEvV4/YjhyumoDdrLV0v8aqY1a3jg9E2/I5yymSy+mosY1Q+mmQM
cSr/QnO4+cU+pk8jMvRSNLdnxCcoDGyFrt+xJOK0YyW5etgf13r3FSLGFWHzQhZAr5/SgWM3FR0Y
8Jz9tLfC37OeJHqwqG8ptwWHhbPl8xTFEWxGzPDbK2V673Zydy9SqUXq4B+ZnjrSWJSqfWEuLN9X
47mgGa8dNSN2ogg9EnqL/AZk8EippNNx3qBgeDlvs0pioA36q3+Qb7C7nvCBna4a2Joe+MpPUeRh
0/zBS5KXG4EBoRe7SVr+k7hJiXaM4amhqFyNkpXHaifc38fwbmfzr4gOz2pMTFA6t0I8wj9mxSPL
HLjZ9kjWs/r/BUkkC+POAo+M+gDjA+zCtpUIxSzTW4kuh0fdWbs5G6E8ig+9EI3C2UfHBl+uiyM2
NZC8kGLgHBvJzAfHlqCr52PjkjIOiFTXYAQh+G4ipJMhiip7O5OiWrr7r/eFk2MG/BfgaMF7S4nx
EnOW3kpyWbG8eiegb5nG4w+973tGqb8s5q2dg8bDC2g916FUwI8b+DuZA3YY1lFpGdWbi2ImzDnd
8zikgNBcYENb2fPp40Tr8SsetljiqDUgd4yoquoe8A3ilL65zm2DONd4oIDD9arf+Y+HPOlmxike
gvQZEzBu26ErFgWiC3ankPr0bFdNznVa1ZW3SpR/rWWYP4TrsJE0VMeu9ymd1uZ3LLobHPHHAQVS
Ex6yABijUIznFek2eNNM7/QR7QUei6M70axMqmFwaX5KqrxF6nO+R/gFgMJNdDLp0Zuc//XbOHW7
zAZM5/ZFJcc06azaRhy9KAS1vOX/VzgfgYk8Vk3PzMuRL19ehgbX9Ff1y+XnLL697CdCYrLVXOR2
qEofiLH5xkLROC+OTlzYOdUVnHK3fIm1XTqex/3GFZu/D/BtkAbP4KHgwu9bOunnE6iI3uFCosKE
Je9gpmQs8eOcDUlvejiiIxlhL4aK4AF4uUpJKFaI2m/EpHSEDWaR7Zmj9rHxCqXAdaKn+A8VY8rU
SoGjMGUSAi5zhnp8dH6XNAH5ydnZRfrXKCZVdaDz0USOQ2tPR2ply87eYJ8VJycU+k93wHZlP6YE
1pME/C7WJkJB+Bzpq1uyYPloRJWhfQvnQEwxGgrDnZ810kD/osyWe5JxahfvZ3huPK3CkmauBOYt
hvZIrmZPC+693YgceniaAWJG9LKxlBW/U/M7tPFleiA28ZkGAQGMY+FSAHHEkWC1zdldT0pTEDmJ
eyvx1/sQEFFyLBoDYJarrnjmnkOUaeeUx2Qq0NcoqTV9Msq6b2VscFn9/A4HhLyGxd9XeVEgJhap
9/wousk5xWVR/dRDzjaTG7fLFe5ok/bikKad64CIRQ22GCX6/H+UEOGJZaLqDSuJGjQ2hDrU+I+S
+zKKTWhPmml1XRSsLoc4vuugxY3HqcAqPG0pGWN8q/NHMfke86iQjEP8FHVNZJ9KPUcHqK6xZ8XR
TuEiXyDteVtF/bfK97re+zvnrNYj7Ch6/o6nBOrxfaUBIEeYgoCM00XkaXFZyZ0OE1w6p9tuUl+u
zwZj0jtLtzeSyAri/kE4CNs60CPEzYaAZoZPk6IHZ8arKbgv9Jhmhegc+/HTRakwKlDbjarJsrmA
AN3V0DMEiV4dCceHzs6/kkmaBQL3lCcSz6p4eu9gCZsmdeXbWsCzbIona/WCSk4iQ6A0+H5xbjO8
OSdzJce2dQwoiMguskv9A8MzeVoW+I7HcJHhR8liSPofgJEQFZcplkX36GsY/xCdqUby8uT7xtNQ
Z1zMIKFk2m0Dw3MXUXiEAUBVvkue4a7XP+KD9y28WjjwWJa55Yy0N7iKkdgWlXpsWsz3mToJxQVc
okHcAnZSMUu6rtAUvHL1H3GNCXBSPQqVovRjfWBHNTo0qAFUqYVGVlJ3wGsyqufOciJ9ykfOIqlS
ZsDV20AbeTV73vflQugttl5rAoskG0tP8jvIKo+LOvnzC4F1HI0AbweF1g==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZDYLcnShrheQ0JiTnSwllCV52mSqEuAdRVCjFB+9rWIpP+oEVlUuxAxij0s9yf316jhqbj0jv+D3
X/XbbgeYBA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pbDHrD9fb9BUcHi2dUqDoZW5VMcYJA8iZ7sLts++DTaTiLZw65o6mkwVRpsC65gySNnYe7e8JkEz
jG9SZGMqzvKQinXbi73ZVluJpOvFHrUZoKX98aTHOpKbeWfgXZCv00zkrF2Dn9hOcgIpprEe7H1e
d2Hrhdf914wUXf7288w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JLcFhvKfxO0Dj64uZjuCsMnjjtaY0MgXgNvHjRsG65tf1vhokFjJzprOY3HaUcXmUQiQjUbD7YBF
3s3+tuwKEDe0BAZGVYA/LJwle/QabbBFIh5i3lS0sv2e+WYRncpxGxqW0sKSG0boSe3iW54hAq4s
Ol7L0T5Smz0SviEBpBZYnLRmAiiv/QjzCXuyrwPcxj3nFqaKDO1HBec1iF+o4ytlkHTvcGcnhWfR
DDZUo+YSsQKHM5+Eci2jOvqzXbmmDWpdQU9/4GY9acykwixiL1FzfZ+xVDU5vDJDx9IozkSAGzd0
wPS7tZxqVsC8P01tN0v0yvzM6Dx43iO+jMIydQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
buIBqF/XoB4m9PyOb/71RRqS9VV/is0sE9Pw4UMmsJ81/8rMUDTR9ARRIpe3WupIpGPKcGlP51DY
CQAKUlwBe89ngbuYJyYJC2jUt2HFOXHMS+AD45kM236hMbUJU4CDeES73p6t7wTF+xtOxXsnxhrb
egOrCpLgJe1g08wMmQo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
hu8CDwpFPxciClS2knQ69Xq7bILdQf1kDhjmbck0g5f65WqiPZ2UejHP8LLexEto+BwykQvfXcGK
7xxhFwLh6rtHzvRjx3v+EI7Ykev3ANtA+3j7eRWRUOqM1ZrevIAyJGNgdmX+YlHjhTypBDq+0bS9
T8k1vq2DBXQsHxE29pmLTZMTNxrYJ/+R8ojQwtTUlubQD+9IReBPgnsdfwv2DpSVy3thoqwQiXAG
Vg7TBLZRTMsx0pB2J/WssF4LaeMrdtxRC+vgCrYvq3iQwhPoEtE2jgoKxNBSFa65AaykcnPWratP
4jGA8soI+pAcKd/aurj204agjTC+Vqpyd3Gxjw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8080)
`protect data_block
bCeor17v4t2OiF+SFgu5qNIHB+CaogOm7C6MhUP8okA9dmyWJDFKiXQW2wK15hCVl6VBXJIamL+f
zL9dIcMmlrj5hmZHzRI7qlPKm9geqntq6jrP6hohVVxiqjzU7j1FePGXIGp+golymca3uFDep2GI
fJaC9adwSS1oQp3a+XFiTOC+JF0cuY0qWdRsmETe0/8ljZpteQlHCqhnVuxfam9oAnqESLHOyPnA
+WyaWcH1EtPWcnPWM32n0poonW0Tetvc7J24xLXMOnme9dFxFsADrTGgvY/lt4r9QjbXY4R6SX5r
OjP7b1F/OOG71F2udzwK/Z3NVKKvLlAnePaqNoLikzQu+jim95iqGzO626CtZdhgFszVy/BVkMkG
S26OuFyd5G71bWBO4iasZ/MrK7/dtSe3kMJ7oqiKqe+JAoDbQbyXwP3eDp4UInfKIr6/4ttZsZwi
JJWNI5JyPOt9NZJc74ITjHxZxpI78u4YRYvJ5/7SBitmN0oSyHAVEonPUL0TVM1JIkG1HbMgNBGH
2V+iHJ8rKYNV8qH6MKGP0Nxa5FtfzyLgwZBfIvQAZRrJuPZf8/6j9xBtXrgcPQl7vd2dqqSngUaE
ycMgWl5TMlrNuyDHMrsYRqptquUbpNLu/CHEzosBcevrET1cED4bN0+xLocUa6Iq/Nz2C6woM8CM
r3h41EwjsfCp1J8g6H+vF2bgWbEu7CpL/LiwBh1j3r1vikK7u/mPWyGAUYMMR8I35gxJijqb+VNa
tJWrC1h58b13IlERaDgASLujP5tsu+aCjqkjdDMw+wqCgtxQSi/0CaXnI5vhvM//oudc0tgEdnGK
y8V2HbaBThyv5mxJop7kYsEvrXWm08ADLoExV0WSTuVArFgTZQk38wavOKjIH7zxtj8vHxmIEbzQ
CgtoftxztQ/Qt5eDk27DjNyHVua5BmpvgERK5V5saz2DFwBXoXX2Bi+BwV/IlwbZnnPvnxrxQNs9
uMuw5/z3mqvAy02+wq6nMwG/OIFqc7iCQd4JibxcoF6uEhjXEeRhJ6XuxXF35TJBcupKYuRth5Ou
QWH5CqMlW0ZYLlIarZivgVXtvutXbt3KXv1tZJcieB95xjGK5q9sFWTDZS1+kjRyPEwu5gdI4YMR
Tt/YtihO394G5kacZJSkOT4lK9ROWijBa1YH3YUdFXJICt+2duDrgc8FtLB6pCMDy6Egz0+UFKyh
sVhfHFSykfWl3CUJhRisY6E36OuLGXvAptg1uNpaQXfnL+p7TclX0ViKV7HZs+0BXoFG/uzCNE7W
2GA2oLg5lLg6p3Nghi3BF2qMHuTEw8j15XJ/xzqOtO3BaV2Wk0UDxGQcTteksqu9U7jSRTKBnn/D
15CRifp/C9CyyjQ/yqjXCs3YR4spfUEaobZOkWnbIT/tj/Pt2qLyhxyNijvQvwU20dmeeY/UVgV2
vCgYqizWls96383z5PipgtnGl4GataGGG8YcK1tV5+4qyCRyQuNBIaoYZosNKNxN8AZ4B76Ib5MT
njZbJmGTtTQVDbi9XHhVuTx2PgPwe6bVJcD1WHNdHPWZuP7oImQuT1hyXdZ2eSkD98jW6cyL4KYa
o7U0gE4TpTeX/A81mgMWpEezLcedQXCzn7wrrIMCQ2r2O3QgNMak7JWpFVW+tDxiLEK0xmIuegv4
8U00+7eQnxeiCjDvoX/uxqMQTkf5Hwhq6y0HKM9cIbzDhJkVH9h+dWbBuhMlMGoLO4s8K1TctXQz
Oyz4Z07pYOnyeexL98wOiZBSe/yDluAWTom1pfJeCBIza+W8O3r+AGgTbM3niU0RKcmABtLL2D4h
6Vo26U0fNv+/yW1K1nBghPowyVetffDnqvlffUvgUefqNCRGdoM5s0BjR6YneH1IGp+jUeD61VXC
CFEYe/uFchE/Hfffl6kJAYSymjoBCh+Or0xv8CT4g1nJtvjlGf7picL72lWACyfS3zJgjxnNmtj4
C2htZSwEKj3TQTOwF+nkJeco4ojsGIYtz//zkhOFqCa3x7C/HGJgcancPB/gUG5WP3rH4XqhCp3c
TqngJq+QdEeZ6xKf2tuHjcO6wFrcTFbvy7ff1eoszasxtAo2gm91k/FXQfk2rPc49Iho+o/Df0Tn
XC+CxcEpjDuc6tol92USI9Ku8s4VIl1nKEJV9+jLlxjml+JzsA8tn5Mby9zkHsoK1UOuxV92n3um
YD6WmhYU4mtGhXCLAvJER80L99a6orWeBR3iE9uoxV77xk/L4La/qm58IXEKw3mYXxlZ9/FmSvWc
a/h9Dh8ArHH/vD/QKz4oNZkcIZ3v5O6phZJpT1N1sqocsRbv0EHkILkvzvjlvvpAPlhfdt5QXTU+
QdmmlkfljA6MlHJm9IOBO9eQwWPtxqN38526Hq/Dr8fVg1WVg4Cv6dNL1tw8iBKNgbFntrg0xIkJ
BuxZ0mjyS8onHlEhVAggFcLKIIIl+YK3aNEqgyZga+kxII9HIBuLmasCnwLvkqinS1oAH4YCfn+H
jHYzB9L2i3jd+gNQzHbfLDNbhwNGsshunZXHxiSDVr+WGWaJCHLdDRi5kXHzkKGmNzX4fESi067e
JQw4iiaZcrm5tcEsFuafPPhnPOT/hOL/b8i1+tosTByT08jQiv3p5zFvR8SIZcisFcSWbwb75Tbe
cxKPiSfyGyZY59CxMHqijOCtNOSkWJM8I09o0b53bq2NfxuyY5+IK4azheXRyViPlAyHN+JjSEXF
miqfzQiR6tavV9n68+2vAL3rn5NOmSh5LgSvZnFXMAeiN8HHh2W3ahbsdrCIgFGW1ZFGfcJMJMAs
HEeb1mfdq6BhqRpASY+BGx7k1akRqPywRW9Tok+Gl5Lpe3kEJWdgN0OF9uVBkAsIsYYYeENN4xPz
pxlqz3d6lAj4CkohuO8rweAEHzeczP4UXIO/f4XNc19DsmackHBv2R1dgm2mbpj7kqIyuBgPZa6M
wLdsFhMsfVIcV2w2XVRkvqNhnkSu/vLFHy8VTZjJ6xHDfN+EFoE6jD/dUsAQUOn/mXB+A8OLokTA
w8djOj9korZHkpJ42NliueT8Fi+8Na8MZzuwRMWezaD+QAv661R8eHGgwa9xop1LbRU/hZpFhXJB
4mXasZNvOF+nhKOjMAUnz/toeJZdWnur6DOhjmMNgteMBtxQhTwQtZbMF2FLICdkJ7QlSZOSqQW7
aMrmxF0kWZoIWDT3QWZ566STtHV4W7vTDjxdfahkSaMgiqi1KrVBJE4/7MzqIq4SNkrysDVG5J9N
xmqIY+DJtvAIkCVhN2nL1V7Z2ieQcpjU4Fo3uQqs5BiJO7V2JeavZwvr+G5aYYAtFkobb/3rcC01
OwO5QQxOlhaGEtW/TYaCffa5dTM45Vdgp2zqcSieclX5Atx3b2uzV0fMh4orOGzBI2Uwc9RuKhvP
zXYviodGJ6V9JJYCWPVnvvfhC39CMV+tDlHIzHhxKlRbTERJrCYtc4NLLu5MeIO7ePypRlUJSQTb
RQ4TSKozhDrcUcWoYFhLqLTyaA1QaKyfJHXOvDg0ZjMXyAJOct35zLoW6f2jvlbn9dTfd1O8WnBD
GOLA2fKqy9fZ1MetVuIsQ1Y7ZnGNdrIKKP2xwA+gcsR9wy3tOSR59SlODY5MEHzwsGXpSsgFBkFn
CPnU4PoqgQogEoHbVMCqivYPRQ8IEMgfs5IUZOhlQsFxcZyzO5LRQz9v7v4nZ1YSI+QKgbBdCyN4
11Z/EaoZmmJMRZGFLFKdlV99lz6Mc+DdbVKJ2VXGy9in+LAXA99tkCJz3E9swq5wpXGsXzEe10Lj
h2SquI1+SKTO9yMUhCfipyJPlHmBIWLIoM/LxL3E5dxMQ5ZPFW2m5yMj/KwFYnB1xWK5Zf13ctac
UvfJpWlOsDSo1QZEDCfLcXGJzI+lAKdyxgYVuvNcNwMseZd7ND6ODnILRsIkdfIcqTLhVTWBod0z
gAEl/ppwiloIdN7bMf8uJNXWGJWzFbVa8SsgEy8cGZRU+3KuMhHtQ9x8Jd31WqceF6+N+nXJrP5B
7iSzgtjDlAoIu1KYOwyCAdPWBNDYbdzGI8Jw20CoH/KY1IEF6OSfGcP8BzedFyZ0thG+oaNjBObL
RhVpkE/fHbO+91kde3MlU1i1+FFihIiW0PZ3hbnVGdJZQY73sZGKABVCaGHuKis+EEF9dz8BintM
uVYTm105c1U6U/4ZWJq0FtUjOfB3ny8Cs+BW8Q60fS69bc9jYISZtJ5rv6zjJAqK7ZMNqgorwM4R
N8zfhJWNOxDNZTY37j+HIlW5LVizsb0vYWwUtdTGVe92UFuetfc4su2sM5q+pPalMSxcmCY5i0VV
5GxTAkSf1nceZ1JZ0qdAtlpFIv8KLJgw0IjfrSh6iPu1NDfv1y0exhAdEhOYwtp22aCHgWvH3p8P
YxZMe9rUTskmIVGlin6za1By2pqgY0VdTMWIfhpRuExQiywPuZx0q4XfTyJcRXD7b/Np/nygrle2
tXZEOIHaRt8q88G6SMPuW2YxYnTCchfJCRDY838H4NaabPtTMGgpnregO33apM22iho7509NFNfd
yRq8Av4pFJ1y5SVIwSyfdqlRauhTI6yOcJw9ib795QVtUu2zLEzQ2+95rywZ/ZKW9H3jm5yAOsKX
t91BedzGOl1CY56BYASBikKyocVTUaoVYAIenAsWrfLj8ctOxsT9AyfpUkQcRVsfltm/S7C0QwF+
+ebpuLAsAm/yfh5FgX6TBrQskCboaYBthWvw7EnC6hQek4b60tytWRvFT2qVPNrNqkoow9eRcxSn
3g5uXcXGz00sjgKGUeTl4zg2UpnaThQe8Ko219Dss1Ol6b5BJRNvMXM9BQR25MVfPBrQo15aQr84
Lfj8kzP0QKwP1IrH5LeyL/nxk2RUgLjeqsbbF0D44XZGyxntLVjMbdxm6znCo547hI3b0ySPJPRz
7/uanMkVVH3ZVoNFknMQRfVr1i7qV+9S2MzybE+Z7quYmu24pPHpDYUjhPtd0adyY2eJIL9pXvhx
eUWAN3UIAeOkzPHYO+MVfakjquvrQDCTChLcRnRwjhcNiTxUYvhkXgqMYOXl3s8yd+N1LFzehLCT
i9Rn3Eb0Q/RBJwQGnFOS24U/sr7HHAhqYQXCNhsufhwZHv6k2ppo5Qm4vbdU7+2/gTUvNtG+SSe7
cjHbBM6pZWwGtmg0t+CNAIKv2H+ovrbXHWDnjTesbh9BTZgpsPCa7W3er7X2o8VUhgmpLlUiRvLw
QaMnGaxiMaWaLdGJ7xeYAnUm7KDkPvP+r+0k5urM9vnImB2tG3OjxOpL1bUIFPZC2+kzRZ2mm1E+
DLx5pqhpXVeK5KSMv7hhyTfZEfSyn0fJkjuhPrU2oeNowA+R0qD9msWlmyF4qD1/ZRRz8ouM8kEW
4LMbcFnxSB5kNKmGhLKs6U7ORLEGyinDoHF2gKIK/11XW4Qh/CJpkBD4DanbXmGQWpVOOhnvSOUe
4rSeDd2BlgZoajnztTmOJcvRd/LUAM6ka+QOYF2r6xyUalOMbf2L+MPWGZn9QuRDHgxcOyX2bT5P
DhSb7ATqR155xsPtrykQGLd095q2T8Fu0gqbdRTnU0ZxUgI5EyDQxVLGcCan8AoMtVjiKs/5OFNx
YtnAjSAint0pTb3g+9IsW3DVFX07i5fxQCGhS6qIXbtj1N/r6Zz/HUJFbcOca7AzCvQJSFjZdqRp
5Gzme2LU4fT8I9rn5tLBfiFQdnfOKc4q6Lav9PcWHlRF6y2MJKR/I7wcFIbGqnVk8D7oaZM8eyTY
9jmnJA0JAZ7keLv1rI7q3OQy2kTccer+DRDTRwdAOLdHZGd70oSMkW3ZguhMnroje8OBC97tSSU+
lDzT5iV+thLSxemv4yAV7maQrtUQYTNoC41KgTOW2FFwt/09zpaRgw8WGN0RQZbMSb9HfdBhuVB4
SRzBfx6jEySdUOJTkphi60Mek5jttDxti34cmHXWbK7oXAgesWSEVqwxv6TnWbKFLZphp/zP3GeU
kvR5wFLop81KlvVBgJ37XzsKb422Fid+MnyInvpCiWCPM1gHAaYRjqFK7dvgCWv4h682cwwhT+lU
QiE0FM6JiqpATqygCElcFcQFP3SJonIiqKSWYpdS1xf6xLbQH7PfVbfrLpD6Ux7fXO9LN10y7NZb
846IR1VbG2r1mdBSY1OdgEp2x9xPFQvU1zFdV5xQAtUNvp6RJKaFO5bKwTm10N7yAQIVZUOtcB4Y
NXBAIhcinsXhatyN5MBJK26oGeqMmIAED6UiXMPmGC/TMUJpARwxG54TrvEB8xcNvoy/ugwWVlfA
IhZE0w7NoxVvEu3f5p9jyL+Us1AXntXT2YTrrUxPuGGjsbeXm83CTAjgWOQ/YvuYDBjJdglERy/Z
DTFbFA//Ih7adIj1EZW3At5+hHqo7rhfGtvjpDv3weGaoE+hlT/9giB1+exOwEjxa//CgA45n+OS
DaxrwXtxX694c/akblU56V8BknahTS2hWbUg6S46rxJenDgM7k8fqUlymfyzqv2HDz/jgSEoVlL2
+3veUq638iKyDFhzrKgr7GwqWfjBSuMRrd2vOt7Nd5JoPRqm18HFjo9+JWfgG/DpZKpteOItElMS
7wvEFIvEW+UnXxmH/93wOqKedc1jVFonBFwaM8ve3kNCYTSf5sBrFLFeZrr0SsMKvup3u5I7DP1R
p/mvG3NdC729YkDPVuWZHZeRCCvs2s7o/Jn3JaLTtsSZ9Sg0iJzE3Yd9s3jNKN0VkD39KxMswurk
zX5AiSTyz+5CLqWZwfc3XpQdrWURlD6VOgi1IqJqi8uaCWuzb7W3brGTLK+kj2Md7kW2PgpRZ0v5
Lypkveub2586LELcFoRjo2t8D9wbTVSLJuxYCaYMPozf/fMy5NX0hridX5wsf3h0LGxrV+QaiOck
j/Tc4CFrfMrj+PmZB/zwL1QZSXt3AKanPq2wsJloFcNrqhuI1ZXbU2ZCLTnfZFO4lzf1Sl/iULRu
HPKyDAMiAOU4ZMGPnW/1IG02u48xAGCi3nGxXWxOrq6SgezRb/iME8w0su2LoyobPD/2MUtVowIQ
cwaIAJwNMbrzIJn1bB5UZqe+lxoRBMzy5cSV81BmZGRsOvFLgTZefELuJzxPDcGln31aykC1lvBy
p8pfoVLnqG0ozpYE+Lv+cLOzjmyubYcCltMLwKKnitD6UY9PJFVtTMyP29GUBmUcoQnK0bizm+UF
N0zUpPYt37T6/+spPVUVxQqQh6fDylPBzwWZttGn2WcwnA4Gqp+1MovObOuAZBrFR9xg4EjBNYUp
9Jc2f0ulQI6+bl4iSrbZ9QxKWcrQR5Thy61aGatDBonJkRDmUQQspV45no0wiCWMjRgGDgSr61jQ
CWhHzwRc6xFtmIg5WkZeB1nIrpLpeXACJBvok0nSh3D/yIdd0qhuS7bFcxcLamhPAP/NsoR6QtSc
rvH5qcvKcT0/VJgyefvxT0O41ZjxBq4GUritCSycwWLOS84XqvV701gGSLoGKmSu7+NGEPIGVAil
0LDK21lrks56IAFc6b5uG0ILkjtiizRAI4upKpJakwKv+3JRm2P0lorpc2dby+39qv6XV8+F6KFM
URoXImUAKKL9rd9N5uiUJ5sgpq3qpdSLBWtdOE8+dId/Uq5O1/ZN3WzTAoU0UK1jhOkCUUFEN8dO
yV6NbkrxMTviASurW3JpaulX21ZcanpPKE00omsWmN74DCy3LNWcSzshjPmcoKX0jIqB0e63fmCq
R8JJG4D9K/s2E/I08cIv0jXF22eF2I3wPbE9HZrwNWlHMGR9I4AQaogHQFaEQ0MbSns86R4CKxBT
NJ3bpy13SGEswXchvM/EUKukSs4lDU7mbrbOMeBuaWMl58RHn+nNHlS0CkvOa+Pj2D0WTAiks+tE
0oByKMtl6JDEYdZK6PF3YuRwH/AnZ/WfzN7aVSSu+B4RteFvAnZFo8bGvJKGgXUbmehotZe9dYR3
57+KRbbBw//6qbhCRPAfSTA2rEBKjRrptKpJECue1/1d57h2ngyIPdtLLTW5yMtVXvSEGb+G6gEs
zWc1SJewNmbHTHMAT3qZBaUREMzbwRptVHVpFA+LNZBZSuYVCBvUp1OlaVO+R/WCfoz3flrY8L/0
27rZlHlZx5FMiB/YnlCpscHbIgPpOmzyCzbKfS0OzGT0PsVUoudTYqhj9Wun4xgM3x0GstPl8zSG
2KU1Wfq2sLdKiVs5uB1eZib6p35op8Qd0LHWS7ks0DPE2hOYL8/8qqM1ordvVpv2/FbJkYA7ZiBe
8GEIauLTeuYR7fpSnQjXv1Dm8JaRNjp1ViDjtKQIqdvgxBq4XKEEBk4R8e2rkJJp7WoxBBMpDAKc
THJDp/U5moR6UADYw+c1O9HbXWAugDxavUCHqdflougQJbeQ4um0CbOxlCpsjCVA6E49M+Ku1OqU
C5GLR+J8QL4zLNYQCL2xRmlw+B7eeAn8HYG4qECOEazpDGS+ftV1vjy0tm6GQu+Rct2OzfUY/uvg
5aGgORdeeR1MU9m6DXxttSxw0wvvijM+xSxdFkJLsmUT35wzxpu+7SboWs5fk7+bf/U6ZWzWQa+s
+hcHnqYZR2ddl/TvFN6rOMXBhJrv5i6//Ct8pEDFSsFckawvyTxEuTyeMUbNArF4CaG/+k91PA77
BIwx1EdXjGKzWFlEnxeYgXAfbMEOqPGTaiS/GOsTfomKQgVBl559KLYW7oMBBRXRxenoiwA9uH4F
E1DzjlWfnaKSa6EbjXoHAo00gEvV4/YjhyumoDdrLV0v8aqY1a3jg9E2/I5yymSy+mosY1Q+mmQM
cSr/QnO4+cU+pk8jMvRSNLdnxCcoDGyFrt+xJOK0YyW5etgf13r3FSLGFWHzQhZAr5/SgWM3FR0Y
8Jz9tLfC37OeJHqwqG8ptwWHhbPl8xTFEWxGzPDbK2V673Zydy9SqUXq4B+ZnjrSWJSqfWEuLN9X
47mgGa8dNSN2ogg9EnqL/AZk8EippNNx3qBgeDlvs0pioA36q3+Qb7C7nvCBna4a2Joe+MpPUeRh
0/zBS5KXG4EBoRe7SVr+k7hJiXaM4amhqFyNkpXHaifc38fwbmfzr4gOz2pMTFA6t0I8wj9mxSPL
HLjZ9kjWs/r/BUkkC+POAo+M+gDjA+zCtpUIxSzTW4kuh0fdWbs5G6E8ig+9EI3C2UfHBl+uiyM2
NZC8kGLgHBvJzAfHlqCr52PjkjIOiFTXYAQh+G4ipJMhiip7O5OiWrr7r/eFk2MG/BfgaMF7S4nx
EnOW3kpyWbG8eiegb5nG4w+973tGqb8s5q2dg8bDC2g916FUwI8b+DuZA3YY1lFpGdWbi2ImzDnd
8zikgNBcYENb2fPp40Tr8SsetljiqDUgd4yoquoe8A3ilL65zm2DONd4oIDD9arf+Y+HPOlmxike
gvQZEzBu26ErFgWiC3ankPr0bFdNznVa1ZW3SpR/rWWYP4TrsJE0VMeu9ymd1uZ3LLobHPHHAQVS
Ex6yABijUIznFek2eNNM7/QR7QUei6M70axMqmFwaX5KqrxF6nO+R/gFgMJNdDLp0Zuc//XbOHW7
zAZM5/ZFJcc06azaRhy9KAS1vOX/VzgfgYk8Vk3PzMuRL19ehgbX9Ff1y+XnLL697CdCYrLVXOR2
qEofiLH5xkLROC+OTlzYOdUVnHK3fIm1XTqex/3GFZu/D/BtkAbP4KHgwu9bOunnE6iI3uFCosKE
Je9gpmQs8eOcDUlvejiiIxlhL4aK4AF4uUpJKFaI2m/EpHSEDWaR7Zmj9rHxCqXAdaKn+A8VY8rU
SoGjMGUSAi5zhnp8dH6XNAH5ydnZRfrXKCZVdaDz0USOQ2tPR2ply87eYJ8VJycU+k93wHZlP6YE
1pME/C7WJkJB+Bzpq1uyYPloRJWhfQvnQEwxGgrDnZ810kD/osyWe5JxahfvZ3huPK3CkmauBOYt
hvZIrmZPC+693YgceniaAWJG9LKxlBW/U/M7tPFleiA28ZkGAQGMY+FSAHHEkWC1zdldT0pTEDmJ
eyvx1/sQEFFyLBoDYJarrnjmnkOUaeeUx2Qq0NcoqTV9Msq6b2VscFn9/A4HhLyGxd9XeVEgJhap
9/wousk5xWVR/dRDzjaTG7fLFe5ok/bikKad64CIRQ22GCX6/H+UEOGJZaLqDSuJGjQ2hDrU+I+S
+zKKTWhPmml1XRSsLoc4vuugxY3HqcAqPG0pGWN8q/NHMfke86iQjEP8FHVNZJ9KPUcHqK6xZ8XR
TuEiXyDteVtF/bfK97re+zvnrNYj7Ch6/o6nBOrxfaUBIEeYgoCM00XkaXFZyZ0OE1w6p9tuUl+u
zwZj0jtLtzeSyAri/kE4CNs60CPEzYaAZoZPk6IHZ8arKbgv9Jhmhegc+/HTRakwKlDbjarJsrmA
AN3V0DMEiV4dCceHzs6/kkmaBQL3lCcSz6p4eu9gCZsmdeXbWsCzbIona/WCSk4iQ6A0+H5xbjO8
OSdzJce2dQwoiMguskv9A8MzeVoW+I7HcJHhR8liSPofgJEQFZcplkX36GsY/xCdqUby8uT7xtNQ
Z1zMIKFk2m0Dw3MXUXiEAUBVvkue4a7XP+KD9y28WjjwWJa55Yy0N7iKkdgWlXpsWsz3mToJxQVc
okHcAnZSMUu6rtAUvHL1H3GNCXBSPQqVovRjfWBHNTo0qAFUqYVGVlJ3wGsyqufOciJ9ykfOIqlS
ZsDV20AbeTV73vflQugttl5rAoskG0tP8jvIKo+LOvnzC4F1HI0AbweF1g==
`protect end_protected
|
--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
--Date : Sun Mar 01 22:41:07 2015
--Host : dodo-PC running 64-bit Service Pack 1 (build 7601)
--Command : generate_target ARM_wrapper.bd
--Design : ARM_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ARM_wrapper is
port (
BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : out STD_LOGIC;
BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : out STD_LOGIC;
BRAM_PORTA_rst : out STD_LOGIC;
BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end ARM_wrapper;
architecture STRUCTURE of ARM_wrapper is
component ARM is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : out STD_LOGIC;
BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : out STD_LOGIC;
BRAM_PORTA_rst : out STD_LOGIC;
BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component ARM;
begin
ARM_i: component ARM
port map (
BRAM_PORTA_addr(12 downto 0) => BRAM_PORTA_addr(12 downto 0),
BRAM_PORTA_clk => BRAM_PORTA_clk,
BRAM_PORTA_din(31 downto 0) => BRAM_PORTA_din(31 downto 0),
BRAM_PORTA_dout(31 downto 0) => BRAM_PORTA_dout(31 downto 0),
BRAM_PORTA_en => BRAM_PORTA_en,
BRAM_PORTA_rst => BRAM_PORTA_rst,
BRAM_PORTA_we(3 downto 0) => BRAM_PORTA_we(3 downto 0),
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_logic;
serve_enable : in std_logic;
serve_inhibit : in std_logic;
timing_addr : in unsigned(2 downto 0) := "000";
edge_recover : in std_logic;
allow_serve : out std_logic;
phi2_tick : out std_logic;
phi2_fall : out std_logic;
phi2_recovered : out std_logic;
clock_det : out std_logic;
vic_cycle : out std_logic;
inhibit : out std_logic;
do_sample_addr : out std_logic;
do_probe_end : out std_logic;
do_sample_io : out std_logic;
do_io_event : out std_logic );
end slot_timing;
architecture gideon of slot_timing is
signal phi2_c : std_logic;
signal phi2_d : std_logic;
signal ba_c : std_logic;
signal phase_h : integer range 0 to 127 := 0;
signal phase_l : integer range 0 to 127 := 0;
signal allow_tick_h : boolean := true;
signal allow_tick_l : boolean := true;
signal phi2_falling : std_logic;
signal ba_hist : std_logic_vector(3 downto 0) := (others => '0');
signal phi2_rec_i : std_logic := '0';
signal phi2_tick_i : std_logic;
signal serve_en_i : std_logic := '0';
signal off_cnt : integer range 0 to 7;
constant c_memdelay : integer := 5;
-- constant c_probe_end : integer := 11; -- was 11: 220 ns
-- constant c_sample_vic : integer := 10; -- was 10: 200 ns
-- constant c_io : integer := 19; -- was 19: 380 ns!
constant c_probe_end : integer := 14; -- 224 ns
constant c_sample_vic : integer := 12; -- 192 ns
constant c_io : integer := 24; -- 384 ns!
signal do_sample_addr_i : std_logic;
attribute register_duplication : string;
attribute register_duplication of ba_c : signal is "no";
attribute register_duplication of phi2_c : signal is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of ba_c : signal is true;
attribute dont_replicate of phi2_c : signal is true;
attribute dont_retime : boolean;
attribute dont_retime of ba_c : signal is true;
attribute dont_retime of phi2_c : signal is true;
begin
vic_cycle <= '1' when (ba_hist = "0000") else '0';
phi2_recovered <= phi2_rec_i;
phi2_tick <= phi2_tick_i;
phi2_fall <= phi2_d and not phi2_c;
do_sample_addr <= do_sample_addr_i;
process(clock)
begin
if rising_edge(clock) then
ba_c <= BA;
phi2_c <= PHI2;
phi2_d <= phi2_c;
phi2_tick_i <= '0';
-- Off counter, to allow software to gracefully quit
if serve_enable='1' and serve_inhibit='0' then
off_cnt <= 7;
serve_en_i <= '1';
elsif off_cnt = 0 then
serve_en_i <= '0';
elsif phi2_tick_i='1' and ba_c='1' then
off_cnt <= off_cnt - 1;
serve_en_i <= '1';
end if;
-- related to rising edge
if ((edge_recover = '1') and (phase_l = 32)) or
((edge_recover = '0') and phi2_d='0' and phi2_c='1' and allow_tick_h) then
ba_hist <= ba_hist(2 downto 0) & ba_c;
phi2_tick_i <= '1';
phi2_rec_i <= '1';
phase_h <= 0;
clock_det <= '1';
allow_tick_h <= false; -- filter
elsif phase_h = 127 then
clock_det <= '0';
else
phase_h <= phase_h + 1;
end if;
if phase_h = 58 then -- max 1.06 MHz
allow_tick_h <= true;
end if;
-- related to falling edge
phi2_falling <= '0';
if phi2_d='1' and phi2_c='0' and allow_tick_l then -- falling edge
phi2_falling <= '1';
phi2_rec_i <= '0';
phase_l <= 0;
allow_tick_l <= false; -- filter
elsif phase_l /= 127 then
phase_l <= phase_l + 1;
end if;
if phase_l = 58 then -- max 1.06 MHz
allow_tick_l <= true;
end if;
do_io_event <= phi2_falling;
-- timing pulses
do_sample_addr_i <= '0';
if phase_h = timing_addr then
do_sample_addr_i <= '1';
end if;
if serve_vic='1' and phase_l = (c_sample_vic - 1) then
do_sample_addr_i <= '1';
end if;
do_probe_end <= '0';
if phase_h = c_probe_end then
do_probe_end <= '1';
end if;
do_sample_io <= '0';
if phase_h = c_io - 1 then
do_sample_io <= '1';
end if;
if (phase_h = 0 and serve_en_i = '1') or
(phase_l = (c_sample_vic - c_memdelay) and serve_vic = '1') then
inhibit <= '1';
elsif do_sample_addr_i = '1' then
inhibit <= '0';
end if;
if reset='1' then
allow_tick_h <= true;
allow_tick_l <= true;
phase_h <= 127;
phase_l <= 127;
inhibit <= '0';
clock_det <= '0';
end if;
end if;
end process;
allow_serve <= serve_en_i;
end gideon;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:32 06/04/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IP_complete_nomac_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IP_complete_nomac
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
ENTITY IP_complete_nomac_tb IS
END IP_complete_nomac_tb;
ARCHITECTURE behavior OF IP_complete_nomac_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
--Inputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_tready : std_logic := '0';
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_rx_tvalid : std_logic := '0';
signal mac_rx_tlast : std_logic := '0';
signal control : ip_control_type;
--Outputs
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
signal ip_rx_start : std_logic;
signal ip_rx : ipv4_rx_type;
signal arp_pkt_count : std_logic_vector(7 downto 0);
signal mac_tx_tdata : std_logic_vector(7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tfirst : std_logic;
signal mac_tx_tlast : std_logic;
signal mac_rx_tready : std_logic;
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IP_complete_nomac PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => clk,
tx_clk => clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control,
arp_pkt_count => arp_pkt_count,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 80 ns;
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
control.arp_controls.clear_cache <= '0';
ip_tx_start <= '0';
mac_tx_tready <= '0';
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
assert mac_tx_tlast = '0' report " mac_tx_tlast not initialised correctly on reset";
assert arp_pkt_count = x"00" report " arp_pkt_count not initialised correctly on reset";
assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
-- insert stimulus here
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
mac_tx_tready <= '1';
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
mac_rx_tdata <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_rx_tdata <= x"45"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- total len
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
-- ID
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- flags & frag
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- TTL
mac_rx_tdata <= x"00"; wait for clk_period;
-- Protocol
mac_rx_tdata <= x"11"; wait for clk_period;
-- Header CKS
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- SRC IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- DST IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
-- user data
mac_rx_tdata <= x"24"; wait for clk_period;
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
assert ip_rx_start = '1' report "T1: ip_rx_start not set";
assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
mac_rx_tdata <= x"25"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"27"; mac_rx_tlast <= '1'; wait for clk_period;
assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
mac_rx_tdata <= x"00";
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait for clk_period;
assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
------------
-- TEST 2 -- respond with IP TX
------------
report "T2: respond with IP TX";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period;
ip_tx_start <= '1'; wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
wait for clk_period*2;
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
-- need to wait for ARP tx to complete
wait for clk_period*50;
assert mac_tx_tvalid = '0' report "T2: mac_tx_tvalid not cleared after ARP tx";
assert mac_tx_tlast = '0' report "T2: mac_tx_tlast not cleared after ARP tx";
-- now create the ARP response (rx)
-- Send the reply
-- Send an ARP reply: x"c0123478" has mac 02:12:03:23:04:54
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"06"; wait for clk_period;
-- HW type
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Protocol type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- HW size
mac_rx_tdata <= x"06"; wait for clk_period;
-- protocol size
mac_rx_tdata <= x"04"; wait for clk_period;
-- Opcode
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"02"; wait for clk_period;
-- Sender MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- Sender IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"34"; wait for clk_period;
mac_rx_tdata <= x"78"; wait for clk_period;
-- Target MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- Target IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '1';
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"56"; wait for clk_period;
ip_tx.data.data_out <= x"57"; wait for clk_period;
ip_tx.data.data_out <= x"58"; wait for clk_period;
ip_tx.data.data_out <= x"59"; wait for clk_period;
ip_tx.data.data_out <= x"5a"; wait for clk_period;
ip_tx.data.data_out <= x"5b";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_tx_tlast = '1' report "T2: mac_tx_tlast not set on last byte";
wait for clk_period;
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be SENT";
wait for clk_period*10;
------------
-- TEST 3 -- Check that sending to the same IP addr doesnt cause an ARP req as the addr is cached
------------
report "T3: Send 2nd IP TX to same IP addr - should not need to do ARP tx/rx";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period;
ip_tx_start <= '1'; wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
wait for clk_period*2;
assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"81"; wait for clk_period;
ip_tx.data.data_out <= x"83"; wait for clk_period;
ip_tx.data.data_out <= x"85"; wait for clk_period;
ip_tx.data.data_out <= x"87"; wait for clk_period;
ip_tx.data.data_out <= x"89"; wait for clk_period;
ip_tx.data.data_out <= x"8b";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_tx_tlast = '1' report "T3: mac_tx_tlast not set on last byte";
wait for clk_period;
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be SENT";
wait for clk_period*2;
report "-- end of tests --";
wait;
end process;
END;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 18 23:18:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.vhdl
-- Design : system_xlconstant_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_xlconstant_0_0 is
Port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_xlconstant_0_0;
architecture stub of system_xlconstant_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "dout[0:0]";
begin
end;
|
-----------------------------------------------------------------------------
-- MUX_branch
-- This MUX is feed with the following inputs:
-- - PCSrc: control signal coming from the MEM stage that eventually
-- tells whether a branch is taken or not.
-- - PC_4: is the current value of the program counter incremented by
-- 4
-- - Branch_Target: is the addrress target coming from the MEM stage
-- Depending on the value of PCSrc:
-- - 0: the output is assigned to PC_4
-- - 1: the output is assigned to Branch_Target
-- The output of this MUX feeds directly MUX_jump
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
entity mux_branch is
port (
-- INPUTS
from_increment_pc : in std_logic_vector(31 downto 0); -- pc incremented by 4 coming from the adder
branch_target : in std_logic_vector(31 downto 0); -- target addrress coming from the MEM stage
pcsrc : in std_logic; -- control signal for the mux coming from the MEM stage
-- OUTPUTS
to_mux_jump : out std_logic_vector(31 downto 0) -- output address directed to the next mux in the chain(MUX_jump)
);
end mux_branch;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behavioral of mux_branch is
begin
to_mux_jump <= branch_target when (pcsrc = '1') else from_increment_pc;
end behavioral;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiplexer is
end entity alt_dspbuilder_multiplexer;
architecture rtl of alt_dspbuilder_multiplexer is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.complex_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity complex_const_mult is
generic(
UNSIGNED_2COMP_opt : boolean := false; --default
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
MIN_OUTPUT_BIT : integer := integer'low; --exception: value not set
MAX_OUTPUT_BIT : integer := integer'low; --exception: value not set
MULTIPLICAND_REAL : real; --compulsory
MULTIPLICAND_IMAG : real --compulsory
);
port(
input_real : in std_ulogic_vector;
input_imag : in std_ulogic_vector;
clk : in std_ulogic;
valid_input : in std_ulogic;
output_real : out std_ulogic_vector;
output_imag : out std_ulogic_vector;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture complex_const_mult_1 of complex_const_mult is
--assumed that both real and imag inputs have the same size
constant NORM_IN_HIGH : integer := input_real'high - SULV_NEW_ZERO;
constant NORM_IN_LOW : integer := input_real'low - SULV_NEW_ZERO;
--constant CHECKS : integer := real_const_mult_CHECKS(input'high,
-- input'low,
-- UNSIGNED_2COMP_opt,
-- ROUND_TO_BIT_opt,
-- MAX_ERROR_PCT_opt,
-- MULTIPLICANDS);
constant NORM_OUT_HIGH : integer := complex_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MAX_OUTPUT_BIT,
(1 => MULTIPLICAND_REAL,
2 => MULTIPLICAND_IMAG),
NORM_IN_HIGH,
NORM_IN_LOW,
not UNSIGNED_2COMP_opt);
constant NORM_OUT_LOW : integer := complex_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MIN_OUTPUT_BIT,
(1 => MULTIPLICAND_REAL,
2 => MULTIPLICAND_IMAG),
NORM_IN_LOW,
not UNSIGNED_2COMP_opt);
constant OUT_HIGH : natural := NORM_OUT_HIGH + SULV_NEW_ZERO;
constant OUT_LOW : natural := NORM_OUT_LOW + SULV_NEW_ZERO;
signal aux_input_real_s : u_sfixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_input_imag_s : u_sfixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_real_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_output_imag_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_input_real_u : u_ufixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_input_imag_u : u_ufixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_real_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_output_imag_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
generate_real_const_mult:
if UNSIGNED_2COMP_opt generate
begin
--aux_input_real_u <= to_ufixed(input_real, aux_input_real_u);
--aux_input_imag_u <= to_ufixed(input_imag, aux_input_imag_u);
--complex_const_mult_u_1:
--entity work.complex_const_mult_u
-- generic map(
-- SPEED_opt => SPEED_opt,
-- ROUND_STYLE_opt => ROUND_STYLE_opt,
-- ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
-- MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
-- MULTIPLICAND_REAL => MULTIPLICAND_REAL,
-- MULTIPLICAND_IMAG => MULTIPLICAND_IMAG
-- )
-- port map(
-- input_real => aux_input_real_u,
-- input_imag => aux_input_imag_u,
-- clk => clk,
-- valid_input => valid_input,
-- output_real => aux_output_real_u,
-- output_imag => aux_output_imag_u,
-- valid_output => valid_output
-- );
--output_real <= to_std_ulogic_vector(aux_output_real_u, output_real);
--output_imag <= to_std_ulogic_vector(aux_output_imag_u, output_imag);
end;
else generate
begin
aux_input_real_s <= to_sfixed(input_real, aux_input_real_s);
aux_input_imag_s <= to_sfixed(input_imag, aux_input_imag_s);
complex_const_mult_s_1:
entity work.complex_const_mult_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MIN_OUTPUT_BIT => MIN_OUTPUT_BIT,
MULTIPLICAND_REAL => MULTIPLICAND_REAL,
MULTIPLICAND_IMAG => MULTIPLICAND_IMAG
)
port map(
input_real => aux_input_real_s,
input_imag => aux_input_imag_s,
clk => clk,
valid_input => valid_input,
output_real => aux_output_real_s,
output_imag => aux_output_imag_s,
valid_output => valid_output
);
output_real <= to_std_ulogic_vector(aux_output_real_s);
output_imag <= to_std_ulogic_vector(aux_output_imag_s);
end;
end generate;
end architecture; |
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_cfa_gamma_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 7);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_cfa_gamma_plbw;
architecture structural of sg_cfa_gamma_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(7 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_cfa_gamma_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity customblock is
port(C : in std_logic;
D : in std_logic;
Q : out std_logic);
end customblock;
architecture bhv of customblock is
signal count: integer:=1; --counts number of CLOCK cycles
signal period: integer:=10; --PWM signal period is 10 times of clock period
signal boost : integer:=9; --number of clock pulses during T_ON
signal buck : integer:=1; --number of clock pulses during T_OFF
begin
process (C,D)
begin
if(C='1' and C'event) then
count<=count+1;
if(count=period)then -- resets count for period
count<=1;
end if;
if(D='1') then --boost duty cycle when compartor output is high--
if(count<=boost)then
Q<='1';
elsif(count>boost) then
Q<='0';
end if;
end if;
if(D='0')then --buck duty cycle when compartor output is low--
if(count<=buck)then --
Q<='1';
elsif(count>buck)then
Q<='0';
end if;
end if;
end if;
end process;
end bhv;
|
-- NEED RESULT: ARCH00599: Index constraints passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00599
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.2.1.1 (13)
-- 3.2.1.1 (14)
-- 3.2.1.1 (15)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00599(ARCH00599)
-- ENT00599_Test_Bench(ARCH00599_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES ; use STANDARD_TYPES.all ;
entity ENT00599 is
generic ( g1 : integer := 2;
g2 : integer := 5) ;
end ENT00599 ;
--
architecture ARCH00599 of ENT00599 is
begin
P :
process
variable a1 : STANDARD_TYPES.t_arr1 (31 downto 0) ; -- 3.2.1.1 (13)
variable a2 : STANDARD_TYPES.t_arr1 (g2 downto g1) ; -- 3.2.1.1 (14)
function f ( lo, hi : integer ) return integer is
variable v : STANDARD_TYPES.t_arr1 (lo to hi) ; -- 3.2.1.1 (15)
begin
return 256*v'high + v'low ;
end f ;
begin
test_report ( "ARCH00599" ,
"Index constraints" ,
(a1'left = 31) and
(a1'right = 0) and
(a2'left = 5) and
(a2'right = 2) and
(f(2,5) = 256*5+2)
) ;
wait ;
end process P ;
end ARCH00599 ;
--
entity ENT00599_Test_Bench is
end ENT00599_Test_Bench ;
architecture ARCH00599_Test_Bench of ENT00599_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00599 ( ARCH00599 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00599_Test_Bench ;
--
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 4;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 4;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- clockman.vhd
--
-- Author: Michael "Mr. Sump" Poppitz
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- This is only a wrapper for Xilinx' DCM component so it doesn't
-- have to go in the main code and can be replaced more easily.
--
-- Creates clk0 with 100MHz.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clockman is
Port (
clkin : in STD_LOGIC; -- clock input
clk0 : out std_logic -- double clock rate output
);
end clockman;
architecture Behavioral of clockman is
signal clkfb, clkfbbuf, realclk0 : std_logic;
begin
-- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
-- Xilinx HDL Language Template version 8.1i
DCM_baseClock : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => clkin, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0', -- DCM asynchronous reset input
CLK2X => realclk0,
CLK0 => clkfb,
CLKFB => clkfbbuf
);
-- clkfb is run through a BUFG only to shut up ISE 8.1
BUFG_clkfb : BUFG
port map (
O => clkfbbuf, -- Clock buffer output
I => clkfb -- Clock buffer input
);
clk0 <= realclk0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- clockman.vhd
--
-- Author: Michael "Mr. Sump" Poppitz
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- This is only a wrapper for Xilinx' DCM component so it doesn't
-- have to go in the main code and can be replaced more easily.
--
-- Creates clk0 with 100MHz.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clockman is
Port (
clkin : in STD_LOGIC; -- clock input
clk0 : out std_logic -- double clock rate output
);
end clockman;
architecture Behavioral of clockman is
signal clkfb, clkfbbuf, realclk0 : std_logic;
begin
-- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
-- Xilinx HDL Language Template version 8.1i
DCM_baseClock : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => clkin, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0', -- DCM asynchronous reset input
CLK2X => realclk0,
CLK0 => clkfb,
CLKFB => clkfbbuf
);
-- clkfb is run through a BUFG only to shut up ISE 8.1
BUFG_clkfb : BUFG
port map (
O => clkfbbuf, -- Clock buffer output
I => clkfb -- Clock buffer input
);
clk0 <= realclk0;
end Behavioral;
|
----------------------------------------------------------------------------------
-- clockman.vhd
--
-- Author: Michael "Mr. Sump" Poppitz
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- This is only a wrapper for Xilinx' DCM component so it doesn't
-- have to go in the main code and can be replaced more easily.
--
-- Creates clk0 with 100MHz.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clockman is
Port (
clkin : in STD_LOGIC; -- clock input
clk0 : out std_logic -- double clock rate output
);
end clockman;
architecture Behavioral of clockman is
signal clkfb, clkfbbuf, realclk0 : std_logic;
begin
-- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
-- Xilinx HDL Language Template version 8.1i
DCM_baseClock : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => clkin, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0', -- DCM asynchronous reset input
CLK2X => realclk0,
CLK0 => clkfb,
CLKFB => clkfbbuf
);
-- clkfb is run through a BUFG only to shut up ISE 8.1
BUFG_clkfb : BUFG
port map (
O => clkfbbuf, -- Clock buffer output
I => clkfb -- Clock buffer input
);
clk0 <= realclk0;
end Behavioral;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - nco_sync.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Synchronization of two oscillators
-- Whenever the master's phase ends, reset slave's phase.
-- Slave's frequency usually higher and not dividable by
-- master's frequency
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity nco_sync is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SAW
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
master_phase_offset : in signed(31 downto 0);
master_phase_incr : in signed(31 downto 0);
slave_phase_offset : in signed(31 downto 0);
slave_phase_incr : in signed(31 downto 0);
soundout : out signed(31 downto 0)
);
end nco_sync;
architecture Behavioral of nco_sync is
component sawtooth
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end component sawtooth;
component nco
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM_SLAVE : WAVEFORM_TYPE := WAVEFORM
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end component nco;
constant master_threshold : signed (31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal master_data : signed(31 downto 0);
signal slave_data : signed(31 downto 0);
signal slave_rst : std_logic := '0';
signal state : integer := 0;
begin
soundout <= slave_data;
SAWTOOTH_MASTER_INSTA : sawtooth
port map(
clk => clk,
ce => ce,
rst => rst,
incr => master_phase_incr,
offset => master_phase_offset,
saw => master_data );
NCO_INSTA : nco
Port map(
clk => clk,
rst => slave_rst,
ce => ce,
phase_offset => slave_phase_offset,
phase_incr => slave_phase_incr,
data => slave_data
);
SYNC_PROCESS : process (clk)
begin
if rising_edge(clk) then
if master_data = master_threshold then
case state is
when 0 =>
slave_rst <= '1';
state <= 1;
when 1 =>
slave_rst <= '0';
state <= 0;
when others =>
state <= 0;
end case;
elsif slave_rst = '1' then
slave_rst <= '0';
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Input synchronizer block
-------------------------------------------------------------------------------
-- Description: The input synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity input_synchronizer is
generic (
g_width : positive := 1;
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of input_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of input_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of input_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of input_synchronizer : entity is true;
---------------------------------------------------------------------------
end input_synchronizer;
architecture rtl of input_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
-- Xilinx attributes
attribute iob : string;
attribute iob of sync1 : signal is "true";
-- Altera attributes
-- Add FAST_INPUT_REGISTER to qsf file to force the sync1 register into an iob
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Input synchronizer block
-------------------------------------------------------------------------------
-- Description: The input synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity input_synchronizer is
generic (
g_width : positive := 1;
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of input_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of input_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of input_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of input_synchronizer : entity is true;
---------------------------------------------------------------------------
end input_synchronizer;
architecture rtl of input_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
-- Xilinx attributes
attribute iob : string;
attribute iob of sync1 : signal is "true";
-- Altera attributes
-- Add FAST_INPUT_REGISTER to qsf file to force the sync1 register into an iob
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Input synchronizer block
-------------------------------------------------------------------------------
-- Description: The input synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity input_synchronizer is
generic (
g_width : positive := 1;
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of input_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of input_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of input_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of input_synchronizer : entity is true;
---------------------------------------------------------------------------
end input_synchronizer;
architecture rtl of input_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
-- Xilinx attributes
attribute iob : string;
attribute iob of sync1 : signal is "true";
-- Altera attributes
-- Add FAST_INPUT_REGISTER to qsf file to force the sync1 register into an iob
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Input synchronizer block
-------------------------------------------------------------------------------
-- Description: The input synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity input_synchronizer is
generic (
g_width : positive := 1;
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of input_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of input_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of input_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of input_synchronizer : entity is true;
---------------------------------------------------------------------------
end input_synchronizer;
architecture rtl of input_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
-- Xilinx attributes
attribute iob : string;
attribute iob of sync1 : signal is "true";
-- Altera attributes
-- Add FAST_INPUT_REGISTER to qsf file to force the sync1 register into an iob
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Input synchronizer block
-------------------------------------------------------------------------------
-- Description: The input synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity input_synchronizer is
generic (
g_width : positive := 1;
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of input_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of input_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of input_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of input_synchronizer : entity is true;
---------------------------------------------------------------------------
end input_synchronizer;
architecture rtl of input_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
-- Xilinx attributes
attribute iob : string;
attribute iob of sync1 : signal is "true";
-- Altera attributes
-- Add FAST_INPUT_REGISTER to qsf file to force the sync1 register into an iob
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver status register ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, gedra@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.3 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.2 2004/06/16 19:03:10 gedra
-- Added channel status decoding.
--
-- Revision 1.1 2004/06/05 17:17:12 gedra
-- Recevier status register
--
--
library ieee;
use ieee.std_logic_1164.all;
entity rx_status_reg is
generic (DATA_WIDTH: integer);
port (
up_clk: in std_logic; -- clock
status_rd: in std_logic; -- status register read
lock: in std_logic; -- signal lock status
chas: in std_logic; -- channel A or B select
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end rx_status_reg;
architecture rtl of rx_status_reg is
signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal cur_pos : integer range 0 to 255;
signal pro_mode : std_logic;
begin
status_dout <= status_vector when status_rd = '1' else (others => '0');
D32: if DATA_WIDTH = 32 generate
status_vector(31 downto 16) <= (others => '0');
end generate D32;
status_vector(0) <= lock;
status_vector(15 downto 7) <= (others => '0');
-- extract channel status bits to be used
CDAT: process (up_clk, lock)
begin
if lock = '0' then
cur_pos <= 0;
pro_mode <= '0';
status_vector(6 downto 1) <= (others => '0');
else
if rising_edge(up_clk) then
-- bit counter, 0 to 191
if rx_block_start = '1' then
cur_pos <= 0;
elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
cur_pos <= cur_pos + 1;
end if;
-- extract status bits used in status register
if (chas = '0' and cs_b_en = '1') or
(chas = '1' and cs_a_en = '1') then
case cur_pos is
when 0 => -- PRO bit
status_vector(1) <= ch_data;
pro_mode <= ch_data;
when 1 => -- AUDIO bit
status_vector(2) <= not ch_data;
when 2 => -- emphasis/copy bit
if pro_mode = '1' then
status_vector(5) <= ch_data;
else
status_vector(6) <= ch_data;
end if;
when 3 => -- emphasis
if pro_mode = '1' then
status_vector(4) <= ch_data;
else
status_vector(5) <= ch_data;
end if;
when 4 => -- emphasis
if pro_mode = '1' then
status_vector(3) <= ch_data;
else
status_vector(4) <= ch_data;
end if;
when 5 => -- emphasis
if pro_mode = '0' then
status_vector(3) <= ch_data;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process CDAT;
end rtl;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY mixer_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16;
max_amplitude : integer := 32767;
min_amplitude : integer := -32767
);
PORT(
a_clk : in std_logic;
reset : in std_logic;
DATA_SI_1, DATA_SI_2 : in std_logic_vector(15 downto 0);
DATA_SQ_1, DATA_SQ_2 : in std_logic_vector(15 downto 0);
DATA_SA_1, DATA_SA_2 : in std_logic_vector(15 downto 0);
DATA_TR_1, DATA_TR_2 : in std_logic_vector(15 downto 0);
WAV_SELECT : in std_logic_vector(7 downto 0);
DATA_TO_AI : OUT std_logic_vector(15 downto 0)
);
END mixer_entity;
ARCHITECTURE behav of mixer_entity is
SIGNAL osc1,osc2,output : integer := 0;
BEGIN
process(a_clk, reset)
variable osc1,osc2 : integer := 0;
begin
if reset = '0' then
osc1 := 0;
osc2 := 0;
output <= 0;
DATA_TO_AI <= (others => '0');
elsif falling_edge(a_clk) then
case(WAV_SELECT) is
WHEN x"00" => -- SINE
osc1 := to_integer(signed(DATA_SI_1));
osc2 := to_integer(signed(DATA_SI_2));
WHEN x"01" => -- SQUARE
osc1 := to_integer(signed(DATA_SQ_1));
osc2 := to_integer(signed(DATA_SQ_2));
WHEN x"02" => -- SAW
osc1 := to_integer(signed(DATA_SA_1));
osc2 := to_integer(signed(DATA_SA_2));
WHEN x"03" => -- TRI
osc1 := to_integer(signed(DATA_TR_1));
osc2 := to_integer(signed(DATA_TR_2));
WHEN others => -- SINE
osc1 := to_integer(signed(DATA_SI_1));
osc2 := to_integer(signed(DATA_SI_2));
END CASE;
osc1 := osc1/4;
osc2 := osc2/4;
output <= osc1 + osc2;
DATA_TO_AI <= std_logic_vector(to_signed(output, DATA_width));
end if;
end process;
END ARCHITECTURE; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_0_arch OF DemoInterconnect_axi_spi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "axi_spi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_axi_spi_master_1_0_arch : ARCHITECTURE IS "DemoInterconnect_axi_spi_master_1_0,axi_spi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_0_arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_8.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_8
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_8
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_8 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_vld : OUT std_logic
);
END TWDLROM_3_8;
ARCHITECTURE rtl OF TWDLROM_3_8 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_8_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_8_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#1#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_8_re_tmp <= twdlIn_re;
twdl_3_8_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_8_re <= std_logic_vector(twdl_3_8_re_tmp);
twdl_3_8_im <= std_logic_vector(twdl_3_8_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_8_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_8_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
-- Core for UART
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_core is
port(
clk_sys: in std_logic; --system clock
clk_uart: in std_logic; --uart clock (14,4?)
res: in std_logic; --reset
tx: out std_logic; --tx TLE pin
rx: in std_logic; --rx TLE pin
rx_data_output: out unsigned(7 downto 0); --rx data read from fifo
rx_data_count: out unsigned(5 downto 0); --byte count in fifo
rx_data_rdreq: in std_logic; --request read from rx fifo
tx_data_input: in unsigned(7 downto 0); --tx data write into fifo
tx_data_count: out unsigned(5 downto 0); --byte count in tx fifo
tx_data_wrreq: in std_logic; --request write into tx fifo
n: in unsigned(15 downto 0); --control signals
txen: in std_logic;
rxen: in std_logic;
tx_done: out std_logic; --byte sended
rx_done: out std_logic --byte recieved
);
end entity uart_core;
architecture uart_core_arch of uart_core is
component baudgen is
port(
clk: in std_logic;
res: in std_logic;
n: in unsigned(15 downto 0);
baud16_clk_en: out std_logic
);
end component baudgen;
component transmitter is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
baud16_clk_en: in std_logic;
tx_data: in unsigned(7 downto 0);
tx: out std_logic;
tx_dcfifo_rdreq: out std_logic;
tx_dcfifo_rdusedw: in std_logic_vector(5 downto 0);
tx_sended: out std_logic
);
end component transmitter;
component reciever is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
rx: in std_logic;
baud16_clk_en: in std_logic;
rx_data: out unsigned(7 downto 0);
rx_done: out std_logic
);
end component reciever;
component dcfifo is
generic(
intended_device_family: string;
lpm_numwords: natural;
lpm_showahead: string;
lpm_type: string;
lpm_width: natural;
lpm_widthu: natural;
overflow_checking: string;
rdsync_delaypipe: natural;
read_aclr_synch: string;
underflow_checking: string;
use_eab: string;
write_aclr_synch: string;
wrsync_delaypipe: natural;
add_usedw_msb_bit: string
);
port(
rdclk : in std_logic ;
q : out std_logic_vector (7 downto 0);
wrclk : in std_logic ;
wrreq : in std_logic ;
wrusedw : out std_logic_vector (5 downto 0);
aclr : in std_logic ;
data : in std_logic_vector (7 downto 0);
rdreq : in std_logic ;
rdusedw : out std_logic_vector (5 downto 0)
);
end component;
signal baud16_clk_en: std_logic;
signal rx_data: unsigned(7 downto 0);
signal rx_dcfifo_q: std_logic_vector(7 downto 0);
signal rx_dcfifo_rdusedw: std_logic_vector(5 downto 0);
signal tx_dcfifo_data: std_logic_vector(7 downto 0);
signal tx_dcfifo_wrusedw: std_logic_vector(5 downto 0);
signal tx_data: unsigned(7 downto 0);
signal tx_dcfifo_rdreq: std_logic;
signal tx_dcfifo_rdusedw: std_logic_vector(5 downto 0);
signal n_uart: unsigned(15 downto 0);
signal rx_dcfifo_data: std_logic_vector(7 downto 0);
signal tx_dcfifo_q: std_logic_vector(7 downto 0);
signal tx_en_sync, rx_en_sync: std_logic;
signal rx_done_uart, tx_done_uart: std_logic;
signal rx_done_raw, tx_done_raw: std_logic;
type statetype is (idle, come, waittocompleted);
signal tx_done_state: statetype;
signal rx_done_state: statetype;
begin
--clk_uart domain
baudgen0: baudgen
port map(clk_uart, res, n_uart, baud16_clk_en);
transmitter0: transmitter
port map(tx_en_sync, clk_uart, res, baud16_clk_en, tx_data, tx, tx_dcfifo_rdreq, tx_dcfifo_rdusedw, tx_done_uart);
reciever0: reciever
port map(rx_en_sync, clk_uart, res, rx, baud16_clk_en, rx_data, rx_done_uart);
rx_dcfifo_data <= std_logic_vector(rx_data);
tx_data <= unsigned(tx_dcfifo_q);
--crossing clk domains
rx_dcfifo : dcfifo
generic map (
intended_device_family => "cyclone iv e",
lpm_numwords => 32,
lpm_showahead => "off",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "on",
rdsync_delaypipe => 4,
read_aclr_synch => "on",
underflow_checking => "on",
use_eab => "on",
write_aclr_synch => "on",
wrsync_delaypipe => 4,
add_usedw_msb_bit => "ON"
)
port map (
rdclk => clk_sys,
wrclk => clk_uart,
wrreq => rx_done_uart,
aclr => res,
data => rx_dcfifo_data,
rdreq => rx_data_rdreq,
q => rx_dcfifo_q,
wrusedw => open,
rdusedw => rx_dcfifo_rdusedw
);
tx_dcfifo : dcfifo
generic map (
intended_device_family => "cyclone iv e",
lpm_numwords => 32,
lpm_showahead => "off",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "on",
rdsync_delaypipe => 4,
read_aclr_synch => "on",
underflow_checking => "on",
use_eab => "on",
write_aclr_synch => "on",
wrsync_delaypipe => 4,
add_usedw_msb_bit => "ON"
)
port map (
rdclk => clk_uart,
wrclk => clk_sys,
wrreq => tx_data_wrreq,
aclr => res,
data => tx_dcfifo_data,
rdreq => tx_dcfifo_rdreq,
q => tx_dcfifo_q,
wrusedw => tx_dcfifo_wrusedw,
rdusedw => tx_dcfifo_rdusedw
);
--from sys to uart
process(clk_uart) is
variable n_d1: unsigned(15 downto 0);
variable n_d2: unsigned(15 downto 0);
variable txen_1: std_logic;
variable txen_2: std_logic;
variable rxen_1: std_logic;
variable rxen_2: std_logic;
begin
if rising_edge(clk_uart) then
if res = '1' then
n_d1 := (others => '0');
n_d2 := (others => '0');
txen_1 := '0';
txen_2 := '0';
rxen_1 := '0';
rxen_2 := '0';
else
n_d2 := n_d1;
n_d1 := n;
txen_2 := txen_1;
txen_1 := txen;
rxen_2 := rxen_1;
rxen_1 := rxen;
end if;
end if;
n_uart <= n_d2;
rx_en_sync <= rxen_2;
tx_en_sync <= txen_2;
end process;
--from uart to sys
process(clk_sys) is
variable rx_done_1: std_logic;
variable rx_done_2: std_logic;
variable tx_done_1: std_logic;
variable tx_done_2: std_logic;
begin
if rising_edge(clk_sys) then
if res = '1' then
rx_done_2 := '0';
rx_done_1 := '0';
tx_done_2 := '0';
tx_done_1 := '0';
else
rx_done_2 := rx_done_1;
rx_done_1 := rx_done_uart;
tx_done_2 := tx_done_1;
tx_done_1 := tx_done_uart;
end if;
end if;
tx_done_raw <= tx_done_2;
rx_done_raw <= rx_done_2;
end process;
--sysclk domain
rx_data_output <= unsigned(rx_dcfifo_q);
rx_data_count <= unsigned(rx_dcfifo_rdusedw);
tx_dcfifo_data <= std_logic_vector(tx_data_input);
tx_data_count <= unsigned(tx_dcfifo_wrusedw);
process(clk_sys) is
begin
if(rising_edge(clk_sys)) then
if(res = '1') then
tx_done_state <= idle;
else
case tx_done_state is
when idle =>
if (tx_done_raw = '1') then
tx_done_state <= come;
else
tx_done_state <= idle;
end if;
when come => tx_done_state <= waittocompleted;
when waittocompleted =>
if(tx_done_raw = '1') then
tx_done_state <= waittocompleted;
else
tx_done_state <= idle;
end if;
end case;
end if;
end if;
end process;
process(tx_done_state) is
begin
case tx_done_state is
when idle => tx_done <= '0';
when come => tx_done <= '1';
when waittocompleted => tx_done <= '0';
end case;
end process;
process(clk_sys) is
begin
if(rising_edge(clk_sys)) then
if(res = '1') then
rx_done_state <= idle;
else
case rx_done_state is
when idle =>
if (rx_done_raw = '1') then
rx_done_state <= come;
else
rx_done_state <= idle;
end if;
when come => rx_done_state <= waittocompleted;
when waittocompleted =>
if(rx_done_raw = '1') then
rx_done_state <= waittocompleted;
else
rx_done_state <= idle;
end if;
end case;
end if;
end if;
end process;
process(rx_done_state) is
begin
case rx_done_state is
when idle => rx_done <= '0';
when come => rx_done <= '1';
when waittocompleted => rx_done <= '0';
end case;
end process;
end architecture uart_core_arch;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(8-1 downto 0) := (others=>'0');
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNHYCSAEGT_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_1: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVTJPHWYT_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_2: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(8-1 downto 0) := (others=>'0');
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNHYCSAEGT_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_1: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVTJPHWYT_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_2: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2017 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file si5351c_config_rom.vhd when simulating
-- the core, si5351c_config_rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY si5351c_config_rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END si5351c_config_rom;
ARCHITECTURE si5351c_config_rom_a OF si5351c_config_rom IS
-- synthesis translate_off
COMPONENT wrapped_si5351c_config_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_si5351c_config_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 7,
c_addrb_width => 7,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "si5351c_config_rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 128,
c_read_depth_b => 128,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 128,
c_write_depth_b => 128,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_si5351c_config_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END si5351c_config_rom_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
port (
-- wejscia
we : in std_logic_vector(3 downto 0);
adr : in std_logic_vector(1 downto 0);
oe : in std_logic ;
-- wyjscia
Y0,Y1,Y2,Y3 : out std_logic_vector (3 downto 0)
);
end demux1_4;
architecture Behavioral of demux1_4 is
begin
process(oe,adr) is
begin
--gdy '1' na wejsciu oe, demltiplexera
-- we zostaje przepisane na Yx w zaleznosci
-- od wejscia adresowego
-- '0' wygasza w 4 segmenty
if oe = '1' then
if adr="00" then
Y0<=we; Y1<="1111"; Y2<="1111"; Y3<="1111";
elsif adr="01" then
Y0<="1111"; Y1<=we; Y2<="1111"; Y3<="1111";
elsif adr="10" then
Y0<="1111"; Y1<="1111"; Y2<=we; Y3<="1111";
elsif adr="11" then
Y0<="1111"; Y1<="1111"; Y2<="1111"; Y3<=we;
end if;
elsif oe='0' then
Y0<="1111"; Y1<="1111"; Y2<="1111"; Y3<="1111";
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity cliente_seguinte is
port( clienseg : in std_logic;
reset : in std_logic;
binOut : out std_logic_vector(6 downto 0);
compareTo: in std_logic_vector(6 downto 0);
resetOut : out std_logic);
end cliente_seguinte;
architecture Behavioral of cliente_seguinte is
signal count : unsigned(6 downto 0);
begin
process(clienseg)
begin
if(rising_edge(clienseg)) then
if(reset='1') then
count <= (others => '0');
resetOut <= '1';
else
if(count="1100011") then --99
count <= "1100011";
elsif(compareTo="0000000") then
resetOut <= '0';
elsif(count<unsigned(compareTo)) then
count <= count+1;
resetOut <= '0';
else
count <= count;
end if;
end if;
end if;
binOut <= std_logic_vector(count);
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:45:53 11/22/2014
-- Design Name:
-- Module Name: commutate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity commutate is
generic (
CLK_FRQ : integer := 50_000_000; -- 50 MHz
PWM_FRQ : integer := 285
);
Port ( clk : in STD_ULOGIC;
rst : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
h : in STD_ULOGIC_VECTOR (2 downto 0);
led : out STD_ULOGIC_VECTOR (7 downto 0);
u_l : out STD_ULOGIC;
u_h : out STD_ULOGIC;
v_l : out STD_ULOGIC;
v_h : out STD_ULOGIC;
w_l : out STD_ULOGIC;
w_h : out STD_ULOGIC;
h_b : out STD_ULOGIC);
end commutate;
architecture Behavioral of commutate is
signal h_buffered : STD_ULOGIC_VECTOR (2 downto 0);
signal pwm : STD_ULOGIC;
signal pwm_clk : STD_ULOGIC;
signal div_cnt : unsigned (15 downto 0);
signal pwm_cnt : STD_ULOGIC_VECTOR (3 downto 0);
begin
f_div : process (rst, clk)
begin
if rst = '1' then
div_cnt <= (others => '0');
pwm_clk <= '0';
elsif rising_edge(clk) then
if div_cnt = to_unsigned(0, 16) then
div_cnt <= to_unsigned(156, 16);
pwm_clk <= '1';
else
div_cnt <= div_cnt - 1;
pwm_clk <= '0';
end if;
end if;
end process;
p_pwm : process (rst, clk, pwm_clk, sw)
begin
if rst = '1' then
pwm_cnt <= "0000";
pwm <= '0';
elsif rising_edge(clk) then
if pwm_clk = '1' then
if pwm_cnt = "1111" then
pwm_cnt <= "0000";
else
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
end if;
if pwm_cnt < sw then
pwm <= '1';
else
pwm <= '0';
end if;
end if;
end if;
end process;
h_buffer : process (pwm, h)
begin
if falling_edge(pwm) then
h_buffered <= h;
else
h_buffered <= h_buffered;
end if;
end process;
h_b <= h_buffered(0);
led(0) <= not h(0);
led(1) <= not h(1);
led(2) <= not h(2);
led(3) <= pwm;
led(4) <= pwm_clk;
led(5) <= '0';
led(6) <= '0';
led(7) <= '0';
comm : process (pwm, h_buffered )
begin
case h_buffered is
when "000" =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= '0';
when "001" =>
u_l <= '0';
u_h <= '0';
v_l <= pwm;
v_h <= '0';
w_l <= '0';
w_h <= pwm;
when "010" =>
u_l <= pwm;
u_h <= '0';
v_l <= '0';
v_h <= pwm;
w_l <= '0';
w_h <= '0';
when "011" =>
u_l <= pwm;
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= pwm;
when "100" =>
u_l <= '0';
u_h <= pwm;
v_l <= '0';
v_h <= '0';
w_l <= pwm;
w_h <= '0';
when "101" =>
u_l <= '0';
u_h <= pwm;
v_l <= pwm;
v_h <= '0';
w_l <= '0';
w_h <= '0';
when "110" =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= pwm;
w_l <= pwm;
w_h <= '0';
when "111" =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= '0';
when others =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= '0';
end case;
end process;
end Behavioral;
|
-- NEED RESULT: ARCH00172.P1: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00172.P2: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172.P3: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00172: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00172: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00172: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00172: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00172
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00172(ARCH00172)
-- ENT00172_Test_Bench(ARCH00172_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00172 is
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00172" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00172" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00172" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00172" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00172 ;
--
architecture ARCH00172 of ENT00172 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00172 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00172_Test_Bench is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
end ENT00172_Test_Bench ;
--
architecture ARCH00172_Test_Bench of ENT00172_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00172 ( ARCH00172 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
) ;
end block L1 ;
end ARCH00172_Test_Bench ;
|
component ghrd_10as066n2_sys_id is
port (
clock : in std_logic := 'X'; -- clk
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X'; -- address
reset_n : in std_logic := 'X' -- reset_n
);
end component ghrd_10as066n2_sys_id;
u0 : component ghrd_10as066n2_sys_id
port map (
clock => CONNECTED_TO_clock, -- clk.clk
readdata => CONNECTED_TO_readdata, -- control_slave.readdata
address => CONNECTED_TO_address, -- .address
reset_n => CONNECTED_TO_reset_n -- reset.reset_n
);
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2361.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p10n02i02361ent IS
END c07s02b07x00p10n02i02361ent;
ARCHITECTURE c07s02b07x00p10n02i02361arch OF c07s02b07x00p10n02i02361ent IS
BEGIN
TESTING: PROCESS
type NEW_INTEGER is range INTEGER'LOW to INTEGER'HIGH;
variable A : integer := 5;
variable k : NEW_INTEGER := 0;
BEGIN
k := A ** (-2); --Failure_here
assert FALSE
report "***FAILED TEST: c07s02b07x00p10n02i02361 - Left operand must be floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p10n02i02361arch;
|
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