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--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity DbgPort is generic (
async_reset : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
-- "RIVER" Debug interface
i_dport_req_valid : in std_logic; -- Debug access from DSU is valid
i_dport_write : in std_logic; -- Write command flag
i_dport_addr : in std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0); -- Debug Port address
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Write value
o_dport_req_ready : out std_logic; -- Ready to accept dbg request
i_dport_resp_ready : in std_logic; -- Read to accept response
o_dport_resp_valid : out std_logic; -- Response is valid
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Response value
-- CPU debugging signals:
o_csr_addr : out std_logic_vector(11 downto 0); -- Address of the sub-region register
o_reg_addr : out std_logic_vector(5 downto 0);
o_core_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Write data
o_csr_ena : out std_logic; -- Region 0: Access to CSR bank is enabled.
o_csr_write : out std_logic; -- Region 0: CSR write enable
i_csr_valid : in std_logic;
i_csr_rdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Region 0: CSR read value
o_ireg_ena : out std_logic; -- Region 1: Access to integer register bank is enabled
o_ireg_write : out std_logic; -- Region 1: Integer registers bank write pulse
i_ireg_rdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Region 1: Integer register read value
i_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Region 1: Instruction pointer
i_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Region 1: Next Instruction pointer
i_e_call : in std_logic; -- pseudo-instruction CALL
i_e_ret : in std_logic -- pseudo-instruction RET
);
end;
architecture arch_DbgPort of DbgPort is
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
constant one64 : std_logic_vector(63 downto 0) := X"0000000000000001";
constant idle : std_logic_vector(2 downto 0) := "000";
constant csr_region : std_logic_vector(2 downto 0) := "001";
constant reg_bank : std_logic_vector(2 downto 0) := "010";
constant reg_stktr_cnt : std_logic_vector(2 downto 0) := "011";
constant reg_stktr_buf_adr : std_logic_vector(2 downto 0) := "100";
constant reg_stktr_buf_dat : std_logic_vector(2 downto 0) := "101";
constant wait_to_accept : std_logic_vector(2 downto 0) := "110";
type RegistersType is record
dport_write : std_logic;
dport_addr : std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0);
dport_wdata : std_logic_vector(RISCV_ARCH-1 downto 0);
dport_rdata : std_logic_vector(RISCV_ARCH-1 downto 0);
dstate : std_logic_vector(2 downto 0);
rdata : std_logic_vector(RISCV_ARCH-1 downto 0);
stack_trace_cnt : std_logic_vector(CFG_LOG2_STACK_TRACE_ADDR-1 downto 0); -- Stack trace buffer counter
end record;
constant R_RESET : RegistersType := (
'0', -- dport_write
(others => '0'), -- dport_addr
(others => '0'), -- dport_wdata
(others => '0'), -- dport_rdata
idle, -- dstate
(others => '0'), -- rdata
(others => '0') -- stack_trace_cnt
);
signal r, rin : RegistersType;
signal wb_stack_raddr : std_logic_vector(CFG_LOG2_STACK_TRACE_ADDR-1 downto 0);
signal wb_stack_rdata : std_logic_vector(2*CFG_CPU_ADDR_BITS-1 downto 0);
signal w_stack_we : std_logic;
signal wb_stack_waddr : std_logic_vector(CFG_LOG2_STACK_TRACE_ADDR-1 downto 0);
signal wb_stack_wdata : std_logic_vector(2*CFG_CPU_ADDR_BITS-1 downto 0);
component StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end component;
begin
stacktr_ena : if CFG_LOG2_STACK_TRACE_ADDR /= 0 generate
stacktr0 : StackTraceBuffer generic map (
abits => CFG_LOG2_STACK_TRACE_ADDR,
dbits => 2*CFG_CPU_ADDR_BITS
) port map (
i_clk => i_clk,
i_raddr => wb_stack_raddr,
o_rdata => wb_stack_rdata,
i_we => w_stack_we,
i_waddr => wb_stack_waddr,
i_wdata => wb_stack_wdata
);
end generate;
comb : process(i_nrst, i_dport_req_valid, i_dport_write,
i_dport_addr, i_dport_wdata, i_dport_resp_ready,
i_csr_valid, i_csr_rdata, i_ireg_rdata, i_pc, i_npc,
i_e_call, i_e_ret, wb_stack_rdata, r)
variable v : RegistersType;
variable wb_o_csr_addr : std_logic_vector(11 downto 0);
variable wb_o_reg_addr : std_logic_vector(5 downto 0);
variable wb_o_core_wdata : std_logic_vector(RISCV_ARCH-1 downto 0);
variable wb_idx : integer range 0 to 4095;
variable w_o_csr_ena : std_logic;
variable w_o_csr_write : std_logic;
variable w_o_ireg_ena : std_logic;
variable w_o_ireg_write : std_logic;
variable v_req_ready : std_logic;
variable v_resp_valid : std_logic;
variable vrdata : std_logic_vector(63 downto 0);
begin
v := r;
wb_o_csr_addr := (others => '0');
wb_o_reg_addr := (others => '0');
wb_o_core_wdata := (others => '0');
wb_idx := conv_integer(i_dport_addr(11 downto 0));
w_o_csr_ena := '0';
w_o_csr_write := '0';
w_o_ireg_ena := '0';
w_o_ireg_write := '0';
wb_stack_raddr <= (others => '0');
w_stack_we <= '0';
wb_stack_waddr <= (others => '0');
wb_stack_wdata <= (others => '0');
v_req_ready := '0';
v_resp_valid := '0';
vrdata := r.dport_rdata;
if CFG_LOG2_STACK_TRACE_ADDR /= 0 then
if i_e_call = '1' and conv_integer(r.stack_trace_cnt) /= (STACK_TRACE_BUF_SIZE - 1) then
w_stack_we <= '1';
wb_stack_waddr <= r.stack_trace_cnt(CFG_LOG2_STACK_TRACE_ADDR-1 downto 0);
wb_stack_wdata <= i_npc & i_pc;
v.stack_trace_cnt := r.stack_trace_cnt + 1;
elsif i_e_ret = '1' and or_reduce(r.stack_trace_cnt) = '1' then
v.stack_trace_cnt := r.stack_trace_cnt - 1;
end if;
end if;
case r.dstate is
when idle =>
v_req_ready := '1';
vrdata := (others => '0');
if i_dport_req_valid = '1' then
v.dport_write := i_dport_write;
v.dport_addr := i_dport_addr;
v.dport_wdata := i_dport_wdata;
if conv_integer(i_dport_addr(CFG_DPORT_ADDR_BITS-1 downto 12)) = 0 then
v.dstate := csr_region;
elsif conv_integer(i_dport_addr(CFG_DPORT_ADDR_BITS-1 downto 12)) = 1 then
if wb_idx < 64 then
v.dstate := reg_bank;
elsif wb_idx = 64 then
v.dstate := reg_stktr_cnt;
elsif (wb_idx >= 128) and (wb_idx < (128 + 2 * STACK_TRACE_BUF_SIZE)) then
v.dstate := reg_stktr_buf_adr;
else
vrdata := (others => '0');
v.dstate := wait_to_accept;
end if;
else
v.dstate := wait_to_accept;
end if;
end if;
when csr_region =>
w_o_csr_ena := '1';
wb_o_csr_addr := r.dport_addr(11 downto 0);
if r.dport_write = '1' then
w_o_csr_write := '1';
wb_o_core_wdata := r.dport_wdata;
end if;
if i_csr_valid = '1' then
vrdata := i_csr_rdata;
v.dstate := wait_to_accept;
end if;
when reg_bank =>
w_o_ireg_ena := '1';
wb_o_reg_addr := r.dport_addr(5 downto 0);
vrdata := i_ireg_rdata;
if r.dport_write = '1' then
w_o_ireg_write := '1';
wb_o_core_wdata := r.dport_wdata;
end if;
v.dstate := wait_to_accept;
when reg_stktr_cnt =>
vrdata := (others => '0');
vrdata(CFG_LOG2_STACK_TRACE_ADDR-1 downto 0) := r.stack_trace_cnt;
if r.dport_write = '1' then
v.stack_trace_cnt := r.dport_wdata(CFG_LOG2_STACK_TRACE_ADDR-1 downto 0);
end if;
v.dstate := wait_to_accept;
when reg_stktr_buf_adr =>
wb_stack_raddr <= r.dport_addr(CFG_LOG2_STACK_TRACE_ADDR downto 1);
v.dstate := reg_stktr_buf_dat;
when reg_stktr_buf_dat =>
if r.dport_addr(0) = '0' then
vrdata(CFG_CPU_ADDR_BITS-1 downto 0) :=
wb_stack_rdata(CFG_CPU_ADDR_BITS-1 downto 0);
else
vrdata(CFG_CPU_ADDR_BITS-1 downto 0) :=
wb_stack_rdata(2*CFG_CPU_ADDR_BITS-1 downto CFG_CPU_ADDR_BITS);
end if;
v.dstate := wait_to_accept;
when wait_to_accept =>
v_resp_valid := '1';
if i_dport_resp_ready = '1' then
v.dstate := idle;
end if;
when others =>
end case;
v.dport_rdata := vrdata;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
o_csr_addr <= wb_o_csr_addr;
o_reg_addr <= wb_o_reg_addr;
o_core_wdata <= wb_o_core_wdata;
o_csr_ena <= w_o_csr_ena;
o_csr_write <= w_o_csr_write;
o_ireg_ena <= w_o_ireg_ena;
o_ireg_write <= w_o_ireg_write;
o_dport_req_ready <= v_req_ready;
o_dport_resp_valid <= v_resp_valid;
o_dport_rdata <= r.dport_rdata;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity sim_top_TB is
end sim_top_TB;
architecture Behavioral of sim_top_TB is
component sim_top is
port(clk : in std_logic;
rst : in std_logic);
end component;
signal rst, clk : std_logic;
begin
uut : sim_top
port map(clk => clk,
rst => rst);
clocker : process is
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
stim : process is
begin
rst <= '1';
wait for 1000 ns;
rst <= '0';
wait;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity sim_top_TB is
end sim_top_TB;
architecture Behavioral of sim_top_TB is
component sim_top is
port(clk : in std_logic;
rst : in std_logic);
end component;
signal rst, clk : std_logic;
begin
uut : sim_top
port map(clk => clk,
rst => rst);
clocker : process is
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
stim : process is
begin
rst <= '1';
wait for 1000 ns;
rst <= '0';
wait;
end process;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
entity debouncevhdl is
Port (
Clock : in std_logic;
Reset : in std_logic;
ClockEn : in std_logic;
Din : in std_logic;
Dout : out std_logic
);
end debouncevhdl;
architecture Behavioral of debouncevhdl is
signal Sync_InSr : std_logic_vector(2 downto 0);
signal Cntr : std_logic_vector(7 downto 0);
begin
process(Clock, Reset)
begin
if (Reset = '1') then
Dout <= '0';
Cntr <= (Others => '0');
Sync_InSr <= (Others => '0');
elsif (Clock'event and Clock = '1') then
Sync_InSr <= Sync_InSr(1 downto 0) & Din;
if (ClockEn = '1') then
if (Sync_InSr(2 downto 1) = "00") then
if (Cntr /= x"00") then
Cntr <= Cntr - 1;
end if;
elsif (Sync_InSr(2 downto 1) = "11") then
if (Cntr /= x"FF") then
Cntr <= Cntr + 1;
end if;
end if;
if (Cntr = x"FF") then
Dout <= '1';
elsif (Cntr = x"00") then
Dout <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY Frame_Buf IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Frame_Buf;
ARCHITECTURE Frame_Buf_arch OF Frame_Buf IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Frame_Buf_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Frame_Buf_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Frame_Buf_arch : ARCHITECTURE IS "Frame_Buf,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Frame_Buf_arch: ARCHITECTURE IS "Frame_Buf,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=Frame_Buf.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.53475 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "Frame_Buf.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.53475 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END Frame_Buf_arch;
|
library verilog;
use verilog.vl_types.all;
entity HW_SW is
port(
address : in vl_logic_vector(7 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(127 downto 0)
);
end HW_SW;
|
library verilog;
use verilog.vl_types.all;
entity HW_SW is
port(
address : in vl_logic_vector(7 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(127 downto 0)
);
end HW_SW;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_clkgen
-- File: pcitb_clkgen.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI clock & reset generator
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pcitb.all;
entity pcitb_clkgen is
generic (
mhz66 : boolean := false;
rstclocks : integer := 20);
port (
rsttrig : in std_logic;
systclk : out pci_syst_type);
end pcitb_clkgen;
architecture tb of pcitb_clkgen is
signal clk : std_logic;
begin
systclk.clk <= clk;
clkgen: process
begin
if mhz66 then
clk <= '1';
wait for 7 ns;
clk <= '0';
wait for 8 ns;
else
clk <= '1';
wait for 15 ns;
clk <= '0';
wait for 15 ns;
end if;
end process;
reset : process
begin
if rsttrig = '1' then
systclk.rst <= '0';
if mhz66 then
wait for rstclocks*15 ns;
else
wait for rstclocks*30 ns;
end if;
wait until clk = '1';
end if;
systclk.rst <= '1';
wait for 1 ns;
end process;
end;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_clkgen
-- File: pcitb_clkgen.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI clock & reset generator
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pcitb.all;
entity pcitb_clkgen is
generic (
mhz66 : boolean := false;
rstclocks : integer := 20);
port (
rsttrig : in std_logic;
systclk : out pci_syst_type);
end pcitb_clkgen;
architecture tb of pcitb_clkgen is
signal clk : std_logic;
begin
systclk.clk <= clk;
clkgen: process
begin
if mhz66 then
clk <= '1';
wait for 7 ns;
clk <= '0';
wait for 8 ns;
else
clk <= '1';
wait for 15 ns;
clk <= '0';
wait for 15 ns;
end if;
end process;
reset : process
begin
if rsttrig = '1' then
systclk.rst <= '0';
if mhz66 then
wait for rstclocks*15 ns;
else
wait for rstclocks*30 ns;
end if;
wait until clk = '1';
end if;
systclk.rst <= '1';
wait for 1 ns;
end process;
end;
-- pragma translate_on
|
-- Core of PS2 driver
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps2core is
port(
clk: in std_logic;
res: in std_logic;
byte_out: out unsigned(7 downto 0);
byte_recieved: out std_logic;
ps2clk: in std_logic;
ps2dat: in std_logic
);
end entity ps2core;
architecture ps2core_arch of ps2core is
type statetype is (
idle, start_bit, wait0, sample0, wait1, sample1, wait2, sample2, wait3, sample3,
wait4, sample4, wait5, sample5, wait6, sample6, wait7, sample7, wait_parity, sample_parity, interrupt
);
signal ps2_state: statetype;
signal ps2clk_synch, ps2dat_synch: std_logic;
signal sample_dat: std_logic;
signal ps2clk_fall: std_logic;
begin
process(clk, res, ps2clk, ps2dat) is
variable ps2clk_var: std_logic_vector(1 downto 0);
variable ps2dat_var: std_logic_vector(1 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
ps2clk_var := "11";
ps2dat_var := "11";
else
ps2dat_var(1) := ps2dat_var(0);
ps2dat_var(0) := ps2dat;
ps2clk_var(1) := ps2clk_var(0);
ps2clk_var(0) := ps2clk;
end if;
end if;
ps2clk_synch <= ps2clk_var(1);
ps2dat_synch <= ps2dat_var(1);
end process;
sipo_shift_reg:
process(clk, res, ps2dat_synch, sample_dat) is
variable data_reg: unsigned(8 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
data_reg := (others => '0');
elsif sample_dat = '1' then
data_reg(7 downto 0) := data_reg(8 downto 1);
data_reg(8) := ps2dat_synch;
end if;
end if;
byte_out <= data_reg(7 downto 0);
end process;
ps2clk_fall_detec:
process(clk, res, ps2clk_synch) is
variable counter: std_logic_vector(1 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := "00";
else
counter(1) := counter(0);
counter(0) := ps2clk_synch;
end if;
end if;
ps2clk_fall <= counter(1) and not(counter(0));
end process;
FSM_transit_functions:
process(clk, res, ps2dat_synch, ps2clk_fall) is
begin
if rising_edge(clk) then
if res = '1' then
ps2_state <= idle;
else
case ps2_state is
when idle =>
if ps2clk_fall = '1' and ps2dat_synch = '0' then
ps2_state <= start_bit;
else
ps2_state <= idle;
end if;
when start_bit =>
ps2_state <= wait0;
when wait0 =>
if ps2clk_fall = '1' then
ps2_state <= sample0;
else
ps2_state <= wait0;
end if;
when sample0 =>
ps2_state <= wait1;
when wait1 =>
if ps2clk_fall = '1' then
ps2_state <= sample1;
else
ps2_state <= wait1;
end if;
when sample1 =>
ps2_state <= wait2;
when wait2 =>
if ps2clk_fall = '1' then
ps2_state <= sample2;
else
ps2_state <= wait2;
end if;
when sample2 =>
ps2_state <= wait3;
when wait3 =>
if ps2clk_fall = '1' then
ps2_state <= sample3;
else
ps2_state <= wait3;
end if;
when sample3 =>
ps2_state <= wait4;
when wait4 =>
if ps2clk_fall = '1' then
ps2_state <= sample4;
else
ps2_state <= wait4;
end if;
when sample4 =>
ps2_state <= wait5;
when wait5 =>
if ps2clk_fall = '1' then
ps2_state <= sample5;
else
ps2_state <= wait5;
end if;
when sample5 =>
ps2_state <= wait6;
when wait6 =>
if ps2clk_fall = '1' then
ps2_state <= sample6;
else
ps2_state <= wait6;
end if;
when sample6 =>
ps2_state <= wait7;
when wait7 =>
if ps2clk_fall = '1' then
ps2_state <= sample7;
else
ps2_state <= wait7;
end if;
when sample7 =>
ps2_state <= wait_parity;
when wait_parity =>
if ps2clk_fall = '1' then
ps2_state <= sample_parity;
else
ps2_state <= wait_parity;
end if;
when sample_parity =>
ps2_state <= interrupt;
when interrupt =>
ps2_state <= idle;
end case;
end if;
end if;
end process;
FSM_output_functions:
process(ps2_state) is
begin
case ps2_state is
when idle => byte_recieved <= '0'; sample_dat <= '0';
when start_bit => byte_recieved <= '0'; sample_dat <= '0';
when wait0 => byte_recieved <= '0'; sample_dat <= '0';
when sample0 => byte_recieved <= '0'; sample_dat <= '1';
when wait1 => byte_recieved <= '0'; sample_dat <= '0';
when sample1 => byte_recieved <= '0'; sample_dat <= '1';
when wait2 => byte_recieved <= '0'; sample_dat <= '0';
when sample2 => byte_recieved <= '0'; sample_dat <= '1';
when wait3 => byte_recieved <= '0'; sample_dat <= '0';
when sample3 => byte_recieved <= '0'; sample_dat <= '1';
when wait4 => byte_recieved <= '0'; sample_dat <= '0';
when sample4 => byte_recieved <= '0'; sample_dat <= '1';
when wait5 => byte_recieved <= '0'; sample_dat <= '0';
when sample5 => byte_recieved <= '0'; sample_dat <= '1';
when wait6 => byte_recieved <= '0'; sample_dat <= '0';
when sample6 => byte_recieved <= '0'; sample_dat <= '1';
when wait7 => byte_recieved <= '0'; sample_dat <= '0';
when sample7 => byte_recieved <= '0'; sample_dat <= '1';
when wait_parity => byte_recieved <= '0'; sample_dat <= '0';
when sample_parity => byte_recieved <= '0'; sample_dat <= '1';
when interrupt => byte_recieved <= '1'; sample_dat <= '0';
end case;
end process;
end architecture ps2core_arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- package declaration -- TODO: deplacer dans un fichier externe
package ComFlow_pkg is
function clog2 ( x : integer) return integer;
-- Number of flow in design
constant NBFLOW : integer := 2;
-- struct pour stocker les ID flow : used for Return Status in USB Driver
type IDFLOW_t is array (0 to NBFLOW-1) of integer range 0 to 255;
constant TX_PACKET_SIZE : integer := 256;
--- Define pour simplifier lecture des codes read/write flow
constant SoF:integer := 0;
constant EoF:integer := 1;
constant Data:integer:= 2;
constant SoL:integer := 3;
constant EoL:integer := 4;
-- Struct pour les flags s
type my_array_t is array (0 to 4) of std_logic_vector(7 downto 0);
constant InitFlagCodes : my_array_t := (
X"AA", -- Start of Frame Flag
X"BA", --End of Frame Flag
X"BC", -- Start+end Flow
X"DA", -- Start of Line
X"DB" -- End of Line
);
-- Component Declaration
component com_to_flow
generic (
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
FLAGS_CODES : my_array_t := InitFlagCodes;
FLOW_SIZE : INTEGER := 16;
DATA_HAL_SIZE : INTEGER := 16
);
port(
clk_hal : in std_logic;
clk_proc : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
pktend_i : in std_logic;
enable_i : in std_logic;
data_o : out std_logic_vector(FLOW_SIZE-1 downto 0);
fv_o : out std_logic;
dv_o : out std_logic;
flow_full_o : out std_logic
);
end component;
component flow_to_com is
generic (
FLOW_SIZE : POSITIVE := 8;
DATA_HAL_SIZE : POSITIVE := 16;
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
PACKET_SIZE : INTEGER := 256;
FLAGS_CODES : my_array_t := InitFlagCodes
);
port(
clk_proc : in std_logic;
clk_hal : in std_logic;
rst_n : in std_logic;
in_data : in std_logic_vector(FLOW_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
rdreq_i : in std_logic;
enable_flow_i : in std_logic;
enable_global_i : in std_logic;
data_o : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end component;
constant BURSTMODE :std_logic_vector(7 downto 0) := X"BC";
component com_to_master_pi
generic (
FIFO_DEPTH : POSITIVE := 64;
FLOW_ID_SET : INTEGER := 12;
--FLOW_ID_GET : INTEGER := 13
MASTER_ADDR_WIDTH : INTEGER;
DATA_HAL_SIZE : POSITIVE := 16
);
port (
clk_hal : in std_logic; -- clk_usb
clk_proc : in std_logic; -- clk_design
rst_n : in std_logic;
-- USB driver connexion
data_wr_i : in std_logic;
data_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
-- rdreq_i : in std_logic;
pktend_i : in std_logic;
fifo_full_o : out std_logic;
-- signaux pour wishbone
param_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 downto 0);
param_data_o : out std_logic_vector(31 downto 0);
param_wr_o : out std_logic;
-- may add RAM arbiter connexion
-- tmp signal to trigger caph update reg
tmp_update_port_o : out std_logic
);
end component;
component flow_to_com_arb4
generic (
DATA_HAL_SIZE : POSITIVE := 16
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- fv 0 signals
rdreq_0_o : out std_logic;
data_0_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_0_i : in std_logic;
f_empty_0_i : in std_logic;
size_packet_0_i : in std_logic_vector(15 downto 0);
-- fv 1signals
rdreq_1_o : out std_logic;
data_1_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_1_i : in std_logic;
f_empty_1_i : in std_logic;
size_packet_1_i : in std_logic_vector(15 downto 0);
-- fv 2 signals
rdreq_2_o : out std_logic;
data_2_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_2_i : in std_logic;
f_empty_2_i : in std_logic;
size_packet_2_i : in std_logic_vector(15 downto 0);
-- fv 3 signals
rdreq_3_o : out std_logic;
data_3_i : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_3_i : in std_logic;
f_empty_3_i : in std_logic;
size_packet_3_i : in std_logic_vector(15 downto 0);
-- fv usb signals
rdreq_usb_i : in std_logic;
data_usb_o : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
flow_rdy_usb_o : out std_logic;
f_empty_usb_o : out std_logic;
size_packet_o : out std_logic_vector(15 downto 0)
);
end component;
component gp_com
generic (
IN0_SIZE : INTEGER := 8;
IN1_SIZE : INTEGER := 8;
IN2_SIZE : INTEGER := 8;
IN3_SIZE : INTEGER := 8;
OUT0_SIZE : INTEGER := 8;
OUT1_SIZE : INTEGER := 8;
IN0_NBWORDS : INTEGER := 1280;
IN1_NBWORDS : INTEGER := 1280;
IN2_NBWORDS : INTEGER := 1280;
IN3_NBWORDS : INTEGER := 1280;
OUT0_NBWORDS : INTEGER := 1024;
OUT1_NBWORDS : INTEGER := 1024;
CLK_PROC_FREQ : INTEGER;
CLK_HAL_FREQ : INTEGER;
DATA_HAL_SIZE : INTEGER;
PACKET_HAL_SIZE : INTEGER;
MASTER_ADDR_WIDTH : INTEGER
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------ hal connections ------
clk_hal : in std_logic;
from_hal_data : in std_logic_vector(DATA_HAL_SIZE-1 downto 0);
from_hal_wr : in std_logic;
from_hal_full : out std_logic;
from_hal_pktend : in std_logic;
to_hal_data : out std_logic_vector(DATA_HAL_SIZE-1 downto 0);
to_hal_rd : in std_logic;
to_hal_empty : out std_logic;
to_hal_rdy : out std_logic;
to_hal_size_packet : out std_logic_vector(15 downto 0);
-------- slave -------
status_enable : in std_logic;
flow_in0_enable : in std_logic;
flow_in1_enable : in std_logic;
flow_in2_enable : in std_logic;
flow_in3_enable : in std_logic;
------ in0 flow ------
in0_data : in std_logic_vector(IN0_SIZE-1 downto 0);
in0_fv : in std_logic;
in0_dv : in std_logic;
------ in1 flow ------
in1_data : in std_logic_vector(IN1_SIZE-1 downto 0);
in1_fv : in std_logic;
in1_dv : in std_logic;
------ in2 flow ------
in2_data : in std_logic_vector(IN2_SIZE-1 downto 0);
in2_fv : in std_logic;
in2_dv : in std_logic;
------ in3 flow ------
in3_data : in std_logic_vector(IN3_SIZE-1 downto 0);
in3_fv : in std_logic;
in3_dv : in std_logic;
------ out0 flow ------
out0_data : out std_logic_vector(OUT0_SIZE-1 downto 0);
out0_fv : out std_logic;
out0_dv : out std_logic;
------ out1 flow ------
out1_data : out std_logic_vector(OUT1_SIZE-1 downto 0);
out1_fv : out std_logic;
out1_dv : out std_logic;
---- ===== Masters =====
------ bus_master ------
master_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 downto 0);
master_wr_o : out std_logic;
master_rd_o : out std_logic;
master_datawr_o : out std_logic_vector(31 downto 0);
master_datard_i : in std_logic_vector(31 downto 0)
);
end component;
end package ComFlow_pkg;
package body ComFlow_pkg is
function clog2(x : integer) return integer is
begin
return integer(ceil(log2(real(x))));
end;
end ComFlow_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_02 is
end entity ch_03_02;
architecture test of ch_03_02 is
signal sel : integer range 0 to 1 := 0;
signal input_0 : integer := 0;
signal input_1 : integer := 10;
signal result : integer;
begin
process_3_1_b : process (sel, input_0, input_1) is
begin
-- code from book:
if sel = 0 then
result <= input_0; -- executed if sel = 0
else
result <= input_1; -- executed if sel /= 0
end if;
-- end of code from book
end process process_3_1_b;
stimulus : process is
begin
sel <= 1 after 40 ns;
input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_02 is
end entity ch_03_02;
architecture test of ch_03_02 is
signal sel : integer range 0 to 1 := 0;
signal input_0 : integer := 0;
signal input_1 : integer := 10;
signal result : integer;
begin
process_3_1_b : process (sel, input_0, input_1) is
begin
-- code from book:
if sel = 0 then
result <= input_0; -- executed if sel = 0
else
result <= input_1; -- executed if sel /= 0
end if;
-- end of code from book
end process process_3_1_b;
stimulus : process is
begin
sel <= 1 after 40 ns;
input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_02 is
end entity ch_03_02;
architecture test of ch_03_02 is
signal sel : integer range 0 to 1 := 0;
signal input_0 : integer := 0;
signal input_1 : integer := 10;
signal result : integer;
begin
process_3_1_b : process (sel, input_0, input_1) is
begin
-- code from book:
if sel = 0 then
result <= input_0; -- executed if sel = 0
else
result <= input_1; -- executed if sel /= 0
end if;
-- end of code from book
end process process_3_1_b;
stimulus : process is
begin
sel <= 1 after 40 ns;
input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
wait;
end process stimulus;
end architecture test;
|
-- A6500 - 6502 CPU and variants
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
entity bench is
end bench;
architecture bench of bench is
constant A: natural := 0;
constant X: natural := 1;
constant Y: natural := 2;
constant S: natural := 3;
constant PCL: natural := 4;
constant PCH: natural := 5;
constant ADL: natural := 6;
constant DL: natural := 7;
constant P: natural := 8;
constant ADH: natural := 8;
-- Flags
constant C: natural := 0;
constant Z: natural := 1;
constant B: natural := 4;
constant V: natural := 6;
constant N: natural := 7;
component A6500 is
port(clk: in std_logic;
rst: in std_logic;
irq: in std_logic;
nmi: in std_logic;
stop: in std_logic;
d: inout std_logic_vector(7 downto 0);
ad: out std_logic_vector(15 downto 0);
r: out std_logic;
a_dbg: out std_logic_vector(7 downto 0);
x_dbg: out std_logic_vector(7 downto 0);
y_dbg: out std_logic_vector(7 downto 0);
s_dbg: out std_logic_vector(7 downto 0);
pcl_dbg: out std_logic_vector(7 downto 0);
pch_dbg: out std_logic_vector(7 downto 0);
adl_dbg: out std_logic_vector(7 downto 0);
adh_dbg: out std_logic_vector(7 downto 0);
p_dbg: out std_logic_vector(7 downto 0));
end component;
signal clk: std_logic;
signal rst: std_logic;
signal irq: std_logic;
signal nmi: std_logic;
signal stop: std_logic;
signal d: std_logic_vector(7 downto 0);
signal ad: std_logic_vector(15 downto 0);
signal r: std_logic;
signal a_dbg: std_logic_vector(7 downto 0);
signal x_dbg: std_logic_vector(7 downto 0);
signal y_dbg: std_logic_vector(7 downto 0);
signal s_dbg: std_logic_vector(7 downto 0);
signal pcl_dbg: std_logic_vector(7 downto 0);
signal pch_dbg: std_logic_vector(7 downto 0);
signal adl_dbg: std_logic_vector(7 downto 0);
signal adh_dbg: std_logic_vector(7 downto 0);
signal p_dbg: std_logic_vector(7 downto 0);
constant clk_period : time := 100 ns;
constant rst_vec: std_logic_vector(15 downto 0) := X"A0F0";
constant irq_vec: std_logic_vector(15 downto 0) := X"B0E0";
constant nmi_vec: std_logic_vector(15 downto 0) := X"C0D0";
shared variable pc: std_logic_vector(15 downto 0);
shared variable last_adr: std_logic_vector(15 downto 0);
shared variable ss_a: std_logic_vector(7 downto 0);
shared variable ss_x: std_logic_vector(7 downto 0);
shared variable ss_y: std_logic_vector(7 downto 0);
shared variable ss_p: std_logic_vector(7 downto 0);
shared variable ss_s: std_logic_vector(7 downto 0);
shared variable op, i, j, k, l, m: natural;
type imm_operands_array is array(0 to 31) of std_logic_vector(7 downto 0);
constant imm_operands : imm_operands_array := (X"00", X"01", X"03", X"05", X"07", X"09", X"10", X"12", X"14", X"16", X"17",
X"30", X"31", X"33", X"36", X"37", X"39", X"40", X"43", X"44", X"46", X"48",
X"70", X"72", X"73", X"74", X"77", X"79", X"90", X"92", X"94", X"99");
type adr_operands_array is array(0 to 1) of std_logic_vector(7 downto 0);
constant adr_operands : adr_operands_array := (X"40", X"F0");
type ad_operands_array is array(0 to 1) of std_logic_vector(15 downto 0);
constant ad_operands : ad_operands_array := (X"4060", X"F030");
type alu_01_opcodes_array is array(0 to 6) of std_logic_vector(2 downto 0);
constant alu_01_opcodes : alu_01_opcodes_array := (b"000", b"001", b"010", b"011", b"101", b"110", b"111");
type alu_10_opcodes_array is array(0 to 5) of std_logic_vector(2 downto 0);
constant alu_10_opcodes : alu_10_opcodes_array := (b"000", b"001", b"010", b"011", b"110", b"111");
procedure assert_report(
constant cond: in boolean;
constant ir: in std_logic_vector(7 downto 0);
constant msg: in string
) is
variable l: line;
begin
if (not cond) then
write(l, msg);
write(l, string'(" Instruction: "));
hwrite(l, ir);
writeline(output, l);
end if;
assert cond;
end assert_report;
procedure status_report(
constant msg: in string
) is
variable l: line;
begin
write(l, msg);
writeline(output, l);
end status_report;
procedure increment_pc is
begin
pc := pc + 1;
end procedure increment_pc;
procedure jump_pc(
constant new_pc: in std_logic_vector(15 downto 0)
) is
begin
pc := new_pc;
end procedure jump_pc;
procedure load_A(
signal d: out std_logic_vector(7 downto 0);
constant v: in std_logic_vector(7 downto 0)
) is
begin
d <= X"A9";
increment_pc;
wait for clk_period;
d <= v;
increment_pc;
wait for clk_period;
end procedure load_A;
procedure load_X(
signal d: out std_logic_vector(7 downto 0);
constant v: in std_logic_vector(7 downto 0)
) is
begin
d <= X"A2";
increment_pc;
wait for clk_period;
d <= v;
increment_pc;
wait for clk_period;
end procedure load_X;
procedure load_Y(
signal d: out std_logic_vector(7 downto 0);
constant v: in std_logic_vector(7 downto 0)
) is
begin
d <= X"A0";
increment_pc;
wait for clk_period;
d <= v;
increment_pc;
wait for clk_period;
end procedure load_Y;
procedure nop(
signal d: out std_logic_vector(7 downto 0)
) is
begin
d <= X"EA";
increment_pc;
wait for clk_period;
wait for clk_period;
end procedure nop;
procedure test_imm_mode(
constant ir: in std_logic_vector(7 downto 0)
) is
begin
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
end procedure test_imm_mode;
procedure test_zp_mode(
constant adr: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0);
signal d: out std_logic_vector(7 downto 0)
) is
begin
d <= adr;
assert_report((ad = pc) and (r = '1'), ir, "Zero page mode failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = ("00000000" & adr)), ir, "Zero page mode failed: ad != (00, adr).");
last_adr := ("00000000" & adr);
end procedure test_zp_mode;
procedure test_zp_idx_mode(
constant adr: in std_logic_vector(7 downto 0);
constant idx: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0);
signal d: out std_logic_vector(7 downto 0)
) is
begin
d <= adr;
assert_report((ad = pc) and (r = '1'), ir, "Zero page mode failed: (ad != pc).");
increment_pc;
wait for clk_period;
assert_report((ad = ("00000000" & adr)) and (r = '1'), ir, "Indexed zero page mode failed: ad != (00, adr)");
wait for clk_period;
assert_report((ad = ("00000000" & (adr + idx))),
ir, "Indexed zero page mode failed: ad != (00, adr + idx)");
last_adr := ("00000000" & (adr + idx));
end procedure test_zp_idx_mode;
procedure test_abs_mode(
constant adr: in std_logic_vector(15 downto 0);
constant ir: in std_logic_vector(7 downto 0);
signal d: out std_logic_vector(7 downto 0)
) is
begin
d <= adr(7 downto 0);
assert_report((ad = pc) and (r = '1'), ir, "Absolute mode failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= adr(15 downto 8);
assert_report((ad = pc) and (r = '1'), ir, "Absolute mode failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = adr), ir, "Absolute mode failed: ad != adr");
last_adr := adr;
end procedure test_abs_mode;
procedure test_abs_idx_mode(
constant adr: in std_logic_vector(15 downto 0);
constant idx: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0);
signal d: out std_logic_vector(7 downto 0)
) is
variable sum: std_logic_vector(8 downto 0);
begin
sum := ('0' & adr(7 downto 0)) + ('0' & idx);
d <= adr(7 downto 0);
assert_report((ad = pc) and (r = '1'), ir, "Zero page mode failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= adr(15 downto 8);
assert_report((ad = pc) and (r = '1'), ir, "Zero page mode failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = (adr(15 downto 8) & sum(7 downto 0))),
ir, "Indexed absolute mode failed: ad != (adr + idx).");
last_adr := (adr(15 downto 8) & sum(7 downto 0));
if (sum(8) = '1') then
wait for clk_period;
assert_report((ad = (adr + ("00000000" & idx))),
ir, "Indexed absolute mode failed: ad != (adr + idx), (page crossing).");
last_adr := (adr + ("00000000" & idx));
end if;
end procedure test_abs_idx_mode;
procedure test_ind_x_mode(
constant bal: in std_logic_vector(7 downto 0);
constant adr: in std_logic_vector(15 downto 0);
constant idx: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0);
signal d: out std_logic_vector(7 downto 0)
) is
begin
d <= bal;
assert_report((ad = pc) and (r = '1'), ir, "Zero page mode failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = ("00000000" & bal)) and (r = '1'), ir, "Indirect X mode failed.");
wait for clk_period;
assert_report((ad = ("00000000" & (bal + idx))) and (r = '1'), ir, "Indirect X mode failed.");
d <= adr(7 downto 0);
wait for clk_period;
assert_report((ad = ("00000000" & (bal + idx + 1))) and (r = '1'), ir, "Indirect X mode failed.");
d <= adr(15 downto 8);
wait for clk_period;
assert_report((ad = adr), ir, "Indirect X mode failed.");
last_adr := adr;
end procedure test_ind_x_mode;
procedure test_ind_y_mode(
constant ial: in std_logic_vector(7 downto 0);
constant adr: in std_logic_vector(15 downto 0);
constant idx: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0);
signal d: out std_logic_vector(7 downto 0)
) is
variable sum: std_logic_vector(8 downto 0);
begin
sum := ('0' & adr(7 downto 0)) + ('0' & idx);
d <= ial;
assert_report((ad = pc) and (r = '1'), ir, "Indirect Y mode failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = ("00000000" & ial)) and (r = '1'), ir, "Indirect Y mode failed: ad != (00, ial).");
d <= adr(7 downto 0);
wait for clk_period;
assert_report((ad = ("00000000" & (ial + 1))) and (r = '1'),
ir, "Indirect Y mode failed: ad != (00, ial + 1).");
d <= adr(15 downto 8);
wait for clk_period;
assert_report((ad = (adr(15 downto 8) & sum(7 downto 0))),
ir, "Indirect Y mode failed: ad != (adr + idx).");
last_adr := (adr(15 downto 8) & sum(7 downto 0));
if (sum(8) = '1') then
wait for clk_period;
assert_report((ad = (adr + ("00000000" & idx))),
ir, "Indirect Y mode failed: ad != (adr + idx), (page crossing).");
last_adr := (adr + ("00000000" & idx));
end if;
end procedure test_ind_y_mode;
procedure reset_cpu(
signal rst: out std_logic;
signal d: out std_logic_vector(7 downto 0)
) is
begin
rst <= '1';
wait for 5 * clk_period / 2;
rst <= '0';
assert (ad = X"FFFC") and (r = '1') report "CPU initialization failed.";
d <= rst_vec(7 downto 0);
wait for clk_period;
assert (ad = X"FFFD") and (r = '1') report "CPU initialization failed.";
d <= rst_vec(15 downto 8);
wait for clk_period;
assert (ad = rst_vec) and (r = '1') report "CPU initialization failed.";
jump_pc(rst_vec);
end procedure reset_cpu;
procedure sample_cpu_state is
begin
ss_a := a_dbg;
ss_x := x_dbg;
ss_y := y_dbg;
ss_p := p_dbg;
ss_s := s_dbg;
end procedure sample_cpu_state;
procedure test_nop(
signal d: out std_logic_vector(7 downto 0)
) is
begin
sample_cpu_state;
d <= X"EA";
assert_report((ad = pc) and (r = '1'), X"EA", "NOP failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = pc) and (r = '1'), X"EA", "NOP failed: ad != pc.");
wait for clk_period;
d <= X"EA";
assert_report((ad = pc) and (r = '1'), X"EA", "NOP failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = pc) and (r = '1'), X"EA", "NOP failed: ad != pc.");
assert_report((ss_a = a_dbg), X"EA", "NOP failed: ss_a != a.");
assert_report((ss_x = x_dbg), X"EA", "NOP failed: ss_x != x.");
assert_report((ss_y = y_dbg), X"EA", "NOP failed: ss_y != y.");
assert_report((ss_p = p_dbg), X"EA", "NOP failed: ss_p != p.");
wait for clk_period;
end procedure test_nop;
procedure test_clsec(
signal d: out std_logic_vector(7 downto 0)
) is
begin
sample_cpu_state;
d <= X"38";
assert_report((ad = pc) and (r = '1'), X"38", "SEC failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = pc) and (r = '1'), X"38", "SEC failed: ad != pc.");
wait for clk_period;
d <= X"18";
assert_report((ad = pc) and (r = '1'), X"18", "CLC failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = pc) and (r = '1'), X"18", "CLC failed: ad != pc.");
assert_report((ss_a = a_dbg), X"38", "SEC failed: ss_a != a.");
assert_report((ss_x = x_dbg), X"38", "SEC failed: ss_x != x.");
assert_report((ss_y = y_dbg), X"38", "SEC failed: ss_y != y.");
assert_report((p_dbg = ss_p(7 downto 1) & '1'), X"38", "SEC failed: C != 1.");
wait for clk_period;
nop(d);
assert_report((ss_a = a_dbg), X"18", "CLC failed: ss_a != a.");
assert_report((ss_x = x_dbg), X"18", "CLC failed: ss_x != x.");
assert_report((ss_y = y_dbg), X"18", "CLC failed: ss_y != y.");
assert_report((p_dbg = ss_p(7 downto 1) & '0'), X"18", "CLC failed: C != 0.");
end procedure test_clsec;
procedure test_clsed(
signal d: out std_logic_vector(7 downto 0)
) is
begin
sample_cpu_state;
d <= X"F8";
assert_report((ad = pc) and (r = '1'), X"F8", "SED failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = pc) and (r = '1'), X"F8", "SED failed: ad != pc.");
wait for clk_period;
d <= X"D8";
assert_report((ad = pc) and (r = '1'), X"D8", "CLD failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = pc) and (r = '1'), X"D8", "CLD failed: ad != pc.");
assert_report((ss_a = a_dbg), X"F8", "SED failed: ss_a != a.");
assert_report((ss_x = x_dbg), X"F8", "SED failed: ss_x != x.");
assert_report((ss_y = y_dbg), X"F8", "SED failed: ss_y != y.");
assert_report((p_dbg = ss_p(7 downto 4) & '1' & ss_p(2 downto 0)), X"F8", "SED failed: D != 1.");
wait for clk_period;
nop(d);
assert_report((ss_a = a_dbg), X"D8", "CLD failed: ss_a != a.");
assert_report((ss_x = x_dbg), X"D8", "CLD failed: ss_x != x.");
assert_report((ss_y = y_dbg), X"D8", "CLD failed: ss_y != y.");
assert_report((p_dbg = ss_p(7 downto 4) & '0' & ss_p(2 downto 0)), X"D8", "CLD failed: D != 0.");
end procedure test_clsed;
procedure test_load_imm(
signal d: out std_logic_vector(7 downto 0)
) is
begin
d <= X"A9";
assert_report((ad = pc) and (r = '1'), X"A9", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= imm_operands(0);
assert_report((ad = pc) and (r = '1'), X"A9", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
for i in 1 to (imm_operands'length - 1) loop
d <= X"A9";
assert_report((ad = pc) and (r = '1'), X"A9", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
d <= imm_operands(i);
assert_report(a_dbg = imm_operands(i - 1), X"A9", "Load immediate failed: a != imm");
assert_report(x_dbg = ss_x, X"A9", "Load immediate failed: x != ss_x");
assert_report(y_dbg = ss_y, X"A9", "Load immediate failed: y != ss_y");
assert_report((ad = pc), X"A9", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
end loop;
d <= X"A2";
assert_report((ad = pc) and (r = '1'), X"A2", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= imm_operands(0);
assert_report((ad = pc) and (r = '1'), X"A2", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
for i in 1 to (imm_operands'length - 1) loop
d <= X"A2";
assert_report((ad = pc) and (r = '1'), X"A2", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
d <= imm_operands(i);
assert_report(a_dbg = ss_a, X"A2", "Load immediate failed: a != ss_a");
assert_report(x_dbg = imm_operands(i - 1), X"A2", "Load immediate failed: x != imm");
assert_report(y_dbg = ss_y, X"A2", "Load immediate failed: y != ss_y");
assert_report((ad = pc), X"A2", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
end loop;
d <= X"A0";
assert_report((ad = pc) and (r = '1'), X"A0", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= imm_operands(0);
assert_report((ad = pc) and (r = '1'), X"A0", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
for i in 1 to (imm_operands'length - 1) loop
d <= X"A0";
assert_report((ad = pc) and (r = '1'), X"A0", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
d <= imm_operands(i);
assert_report(a_dbg = ss_a, X"A0", "Load immediate failed: a != ss_a");
assert_report(x_dbg = ss_x, X"A0", "Load immediate failed: x != ss_x");
assert_report(y_dbg = imm_operands(i - 1), X"A0", "Load immediate failed: y != imm");
assert_report((ad = pc), X"A0", "Load immediate failed: ad != pc.");
increment_pc;
wait for clk_period;
end loop;
end procedure test_load_imm;
function bcd_add(
constant oper1: in std_logic_vector(7 downto 0);
constant oper2: in std_logic_vector(7 downto 0);
constant c: in std_logic
) return std_logic_vector is
variable result: std_logic_vector(8 downto 0);
variable result_l: std_logic_vector(4 downto 0);
variable result_h: std_logic_vector(4 downto 0);
begin
result_l := (("0" & oper1(3 downto 0)) + ("0" & oper2(3 downto 0)) + ("0000" & c));
if (result_l > 9) then
result_l := result_l + 6;
end if;
result_h := (("0" & oper1(7 downto 4)) + ("0" & oper2(7 downto 4)) + ("0000" & result_l(4)));
if (result_h > 9) then
result_h := result_h + 6;
end if;
result := result_h & result_l(3 downto 0);
return result;
end function bcd_add;
function bcd_sub(
constant oper1: in std_logic_vector(7 downto 0);
constant oper2: in std_logic_vector(7 downto 0);
constant c: in std_logic
) return std_logic_vector is
variable result: std_logic_vector(7 downto 0);
variable result_int: integer range 0 to 255;
variable oper1_int: integer range 0 to 255;
variable oper2_int: integer range 0 to 255;
begin
oper1_int := 10 * conv_integer(oper1(7 downto 4)) + conv_integer(oper1(3 downto 0));
oper2_int := 10 * conv_integer(oper2(7 downto 4)) + conv_integer(oper2(3 downto 0));
result_int := oper1_int - oper2_int;
result := std_logic_vector(conv_unsigned(result_int, 8));
return result;
end function bcd_sub;
procedure alu_01_assert_result(
constant oper1: in std_logic_vector(7 downto 0);
constant oper2: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
variable result: std_logic_vector(8 downto 0);
variable s_result: std_logic_vector(7 downto 0);
begin
if ((ir(1 downto 0) = "00") and not (ir(7 downto 5) = "001")) then
result := ("0" & oper1) + ("0" & not oper2) + 1;
else
case ir(7 downto 5) is
when "000" => result := "0" & (oper1 or oper2);
when "001" => result := "0" & (oper1 and oper2);
when "010" => result := "0" & (oper1 xor oper2);
when "011" => result := ("0" & oper1) + ("0" & oper2) + ("00000000" & ss_p(C));
when "101" => result := "0" & oper2;
when "110" => result := ("0" & oper1) + ("0" & not oper2) + 1;
when "111" => result := ("0" & oper1) + ("0" & not oper2) + ("00000000" & ss_p(C));
when others => null;
end case;
end if;
if (ir(7 downto 5) = "011") and (p_dbg(3) = '1') then
result := bcd_add(oper1, oper2, ss_p(C));
end if;
if (ir(7 downto 5) = "111") and (p_dbg(3) = '1') then
result := bcd_sub(oper1, oper2, ss_p(C));
end if;
s_result := result(7 downto 0);
if ((ir(7 downto 5) = "110") or (ir(1 downto 0) = "00") or (ir = X"24") or (ir = X"2C")) then
assert_report((a_dbg = ss_a ), ir, "ALU Failed: a != ss_a.");
else
assert_report((a_dbg = s_result), ir, "ALU Failed: a != result.");
end if;
if (s_result = 0) then
assert_report((p_dbg(Z) = '1'), ir, "ALU Failed: Z incorrect.");
else
assert_report((p_dbg(Z) = '0'), ir, "ALU Failed: Z incorrect.");
end if;
if ((ir = X"24") or (ir = X"2C")) then
assert_report((oper2(7) = p_dbg(N)), ir, "ALU Failed: N incorrect.");
else
assert_report((s_result(7) = p_dbg(N)), ir, "ALU Failed: N incorrect.");
end if;
if ((ir(7 downto 5) = "011") or (ir(7 downto 5) = "110") or (ir(7 downto 5) = "111")) then
assert_report((p_dbg(C) = result(8)), ir, "ALU Failed: C incorrect.");
else
assert_report((p_dbg(C) = ss_p(C)), ir, "ALU Failed: C changed.");
end if;
assert_report((ss_x = x_dbg), ir, "ALU Failed: ss_x != x.");
assert_report((ss_y = y_dbg), ir, "ALU Failed: ss_y != y.");
end procedure alu_01_assert_result;
procedure alu_10_assert_result(
signal d: in std_logic_vector(7 downto 0);
constant oper: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
variable result : std_logic_vector(7 downto 0);
begin
case ir(7 downto 5) is
when "000" => result := oper(6 downto 0) & "0";
when "001" => result := oper(6 downto 0) & ss_p(C);
when "010" => result := "0" & oper(7 downto 1);
when "011" => result := ss_p(C) & oper(7 downto 1);
when "110" => result := oper - 1;
when "111" => result := oper + 1;
when others => null;
end case;
assert_report((result = d), ir, "ALU Failed: d != result.");
assert_report((result(7) = p_dbg(N)), ir, "ALU Failed: N incorrect.");
if (result = 0) then
assert_report((p_dbg(Z) = '1'), ir, "ALU Failed: Z incorrect.");
else
assert_report((p_dbg(Z) = '0'), ir, "ALU Failed: Z incorrect.");
end if;
case ir(7 downto 5) is
when "000" => assert_report((oper(7) = p_dbg(C)), ir, "ALU Failed: C incorrect.");
when "001" => assert_report((oper(7) = p_dbg(C)), ir, "ALU Failed: C incorrect.");
when "010" => assert_report((oper(0) = p_dbg(C)), ir, "ALU Failed: C incorrect.");
when "011" => assert_report((oper(0) = p_dbg(C)), ir, "ALU Failed: C incorrect.");
when "110" => assert_report((ss_p(C) = p_dbg(C)), ir, "ALU Failed: C changed.");
when "111" => assert_report((ss_p(C) = p_dbg(C)), ir, "ALU Failed: C changed.");
when others => null;
end case;
assert_report((ss_x = x_dbg), ir, "ALU Failed: ss_x != x.");
assert_report((ss_y = y_dbg), ir, "ALU Failed: ss_y != y.");
end procedure alu_10_assert_result;
procedure load_assert_result(
constant oper: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
if (ir(1 downto 0) = "10") then
assert_report((oper = x_dbg), ir, "ALU Failed: x != result.");
assert_report((ss_a = a_dbg), ir, "ALU Failed: ss_a != a.");
assert_report((ss_y = y_dbg), ir, "ALU Failed: ss_y != y.");
else
assert_report((oper = y_dbg), ir, "ALU Failed: y != result.");
assert_report((ss_a = a_dbg), ir, "ALU Failed: ss_a != a.");
assert_report((ss_x = x_dbg), ir, "ALU Failed: ss_x != x.");
end if;
if (oper = 0) then
assert_report((p_dbg(Z) = '1'), ir, "ALU Failed: Z incorrect.");
else
assert_report((p_dbg(Z) = '0'), ir, "ALU Failed: Z incorrect.");
end if;
assert_report((oper(7) = p_dbg(N)), ir, "ALU Failed: N incorrect.");
end procedure load_assert_result;
procedure alu_01_prepare_op(
signal d: out std_logic_vector(7 downto 0);
constant oper1: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
load_A(d, oper1);
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
end procedure alu_01_prepare_op;
procedure alu_10_prepare_op(
signal d: out std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
end procedure alu_10_prepare_op;
procedure load_prepare_op(
signal d: out std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
end procedure load_prepare_op;
procedure cmp_prepare_op(
signal d: out std_logic_vector(7 downto 0);
constant oper1: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
if (ir(7 downto 5) = "110") then
load_Y(d, oper1);
else
load_X(d, oper1);
end if;
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
end procedure cmp_prepare_op;
procedure stxy_prepare_op(
signal d: out std_logic_vector(7 downto 0);
constant oper1: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
if (ir(1 downto 0) = "00") then
load_Y(d, oper1);
else
load_X(d, oper1);
end if;
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
end procedure stxy_prepare_op;
procedure alu_01_finalize_op(
signal d: out std_logic_vector(7 downto 0);
constant oper2: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
d <= oper2;
assert_report((r = '1'), ir, "Failed: r != 1.");
wait for clk_period;
nop(d);
end procedure alu_01_finalize_op;
procedure load_finalize_op(
signal d: out std_logic_vector(7 downto 0);
constant oper: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
d <= oper;
assert_report((r = '1'), ir, "Failed: r != 1.");
wait for clk_period;
nop(d);
end procedure load_finalize_op;
procedure store_finalize_op(
signal d: in std_logic_vector(7 downto 0);
constant oper: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
assert_report((d = oper), ir, "Store failed: d != oper.");
assert_report((r = '0'), ir, "Store failed: r != 0.");
assert_report((ss_a = a_dbg), ir, "Store failed: ss_x != x.");
assert_report((ss_x = x_dbg), ir, "Store failed: ss_x != x.");
assert_report((ss_y = y_dbg), ir, "Store failed: ss_y != y.");
assert_report((ss_p = p_dbg), ir, "Store failed: P changed.");
end procedure store_finalize_op;
procedure alu_10_finalize_op(
signal d: out std_logic_vector(7 downto 0);
constant oper: in std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
d <= oper;
assert_report((r = '1'), ir, "Failed: r != 1.");
wait for clk_period;
d <= "ZZZZZZZZ";
assert_report((r = '0'), ir, "Failed: r != 0.");
--assert_report((d = oper), ir, "Failed: d != oper.");
wait for clk_period;
assert_report((r = '0'), ir, "Failed: r != 0.");
end procedure alu_10_finalize_op;
procedure test_alu_01(
signal d: out std_logic_vector(7 downto 0);
constant op: in std_logic_vector(2 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
for j in 0 to (imm_operands'length - 1) loop
ir := op & "01001";
alu_01_prepare_op(d, imm_operands(i), ir);
test_imm_mode(ir);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
for k in 0 to (adr_operands'length - 1) loop
ir := op & "00101";
alu_01_prepare_op(d, imm_operands(i), ir);
test_zp_mode(adr_operands(k), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
ir := op & "01101";
alu_01_prepare_op(d, imm_operands(i), ir);
test_abs_mode(ad_operands(k), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
for l in 0 to (adr_operands'length - 1) loop
ir := op & "10101";
load_X(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_zp_idx_mode(adr_operands(k), adr_operands(l), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
ir := op & "11101";
load_X(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_abs_idx_mode(ad_operands(k), adr_operands(l), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
ir := op & "11001";
load_Y(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_abs_idx_mode(ad_operands(k), adr_operands(l), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
for m in 0 to (adr_operands'length - 1) loop
ir := op & "00001";
load_X(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_ind_x_mode(adr_operands(m), ad_operands(k), adr_operands(l), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
ir := op & "10001";
load_Y(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_ind_y_mode(adr_operands(m), ad_operands(k), adr_operands(l), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
end loop;
end loop;
end loop;
end loop;
end loop;
end procedure test_alu_01;
procedure test_bit(
signal d: out std_logic_vector(7 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
for j in 0 to (imm_operands'length - 1) loop
for k in 0 to (adr_operands'length - 1) loop
ir := X"24";
alu_01_prepare_op(d, imm_operands(i), ir);
test_zp_mode(adr_operands(k), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
ir := X"2C";
alu_01_prepare_op(d, imm_operands(i), ir);
test_abs_mode(ad_operands(k), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
end loop;
end loop;
end loop;
end procedure test_bit;
procedure test_alu_10(
signal d: inout std_logic_vector(7 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for op in 0 to (alu_10_opcodes'length - 1) loop
for i in 0 to (imm_operands'length - 1) loop
for k in 0 to (adr_operands'length - 1) loop
ir := alu_10_opcodes(op) & "00110";
alu_10_prepare_op(d, ir);
test_zp_mode(adr_operands(k), ir, d);
alu_10_finalize_op(d, imm_operands(i), ir);
alu_10_assert_result(d, imm_operands(i), ir);
wait for clk_period;
ir := alu_10_opcodes(op) & "01110";
alu_10_prepare_op(d, ir);
test_abs_mode(ad_operands(k), ir, d);
alu_10_finalize_op(d, imm_operands(i), ir);
alu_10_assert_result(d, imm_operands(i), ir);
wait for clk_period;
for l in 0 to (adr_operands'length - 1) loop
ir := alu_10_opcodes(op) & "10110";
load_X(d, adr_operands(l));
alu_10_prepare_op(d, ir);
test_zp_idx_mode(adr_operands(k), adr_operands(l), ir, d);
alu_10_finalize_op(d, imm_operands(i), ir);
alu_10_assert_result(d, imm_operands(i), ir);
wait for clk_period;
ir := alu_10_opcodes(op) & "11110";
load_X(d, adr_operands(l));
alu_10_prepare_op(d, ir);
test_abs_idx_mode(ad_operands(k), adr_operands(l), ir, d);
alu_10_finalize_op(d, imm_operands(i), ir);
alu_10_assert_result(d, imm_operands(i), ir);
wait for clk_period;
end loop;
end loop;
end loop;
end loop;
end procedure test_alu_10;
procedure test_store(
signal d: inout std_logic_vector(7 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
for k in 0 to (adr_operands'length - 1) loop
ir := "10000101";
alu_01_prepare_op(d, imm_operands(i), ir);
test_zp_mode(adr_operands(k), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
ir := "10001101";
alu_01_prepare_op(d, imm_operands(i), ir);
test_abs_mode(ad_operands(k), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
for l in 0 to (adr_operands'length - 1) loop
ir := "10010101";
load_X(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_zp_idx_mode(adr_operands(k), adr_operands(l), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
ir := "10011101";
load_X(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_abs_idx_mode(ad_operands(k), adr_operands(l), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
ir := "10011001";
load_Y(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_abs_idx_mode(ad_operands(k), adr_operands(l), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
for m in 0 to (adr_operands'length - 1) loop
ir := "10000001";
load_X(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_ind_x_mode(adr_operands(m), ad_operands(k), adr_operands(l), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
ir := "10010001";
load_Y(d, adr_operands(l));
alu_01_prepare_op(d, imm_operands(i), ir);
test_ind_y_mode(adr_operands(m), ad_operands(k), adr_operands(l), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
end loop;
end loop;
end loop;
end loop;
end procedure test_store;
procedure test_load(
signal d: out std_logic_vector(7 downto 0);
constant cc: in std_logic_vector(1 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
for k in 0 to (adr_operands'length - 1) loop
ir := "101001" & cc;
load_prepare_op(d, ir);
test_zp_mode(adr_operands(k), ir, d);
load_finalize_op(d, imm_operands(i), ir);
load_assert_result(imm_operands(i), ir);
ir := "101011" & cc;
load_prepare_op(d, ir);
test_abs_mode(ad_operands(k), ir, d);
load_finalize_op(d, imm_operands(i), ir);
load_assert_result(imm_operands(i), ir);
for l in 0 to (adr_operands'length - 1) loop
ir := "101101" & cc;
if (cc = "00") then
load_X(d, adr_operands(l));
else
load_Y(d, adr_operands(l));
end if;
load_prepare_op(d, ir);
test_zp_idx_mode(adr_operands(k), adr_operands(l), ir, d);
load_finalize_op(d, imm_operands(i), ir);
load_assert_result(imm_operands(i), ir);
ir := "101111" & cc;
if (cc = "00") then
load_X(d, adr_operands(l));
else
load_Y(d, adr_operands(l));
end if;
load_prepare_op(d, ir);
test_abs_idx_mode(ad_operands(k), adr_operands(l), ir, d);
load_finalize_op(d, imm_operands(i), ir);
load_assert_result(imm_operands(i), ir);
end loop;
end loop;
end loop;
end procedure test_load;
procedure test_cmp(
signal d: out std_logic_vector(7 downto 0);
constant aaa: in std_logic_vector(2 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
for j in 0 to (imm_operands'length - 1) loop
ir := aaa & "00000";
cmp_prepare_op(d, imm_operands(i), ir);
test_imm_mode(ir);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
for k in 0 to (adr_operands'length - 1) loop
ir := aaa & "00100";
cmp_prepare_op(d, imm_operands(i), ir);
test_zp_mode(adr_operands(k), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
ir := aaa & "01100";
cmp_prepare_op(d, imm_operands(i), ir);
test_abs_mode(ad_operands(k), ir, d);
alu_01_finalize_op(d, imm_operands(j), ir);
alu_01_assert_result(imm_operands(i), imm_operands(j), ir);
end loop;
end loop;
end loop;
end procedure test_cmp;
procedure test_inxy_dexy(
signal d: out std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
variable op, i, j, k, l, m: natural;
variable result : std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
if (ir = X"E8" or ir = X"CA") then
load_X(d, imm_operands(i));
else
load_Y(d, imm_operands(i));
end if;
if (ir = X"E8" or ir = X"C8") then
result := imm_operands(i) + 1;
else
result := imm_operands(i) - 1;
end if;
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
wait for clk_period;
nop(d);
assert_report((a_dbg = ss_a), ir, "Failed: a != ss_a");
if (ir = X"E8" or ir = X"CA") then
assert_report((x_dbg = result), ir, "Failed: x != result.");
assert_report((y_dbg = ss_y), ir, "Failed: y != ss_y");
else
assert_report((y_dbg = result), ir, "Failed: y != result.");
assert_report((x_dbg = ss_x), ir, "Failed: x != ss_x");
end if;
if (result = 0) then
assert_report((p_dbg(Z) = '1'), ir, "ALU Failed: Z incorrect.");
else
assert_report((p_dbg(Z) = '0'), ir, "ALU Failed: Z incorrect.");
end if;
assert_report((result(7) = p_dbg(N)), ir, "ALU Failed: N incorrect.");
assert_report((p_dbg(C) = ss_p(C)), ir, "ALU Failed: C changed.");
end loop;
end procedure test_inxy_dexy;
procedure test_stxy(
signal d: inout std_logic_vector(7 downto 0);
constant cc: in std_logic_vector(1 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
for k in 0 to (adr_operands'length - 1) loop
ir := "100001" & cc;
stxy_prepare_op(d, imm_operands(i), ir);
test_zp_mode(adr_operands(k), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
ir := "100011" & cc;
stxy_prepare_op(d, imm_operands(i), ir);
test_abs_mode(ad_operands(k), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
for l in 0 to (adr_operands'length - 1) loop
ir := "100101" & cc;
if (cc = "10") then
load_Y(d, adr_operands(l));
else
load_X(d, adr_operands(l));
end if;
stxy_prepare_op(d, imm_operands(i), ir);
test_zp_idx_mode(adr_operands(k), adr_operands(l), ir, d);
d <= "ZZZZZZZZ";
wait for clk_period / 4;
store_finalize_op(d, imm_operands(i), ir);
wait for 3 * clk_period / 4;
end loop;
end loop;
end loop;
end procedure test_stxy;
procedure test_alu_10_acc(
signal d: inout std_logic_vector(7 downto 0)
) is
variable ir : std_logic_vector(7 downto 0);
begin
for op in 0 to 3 loop
for i in 0 to (imm_operands'length - 1) loop
ir := alu_10_opcodes(op) & "01010";
alu_01_prepare_op(d, imm_operands(i), ir);
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
wait for clk_period;
nop(d);
alu_10_assert_result(a_dbg, imm_operands(i), ir);
end loop;
end loop;
end procedure test_alu_10_acc;
procedure init_stack(
signal d: inout std_logic_vector(7 downto 0)
) is
begin
load_X(d, X"FF");
d <= X"9A";
increment_pc;
wait for clk_period;
wait for clk_period;
nop(d);
assert (s_dbg = X"FF") report "Stack initialization failed.";
end procedure init_stack;
procedure test_pha(
signal d: inout std_logic_vector(7 downto 0)
) is
variable k: std_logic_vector(7 downto 0);
begin
for i in 0 to (imm_operands'length - 1) loop
load_A(d, imm_operands(i));
d <= X"48";
assert_report((ad = pc) and (r = '1'), X"48", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
assert_report((ad = pc) and (r = '1'), X"48", "Failed: ad != pc.");
wait for clk_period;
d <= "ZZZZZZZZ";
wait for clk_period / 4;
assert_report((ad = (X"01" & s_dbg)) and (r = '0'), X"48", "Failed: ad != s.");
k := d; --Stupid Xilinx ISE Simulator: "Generated C++ compilation was unsuccessful".
assert_report((k = imm_operands(i)), X"48", "Failed: d != oper.");
wait for 3 * clk_period / 4;
nop(d);
assert_report((s_dbg = (ss_s - 1)), X"48", "Failed: s != s - 1.");
assert_report((a_dbg = ss_a), X"48", "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), X"48", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"48", "Failed: y != ss_y.");
end loop;
end procedure test_pha;
procedure test_php(
signal d: inout std_logic_vector(7 downto 0)
) is
variable k: std_logic_vector(7 downto 0);
begin
d <= X"08";
assert_report((ad = pc) and (r = '1'), X"08", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
assert_report((ad = pc) and (r = '1'), X"08", "Failed: ad != pc.");
wait for clk_period;
d <= "ZZZZZZZZ";
wait for clk_period / 4;
assert_report((ad = (X"01" & s_dbg)) and (r = '0'), X"08", "Failed: ad != s.");
k := d; --Stupid Xilinx ISE Simulator: "Generated C++ compilation was unsuccessful".
assert_report((k = ss_p), X"08", "Failed: d != p.");
wait for 3 * clk_period / 4;
nop(d);
assert_report((s_dbg = (ss_s - 1)), X"48", "Failed: s != s - 1.");
assert_report((a_dbg = ss_a), X"48", "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), X"48", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"48", "Failed: y != ss_y.");
end procedure test_php;
procedure test_pla(
signal d: inout std_logic_vector(7 downto 0)
) is
begin
for i in 0 to (imm_operands'length - 1) loop
d <= X"68";
assert_report((ad = pc) and (r = '1'), X"68", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
assert_report((ad = pc) and (r = '1'), X"68", "Failed: ad != pc.");
wait for clk_period;
assert_report((ad = (X"01" & s_dbg)) and (r = '1'), X"68", "Failed: ad != s.");
wait for clk_period;
d <= imm_operands(i);
assert_report((ad = (X"01" & (ss_s + 1))) and (r = '1'), X"68", "Failed: ad != s.");
wait for clk_period;
nop(d);
assert_report((s_dbg = (ss_s + 1)), X"68", "Failed: s != s + 1.");
assert_report((a_dbg = imm_operands(i)), X"68", "Failed: a != oper.");
assert_report((x_dbg = ss_x), X"68", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"68", "Failed: y != ss_y.");
end loop;
end procedure test_pla;
procedure test_plp(
signal d: inout std_logic_vector(7 downto 0)
) is
begin
d <= X"28";
assert_report((ad = pc) and (r = '1'), X"28", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
assert_report((ad = pc) and (r = '1'), X"28", "Failed: ad != pc.");
wait for clk_period;
assert_report((ad = (X"01" & s_dbg)) and (r = '1'), X"28", "Failed: ad != s.");
wait for clk_period;
d <= X"FF";
assert_report((ad = (X"01" & (ss_s + 1))) and (r = '1'), X"28", "Failed: ad != s.");
wait for clk_period;
nop(d);
assert_report((s_dbg = (ss_s + 1)), X"28", "Failed: s != s + 1.");
assert_report((p_dbg = X"FF"), X"28", "Failed: p != oper."); -- FIXME
assert_report((a_dbg = ss_a), X"28", "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), X"28", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"28", "Failed: y != ss_y.");
end procedure test_plp;
procedure test_jsr(
signal d: inout std_logic_vector(7 downto 0)
) is
variable k: std_logic_vector(7 downto 0);
begin
for i in 0 to (ad_operands'length - 1) loop
d <= X"20";
assert_report((ad = pc) and (r = '1'), X"20", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
d <= ad_operands(i)(7 downto 0);
assert_report((ad = pc) and (r = '1'), X"20", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
assert_report((ad = (X"01" & s_dbg)) and (r = '1'), X"20", "Failed: ad != s.");
wait for clk_period;
d <= "ZZZZZZZZ";
wait for clk_period / 4;
assert_report((ad = (X"01" & s_dbg)) and (r = '0'), X"20", "Failed: ad != s.");
k := d; --Stupid Xilinx ISE Simulator: "Generated C++ compilation was unsuccessful".
assert_report((k = pc(15 downto 8)), X"20", "Failed: d != pch.");
wait for clk_period;
assert_report((ad = (X"01" & (ss_s - 1))) and (r = '0'), X"20", "Failed: ad != s - 1.");
k := d; --Stupid Xilinx ISE Simulator: "Generated C++ compilation was unsuccessful".
assert_report((k = pc(7 downto 0)), X"20", "Failed: d != pcl.");
wait for 3 * clk_period / 4;
d <= ad_operands(i)(15 downto 8);
assert_report((ad = pc) and (r = '1'), X"20", "Failed: ad != pc.");
wait for clk_period;
jump_pc(ad_operands(i));
assert_report((ad = pc) and (r = '1'), X"20", "Failed: ad != new_pc.");
assert_report((s_dbg = (ss_s - 2)), X"20", "Failed: s != s - 2.");
assert_report((a_dbg = ss_a), X"20", "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), X"20", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"20", "Failed: y != ss_y.");
assert_report((p_dbg = ss_p), X"20", "Failed: p != ss_p.");
end loop;
end procedure test_jsr;
procedure test_brk(
signal d: inout std_logic_vector(7 downto 0);
constant adr: std_logic_vector(15 downto 0);
constant vec: std_logic_vector(15 downto 0);
constant intr: boolean
) is
variable k: std_logic_vector(7 downto 0);
begin
sample_cpu_state;
if (intr) then
d <= X"EA";
else
d <= X"00";
end if;
assert_report((ad = pc) and (r = '1'), X"00", "Failed: ad != pc.");
if (not intr) then
increment_pc;
end if;
wait for clk_period;
assert_report((ad = pc) and (r = '1'), X"00", "Failed: ad != pc.");
if (not intr) then
increment_pc;
end if;
wait for clk_period;
d <= "ZZZZZZZZ";
wait for clk_period / 4;
assert_report((ad = (X"01" & s_dbg)) and (r = '0'), X"00", "Failed: ad != s.");
k := d; --Stupid Xilinx ISE Simulator: "Generated C++ compilation was unsuccessful".
assert_report((k = pc(15 downto 8)), X"00", "Failed: d != pch.");
wait for clk_period;
assert_report((ad = (X"01" & (ss_s - 1))) and (r = '0'), X"00", "Failed: ad != s - 1.");
k := d; --Stupid Xilinx ISE Simulator: "Generated C++ compilation was unsuccessful".
assert_report((k = pc(7 downto 0)), X"00", "Failed: d != pcl.");
wait for clk_period;
assert_report((ad = (X"01" & (ss_s - 2))) and (r = '0'), X"00", "Failed: ad != s - 2.");
k := d; --Stupid Xilinx ISE Simulator: "Generated C++ compilation was unsuccessful".
if (not intr) then
assert_report((p_dbg = ss_p(7 downto 5) & "1" & ss_p(3 downto 0)), X"00", "Failed: d != p.");
else
assert_report((p_dbg = ss_p(7 downto 5) & "0" & ss_p(3 downto 0)), X"00", "Failed: d != p.");
end if;
wait for 3 * clk_period / 4;
assert_report((ad = adr) and (r = '1'), X"00", "Failed: ad != adr.");
d <= vec(7 downto 0);
wait for clk_period;
assert_report((ad = adr + 1) and (r = '1'), X"00", "Failed: ad != adr + 1.");
d <= vec(15 downto 8);
wait for clk_period;
assert_report((ad = vec) and (r = '1'), X"00", "Failed: ad != vec.");
jump_pc(vec);
assert_report((s_dbg = (ss_s - 3)), X"00", "Failed: s != s - 3.");
assert_report((a_dbg = ss_a), X"00", "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), X"00", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"00", "Failed: y != ss_y.");
--assert_report((p_dbg = ss_p(7 downto 3) & "1" & ss_p(1 downto 0)), X"00", "Failed: p != ss_p.");
end procedure test_brk;
procedure test_jmp(
signal d: inout std_logic_vector(7 downto 0)
) is
begin
for i in 0 to (ad_operands'length - 1) loop
d <= X"4C";
assert_report((ad = pc) and (r = '1'), X"4C", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
d <= ad_operands(i)(7 downto 0);
assert_report((ad = pc) and (r = '1'), X"4C", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= ad_operands(i)(15 downto 8);
assert_report((ad = pc) and (r = '1'), X"4C", "Failed: ad != pc.");
wait for clk_period;
jump_pc(ad_operands(i));
assert_report((ad = pc) and (r = '1'), X"4C", "Failed: ad != new_pc.");
assert_report((s_dbg = ss_s), X"4C", "Failed: s != ss_s.");
assert_report((a_dbg = ss_a), X"4C", "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), X"4C", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"4C", "Failed: y != ss_y.");
assert_report((p_dbg = ss_p), X"4C", "Failed: p != ss_p.");
end loop;
end procedure test_jmp;
procedure test_jmp_abs(
signal d: inout std_logic_vector(7 downto 0)
) is
begin
for i in 0 to (ad_operands'length - 1) loop
for j in 0 to (ad_operands'length - 1) loop
d <= X"6C";
assert_report((ad = pc) and (r = '1'), X"6C", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
d <= ad_operands(i)(7 downto 0);
assert_report((ad = pc) and (r = '1'), X"6C", "Failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= ad_operands(i)(15 downto 8);
assert_report((ad = pc) and (r = '1'), X"6C", "Failed: ad != pc.");
wait for clk_period;
d <= ad_operands(j)(7 downto 0);
assert_report((ad = ad_operands(i)) and (r = '1'), X"6C", "Failed: ad != oper.");
wait for clk_period;
d <= ad_operands(j)(15 downto 8);
-- FIXME below: 6502 bug.
assert_report((ad = (ad_operands(i) + 1)) and (r = '1'), X"6C", "Failed: ad != oper.");
wait for clk_period;
jump_pc(ad_operands(j));
assert_report((ad = pc) and (r = '1'), X"6C", "Failed: ad != new_pc.");
assert_report((s_dbg = ss_s), X"6C", "Failed: s != ss_s.");
assert_report((a_dbg = ss_a), X"6C", "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), X"6C", "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), X"6C", "Failed: y != ss_y.");
assert_report((p_dbg = ss_p), X"6C", "Failed: p != ss_p.");
end loop;
end loop;
end procedure test_jmp_abs;
procedure test_rt(
signal d: out std_logic_vector(7 downto 0);
constant ir: in std_logic_vector(7 downto 0)
) is
begin
for i in 0 to (ad_operands'length - 1) loop
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
sample_cpu_state;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
wait for clk_period;
assert_report((ad = (X"01" & s_dbg)) and (r = '1'), ir, "Failed: ad != s.");
wait for clk_period;
if (ir = X"40") then
d <= X"FF";
ss_s := ss_s + 1;
assert_report((ad = (X"01" & s_dbg)) and (r = '1'), ir, "Failed: ad != s.");
wait for clk_period;
end if;
d <= ad_operands(i)(7 downto 0);
assert_report((ad = (X"01" & (ss_s + 1))) and (r = '1'), ir, "Failed: ad != s.");
wait for clk_period;
d <= ad_operands(i)(15 downto 8);
assert_report((ad = (X"01" & (ss_s + 2))) and (r = '1'), ir, "Failed: ad != s.");
wait for clk_period;
jump_pc(ad_operands(i));
if (ir = X"60") then
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != new_pc.");
increment_pc;
wait for clk_period;
end if;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != new_pc + 1.");
assert_report((s_dbg = (ss_s + 2)), ir, "Failed: s != s + 2.");
assert_report((a_dbg = ss_a), ir, "Failed: a != ss_a.");
assert_report((x_dbg = ss_x), ir, "Failed: x != ss_x.");
assert_report((y_dbg = ss_y), ir, "Failed: y != ss_y.");
if (ir = X"40") then
assert_report((p_dbg = X"FF"), ir, "Failed: p != (s)."); -- FIXME
else
assert_report((p_dbg = ss_p), ir, "Failed: p != ss_p.");
end if;
end loop;
end procedure test_rt;
procedure load_flags(
signal d: out std_logic_vector(7 downto 0);
constant v: in std_logic_vector(7 downto 0)
) is
begin
d <= X"28";
increment_pc;
wait for clk_period;
wait for clk_period;
d <= v;
wait for clk_period;
wait for clk_period;
end procedure load_flags;
procedure test_branch(
signal d: out std_logic_vector(7 downto 0)
) is
variable flgs: std_logic_vector(7 downto 0);
variable ir: std_logic_vector(7 downto 0);
variable flg: std_logic;
variable sum: std_logic_vector(8 downto 0);
variable flgs_pack: std_logic_vector(3 downto 0);
begin
flgs(5 downto 2) := "0000";
for i in 0 to 15 loop
flgs_pack := conv_std_logic_vector(i, 4);
flgs(C) := flgs_pack(0);
flgs(Z) := flgs_pack(1);
flgs(V) := flgs_pack(2);
flgs(N) := flgs_pack(3);
load_flags(d, flgs);
for j in 0 to 3 loop
for k in 0 to 1 loop
ir := conv_std_logic_vector(j, 2) &
conv_std_logic_vector(k, 1) &
"10000";
case j is
when 0 => flg := flgs(N);
when 1 => flg := flgs(V);
when 2 => flg := flgs(C);
when 3 => flg := flgs(Z);
end case;
for l in 0 to (adr_operands'length - 1) loop
d <= ir;
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
d <= adr_operands(l);
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
increment_pc;
wait for clk_period;
if (flg = conv_std_logic_vector(k, 1)(0)) then
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != pc.");
wait for clk_period;
sum := ('0' & pc(7 downto 0)) + ('0' & adr_operands(l));
assert_report((ad = pc(15 downto 8) & sum(7 downto 0)) and (r = '1'), ir, "Failed: ad != new_pc.");
if (sum(8) = '1') and (adr_operands(l)(7) = '0') then
wait for clk_period;
jump_pc((pc(15 downto 8) + 1) & sum(7 downto 0));
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != new_pc.");
elsif (sum(8) = '0') and (adr_operands(l)(7) = '1') then
wait for clk_period;
jump_pc((pc(15 downto 8) - 1) & sum(7 downto 0));
assert_report((ad = pc) and (r = '1'), ir, "Failed: ad != new_pc.");
else
jump_pc(pc(15 downto 8) & sum(7 downto 0));
end if;
end if;
end loop;
end loop;
end loop;
end loop;
end procedure test_branch;
procedure test_interrupt(
signal d: inout std_logic_vector(7 downto 0);
signal irq: out std_logic;
signal nmi: out std_logic
) is
begin
d <= X"58";
increment_pc;
wait for clk_period;
wait for clk_period;
d <= X"EA";
increment_pc;
wait for clk_period;
irq <= '0';
wait for clk_period;
test_brk(d, X"FFFE", irq_vec, true);
irq <= '1';
d <= X"58";
increment_pc;
wait for clk_period;
wait for clk_period;
d <= X"EA";
increment_pc;
wait for clk_period;
nmi <= '0';
wait for clk_period;
test_brk(d, X"FFFA", nmi_vec, true);
end procedure test_interrupt;
begin
test_A6500: A6500
port map(clk, rst, irq, nmi, stop, d, ad, r,
a_dbg, x_dbg, y_dbg, s_dbg, pcl_dbg, pch_dbg, adl_dbg, adh_dbg, p_dbg);
clk_sig: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process;
process
variable l : line;
begin
wait for 100 ns;
irq <= '1';
nmi <= '1';
stop <= '0';
reset_cpu(rst, d);
status_report("CPU Initialization: Done.");
test_nop(d);
status_report("NOP Test: Done.");
test_clsec(d);
status_report("SEC/CLC Test: Done.");
test_clsed(d);
status_report("SED/CLD Test: Done.");
test_load_imm(d);
status_report("Load Immediate Test: Done.");
for op in 0 to (alu_01_opcodes'length - 1) loop
if ((op = 3) or (op = 7)) then
d <= X"F8";
increment_pc;
wait for clk_period;
wait for clk_period;
test_alu_01(d, alu_01_opcodes(op));
d <= X"D8";
increment_pc;
wait for clk_period;
wait for clk_period;
end if;
test_alu_01(d, alu_01_opcodes(op));
end loop;
status_report("ALU 01 Test: Done.");
test_alu_10(d);
test_alu_10_acc(d);
status_report("ALU 10 Test: Done.");
test_bit(d);
status_report("BIT Test: Done.");
test_store(d);
status_report("STA Test: Done.");
test_stxy(d, "00");
test_stxy(d, "10");
status_report("STX/Y Test: Done.");
test_load(d, "10");
test_load(d, "00");
status_report("LDX/Y Test: Done.");
test_cmp(d, "110");
test_cmp(d, "111");
status_report("CPX/Y Test: Done.");
test_inxy_dexy(d, X"C8");
test_inxy_dexy(d, X"E8");
status_report("INX/Y Test: Done.");
test_inxy_dexy(d, X"88");
test_inxy_dexy(d, X"CA");
status_report("DEX/Y Test: Done.");
init_stack(d);
status_report("Stack Initialization: Done.");
test_pha(d);
test_pla(d);
test_php(d);
test_plp(d);
status_report("Stack Test: Done.");
test_jsr(d);
test_jmp(d);
test_jmp_abs(d);
test_brk(d, X"FFFE", irq_vec, false);
test_rt(d, X"60");
test_rt(d, X"40");
status_report("JMP/JSR/BRK/RTS/RTI Test: Done.");
test_branch(d);
status_report("Branch Test: Done.");
test_interrupt(d, irq, nmi);
status_report("IRQ/NMI Test: Done.");
wait;
end process;
end bench;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.55e-06,
W => Wdiff_0,
Wdiff_0init => 4.2e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.55e-06,
W => Wdiff_0,
Wdiff_0init => 4.2e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => W_0,
W_0init => 3.8e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcm_2,
Wcm_2init => 9.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcmout_2,
Wcmout_2init => 5.7e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcm_2,
Wcm_2init => 9.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcmout_2,
Wcmout_2init => 5.7e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.35e-06,
W => Wcm_1,
Wcm_1init => 1.37e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.35e-06,
W => Wcmcout_1,
Wcmcout_1init => 5.025e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => (pfak)*(WBias),
WBiasinit => 7.25e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.2e-06,
W => (pfak)*(WBias),
WBiasinit => 7.25e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_control IS
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END sram_control;
ARCHITECTURE primitive OF sram_control IS
SIGNAL reset_on : std_logic;
BEGIN
reset_logic: PROCESS
BEGIN
reset_on <= '0';
WAIT UNTIL RESET='1';
WAIT UNTIL falling_edge(CLK);
reset_on <= '1';
WAIT UNTIL rising_edge(CLK);
END PROCESS;
SELECT_ALL <= reset_on;
WE <= (NOT CLK) AND (reset_on OR (NOT C_READ));
CS <= (NOT CLK) AND (C_WRITE OR C_READ);
TO_DATA_IN <= (OTHERS => '0') WHEN reset_on='1'
ELSE DATA_IN;
END primitive;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_control IS
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END sram_control;
ARCHITECTURE primitive OF sram_control IS
SIGNAL reset_on : std_logic;
BEGIN
reset_logic: PROCESS
BEGIN
reset_on <= '0';
WAIT UNTIL RESET='1';
WAIT UNTIL falling_edge(CLK);
reset_on <= '1';
WAIT UNTIL rising_edge(CLK);
END PROCESS;
SELECT_ALL <= reset_on;
WE <= (NOT CLK) AND (reset_on OR (NOT C_READ));
CS <= (NOT CLK) AND (C_WRITE OR C_READ);
TO_DATA_IN <= (OTHERS => '0') WHEN reset_on='1'
ELSE DATA_IN;
END primitive;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_control IS
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END sram_control;
ARCHITECTURE primitive OF sram_control IS
SIGNAL reset_on : std_logic;
BEGIN
reset_logic: PROCESS
BEGIN
reset_on <= '0';
WAIT UNTIL RESET='1';
WAIT UNTIL falling_edge(CLK);
reset_on <= '1';
WAIT UNTIL rising_edge(CLK);
END PROCESS;
SELECT_ALL <= reset_on;
WE <= (NOT CLK) AND (reset_on OR (NOT C_READ));
CS <= (NOT CLK) AND (C_WRITE OR C_READ);
TO_DATA_IN <= (OTHERS => '0') WHEN reset_on='1'
ELSE DATA_IN;
END primitive;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Dec 25 17:16:48 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_small/ball_small_sim_netlist.vhdl
-- Design : ball_small
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end ball_small_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of ball_small_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000013301330133013301330133013301330",
INIT_01 => X"1330133013301330133013301330133013301330133013300000000000000000",
INIT_02 => X"3C003C003C003C003C003C003C003C003C000000000013301330133013301330",
INIT_03 => X"133013301330133013301330133013301330133013301330000000001C001C00",
INIT_04 => X"00001C0000003C003C003C003C003C003C003C003C003C003C00000013301330",
INIT_05 => X"0000000013301330133013301330133013301330133013300000000026190000",
INIT_06 => X"2619261900001C0000003C003C003C003C003C003C003C003C003C003C003C00",
INIT_07 => X"3C003C003C00000000001330133013301330133013301330133000002E3B2619",
INIT_08 => X"261926192E3B2E3B00001C001C0000003C003C003C003C003C003C003C003C00",
INIT_09 => X"3C003C003C003C003C003C000000133013301330133013301330133000002619",
INIT_0A => X"261926192E3B261926192619261900001C0000003C003C003C003C003C003C00",
INIT_0B => X"3C003C003C003C003C003C003C003C003C000000000013301330133013300000",
INIT_0C => X"000026192E3B26192E3B261926192619261900001C001C0000003C003C003C00",
INIT_0D => X"3C003C003C003C003C003C003C003C003C003C003C0000000000133013301330",
INIT_0E => X"1330000000002E3B26192619261926192E3B26192E3B26191C001C0000003C00",
INIT_0F => X"00003C003C003C003C003C003C003C003C003C003C003C003C003C0000001330",
INIT_10 => X"0000000013300000261926192E3B26192E3B26192619261926192E3B1C001C00",
INIT_11 => X"00001C001C001C001C0000003C003C003C003C003C003C003C003C003C003C00",
INIT_12 => X"3C003C003C000000133000002E3B26192E3B26192E3B26192619261926192E3B",
INIT_13 => X"2E3B000000001C001C001C001C001C003C003C003C003C003C003C003C003C00",
INIT_14 => X"3C003C003C003C003C0000000000261926192E3B26192619261926192E3B2619",
INIT_15 => X"26192E3B26191C001C001C001C001C001C001C001C0000003C003C003C003C00",
INIT_16 => X"3C003C003C003C003C003C003C00000000002E3B2619261926192E3B26192E3B",
INIT_17 => X"26192E3B26192E3B00001C001C001C003F3F3F3F3F3F1C001C0000003C003C00",
INIT_18 => X"00003C003C003C003C003C003C003C003C00000000002E3B2619261926192E3B",
INIT_19 => X"2E3B26192E3B26192619261900001C001C003F3F3F3F00003F3F3F3F1C001C00",
INIT_1A => X"1C001C0000003C003C003C003C003C003C003C003C0000000000261926192619",
INIT_1B => X"2619261926192E3B26192E3B261900001C001C001C003F3F00003F3F00003F3F",
INIT_1C => X"3F3F3F3F1C001C0000003C003C003C003C003C003C003C003C00000000002E3B",
INIT_1D => X"00002E3B2619261926192E3B261926192E3B261900001C0000003F3F3F3F0000",
INIT_1E => X"3F3F3F3F3F3F1C001C001C0000003C003C003C003C003C003C003C003C000000",
INIT_1F => X"3C00000000002619261926192E3B26192E3B26192619261900001C001C001C00",
INIT_20 => X"1C001C001C00000000001C001C0000003C003C003C003C003C003C003C003C00",
INIT_21 => X"3C003C003C00000000002E3B2619261926192E3B26192E3B26192E3B26190000",
INIT_22 => X"2E3B26191C001C001C001C001C001C00000000003C003C003C003C003C003C00",
INIT_23 => X"3C003C003C003C003C000000000000002E3B26192E3B26192E3B261926192619",
INIT_24 => X"2E3B261926192E3B261900001C0000001C001C003C003C003C003C003C003C00",
INIT_25 => X"3C003C003C003C003C003C00000000000000000026192E3B2619261926192619",
INIT_26 => X"2E3B2619261926192619261926192619000000001C001C003C003C003C003C00",
INIT_27 => X"3C003C003C003C003C003C003C003C0000001330133000002E3B26192E3B2619",
INIT_28 => X"2E3B26192E3B261926192619261926192E3B26192619261900001C0000003C00",
INIT_29 => X"00003C003C003C003C003C003C003C003C000000133013301330000000002619",
INIT_2A => X"00002E3B26192619261926192E3B26192E3B2619261926192E3B2E3B00001C00",
INIT_2B => X"261900001C0000003C003C003C003C003C003C003C0000001330133013301330",
INIT_2C => X"13301330000026192E3B26192E3B261926192619261926192E3B261926192619",
INIT_2D => X"26192619261900001C0000003C003C003C003C003C003C000000133013301330",
INIT_2E => X"13301330133013301330000000002619261926192E3B26192E3B26192E3B2619",
INIT_2F => X"261926192E3B26192E3B26191C001C0000003C003C003C003C00000013301330",
INIT_30 => X"133013301330133013301330133013300000000026192E3B26192E3B26192619",
INIT_31 => X"2E3B26192E3B26192619261926192E3B1C001C0000003C003C003C0000001330",
INIT_32 => X"133013301330133013301330133013301330133013300000000026192E3B2619",
INIT_33 => X"000026192E3B26192E3B26192619261926192E3B00001C001C00000000000000",
INIT_34 => X"0000133013301330133013301330133013301330133013301330133000000000",
INIT_35 => X"133013300000000000002619261926192E3B26192E3B26190000000000000000",
INIT_36 => X"0000133013301330133013301330133013301330133013301330133013301330",
INIT_37 => X"1330133013301330133013300000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000001330133013301330",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => addra(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => dina(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_1\,
DOADO(13 downto 8) => douta(11 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\,
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end ball_small_blk_mem_gen_prim_width;
architecture STRUCTURE of ball_small_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.ball_small_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end ball_small_blk_mem_gen_generic_cstr;
architecture STRUCTURE of ball_small_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.ball_small_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_top : entity is "blk_mem_gen_top";
end ball_small_blk_mem_gen_top;
architecture STRUCTURE of ball_small_blk_mem_gen_top is
begin
\valid.cstr\: entity work.ball_small_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end ball_small_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of ball_small_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.ball_small_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of ball_small_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of ball_small_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of ball_small_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of ball_small_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of ball_small_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 1.43485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of ball_small_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of ball_small_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of ball_small_blk_mem_gen_v8_3_5 : entity is "ball_small.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of ball_small_blk_mem_gen_v8_3_5 : entity is "ball_small.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of ball_small_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of ball_small_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of ball_small_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of ball_small_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of ball_small_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 900;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of ball_small_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of ball_small_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of ball_small_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of ball_small_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ball_small_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_small_blk_mem_gen_v8_3_5 : entity is "yes";
end ball_small_blk_mem_gen_v8_3_5;
architecture STRUCTURE of ball_small_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.ball_small_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ball_small is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ball_small : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ball_small : entity is "ball_small,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ball_small : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ball_small : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end ball_small;
architecture STRUCTURE of ball_small is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 1.43485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "ball_small.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "ball_small.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 900;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 900;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 900;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 900;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.ball_small_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- lmouton@enserg.fr
-- oschneid@enserg.fr
-- shangoue@enserg.fr
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : miniMIPS processor --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2004 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pack_mips.all;
entity minimips is
port (
clock : in std_logic;
reset : in std_logic;
-- Ram connexion
ram_req : out std_logic;
ram_adr : out bus32;
ram_r_w : out std_logic;
ram_data : inout bus32;
ram_ack : in std_logic;
-- Hardware interruption
it_mat : in std_logic
);
end minimips;
architecture rtl of minimips is
-- General signals
signal stop_all : std_logic; -- Lock the pipeline evolution
signal it_mat_clk : std_logic; -- Synchronised hardware interruption
-- interface PF - EI
signal PF_pc : bus32; -- PC value
-- interface Controler - EI
signal CTE_instr : bus32; -- Instruction from the memory
signal ETC_adr : bus32; -- Address to read in memory
-- interface EI - DI
signal EI_instr : bus32; -- Read interface
signal EI_adr : bus32; -- Address from the read instruction
signal EI_it_ok : std_logic; -- Allow hardware interruptions
-- Asynchronous connexion with the bypass unit
signal adr_reg1 : adr_reg_type; -- Operand 1 address
signal adr_reg2 : adr_reg_type; -- Operand 2 address
signal use1 : std_logic; -- Operand 1 utilisation
signal use2 : std_logic; -- Operand 2 utilisation
signal data1 : bus32; -- First register value
signal data2 : bus32; -- Second register value
signal alea : std_logic; -- Unresolved hazards detected
-- interface DI - EX
signal DI_bra : std_logic; -- Branch decoded
signal DI_link : std_logic; -- A link for that instruction
signal DI_op1 : bus32; -- operand 1 for alu
signal DI_op2 : bus32; -- operand 2 for alu
signal DI_code_ual : alu_ctrl_type; -- Alu operation
signal DI_offset : bus32; -- Offset for the address calculation
signal DI_adr_reg_dest : adr_reg_type; -- Address of the destination register of the result
signal DI_ecr_reg : std_logic; -- Effective writing of the result
signal DI_mode : std_logic; -- Address mode (relative to pc or indexed to a register)
signal DI_op_mem : std_logic; -- Memory operation request
signal DI_r_w : std_logic; -- Type of memory operation (reading or writing)
signal DI_adr : bus32; -- Address of the decoded instruction
signal DI_exc_cause : bus32; -- Potential exception detected
signal DI_level : level_type; -- Availability of the result for the data bypass
signal DI_it_ok : std_logic; -- Allow hardware interruptions
-- interface EX - MEM
signal EX_adr : bus32; -- Instruction address
signal EX_bra_confirm : std_logic; -- Branch execution confirmation
signal EX_data_ual : bus32; -- Ual result
signal EX_adresse : bus32; -- Address calculation result
signal EX_adr_reg_dest : adr_reg_type; -- Destination register for the result
signal EX_ecr_reg : std_logic; -- Effective writing of the result
signal EX_op_mem : std_logic; -- Memory operation needed
signal EX_r_w : std_logic; -- Type of memory operation (read or write)
signal EX_exc_cause : bus32; -- Potential cause exception
signal EX_level : level_type; -- Availability stage of result for bypassing
signal EX_it_ok : std_logic; -- Allow hardware interruptions
-- interface Controler - MEM
signal MTC_data : bus32; -- Data to write in memory
signal MTC_adr : bus32; -- Address for memory
signal MTC_r_w : std_logic; -- Read/Write in memory
signal MTC_req : std_logic; -- Request access to memory
signal CTM_data : bus32; -- Data from memory
-- interface MEM - REG
signal MEM_adr : bus32; -- Instruction address
signal MEM_adr_reg_dest : adr_reg_type; -- Destination register address
signal MEM_ecr_reg : std_logic; -- Writing of the destination register
signal MEM_data_ecr : bus32; -- Data to write (from alu or memory)
signal MEM_exc_cause : bus32; -- Potential exception cause
signal MEM_level : level_type; -- Availability stage for the result for bypassing
signal MEM_it_ok : std_logic; -- Allow hardware interruptions
-- connexion to the register banks
-- Writing commands in the register banks
signal write_data : bus32; -- Data to write
signal write_adr : bus5; -- Address of the register to write
signal write_GPR : std_logic; -- Selection in the internal registers
signal write_SCP : std_logic; -- Selection in the coprocessor system registers
-- Reading commands for Reading in the registers
signal read_adr1 : bus5; -- Address of the first register to read
signal read_adr2 : bus5; -- Address of the second register to read
signal read_data1_GPR : bus32; -- Value of operand 1 from the internal registers
signal read_data1_SCP : bus32; -- Value of operand 2 from the internal registers
signal read_data2_GPR : bus32; -- Value of operand 1 from the coprocessor system registers
signal read_data2_SCP : bus32; -- Value of operand 2 from the coprocessor system registers
-- Interruption controls
signal interrupt : std_logic; -- Interruption to take into account
signal vecteur_it : bus32; -- Interruption vector
-- Connexion with predict
signal PR_bra_cmd : std_logic; -- Defined a branch
signal PR_bra_bad : std_logic; -- Defined a branch to restore from a bad prediction
signal PR_bra_adr : std_logic_vector(31 downto 0); -- New PC
signal PR_clear : std_logic; -- Clear the three pipeline stage : EI, DI, EX
-- Clear asserted when interrupt or PR_clear are asserted
signal clear : std_logic;
begin
clear <= interrupt or PR_clear;
-- Take into account the hardware interruption on rising edge
process (clock)
begin
if clock='1' and clock'event then
it_mat_clk <= it_mat;
end if;
end process;
U1_pf : pps_pf port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of the pipeline stage
-- entrees asynchrones
bra_adr => PR_bra_adr, -- Branch
bra_cmd => PR_bra_cmd, -- Address to load when an effective branch
bra_cmd_pr => PR_bra_bad, -- Branch which have a priority on stop_pf (bad prediction branch)
exch_adr => vecteur_it, -- Exception branch
exch_cmd => interrupt, -- Exception vector
-- Lock the stage
stop_pf => alea,
-- Synchronous output to EI stage
PF_pc => PF_pc -- PC value
);
U2_ei : pps_ei port map (
clock => clock,
reset => reset,
clear => clear, -- Clear the pipeline stage
stop_all => stop_all, -- Evolution locking signal
-- Asynchronous inputs
stop_ei => alea, -- Lock the EI_adr and Ei_instr registers
-- interface Controler - EI
CTE_instr => CTE_instr, -- Instruction from the memory
ETC_adr => ETC_adr, -- Address to read in memory
-- Synchronous inputs from PF stage
PF_pc => PF_pc, -- Current value of the pc
-- Synchronous outputs to DI stage
EI_instr => EI_instr, -- Read interface
EI_adr => EI_adr, -- Address from the read instruction
EI_it_ok => EI_it_ok -- Allow hardware interruptions
);
U3_di : pps_di port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of the outputs
clear => clear, -- Clear the pipeline stage (nop in the outputs)
-- Asynchronous connexion with the register management and data bypass unit
adr_reg1 => adr_reg1, -- Address of the first register operand
adr_reg2 => adr_reg2, -- Address of the second register operand
use1 => use1, -- Effective use of operand 1
use2 => use2, -- Effective use of operand 2
stop_di => alea, -- Unresolved detected : send nop in the pipeline
data1 => data1, -- Operand register 1
data2 => data2, -- Operand register 2
-- Datas from EI stage
EI_adr => EI_adr, -- Address of the instruction
EI_instr => EI_instr, -- The instruction to decode
EI_it_ok => EI_it_ok, -- Allow hardware interruptions
-- Synchronous output to EX stage
DI_bra => DI_bra, -- Branch decoded
DI_link => DI_link, -- A link for that instruction
DI_op1 => DI_op1, -- operand 1 for alu
DI_op2 => DI_op2, -- operand 2 for alu
DI_code_ual => DI_code_ual, -- Alu operation
DI_offset => DI_offset, -- Offset for the address calculation
DI_adr_reg_dest => DI_adr_reg_dest, -- Address of the destination register of the result
DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
DI_mode => DI_mode, -- Address mode (relative to pc or indexed to a register)
DI_op_mem => DI_op_mem, -- Memory operation request
DI_r_w => DI_r_w, -- Type of memory operation (reading or writing)
DI_adr => DI_adr, -- Address of the decoded instruction
DI_exc_cause => DI_exc_cause, -- Potential exception detected
DI_level => DI_level, -- Availability of the result for the data bypass
DI_it_ok => DI_it_ok -- Allow hardware interruptions
);
U4_ex : pps_ex port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of outputs
clear => clear, -- Clear the pipeline stage
-- Datas from DI stage
DI_bra => DI_bra, -- Branch instruction
DI_link => DI_link, -- Branch with link
DI_op1 => DI_op1, -- Operand 1 for alu
DI_op2 => DI_op2, -- Operand 2 for alu
DI_code_ual => DI_code_ual, -- Alu operation
DI_offset => DI_offset, -- Offset for address calculation
DI_adr_reg_dest => DI_adr_reg_dest, -- Destination register address for the result
DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
DI_mode => DI_mode, -- Address mode (relative to pc ou index by a register)
DI_op_mem => DI_op_mem, -- Memory operation
DI_r_w => DI_r_w, -- Type of memory operation (read or write)
DI_adr => DI_adr, -- Instruction address
DI_exc_cause => DI_exc_cause, -- Potential cause exception
DI_level => DI_level, -- Availability stage of the result for bypassing
DI_it_ok => DI_it_ok, -- Allow hardware interruptions
-- Synchronous outputs to MEM stage
EX_adr => EX_adr, -- Instruction address
EX_bra_confirm => EX_bra_confirm, -- Branch execution confirmation
EX_data_ual => EX_data_ual, -- Ual result
EX_adresse => EX_adresse, -- Address calculation result
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register for the result
EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
EX_op_mem => EX_op_mem, -- Memory operation needed
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
EX_exc_cause => EX_exc_cause, -- Potential cause exception
EX_level => EX_level, -- Availability stage of result for bypassing
EX_it_ok => EX_it_ok -- Allow hardware interruptions
);
U5_mem : pps_mem port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of the outputs
clear => interrupt, -- Clear the pipeline stage
-- Interface with the control bus
MTC_data => MTC_data, -- Data to write in memory
MTC_adr => MTC_adr, -- Address for memory
MTC_r_w => MTC_r_w, -- Read/Write in memory
MTC_req => MTC_req, -- Request access to memory
CTM_data => CTM_data, -- Data from memory
-- Datas from Execution stage
EX_adr => EX_adr, -- Instruction address
EX_data_ual => EX_data_ual, -- Result of alu operation
EX_adresse => EX_adresse, -- Result of the calculation of the address
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register address for the result
EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
EX_op_mem => EX_op_mem, -- Memory operation needed
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
EX_exc_cause => EX_exc_cause, -- Potential exception cause
EX_level => EX_level, -- Availability stage for the result for bypassing
EX_it_ok => EX_it_ok, -- Allow hardware interruptions
-- Synchronous outputs for bypass unit
MEM_adr => MEM_adr, -- Instruction address
MEM_adr_reg_dest=>MEM_adr_reg_dest, -- Destination register address
MEM_ecr_reg => MEM_ecr_reg, -- Writing of the destination register
MEM_data_ecr => MEM_data_ecr, -- Data to write (from alu or memory)
MEM_exc_cause => MEM_exc_cause, -- Potential exception cause
MEM_level => MEM_level, -- Availability stage for the result for bypassing
MEM_it_ok => MEM_it_ok -- Allow hardware interruptions
);
U6_renvoi : renvoi port map (
-- Register access signals
adr1 => adr_reg1, -- Operand 1 address
adr2 => adr_reg2, -- Operand 2 address
use1 => use1, -- Operand 1 utilisation
use2 => use2, -- Operand 2 utilisation
data1 => data1, -- First register value
data2 => data2, -- Second register value
alea => alea, -- Unresolved hazards detected
-- Bypass signals of the intermediary datas
DI_level => DI_level, -- Availability level of the data
DI_adr => DI_adr_reg_dest, -- Register destination of the result
DI_ecr => DI_ecr_reg, -- Writing register request
DI_data => DI_op2, -- Data to used
EX_level => EX_level, -- Availability level of the data
EX_adr => EX_adr_reg_dest, -- Register destination of the result
EX_ecr => EX_ecr_reg, -- Writing register request
EX_data => EX_data_ual, -- Data to used
MEM_level => MEM_level, -- Availability level of the data
MEM_adr => MEM_adr_reg_dest, -- Register destination of the result
MEM_ecr => MEM_ecr_reg, -- Writing register request
MEM_data => MEM_data_ecr, -- Data to used
interrupt => interrupt, -- Exceptions or interruptions
-- Connexion to the differents bank of register
-- Writing commands for writing in the registers
write_data => write_data, -- Data to write
write_adr => write_adr, -- Address of the register to write
write_GPR => write_GPR, -- Selection in the internal registers
write_SCP => write_SCP, -- Selection in the coprocessor system registers
-- Reading commands for Reading in the registers
read_adr1 => read_adr1, -- Address of the first register to read
read_adr2 => read_adr2, -- Address of the second register to read
read_data1_GPR => read_data1_GPR, -- Value of operand 1 from the internal registers
read_data1_SCP => read_data1_SCP, -- Value of operand 2 from the internal registers
read_data2_GPR => read_data2_GPR, -- Value of operand 1 from the coprocessor system registers
read_data2_SCP => read_data2_SCP -- Value of operand 2 from the coprocessor system registers
);
U7_banc : banc port map(
clock => clock,
reset => reset,
-- Register addresses to read
reg_src1 => read_adr1,
reg_src2 => read_adr2,
-- Register address to write and its data
reg_dest => write_adr,
donnee => write_data,
-- Write signal
cmd_ecr => write_GPR,
-- Bank outputs
data_src1 => read_data1_GPR,
data_src2 => read_data2_GPR
);
U8_syscop : syscop port map (
clock => clock,
reset => reset,
-- Datas from the pipeline
MEM_adr => MEM_adr, -- Address of the current instruction in the pipeline end -> responsible of the exception
MEM_exc_cause => MEM_exc_cause, -- Potential cause exception of that instruction
MEM_it_ok => MEM_it_ok, -- Allow hardware interruptions
-- Hardware interruption
it_mat => it_mat_clk, -- Hardware interruption detected
-- Interruption controls
interrupt => interrupt, -- Interruption to take into account
vecteur_it => vecteur_it, -- Interruption vector
-- Writing request in register bank
write_data => write_data, -- Data to write
write_adr => write_adr, -- Address of the register to write
write_SCP => write_SCP, -- Writing request
-- Reading request in register bank
read_adr1 => read_adr1, -- Address of the first register
read_adr2 => read_adr2, -- Address of the second register
read_data1 => read_data1_SCP, -- Value of register 1
read_data2 => read_data2_SCP -- Value of register 2
);
U9_bus_ctrl : bus_ctrl port map (
clock => clock,
reset => reset,
-- Interruption in the pipeline
interrupt => interrupt,
-- Interface for the Instruction Extraction Stage
adr_from_ei => ETC_adr, -- The address of the data to read
instr_to_ei => CTE_instr, -- Instruction from the memory
-- Interface with the MEMory Stage
req_from_mem => MTC_req, -- Request to access the ram
r_w_from_mem => MTC_r_w, -- Read/Write request
adr_from_mem => MTC_adr, -- Address in ram
data_from_mem => MTC_data, -- Data to write in ram
data_to_mem => CTM_data, -- Data from the ram to the MEMory stage
-- RAM interface signals
req_to_ram => ram_req, -- Request to ram
adr_to_ram => ram_adr, -- Address of the data to read or write
r_w_to_ram => ram_r_w, -- Read/Write request
ack_from_ram => ram_ack, -- Acknowledge from the memory
data_inout_ram => ram_data, -- Data from/to the memory
-- Pipeline progress control signal
stop_all => stop_all
);
U10_predict : predict port map (
clock => clock,
reset => reset,
-- Datas from PF pipeline stage
PF_pc => PF_pc, -- PC of the current instruction extracted
-- Datas from DI pipeline stage
DI_bra => DI_bra, -- Branch detected
DI_adr => DI_adr, -- Address of the branch
-- Datas from EX pipeline stage
EX_bra_confirm => EX_bra_confirm, -- Confirm if the branch test is ok
EX_adr => EX_adr, -- Address of the branch
EX_adresse => EX_adresse, -- Result of the branch
EX_uncleared => EX_it_ok, -- Define if the EX stage is cleared
-- Outputs to PF pipeline stage
PR_bra_cmd => PR_bra_cmd, -- Defined a branch
PR_bra_bad => PR_bra_bad, -- Defined a branch to restore from a bad prediction
PR_bra_adr => PR_bra_adr, -- New PC
-- Clear the three pipeline stage : EI, DI, EX
PR_clear => PR_clear
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:24:44 10/08/2016
-- Design Name:
-- Module Name: Control_Unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Control_Unit is
port(
command : IN STD_LOGIC_VECTOR(7 downto 0); -- comamnd that comes from memory
alu_command_o : INOUT STD_LOGIC_VECTOR(7 downto 0); -- command that we will parse to ALU
ram_command_o : INOUT STD_LOGIC; -- command that we will parse to RAM
pc_command_o : INOUT STD_LOGIC_VECTOR (3 downto 0); -- command tat we will parse to Program_Counter
clk : IN STD_LOGIC
);
end Control_Unit;
architecture Behavioral of Control_Unit is
begin
CONTROL_PROCESS : process (clk)
begin
if clk = '1' and clk'event then
-- ALU commands
if command = "00000001" then
alu_command_o <= "00000001"; --addition of input signals
elsif command = "00000010" then
alu_command_o <= "00000010"; -- substraction of input signals
elsif command = "00000011" then
alu_command_o <= "00000011"; -- AND operation
elsif command = "00000100" then
alu_command_o <= "00000100"; -- OR operation
elsif command = "00000101" then
alu_command_o <= "00000101"; -- XOR operation
elsif command = "00000110" then
alu_command_o <= "00000110"; -- NOT operation
elsif command= "00000111" then
alu_command_o <= "00000111"; --shift right
elsif command = "00001000" then
alu_command_o<= "00001000"; --shift left
-- RAM commands
elsif command = "00001001" then
ram_command_o <= '1'; -- read from ram
elsif command = "00001010" then
ram_command_o <= '1'; -- write to ram
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2599.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02599ent IS
END c13s03b01x00p02n01i02599ent;
ARCHITECTURE c13s03b01x00p02n01i02599arch OF c13s03b01x00p02n01i02599ent IS
BEGIN
TESTING: PROCESS
variable k' : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02599 - Identifier can not end with '''."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02599arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2599.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02599ent IS
END c13s03b01x00p02n01i02599ent;
ARCHITECTURE c13s03b01x00p02n01i02599arch OF c13s03b01x00p02n01i02599ent IS
BEGIN
TESTING: PROCESS
variable k' : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02599 - Identifier can not end with '''."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02599arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2599.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02599ent IS
END c13s03b01x00p02n01i02599ent;
ARCHITECTURE c13s03b01x00p02n01i02599arch OF c13s03b01x00p02n01i02599ent IS
BEGIN
TESTING: PROCESS
variable k' : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02599 - Identifier can not end with '''."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02599arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:31 07/23/2015
-- Design Name:
-- Module Name: S6EthTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity S6EthTop is
generic (
NUM_IP_G : integer := 2;
GATE_DELAY_G : time := 1 ns
);
port (
-- Direct GT connections
gtTxP : out sl;
gtTxN : out sl;
gtRxP : in sl;
gtRxN : in sl;
gtClkP : in sl;
gtClkN : in sl;
-- Alternative clock input from fabric
fabClkIn : in sl := '0';
-- SFP transceiver disable pin
txDisable : out sl;
-- Clocks out from Ethernet core
ethUsrClk62 : out sl;
ethUsrClk125 : out sl;
-- Status and diagnostics out
ethSync : out sl;
ethReady : out sl;
led : out slv(15 downto 0);
-- Core settings in
macAddr : in MacAddrType := MAC_ADDR_DEFAULT_C;
ipAddrs : in IpAddrArray(NUM_IP_G-1 downto 0) := (others => IP_ADDR_DEFAULT_C);
udpPorts : in Word16Array(NUM_IP_G-1 downto 0) := (others => (others => '0'));
-- User clock inputs
userClk : in sl;
userRstIn : in sl;
userRstOut : out sl;
-- User data interfaces
userTxData : in Word32Array(NUM_IP_G-1 downto 0);
userTxDataValid : in slv(NUM_IP_G-1 downto 0);
userTxDataLast : in slv(NUM_IP_G-1 downto 0);
userTxDataReady : out slv(NUM_IP_G-1 downto 0);
userRxData : out Word32Array(NUM_IP_G-1 downto 0);
userRxDataValid : out slv(NUM_IP_G-1 downto 0);
userRxDataLast : out slv(NUM_IP_G-1 downto 0);
userRxDataReady : in slv(NUM_IP_G-1 downto 0)
);
end S6EthTop;
architecture Behavioral of S6EthTop is
signal fabClk : sl;
signal fabClkRst : sl;
signal gtClk : sl;
signal ethClk62 : sl;
signal ethClk62Rst : sl;
signal ethClk125 : sl;
signal ethClk125Rst : sl;
signal dcmClkValid : sl;
signal dcmSpLocked : sl;
signal usrClkValid : sl;
signal usrClkLocked : sl;
signal pllLock0 : sl;
signal gtpResetDone0 : sl;
signal gtpReset0 : sl;
signal gtpReset1 : sl;
signal txReset0 : sl;
signal txReset1 : sl;
signal rxReset0 : sl;
signal rxReset1 : sl;
signal rxBufReset0 : sl;
signal rxBufReset1 : sl;
signal rxBufStatus0 : slv(2 downto 0);
signal rxBufStatus1 : slv(2 downto 0);
signal txBufStatus0 : slv(1 downto 0);
signal txBufStatus1 : slv(1 downto 0);
signal rxBufError0 : sl;
signal rxBufError1 : sl;
signal rxByteAligned0 : sl;
signal rxByteAligned1 : sl;
signal rxEnMCommaAlign0 : sl;
signal rxEnMCommaAlign1 : sl;
signal rxEnPCommaAlign0 : sl;
signal rxEnPCommaAlign1 : sl;
signal ethRxLinkSync : sl;
signal ethAutoNegDone : sl;
signal phyRxLaneIn : EthRxPhyLaneInType;
signal phyTxLaneOut : EthTxPhyLaneOutType;
signal tpData : slv(31 downto 0);
signal tpDataValid : sl;
signal tpDataLast : sl;
signal tpDataReady : sl;
signal userRst : sl;
begin
txDisable <= '0';
ethSync <= ethRxLinkSync;
ethReady <= ethAutoNegDone;
ethUsrClk62 <= ethClk62;
ethUsrClk125 <= ethClk125;
userRstOut <= userRst;
led(0) <= dcmSpLocked;
led(1) <= dcmClkValid;
led(2) <= not(gtpReset0);
led(3) <= gtpResetDone0;
led(4) <= pllLock0;
led(5) <= usrClkLocked;
led(6) <= usrClkValid;
led(7) <= ethRxLinkSync;
led(8) <= ethAutoNegDone;
led(9) <= not(ethClk62Rst);
led(10) <= not(ethClk125Rst);
led(15 downto 11) <= (others => '1');
fabClk <= fabClkIn;
U_IBUFDS : IBUFDS port map ( I => gtClkP, IB => gtClkN, O => gtClk);
U_GtpS6 : entity work.GtpS6
generic map (
-- Reference clock selection --
-- 000: CLK00/CLK01 selected
-- 001: GCLK00/GCLK01 selected
-- 010: PLLCLK00/PLLCLK01 selected
-- 011: CLKINEAST0/CLKINEAST0 selected
-- 100: CLK10/CLK11 selected
-- 101: GCLK10/GCLK11 selected
-- 110: PLLCLK10/PLLCLK11 selected
-- 111: CLKINWEST0/CLKINWEST1 selected
REF_SEL_PLL0_G => "001",
REF_SEL_PLL1_G => "001"
)
port map (
-- Clocking & reset
gtpClkIn => fabClk,
gtpReset0 => gtpReset0,
gtpReset1 => gtpReset1,
txReset0 => txReset0,
txReset1 => txReset1,
rxReset0 => rxReset0,
rxReset1 => rxReset1,
rxBufReset0 => rxBufReset0,
rxBufReset1 => rxBufReset1,
-- User clock out
usrClkOut => ethClk62,
usrClkX2Out => ethClk125,
-- DCM clocking
dcmClkValid => dcmClkValid,
dcmSpLocked => dcmSpLocked,
usrClkValid => usrClkValid,
usrClkLocked => usrClkLocked,
-- General status outputs
pllLock0 => pllLock0,
pllLock1 => open,
gtpResetDone0 => gtpResetDone0,
gtpResetDone1 => open,
-- Input signals (raw)
gtpRxP0 => gtRxP,
gtpRxN0 => gtRxN,
gtpTxP0 => gtTxP,
gtpTxN0 => gtTxN,
gtpRxP1 => '0',
gtpRxN1 => '0',
gtpTxP1 => open,
gtpTxN1 => open,
-- Data interfaces
rxDataOut0 => phyRxLaneIn.data,
rxDataOut1 => open,
txDataIn0 => phyTxLaneOut.data,
txDataIn1 => (others => '0'),
-- RX status
rxCharIsComma0 => open,
rxCharIsComma1 => open,
rxCharIsK0 => phyRxLaneIn.dataK,
rxCharIsK1 => open,
rxDispErr0 => phyRxLaneIn.dispErr, -- out slv(1 downto 0);
rxDispErr1 => open, -- out slv(1 downto 0);
rxNotInTable0 => phyRxLaneIn.decErr, -- out slv(1 downto 0);
rxNotInTable1 => open, -- out slv(1 downto 0);
rxRunDisp0 => open, -- out slv(1 downto 0);
rxRunDisp1 => open, -- out slv(1 downto 0);
rxClkCor0 => open, -- out slv(2 downto 0);
rxClkCor1 => open, -- out slv(2 downto 0);
rxByteAligned0 => rxByteAligned0, -- out std_logic;
rxByteAligned1 => rxByteAligned1, -- out std_logic;
rxEnMCommaAlign0 => rxEnMCommaAlign0, -- in std_logic;
rxEnMCommaAlign1 => rxEnMCommaAlign1, -- in std_logic;
rxEnPCommaAlign0 => rxEnPCommaAlign0, -- in std_logic;
rxEnPCommaAlign1 => rxEnPCommaAlign1, -- in std_logic;
rxBufStatus0 => rxBufStatus0, -- out slv(2 downto 0);
rxBufStatus1 => rxBufStatus1, -- out slv(2 downto 0);
-- TX status
txCharDispMode0 => "00", -- in slv(1 downto 0) := "00";
txCharDispMode1 => "00", -- in slv(1 downto 0) := "00";
txCharDispVal0 => "00", -- in slv(1 downto 0) := "00";
txCharDispVal1 => "00", -- in slv(1 downto 0) := "00";
txCharIsK0 => phyTxLaneOut.dataK, -- in slv(1 downto 0);
txCharIsK1 => "00", -- in slv(1 downto 0);
txRunDisp0 => open, -- out slv(1 downto 0);
txRunDisp1 => open, -- out slv(1 downto 0);
txBufStatus0 => txBufStatus0, -- out slv(1 downto 0);
txBufStatus1 => txBufStatus1, -- out slv(1 downto 0);
-- Loopback settings
loopbackIn0 => "000", -- : in slv(2 downto 0) := "000";
loopbackIn1 => "000" -- : in slv(2 downto 0) := "000";
);
-- Simple comma alignment
rxEnMCommaAlign0 <= not(rxByteAligned0);
rxEnPCommaAlign0 <= not(rxByteAligned0);
rxEnMCommaAlign1 <= not(rxByteAligned1);
rxEnPCommaAlign1 <= not(rxByteAligned1);
-- Reset sequencing, as per UG386, Table 2-14
-- Not all resets are implemented, only those for the functionality
-- we care about.
--
-- 1. Perform GTP reset after turning on the reference clock
U_GtpReset0 : entity work.SyncBit
port map (
clk => fabClk,
rst => not(dcmClkValid),
asyncBit => '0',
syncBit => gtpReset0
);
gtpReset1 <= gtpReset0;
-- 2. Assert rxReset and txReset when usrClk, usrClk2 is not stable
-- 3. txReset should be asserted on tx Buffer over/underflow
U_RxReset0 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => not(usrClkValid) or not(dcmClkValid),
asyncBit => '0',
syncBit => rxReset0
);
rxReset1 <= rxReset0;
U_TxReset0 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => not(usrClkValid) or txBufStatus0(1),
asyncBit => '0',
syncBit => txReset0
);
U_TxReset1 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => not(usrClkValid) or txBufStatus1(1),
asyncBit => '0',
syncBit => txReset1
);
-- 4. rxBufReset should be asserted on rx buffer over/underflow
rxBufError0 <= '1' when rxBufStatus0 = "101" or rxBufStatus0 = "110" else '0';
U_RxBufReset0 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => rxBufError0,
asyncBit => '0',
syncBit => rxBufReset0
);
rxBufError1 <= '1' when rxBufStatus1 = "101" or rxBufStatus1 = "110" else '0';
U_RxBufReset1 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => rxBufError1,
asyncBit => '0',
syncBit => rxBufReset1
);
--------------------------------
-- Gigabit Ethernet Interface --
--------------------------------
U_Eth1000BaseXCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => NUM_IP_G,
MTU_SIZE_G => 1500,
LITTLE_ENDIAN_G => true,
EN_AUTONEG_G => true,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => macAddr,
ipAddrs => ipAddrs,
udpPorts => udpPorts,
-- Data to/from GT
phyRxData => phyRxLaneIn,
phyTxData => phyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => userClk,
userRst => userRst,
-- User data
userTxData => userTxData,
userTxDataValid => userTxDataValid,
userTxDataLast => userTxDataLast,
userTxDataReady => userTxDataReady,
userRxData => userRxData,
userRxDataValid => userRxDataValid,
userRxDataLast => userRxDataLast,
userRxDataReady => userRxDataReady
);
---------------------------------------------------------------------------
-- Resets
---------------------------------------------------------------------------
-- Generate stable reset signal
U_PwrUpRst : entity work.InitRst
generic map (
RST_CNT_G => 25000000,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => fabClk,
syncRst => fabClkRst
);
-- Synchronize the reset to the 125 MHz domain
U_RstSync125 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst,
syncBit => ethClk125Rst
);
-- Synchronize the reset to the 62 MHz domain
U_RstSync62 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => fabClkRst,
syncBit => ethClk62Rst
);
-- User reset
U_RstSyncUser : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst or not(ethAutoNegDone) or userRstIn,
syncBit => userRst
);
end Behavioral;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - Clock - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A clock manager which can be configures via the AXI
-- bus. Therefore it provides the following write only
-- registers:
-- Reg#i#: Clock 1 and 2 register of pll#i#
--
-- ======================================================================
<<reconos_preproc>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity reconos_clock_user_logic is
--
-- Generic definitions
--
-- C_NUM_CLOCKS - number of clocks
--
-- C_CLKIN_PERIOD - input clock period
--
-- C_CLK#i# - pll generics
--
generic (
C_NUM_CLOCKS : integer := 1;
C_CLKIN_PERIOD : real := 10.00;
<<generate for CLOCKS>>
C_CLK<<Id>>_CLKFBOUT_MULT : integer := 16;
C_CLK<<Id>>_DIVCLK_DIVIDE : integer := 1;
C_CLK<<Id>>_CLKOUT_DIVIDE : integer := 16<<c;>>
<<end generate>>
);
--
-- Port defintions
--
-- CLK_Ref - reference clock
--
-- CLK#i#_ - clock outputs
--
-- BUS2IP_/IP2BUS_ - axi ipif signals
--
port (
CLK_Ref : in std_logic;
<<generate for CLOCKS>>
CLK<<Id>>_Out : out std_logic;
CLK<<Id>>_Locked : out std_logic;
<<end generate>>
BUS2IP_Clk : in std_logic;
BUS2IP_Resetn : in std_logic;
BUS2IP_Data : in std_logic_vector(31 downto 0);
BUS2IP_CS : in std_logic_vector(C_NUM_CLOCKS - 1 downto 0);
BUS2IP_RdCE : in std_logic_vector(C_NUM_CLOCKS - 1 downto 0);
BUS2IP_WrCE : in std_logic_vector(C_NUM_CLOCKS - 1 downto 0);
IP2BUS_Data : out std_logic_vector(31 downto 0);
IP2BUS_RdAck : out std_logic;
IP2BUS_WrAck : out std_logic;
IP2BUS_Error : out std_logic
);
end entity reconos_clock_user_logic;
architecture imp of reconos_clock_user_logic is
--
-- Internal state machine
--
-- state_type - vhdl type of the states
-- state - instatntiation of the state
--
type state_type is (STATE_WAIT,STATE_RESET,STATE_ACK,
STATE_READ0,STATE_READRDY0,STATE_WRITE0,STATE_WRITERDY0,
STATE_READ1,STATE_READRDY1,STATE_WRITE1,STATE_WRITERDY1);
signal state : state_type := STATE_WAIT;
--
-- Internal signals
--
-- req - indication of write request
-- pll_ - pll drp multiplexed signals
-- pll#i#_ - pll drp signal
--
-- pll#i#_clk, pll#i#_clkbuf - pll clock (buffered) output
--
signal req : std_logic;
signal pll_daddr : std_logic_vector(7 downto 0);
signal pll_di, pll_do : std_logic_vector(15 downto 0);
signal pll_den, pll_dwe : std_logic;
signal pll_drdy, pll_rst : std_logic;
<<generate for CLOCKS>>
signal pll<<Id>>_daddr : std_logic_vector(7 downto 0);
signal pll<<Id>>_di, pll<<Id>>_do : std_logic_vector(15 downto 0);
signal pll<<Id>>_den, pll<<Id>>_dwe : std_logic;
signal pll<<Id>>_drdy, pll<<Id>>_rst : std_logic;
signal pll<<Id>>_locked : std_logic;
signal pll<<Id>>_clk, pll<<Id>>_clkfb, pll<<Id>>_clkbuf : std_logic;
<<end generate>>
begin
-- == Instantiation of pll primitives =================================
<<generate for CLOCKS>>
pll<<Id>> : PLLE2_ADV
generic map (
CLKIN1_PERIOD => C_CLKIN_PERIOD,
CLKFBOUT_MULT => C_CLK<<Id>>_CLKFBOUT_MULT,
DIVCLK_DIVIDE => C_CLK<<Id>>_DIVCLK_DIVIDE,
CLKOUT0_DIVIDE => C_CLK<<Id>>_CLKOUT_DIVIDE
)
port map (
CLKIN1 => CLK_Ref,
CLKIN2 => '0',
CLKINSEL => '1',
CLKFBOUT => pll<<Id>>_clkfb,
CLKFBIN => pll<<Id>>_clkfb,
CLKOUT0 => pll<<Id>>_clk,
DCLK => BUS2IP_Clk,
DADDR => pll<<Id>>_daddr(6 downto 0),
DO => pll<<Id>>_do,
DI => pll<<Id>>_di,
DEN => pll<<Id>>_den,
DWE => pll<<Id>>_dwe,
DRDY => pll<<Id>>_drdy,
PWRDWN => '0',
LOCKED => pll<<Id>>_locked,
RST => pll<<Id>>_rst
);
bufg_pll<<Id>> : BUFGCE
port map (
I => pll<<Id>>_clk,
O => pll<<Id>>_clkbuf,
CE => pll<<Id>>_locked
);
<<end generate>>
-- == Process definitions =============================================
--
-- Implements the access logic via the drp port
--
clk_mg : process(BUS2IP_Clk,BUS2IP_Resetn) is
begin
if BUS2IP_Resetn = '0' then
state <= STATE_WAIT;
elsif rising_edge(BUS2IP_Clk) then
case state is
when STATE_WAIT =>
if req = '1' then
state <= STATE_RESET;
end if;
when STATE_RESET =>
state <= STATE_READ0;
when STATE_READ0 =>
state <= STATE_READRDY0;
when STATE_READRDY0 =>
if pll_drdy = '1' then
state <= STATE_WRITE0;
end if;
when STATE_WRITE0 =>
state <= STATE_WRITERDY0;
when STATE_WRITERDY0 =>
if pll_drdy = '1' then
state <= STATE_READ1;
end if;
when STATE_READ1 =>
state <= STATE_READRDY1;
when STATE_READRDY1 =>
if pll_drdy = '1' then
state <= STATE_WRITE1;
end if;
when STATE_WRITE1 =>
state <= STATE_WRITERDY1;
when STATE_WRITERDY1 =>
if pll_drdy = '1' then
state <= STATE_ACK;
end if;
when STATE_ACK =>
state <= STATE_WAIT;
when others =>
end case;
end if;
end process clk_mg;
req <=
<<generate for CLOCKS>>
BUS2IP_CS(<<_i>>) or
<<end generate>>
'0';
pll_daddr <=
x"08" when state = STATE_READ0 else
x"08" when state = STATE_READRDY0 else
x"08" when state = STATE_WRITE0 else
x"08" when state = STATE_WRITERDY0 else
x"09" when state = STATE_READ1 else
x"09" when state = STATE_READRDY1 else
x"09" when state = STATE_WRITE1 else
x"09" when state = STATE_WRITERDY1 else
x"00";
pll_den <=
'1' when state = STATE_READ0 else
'1' when state = STATE_WRITE0 else
'1' when state = STATE_READ1 else
'1' when state = STATE_WRITE1 else
'0';
pll_dwe <=
'1' when state = STATE_WRITE0 else
'1' when state = STATE_WRITERDY0 else
'1' when state = STATE_WRITE1 else
'1' when state = STATE_WRITERDY1 else
'0';
pll_rst <=
'0' when state = STATE_WAIT else
'1';
pll_di <=
BUS2IP_Data(15 downto 13) & pll_do(12) & BUS2IP_Data(11 downto 0) when state = STATE_WRITE0 else
BUS2IP_Data(15 downto 13) & pll_do(12) & BUS2IP_Data(11 downto 0) when state = STATE_WRITERDY0 else
pll_do(15 downto 8) & BUS2IP_Data(23 downto 16) when state = STATE_WRITE1 else
pll_do(15 downto 8) & BUS2IP_Data(23 downto 16) when state = STATE_WRITERDY1 else
(others => '0');
<<generate for CLOCKS>>
pll<<Id>>_rst <= pll_rst when BUS2IP_CS(C_NUM_CLOCKS - <<_i>> - 1) = '1' else '0';
pll<<Id>>_daddr <= pll_daddr;
pll<<Id>>_den <= pll_den when BUS2IP_CS(C_NUM_CLOCKS - <<_i>> - 1) = '1' else '0';
pll<<Id>>_dwe <= pll_dwe when BUS2IP_CS(C_NUM_CLOCKS - <<_i>> - 1) = '1' else '0';
pll<<Id>>_di <= pll_di;
<<end generate>>
pll_drdy <=
<<generate for CLOCKS>>
(pll<<Id>>_drdy and BUS2IP_CS(C_NUM_CLOCKS - <<_i>> - 1)) or
<<end generate>>
'0';
pll_do <=
<<generate for CLOCKS>>
(pll<<Id>>_do and (pll<<Id>>_do'Range => BUS2IP_CS(C_NUM_CLOCKS - <<_i>> - 1))) or
<<end generate>>
(15 downto 0 => '0');
-- == Assignment of ouput ports =======================================
<<generate for CLOCKS>>
CLK<<Id>>_Out <= pll<<Id>>_clkbuf;
CLK<<Id>>_Locked <= pll<<Id>>_locked;
<<end generate>>
IP2BUS_Data <= (others => '0');
IP2BUS_RdAck <= '0';
IP2BUS_WrAck <= '1' when state = STATE_ACK else '0';
IP2BUS_Error <= '0';
end architecture imp; |
-- whole_design.vhd
--
-- Created on: 21 May 2017
-- Author: Fabian Meyer
--
-- Integrates LCD display to show a custom text.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity whole_design is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
led: out std_logic; -- led, high active
en: out std_logic; -- enable, high active
rw: out std_logic;
rs: out std_logic;
bl: out std_logic; -- backlight, high active
data: inout std_logic_vector(3 downto 0)); -- data, dual direction
end whole_design;
architecture behavioral of whole_design is
-- import lcd component
component lcd
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic;
clk: in std_logic;
din: in std_logic_vector(7 downto 0);
posx: in std_logic_vector(3 downto 0);
posy: in std_logic;
flush: in std_logic;
rdy: out std_logic;
en: out std_logic;
rw: out std_logic;
rs: out std_logic;
bl: out std_logic;
data: inout std_logic_vector(3 downto 0));
end component;
-- counter defines which character is printed and at which position
signal cnt: std_logic_vector(4 downto 0) := (others => '0');
signal din: std_logic_vector(7 downto 0) := (others => '0');
signal posx: std_logic_vector(3 downto 0) := (others => '0');
signal posy: std_logic := '0';
signal flush: std_logic := '0';
signal rdy: std_logic := '0';
begin
mylcd: lcd
port map (rst => rst,
clk => clk,
din => din,
posx => posx,
posy => posy,
flush => flush,
rdy => rdy,
en => en,
rw => rw,
rs => rs,
bl => bl,
data => data);
led <= rst;
-- lower bits of cnt define x position of character to write
posx <= cnt(3 downto 0);
-- carry bit of cnt defines line
posy <= cnt(4);
-- map current cnt to a ASCII character
with conv_integer(cnt) select din <=
X"48" when 0, -- 'H'
X"65" when 1, -- 'e'
X"6c" when 2, -- 'l'
X"6c" when 3, -- 'l'
X"6f" when 4, -- 'o'
X"20" when 5, -- ' '
X"57" when 6, -- 'W'
X"6f" when 7, -- 'o'
X"72" when 8, -- 'r'
X"6c" when 9, -- 'l'
X"64" when 10, -- 'd'
X"21" when 11, -- '!'
X"46" when 16, -- 'F'
X"6f" when 17, -- 'o'
X"6f" when 18, -- 'o'
X"62" when 19, -- 'b'
X"61" when 20, -- 'a'
X"72" when 21, -- 'r'
X"20" when others;
process(rst, clk)
begin
if rst = RSTDEF then
cnt <= (others => '0');
flush <= '0';
elsif rising_edge(clk) then
-- disable flush every cycle
-- flush will always only stay enabled for one cycle
flush <= '0';
if rdy = '1' and flush = '0' then
-- increment counter whenever LCD is ready again
cnt <= cnt + 1;
-- flush input
flush <= '1';
end if;
end if;
end process;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc780.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p11n01i00780ent IS
port ( S : buffer bit );
END c01s01b01x02p11n01i00780ent;
ARCHITECTURE c01s01b01x02p11n01i00780arch OF c01s01b01x02p11n01i00780ent IS
BEGIN
TEST : PROCESS
BEGIN
S <= bit'('1');
wait for 15 ns;
END PROCESS TEST;
TESTING: PROCESS
BEGIN
S <= bit'('0'); -- Failure_here
-- signal S of mode buffer is being
-- driven by two sources one in each
-- process. Signal S can be driven by
-- only one source.
-- This error will be indicated at elaboration time
wait for 11 ns;
assert FALSE
report "***FAILED TEST: c01s01b01x02p11n01i00780 - A buffer port can have at most one source."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p11n01i00780arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc780.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p11n01i00780ent IS
port ( S : buffer bit );
END c01s01b01x02p11n01i00780ent;
ARCHITECTURE c01s01b01x02p11n01i00780arch OF c01s01b01x02p11n01i00780ent IS
BEGIN
TEST : PROCESS
BEGIN
S <= bit'('1');
wait for 15 ns;
END PROCESS TEST;
TESTING: PROCESS
BEGIN
S <= bit'('0'); -- Failure_here
-- signal S of mode buffer is being
-- driven by two sources one in each
-- process. Signal S can be driven by
-- only one source.
-- This error will be indicated at elaboration time
wait for 11 ns;
assert FALSE
report "***FAILED TEST: c01s01b01x02p11n01i00780 - A buffer port can have at most one source."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p11n01i00780arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc780.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p11n01i00780ent IS
port ( S : buffer bit );
END c01s01b01x02p11n01i00780ent;
ARCHITECTURE c01s01b01x02p11n01i00780arch OF c01s01b01x02p11n01i00780ent IS
BEGIN
TEST : PROCESS
BEGIN
S <= bit'('1');
wait for 15 ns;
END PROCESS TEST;
TESTING: PROCESS
BEGIN
S <= bit'('0'); -- Failure_here
-- signal S of mode buffer is being
-- driven by two sources one in each
-- process. Signal S can be driven by
-- only one source.
-- This error will be indicated at elaboration time
wait for 11 ns;
assert FALSE
report "***FAILED TEST: c01s01b01x02p11n01i00780 - A buffer port can have at most one source."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p11n01i00780arch;
|
-- Create Date: 17:41:55 05/14/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity binToBCD is
Port ( binary : in STD_LOGIC_VECTOR (7 downto 0);
bcd : out STD_LOGIC_VECTOR (9 downto 0)
);
end binToBCD;
architecture Behavioral of binToBCD is
begin
process(binary)
variable var : STD_LOGIC_VECTOR (17 downto 0);
begin
var := "000000000000000000";
var(10 downto 3) := binary;
for i in 0 to 4 loop
if var(11 downto 8) > 4 then
var(11 downto 8) := var(11 downto 8) + 3;
end if;
if var(15 downto 12) > 4 then
var(15 downto 12) := var(15 downto 12) + 3;
end if;
var(17 downto 1) := var(16 downto 0);
end loop;
bcd <= var(17 downto 8);
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
package crash_pkg is
function reorder_vector(inp : std_logic_vector) return std_logic_vector;
end package crash_pkg;
package body crash_pkg is
function reorder_vector(inp : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(inp'reverse_range);
begin
return inp;
if inp'left < inp'right then
for i in inp'range loop
ret(inp'right - i) := inp(i);
end loop;
elsif inp'left > inp'right then
for i in inp'range loop
ret(inp'left - i) := inp(i);
end loop;
else
ret(inp'left) := inp(inp'left);
end if;
return ret;
end function;
end package body crash_pkg;
|
library verilog;
use verilog.vl_types.all;
entity View_vlg_sample_tst is
port(
Clock : in vl_logic;
DIN : in vl_logic_vector(15 downto 0);
Resetn : in vl_logic;
Run : in vl_logic;
sampler_tx : out vl_logic
);
end View_vlg_sample_tst;
|
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.commons.all;
entity cpu is port (
clk,reset: in std_logic; -- 时钟、重置
en,rw: out std_logic; -- 内存开关
aBus: out address; -- 地址总线
dBus: inout word; -- 数据总线
step: in std_logic; -- 单步执行
pause: in std_logic; -- 暂停
-- 以下为仿真时可视化
pcX: out address;
accX: out word;
tickX: out hword;
iRegX: out word;
dRegX: out word
);
end cpu;
architecture cpuArch of cpu is
type state_type is ( -- CPU状态类型
halt, -- 停机
resetState, -- 重置
pauseState, -- 暂停
fetch, -- 获取指令
loadD, loadA, -- 载入Acc
storeA, -- 存储内存
jmp, jz, jp, jn, -- 跳转、条件跳转
addD, addA, -- 加法
andD, andA, -- 取并
notAcc -- 取反
);
signal state: state_type := halt; -- CPU状态
signal tick: hword := x"0"; -- CPU时刻
signal pc: address; -- 程序计数器
signal iReg: word; -- 操作符
signal dReg: word; -- 操作数（数据、地址）
signal acc: word; -- 累加器
signal alu: word; -- 运算器
begin
pcX<=pc;
accX<=acc;
tickX<=tick;
iRegX<=iReg;
dRegX<=dReg;
-- 以上为仿真时可视化
alu <= not acc when state = notAcc else -- 取反
acc + dReg when state = addD else -- 加立即数
acc + dBus when state = addA else -- 加内存数
acc and dReg when state = andD else -- 并立即数
acc and dBus when state= andA else -- 并内存数
(alu'range => '0'); -- 其他状态置零
process (clk)
constant clkCnm : integer := 100000; -- 按键消抖时钟计数最大值
variable clkCnt : integer range 0 to clkCnm; -- 按键消抖时钟计数
function decode(instr: word) return state_type is -- 操作符解码
begin
case instr is
when x"00" => return halt; -- 停机
when x"10" => return loadD; -- 载入立即数
when x"11" => return loadA; -- 载入内存数
when x"21" => return storeA; -- 存储Acc
when x"30" => return jmp; -- 无条件跳转
when x"31" => return jz; -- Acc=0跳转
when x"32" => return jp; -- Acc>0跳转
when x"33" => return jn; -- Acc<0跳转
when x"40" => return addD; -- 加立即数
when x"41" => return addA; -- 加内存数
when x"50" => return andD; -- 并立即数
when x"51" => return andA; -- 并内存数
when x"A0" => return notAcc; -- 取反
when others => return halt; -- 停机
end case;
end function decode;
procedure wrapup is -- 指令结束通用操作
begin
if step = '1' then -- 单步执行信号
state <= pauseState; -- 进入暂停状态
else
state <= fetch; -- 取下一指令
tick <= x"0"; -- 时刻置零
end if;
end procedure wrapup;
begin
if rising_edge(clk) then
if reset = '1' then -- 重置
state <= resetState; -- 重置状态
tick <= x"0"; -- 时刻置零
pc <= (others => '0'); -- PC置零
iReg <= (others => '0'); -- 操作符置零
dReg <= (others => '0'); -- 操作数置零
acc <= (others => '0'); -- Acc置零
en <= '0'; -- 内存关闭
rw <= '1'; -- 读状态
aBus <= (others => 'Z'); -- 地址总线高阻态
dBus <= (others => 'Z'); -- 数据总线高阻态
elsif state /= halt then -- 状态非停机
tick <= tick + 1; -- 时刻加一
case state is
when resetState => -- 重置状态
wrapup; -- 直接进入下一指令
when pauseState => -- 暂停状态
if step='0' then -- 单步执行关闭
state <= fetch; -- 进入获取状态
tick <= x"0"; -- 时刻置零
elsif pause = '0' then -- 单步执行开启且继续按键按下
if clkCnt=clkCnm then -- 按键按下时间计数
clkCnt:=clkCnt;
else
clkCnt:=clkCnt+1;
end if;
if clkCnt=clkCnm-1 then -- 按键消抖结束
state <= fetch; -- 进入获取状态
tick <= x"0"; -- 时刻置零
end if;
else
clkCnt:=0; -- 按键消抖统计置零
end if;
when fetch => -- 获取指令状态
case tick is
when x"0" =>
en <= '1'; -- 内存开启
aBus <= pc; -- 操作符地址送入地址总线
when x"1" =>
iReg <= dBus; -- 数据总线送入操作符
when x"2" =>
pc <= pc + 1; -- 程序计数器加一
when x"3" =>
en<='1'; -- 内存开启
aBus<=pc; -- 操作数地址送入地址总线
when x"4" =>
dReg<=dBus; -- 数据总线送入操作数
when x"5" =>
en<='0'; -- 内存关闭
aBus<=(others => 'Z'); -- 地址总线高阻态
when others =>
pc <= pc + 1; -- 程序计数器加一
state <= decode(iReg); -- 操作符解码
tick <= x"0"; -- 时刻置零
end case;
-- jump
when jmp => -- 无条件跳转
pc <= dReg; -- 操作数送入PC
wrapup; -- 下一指令
when jz => -- Acc=0跳转
if acc = x"00" then -- Acc=0
pc <= dReg; -- 操作数送入PC
end if;
wrapup; -- 下一指令
when jp => -- Acc>0跳转
if acc(7) = '0' and acc /= x"00" then -- 符号位零且Acc不等于零
pc <= dReg; -- 操作数送入PC
end if;
wrapup; -- 下一指令
when jn => -- Acc<0跳转
if acc(7) = '1' then -- 符号位为1
pc <= dReg; -- 操作数送入PC
end if;
wrapup; -- 下一指令
-- load
when loadD => -- 载入立即数
acc <= dReg; -- 操作数送入Acc
wrapup; -- 下一指令
when loadA => -- 载入内存数
case tick is
when x"0" =>
en <= '1'; -- 内存开启
aBus <= dReg; -- 数据地址送入地址总线
when x"1" =>
acc <= dBus; -- 地址总线送入Acc
when x"2" =>
en<='0'; -- 内存关闭
aBus<=(others => 'Z'); -- 地址总线高阻态
when others =>
wrapup; -- 下一指令
end case;
-- store
when storeA => -- 存储状态
case tick is
when x"0" =>
en <= '1'; -- 内存开启
rw <= '0'; -- 写状态
aBus <= dReg; -- 数据地址送入地址总线
dBus <= acc; -- Acc送入数据总线
when x"1" =>
en<='0'; -- 内存关闭
rw<='1'; -- 读状态
aBus <= (others => 'Z'); -- 地址总线高阻态
dBus <= (others => 'Z'); -- 数据总线高阻态
when others =>
wrapup; -- 下一指令
end case;
-- Math
when notAcc | addD | andD => -- 取反、加立即数、并立即数
acc <= alu; -- 运算器结果送入Acc
wrapup; -- 下一指令
when addA | andA => -- 加内存数、并内存数
case tick is
when x"0" =>
en <= '1'; -- 内存开启
aBus <= dReg; -- 数据地址送入地址总线
when x"1" =>
acc <= alu; -- 运算器结果送入Acc
when x"2" =>
en<='0'; -- 内存关闭
aBus<=(others => 'Z'); -- 地址总线高阻态
when others =>
wrapup; -- 下一指令
end case;
when others =>
state <= halt; -- 进入停机状态
end case;
else
tick <= x"F"; -- 停机状态tick置高
end if;
end if;
end process;
end cpuArch;
|
-------------------------------------------------------------------------------
--
-- File: ADI_SPI.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module manages the SPI communication with the Analog Devices 3 wire SPI
-- configuration interface
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.math_real.all;
use work.PkgZmodDigitizer.all;
entity ADI_SPI is
Generic
(
-- The sSPI_Clk signal is obtained by dividing SysClk100 to 2^kSysClkDiv.
kSysClkDiv : integer range 2 to 63 := 4;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 8 to 16 := 16
);
Port (
-- input clock (100MHZ).
SysClk100 : in STD_LOGIC;
-- active low synchronous reset signal.
asRst_n : in STD_LOGIC;
--AD92xx/AD96xx SPI interface signals.
sSPI_Clk : out STD_LOGIC;
sSDIO : inout STD_LOGIC;
sCS : out STD_LOGIC := '1';
--Upper layer Interface signals
--a pulse on this input initiates the transfers, also used to register upper layer interface inputs.
sApStart : in STD_LOGIC;
--SPI read data output.
sRdData : out std_logic_vector(kDataWidth - 1 downto 0);
--SPI command data.
sWrData : in std_logic_vector(kDataWidth - 1 downto 0);
--SPI command register address.
sAddr : in std_logic_vector(kCommandWidth - 4 downto 0);
--Number of data bytes + 1; not currently used (for future development).
sWidth : in std_logic_vector(1 downto 0);
--Select between Read/Write operations.
sRdWr : in STD_LOGIC;
--A pulse is generated on this output once the SPI transfer is successfully completed.
sDone : out STD_LOGIC;
--Busy flag; sApStart ignored while this signal is asserted .
sBusy : out STD_LOGIC);
end ADI_SPI;
architecture Behavioral of ADI_SPI is
function MAX(In1 : integer; In2 : integer)
return integer is
begin
if (In1 > In2) then
return In1;
else
return In2;
end if;
end function;
constant kZeros : unsigned (kSysClkDiv - 1 downto 0) := (others => '0');
constant kOnes : unsigned (kSysClkDiv - 1 downto 0) := (others => '1');
signal sClkCounter : unsigned(kSysClkDiv - 1 downto 0) := (others => '0');
signal sSPI_ClkRst: std_logic;
signal sRdDataR : std_logic_vector(kDataWidth - 1 downto 0);
signal sTxVector : std_logic_vector (kDataWidth + kCommandWidth - 1 downto 0);
signal sRxData : std_logic;
signal sTxData : std_logic := '0';
signal sTxShift, sRxShift : std_logic;
signal sLdTx : std_logic;
signal sApStartR, sApStartPulse : std_logic;
constant kCounterMax : integer := MAX((kDataWidth + kCommandWidth + 1), kCS_PulseWidthHigh);
constant kCounterNumBits : integer := integer(ceil(log2(real(kCounterMax))));
signal sCounter : unsigned (kCounterNumBits-1 downto 0);
signal sCounterInt : integer range 0 to (2**kCounterNumBits-1);
signal sCntRst_n, sTxCntEn, sRxCntEn, sDoneCntEn : std_logic := '0';
signal sBitCount : integer range 0 to kDataWidth; --Maximum 4 byte transfers for Analog Devices 2 Wire SPI
signal sDir : std_logic := '0';
signal sDirFsm : std_logic;
signal sCS_Fsm : std_logic;
signal sDoneFsm : std_logic;
signal sBusyFsm : std_logic;
signal sCurrentState : FsmStatesSPI_t := StIdle;
signal sNextState : FsmStatesSPI_t;
-- signals used for debug purposes
-- signal fsm_state, fsm_state_r : std_logic_vector(3 downto 0);
signal kHalfScale : unsigned (kSysClkDiv - 1 downto 0);
begin
kHalfScale <= '1' & kZeros(kSysClkDiv - 2 downto 0);
------------------------------------------------------------------------------------------
-- SPI interface signal assignment
------------------------------------------------------------------------------------------
InstIOBUF : IOBUF -- instantiate SDIO three state output buffer.
generic map (
DRIVE => 12,
IOSTANDARD => "LVCMOS18",
SLEW => "SLOW")
port map (
O => sRxData, -- Buffer output
IO => sSDIO, -- Buffer inout port (connect directly to top-level port)
I => sTxData, -- Buffer input
T => sDir -- 3-state enable input, high=input, low=output
);
-- Three state buffer direction control register.
ProcDir: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDir <= '0';
elsif (rising_edge(SysClk100)) then
if (sLdTx = '1') then
sDir <= sDirFsm;
else
if ((sClkCounter = kOnes) or (sCS_Fsm = '1')) then
sDir <= sDirFsm;
end if;
end if;
end if;
end process;
ProcRegCS: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCS <= '1';
--fsm_state_r <= (others => '0');
elsif (rising_edge (SysClk100)) then
sCS <= sCS_Fsm;
--fsm_state_r <= fsm_state;
end if;
end process;
sSPI_Clk <= sClkCounter(kSysClkDiv - 1 );
------------------------------------------------------------------------------------------
-- Input clock frequency divider
------------------------------------------------------------------------------------------
ProcClkCounter: process (SysClk100, asRst_n) --clock frequency divider
begin
if (asRst_n = '0') then
sClkCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sSPI_ClkRst = '1') then
sClkCounter <= (others => '0');
else
sClkCounter <= sClkCounter + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Transmit logic
------------------------------------------------------------------------------------------
sBitCount <= kDataWidth;
ProcApStartReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sApStartR <= sApStart;
end if;
end process;
sApStartPulse <= sApStart and (not sApStartR);
ProcShiftTx: process (SysClk100, asRst_n) --Transmit shift register
begin
if (asRst_n = '0') then
sTxVector <= (others => '0');--sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
elsif (rising_edge(SysClk100)) then
if (sApStartPulse = '1') then
--sTxVector <= sRdWr & sWidth & sAddr & sWrData;
sTxVector <= sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
else
if(sTxShift = '1') then
--data is placed on the falling edge (sClkCounter = kZeros) of sSPI_Clk for the transmit phase.
if ((sClkCounter = kZeros) and (sCounterInt <= kDataWidth+kCommandWidth)) then
sTxVector(kDataWidth + kCommandWidth - 1 downto 0) <= sTxVector(kDataWidth + kCommandWidth - 2 downto 0) & '0';
sTxData <= sTxVector(kDataWidth + kCommandWidth - 1);
elsif (sCounterInt > kDataWidth+kCommandWidth) then
sTxData <= '0';
end if;
else
sTxData <= '0';
end if;
end if;
end if;
end process;
ProcTxCount: process (asRst_n, sTxShift, sLdTx, sClkCounter) --Transmit bit count
begin
if ((asRst_n = '0') or (sLdTx = '1')) then
sTxCntEn <= '0';
else
if(sTxShift = '1') then
--The TX bit count incremented on the falling edge of the sSPI_Clk (sClkCounter = kZeros).
if (sClkCounter = kZeros) then
sTxCntEn <= '1';
else
sTxCntEn <= '0';
end if;
else
sTxCntEn <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Receive logic
------------------------------------------------------------------------------------------
-- Receive deserializer.
ProcShiftRx: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdDataR <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sRxShift = '0') then
sRdDataR <= (others =>'0');
else
if ((sRxShift = '1') and (sClkCounter = kHalfScale)) then
--The read data is sampled on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
sRdDataR(kDataWidth - 1 downto 0) <= sRdDataR(kDataWidth - 2 downto 0) & sRxData;
end if;
end if;
end if;
end process;
ProcRxCount: process (asRst_n, sRxShift, sClkCounter, kHalfScale) --Receive bit count
begin
if ((asRst_n = '0') or (sRxShift = '0')) then
sRxCntEn <= '0';
else
if (sRxShift = '1') then
--The RX bit count is incremented on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
if (sClkCounter = kHalfScale) then
sRxCntEn <= '1';
else
sRxCntEn <= '0';
end if;
else
sRxCntEn <= '0';
end if;
end if;
end process;
-- Register SPI read data once read instruction is completed.
ProcRdData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdData <= (others => '0');
sDone <= '0';
elsif (rising_edge (SysClk100)) then
sDone <= sDoneFsm;
if (sDoneFsm = '1') then
sRdData <= sRdDataR;
end if;
end if;
end process;
ProcBusy: process (SysClk100, asRst_n) --register sBusyFsm output
begin
if (asRst_n = '0') then
sBusy <= '1';
elsif (rising_edge (SysClk100)) then
sBusy <= sBusyFsm;
end if;
end process;
--Counter used by both transmit and receive logic; sCS minimum pulse width high is also timed by this counter.
ProcCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCntRst_n = '0') then
sCounter <= (others => '0');
else
if ((sTxCntEn = '1') or (sRxCntEn = '1') or (sDoneCntEn = '1')) then
sCounter <= sCounter + 1;
end if;
end if;
end if;
end process;
sCounterInt <= to_integer (sCounter);
------------------------------------------------------------------------------------------
-- SPI State Machine
------------------------------------------------------------------------------------------
ProcFsmSync: process (SysClk100, asRst_n) --State machine synchronous process
begin
if (asRst_n = '0') then
sCurrentState <= StIdle;
elsif (rising_edge (SysClk100)) then
sCurrentState <= sNextState;
end if;
end process;
--Next State decode logic
ProcNextStateAndOutputDecode: process (sCurrentState, sApStart, sRdWr, sCounterInt, sClkCounter, sBitCount)
begin
sNextState <= sCurrentState;
sDirFsm <= '0';
sCS_Fsm <= '1';
sDoneFsm <= '0';
sRxShift <= '0';
sTxShift <= '0';
--fsm_state <= (others => '0');
sLdTx <= '0';
sSPI_ClkRst <= '1';
sCntRst_n <= '0';
sDoneCntEn <= '0';
sBusyFsm <= '1';
case (sCurrentState) is
when StIdle =>
--fsm_state <= "0000";
sBusyFsm <= '0';
sLdTx <= '1';
if (sApStart = '1') then
if (sRdWr = '1') then
sNextState <= StRead1;
else
sNextState <= StWrite;
end if;
end if;
when StRead1 => --send command bytes
--fsm_state <= "0001";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth) then
sDirFsm <= '1';
sNextState <= StRead2;
end if;
when StRead2 => --send last command bit; change three state buffer direction
--fsm_state <= "0010";
sDirFsm <= '1';
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth + 1) then
sNextState <= StRead3;
sCntRst_n <= '0';
end if;
when StRead3 => --receive register read data
--fsm_state <= "0011";
sDirFsm <= '1';
sCS_Fsm <= '0';
sRxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if ((sCounterInt = sBitCount) and (sClkCounter = kOnes + 1)) then
--this condition assures a sSPI_Clk pulse width low of 2 SysClk100 cycles for last data bit
sCntRst_n <= '0';
sDirFsm <= '0';
sNextState <= StDone;
end if;
when StWrite => --send SPI command and register data
--fsm_state <= "0100";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = (sBitCount + kCommandWidth + 1)) then
sSPI_ClkRst <= '1';
sNextState <= StDone;
end if;
when StDone => --signal SPI instruction complete
--fsm_state <= "0101";
sDoneFsm <= '1';
sNextState <= StAssertCS;
when StAssertCS => --hold CS high for at least kCS_PulseWidthHigh SysClk100 cycles
--fsm_state <= "0111";
sCntRst_n <= '1';
sDoneCntEn <= '1';
if (sCounterInt = kCS_PulseWidthHigh) then
sNextState <= StIdle;
end if;
when others =>
--fsm_state <= (others => '1');
sNextState <= StIdle;
end case;
end process;
end Behavioral; |
-- $Id: cdata2byte.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: cdata2byte - syn
-- Description: 9 bit comma,data to Byte stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-10-12 596 2.0 re-write, commas now 2 byte sequences
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
entity cdata2byte is -- 9bit comma,data -> byte stream
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ESCXON : in slbit; -- enable xon/xoff escaping
ESCFILL : in slbit; -- enable fill escaping
DI : in slv9; -- input data; bit 8 = comma flag
ENA : in slbit; -- input data enable
BUSY : out slbit; -- input data busy
DO : out slv8; -- output data
VAL : out slbit; -- output data valid
HOLD : in slbit -- output data hold
);
end cdata2byte;
architecture syn of cdata2byte is
type regs_type is record
data : slv8; -- data
ecode : slv3; -- ecode
dataval : slbit; -- data valid
ecodeval : slbit; -- ecode valid
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- data
(others=>'0'), -- ecode
'0','0' -- dataval,ecodeval
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, HOLD, ESCXON, ESCFILL)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idata : slv8 := (others=>'0');
variable iecode : slv3 := (others=>'0');
variable iesc : slbit := '0';
variable ibusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
-- data path logic
iesc := '0';
iecode := '0' & DI(1 downto 0);
if DI(8) = '1' then
iesc := '1';
else
case DI(7 downto 0) is
when c_cdata_xon =>
if ESCXON = '1' then
iesc := '1';
iecode := c_cdata_ec_xon;
end if;
when c_cdata_xoff =>
if ESCXON = '1' then
iesc := '1';
iecode := c_cdata_ec_xoff;
end if;
when c_cdata_fill =>
if ESCFILL = '1' then
iesc := '1';
iecode := c_cdata_ec_fill;
end if;
when c_cdata_escape =>
iesc := '1';
iecode := c_cdata_ec_esc;
when others => null;
end case;
end if;
if iesc = '0' then
idata := DI(7 downto 0);
else
idata := c_cdata_escape;
end if;
-- control path logic
ibusy := '1';
if HOLD = '0' then
n.dataval := '0';
if r.ecodeval = '1' then
n.data(c_cdata_edf_pref) := c_cdata_ed_pref;
n.data(c_cdata_edf_eci) := not r.ecode;
n.data(c_cdata_edf_ec ) := r.ecode;
n.dataval := '1';
n.ecodeval := '0';
else
ibusy := '0';
if ENA = '1' then
n.data := idata;
n.dataval := '1';
n.ecode := iecode;
n.ecodeval := iesc;
end if;
end if;
end if;
N_REGS <= n;
DO <= r.data;
VAL <= r.dataval;
BUSY <= ibusy;
end process proc_next;
end syn;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerRecord is record
foo : integer;
bar : integer;
end record;
variable myRecord : integerRecord;
begin -- process p
myRecord.foo := 0;
myRecord.bar := 1;
assert myRecord.foo = 0 report "TEST FAILED" severity FAILURE;
assert myRecord.bar = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerRecord is record
foo : integer;
bar : integer;
end record;
variable myRecord : integerRecord;
begin -- process p
myRecord.foo := 0;
myRecord.bar := 1;
assert myRecord.foo = 0 report "TEST FAILED" severity FAILURE;
assert myRecord.bar = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerRecord is record
foo : integer;
bar : integer;
end record;
variable myRecord : integerRecord;
begin -- process p
myRecord.foo := 0;
myRecord.bar := 1;
assert myRecord.foo = 0 report "TEST FAILED" severity FAILURE;
assert myRecord.bar = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 44
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 44
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 44
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_xfirst_gen_unisim;
architecture syn of ram_2swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => O"000000000000",
INIT_B => O"000000000000",
SRVAL_A => O"000000000000",
SRVAL_B => O"000000000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(36*i+31 downto 36*i),
DOB => L_DOB(36*i+31 downto 36*i),
DOPA => L_DOA(36*i+35 downto 36*i+32),
DOPB => L_DOB(36*i+35 downto 36*i+32),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(36*i+31 downto 36*i),
DIB => L_DIB(36*i+31 downto 36*i),
DIPA => L_DIA(36*i+35 downto 36*i+32),
DIPB => L_DIB(36*i+35 downto 36*i+32),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => X"00000000",
INIT_B => X"00000000",
SRVAL_A => X"00000000",
SRVAL_B => X"00000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(32*i+31 downto 32*i),
DOB => DOB(32*i+31 downto 32*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(32*i+31 downto 32*i),
DIB => DIB(32*i+31 downto 32*i),
DIPA => "0000",
DIPB => "0000",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => O"000000",
INIT_B => O"000000",
SRVAL_A => O"000000",
SRVAL_B => O"000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(18*i+15 downto 18*i),
DOB => L_DOB(18*i+15 downto 18*i),
DOPA => L_DOA(18*i+17 downto 18*i+16),
DOPB => L_DOB(18*i+17 downto 18*i+16),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(18*i+15 downto 18*i),
DIB => L_DIB(18*i+15 downto 18*i),
DIPA => L_DIA(18*i+17 downto 18*i+16),
DIPB => L_DIB(18*i+17 downto 18*i+16),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => X"0000",
INIT_B => X"0000",
SRVAL_A => X"0000",
SRVAL_B => X"0000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(16*i+15 downto 16*i),
DOB => DOB(16*i+15 downto 16*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(16*i+15 downto 16*i),
DIB => DIB(16*i+15 downto 16*i),
DIPA => "00",
DIPB => "00",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => O"000",
INIT_B => O"000",
SRVAL_A => O"000",
SRVAL_B => O"000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(9*i+7 downto 9*i),
DOB => L_DOB(9*i+7 downto 9*i),
DOPA => L_DOA(9*i+8 downto 9*i+8),
DOPB => L_DOB(9*i+8 downto 9*i+8),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(9*i+7 downto 9*i),
DIB => L_DIB(9*i+7 downto 9*i),
DIPA => L_DIA(9*i+8 downto 9*i+8),
DIPB => L_DIB(9*i+8 downto 9*i+8),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => X"00",
INIT_B => X"00",
SRVAL_A => X"00",
SRVAL_B => X"00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(8*i+7 downto 8*i),
DOB => DOB(8*i+7 downto 8*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(8*i+7 downto 8*i),
DIB => DIB(8*i+7 downto 8*i),
DIPA => "0",
DIPB => "0",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4_S4
generic map (
INIT_A => X"0",
INIT_B => X"0",
SRVAL_A => X"0",
SRVAL_B => X"0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(4*i+3 downto 4*i),
DOB => L_DOB(4*i+3 downto 4*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(4*i+3 downto 4*i),
DIB => L_DIB(4*i+3 downto 4*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2_S2
generic map (
INIT_A => "00",
INIT_B => "00",
SRVAL_A => "00",
SRVAL_B => "00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(2*i+1 downto 2*i),
DOB => L_DOB(2*i+1 downto 2*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(2*i+1 downto 2*i),
DIB => L_DIB(2*i+1 downto 2*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(i downto i),
DOB => DOB(i downto i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_14_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
|
-------------------------------------------------------------------------------
-- Title : includeModuleAVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleAVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleAVHDL is
end entity includeModuleAVHDL;
architecture Behavioral of includeModuleAVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_fifo_v1_0_5;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_3.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_3.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_3.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : mc.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Tue Jun 30 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- Top level memory sequencer structural block. This block
-- instantiates the rank, bank, and column machines.
entity mc is
generic (
TCQ : integer := 100;
ADDR_CMD_MODE : string := "1T";
BANK_WIDTH : integer := 3;
BM_CNT_WIDTH : integer := 2;
BURST_MODE : string := "8";
CL : integer := 5;
COL_WIDTH : integer := 12;
CMD_PIPE_PLUS1 : string := "ON";
CS_WIDTH : integer := 4;
CWL : integer := 5;
DATA_WIDTH : integer := 64;
DATA_BUF_ADDR_WIDTH : integer := 8;
DATA_BUF_OFFSET_WIDTH : integer := 1;
--DELAY_WR_DATA_CNTRL : integer := 0; --Making it as a constant
nREFRESH_BANK : integer := 8; --Reverted back to 8
DRAM_TYPE : string := "DDR3";
DQS_WIDTH : integer := 8;
DQ_WIDTH : integer := 64;
ECC : string := "OFF";
ECC_WIDTH : integer := 8;
MC_ERR_ADDR_WIDTH : integer := 31;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
nCS_PER_RANK : integer := 1;
ORDERING : string := "NORM";
PAYLOAD_WIDTH : integer := 64;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
PHASE_DETECT : string := "OFF"; --Added to control periodic reads
ROW_WIDTH : integer := 16;
RTT_NOM : string := "40";
RTT_WR : string := "120";
STARVE_LIMIT : integer := 2;
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000101";
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00001010";
nSLOTS : integer := 2;
tCK : integer := 2500; -- pS
tFAW : integer := 40000; -- pS
tPRDI : integer := 1000000; -- pS
tRAS : integer := 37500; -- pS
tRCD : integer := 12500; -- pS
tREFI : integer := 7800000; -- pS
tRFC : integer := 110000; -- pS
tRP : integer := 12500; -- pS
tRRD : integer := 10000; -- pS
tRTP : integer := 7500; -- pS
tWTR : integer := 7500; -- pS
tZQI : integer := 128000000; -- nS
tZQCS : integer := 64 -- CKs
);
port (
wr_data_en : out std_logic; -- From col_mach0 of col_mach.v
rd_data_end : out std_logic;
rd_data_en : out std_logic;
io_config_strobe : out std_logic;
ecc_err_addr : out std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
dfi_wrdata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dfi_we_n1 : out std_logic;
dfi_we_n0 : out std_logic;
dfi_rddata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dfi_ras_n1 : out std_logic;
dfi_ras_n0 : out std_logic;
dfi_odt_wr1 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_odt_wr0 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_odt_nom1 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_odt_nom0 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_cs_n1 : out std_logic_vector((CS_WIDTH * nCS_PER_RANK) - 1 downto 0);
dfi_cs_n0 : out std_logic_vector((CS_WIDTH * nCS_PER_RANK) - 1 downto 0);
dfi_cas_n1 : out std_logic;
dfi_cas_n0 : out std_logic;
dfi_bank1 : out std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_bank0 : out std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_address1 : out std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_address0 : out std_logic_vector(ROW_WIDTH - 1 downto 0);
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
accept_ns : out std_logic;
accept : out std_logic;
dfi_dram_clk_disable : out std_logic; --= 1'b0;
dfi_reset_n : out std_logic; -- = 1'b1;
io_config : out std_logic_vector(RANK_WIDTH downto 0);
rd_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rd_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
wr_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
wr_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
dfi_wrdata : out std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
dfi_wrdata_mask : out std_logic_vector((4 * DQ_WIDTH / 8) - 1 downto 0);
rd_data : out std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0);
ecc_single : out std_logic_vector(3 downto 0);
ecc_multiple : out std_logic_vector(3 downto 0);
use_addr : in std_logic;
slot_1_present : in std_logic_vector(7 downto 0);
slot_0_present : in std_logic_vector(7 downto 0);
size : in std_logic;
rst : in std_logic;
row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
raw_not_ecc : in std_logic_vector(3 downto 0);
rank : in std_logic_vector(RANK_WIDTH - 1 downto 0);
hi_priority : in std_logic;
dfi_rddata_valid : in std_logic;
dfi_init_complete : in std_logic;
data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
correct_en : in std_logic;
col : in std_logic_vector(COL_WIDTH - 1 downto 0);
cmd : in std_logic_vector(2 downto 0);
clk : in std_logic;
bank : in std_logic_vector(BANK_WIDTH - 1 downto 0);
app_zq_req : in std_logic;
app_ref_req : in std_logic;
app_periodic_rd_req : in std_logic;
dfi_rddata : in std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
wr_data : in std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0);
wr_data_mask : in std_logic_vector(4 * DATA_WIDTH / 8 - 1 downto 0)
);
end entity mc;
architecture trans of mc is
function fRD_EN2CNFG_WR (CL: integer; DRAM_TYPE: string) return integer is
begin
if ( DRAM_TYPE = "DDR2" ) then
return 5;
elsif ( CL <= 6 ) then
return 7;
elsif ( (CL = 7) or (CL = 8) ) then
return 8;
else
return 9;
end if;
end function fRD_EN2CNFG_WR;
function fPHY_WRLAT (CWL: integer) return integer is
begin
if ( CWL < 7 ) then --modified "<=" to '<' to fix CR #531967 (tPHY_WRLAT issue)
return 0;
else
return 1;
end if;
end function fPHY_WRLAT;
function cdiv (num,div: integer) return integer is
variable tmp : integer;
begin
tmp := (num/div);
if ( (num mod div) > 0 ) then
tmp := tmp + 1;
end if;
return tmp;
end function cdiv;
function fRRD ( nRRD_CK: integer; DRAM_TYPE: string) return integer is
begin
if ( DRAM_TYPE = "DDR3" ) then
if ( nRRD_CK < 4 ) then
return 4;
else
return nRRD_CK;
end if;
else
if ( nRRD_CK < 2 ) then
return 2;
else
return nRRD_CK;
end if;
end if;
end function fRRD;
function fWTR ( nWTR_CK: integer; DRAM_TYPE: string) return integer is
begin
if ( DRAM_TYPE = "DDR3" ) then
if ( nWTR_CK < 4 ) then
return 4;
else
return nWTR_CK;
end if;
else
if ( nWTR_CK < 2 ) then
return 2;
else
return nWTR_CK;
end if;
end if;
end function fWTR;
function fRTP ( nRTP_CK: integer; DRAM_TYPE: string) return integer is
begin
if ( DRAM_TYPE = "DDR3" ) then
if ( nRTP_CK < 4 ) then
return 4;
else
return nRTP_CK;
end if;
else
if ( nRTP_CK < 2 ) then
return 2;
else
return nRTP_CK;
end if;
end if;
end function fRTP;
function fEARLY_WR_DATA_ADDR (ECC: string; CWL: integer) return string is
begin
if ( (ECC = "ON") and (CWL < 7) ) then
return "ON";
else
return "OFF";
end if;
end function fEARLY_WR_DATA_ADDR;
function fnWR ( nWR_CK : integer) return integer is
begin
if ( nWR_CK = 9 ) then
return 10;
elsif ( nWR_CK = 11 ) then
return 12;
else
return nWR_CK;
end if;
end function fnWR;
function fDELAY_WR_DATA_CNTRL (ECC: string; CWL: integer) return integer is
begin
if ( (ECC = "ON") or (CWL < 7) ) then
return 0;
else
return 1;
end if;
end function fDELAY_WR_DATA_CNTRL;
constant nRD_EN2CNFG_WR : integer := fRD_EN2CNFG_WR(CL,DRAM_TYPE);
constant nWR_EN2CNFG_RD : integer := 4;
constant nWR_EN2CNFG_WR : integer := 4;
constant nCNFG2RD_EN : integer := 2;
constant nCNFG2WR : integer := 2;
constant nPHY_WRLAT : integer := fPHY_WRLAT(CWL);
constant nRCD : integer := cdiv(tRCD,tCK);
constant nRP : integer := cdiv(tRP, tCK);
constant nRAS : integer := cdiv(tRAS, tCK);
constant nFAW : integer := cdiv(tFAW, tCK);
constant nRRD_CK : integer := cdiv(tRRD, tCK);
--As per specification, Write recover for autoprecharge ( cycles) doesn't support
--values of 9 and 11. Rounding off the value 9, 11 to next integer.
constant nWR_CK : integer := cdiv(15000, tCK);
constant nWR : integer := fnWR(nWR_CK);
constant nRRD : integer := fRRD(nRRD_CK,DRAM_TYPE);
constant nWTR_CK : integer := cdiv(tWTR,tCK);
constant nWTR : integer := fWTR(nWTR_CK,DRAM_TYPE);
constant nRTP_CK : integer := cdiv(tRTP, tCK);
constant nRTP : integer := fRTP(nRTP_CK,DRAM_TYPE);
constant nRFC : integer := cdiv(tRFC,tCK);
constant EARLY_WR_DATA_ADDR : string := fEARLY_WR_DATA_ADDR(ECC,CWL);
--DELAY_WR_DATA_CNTRL is made as localprameter as the values of this
--parameter are fixed for pirticular ECC-CWL combinations.
constant DELAY_WR_DATA_CNTRL : integer := fDELAY_WR_DATA_CNTRL ( ECC,CWL);
--constant nSLOTS : integer := 1 + 1 when (or_br(SLOT_1_CONFIG) /= 0) else
-- 0;
--This constant nSLOTS is changed as generic
-- Maintenance functions.
constant MAINT_PRESCALER_PERIOD : integer := 200000; -- 200 nS nominal.
constant MAINT_PRESCALER_DIV : integer := MAINT_PRESCALER_PERIOD / (tCK * nCK_PER_CLK); -- Round down.
constant REFRESH_TIMER_DIV : integer := (tREFI )/ MAINT_PRESCALER_PERIOD;
--constant nREFRESH_BANK : integer := 8; --This constant is made as generic inorder to give a
--flexibiity to override it for super users.
constant PERIODIC_RD_TIMER_DIV : integer := tPRDI / MAINT_PRESCALER_PERIOD;
constant MAINT_PRESCALER_PERIOD_NS : integer := MAINT_PRESCALER_PERIOD / 1000;
constant ZQ_TIMER_DIV : integer := tZQI / MAINT_PRESCALER_PERIOD_NS;
-- Reserved feature control.
-- Open page wait mode is reserved.
-- nOP_WAIT is the number of states a bank machine will park itself
-- on an otherwise inactive open page before closing the page. If
-- nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1,
-- the bank machine will remain parked until the pool of idle bank machines
-- are less than LOW_IDLE_CNT. At which point parked bank machines
-- is selected to exit until the number of idle bank machines exceeds
-- the LOW_IDLE_CNT.
-- Note: Setting this value to a value greater than zero may result in
-- better efficiency for specific traffic patterns as the controller will
-- attempt to keep the page open for this time value. However, this should
-- only be used in situations where the number of bank machines (nBANK_MACH)
-- is equal to or greater than the number of pages that will be open.
-- If the user attempts to open more pages than bank machines, the controller
-- will stall for a time period up to the value set which will likely result
-- in a serious efficiency degradation. Increasing the number of bank
-- machines may result in difficulty meeting timing closure.
-- Check timing closure in the ISE tools before increasing the
-- number of bank machines.
constant nOP_WAIT : integer := 0;
constant LOW_IDLE_CNT : integer := 0;
constant RANK_BM_BV_WIDTH : integer := nBANK_MACHS * RANKS;
component ecc_buf is
generic (
TCQ : integer := 100;
PAYLOAD_WIDTH : integer := 64;
DATA_BUF_ADDR_WIDTH : integer := 4;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DATA_WIDTH : integer := 64
);
port (
rd_merge_data : out std_logic_vector(4 * DATA_WIDTH - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
rd_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rd_data_offset : in std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
wr_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
wr_data_offset : in std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
rd_data : in std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0);
wr_ecc_buf : in std_logic
);
end component;
component ecc_dec_fix is
generic (
TCQ : integer := 100;
PAYLOAD_WIDTH : integer := 64;
CODE_WIDTH : integer := 72;
DATA_WIDTH : integer := 64;
DQ_WIDTH : integer := 72;
ECC_WIDTH : integer := 8
);
port (
rd_data : out std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0);
ecc_single : out std_logic_vector(3 downto 0);
ecc_multiple : out std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logic;
h_rows : in std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0);
dfi_rddata : in std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
correct_en : in std_logic;
ecc_status_valid : in std_logic
);
end component;
component ecc_gen is
generic (
CODE_WIDTH : integer := 72;
ECC_WIDTH : integer := 8;
DATA_WIDTH : integer := 64
);
port (
h_rows : out std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
end component;
component ecc_merge_enc is
generic (
TCQ : integer := 100;
PAYLOAD_WIDTH : integer := 64;
CODE_WIDTH : integer := 72;
DATA_BUF_ADDR_WIDTH : integer := 4;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DATA_WIDTH : integer := 64;
DQ_WIDTH : integer := 72;
ECC_WIDTH : integer := 8
);
port (
dfi_wrdata : out std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
dfi_wrdata_mask : out std_logic_vector(4 * DQ_WIDTH / 8 - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
wr_data : in std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0);
wr_data_mask : in std_logic_vector(4 * DATA_WIDTH / 8 - 1 downto 0);
rd_merge_data : in std_logic_vector(4 * DATA_WIDTH - 1 downto 0);
h_rows : in std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0);
raw_not_ecc : in std_logic_vector(3 downto 0)
);
end component;
component bank_mach is
generic (
TCQ : integer := 100;
ADDR_CMD_MODE : string := "1T";
BANK_WIDTH : integer := 3;
BM_CNT_WIDTH : integer := 2;
BURST_MODE : string := "8";
COL_WIDTH : integer := 12;
CS_WIDTH : integer := 4;
CWL : integer := 5;
DATA_BUF_ADDR_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
EARLY_WR_DATA_ADDR : string := "OFF";
ECC : string := "OFF";
LOW_IDLE_CNT : integer := 1;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
nCNFG2RD_EN : integer := 2;
nCNFG2WR : integer := 2;
nCS_PER_RANK : integer := 1;
nOP_WAIT : integer := 0;
nRAS : integer := 20;
nRCD : integer := 5;
nRFC : integer := 44;
nRTP : integer := 4;
nRP : integer := 10;
nSLOTS : integer := 2;
nWR : integer := 6;
ORDERING : string := "NORM";
RANK_BM_BV_WIDTH : integer := 16;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
ROW_WIDTH : integer := 16;
RTT_NOM : string := "40";
RTT_WR : string := "120";
STARVE_LIMIT : integer := 2;
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000101";
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00001010";
tZQCS : integer := 64
);
port (
maint_wip_r : out std_logic;
insert_maint_r1 : out std_logic;
dfi_we_n1 : out std_logic;
dfi_we_n0 : out std_logic;
dfi_ras_n1 : out std_logic;
dfi_ras_n0 : out std_logic;
dfi_odt_wr1 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_odt_wr0 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_odt_nom1 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_odt_nom0 : out std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
dfi_cs_n1 : out std_logic_vector((CS_WIDTH * nCS_PER_RANK) - 1 downto 0);
dfi_cs_n0 : out std_logic_vector((CS_WIDTH * nCS_PER_RANK) - 1 downto 0);
dfi_cas_n1 : out std_logic;
dfi_cas_n0 : out std_logic;
dfi_bank1 : out std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_bank0 : out std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_address1 : out std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_address0 : out std_logic_vector(ROW_WIDTH - 1 downto 0);
col_wr_data_buf_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col_size : out std_logic;
col_row : out std_logic_vector(ROW_WIDTH - 1 downto 0);
col_rmw : out std_logic;
col_ra : out std_logic_vector(RANK_WIDTH - 1 downto 0);
col_periodic_rd : out std_logic;
col_data_buf_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col_ba : out std_logic_vector(BANK_WIDTH - 1 downto 0);
col_a : out std_logic_vector(ROW_WIDTH - 1 downto 0);
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
accept_ns : out std_logic;
accept : out std_logic;
io_config : out std_logic_vector(RANK_WIDTH downto 0);
io_config_strobe : out std_logic;
sending_row : out std_logic_vector(nBANK_MACHS - 1 downto 0);
sending_col : out std_logic_vector(nBANK_MACHS - 1 downto 0);
sent_col : out std_logic;
periodic_rd_ack_r : out std_logic;
act_this_rank_r : out std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
wr_this_rank_r : out std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
rd_this_rank_r : out std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
rank_busy_r : out std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
wtr_inhbt_config_r : in std_logic_vector(RANKS - 1 downto 0);
use_addr : in std_logic;
slot_1_present : in std_logic_vector(7 downto 0);
slot_0_present : in std_logic_vector(7 downto 0);
size : in std_logic;
rst : in std_logic;
row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
rd_rmw : in std_logic;
rd_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rank : in std_logic_vector(RANK_WIDTH - 1 downto 0);
periodic_rd_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
periodic_rd_r : in std_logic;
maint_zq_r : in std_logic;
maint_req_r : in std_logic;
maint_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
inhbt_wr_config : in std_logic;
inhbt_rd_r : in std_logic_vector(RANKS - 1 downto 0);
inhbt_rd_config : in std_logic;
inhbt_act_faw_r : in std_logic_vector(RANKS - 1 downto 0);
hi_priority : in std_logic;
dq_busy_data : in std_logic;
dfi_rddata_valid : in std_logic;
dfi_init_complete : in std_logic;
data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col : in std_logic_vector(COL_WIDTH - 1 downto 0);
cmd : in std_logic_vector(2 downto 0);
clk : in std_logic;
bank : in std_logic_vector(BANK_WIDTH - 1 downto 0)
);
end component;
component rank_mach is
generic (
BURST_MODE : string := "8";
CS_WIDTH : integer := 4;
DRAM_TYPE : string := "DDR3";
MAINT_PRESCALER_DIV : integer := 40;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
CL : integer := 5;
nFAW : integer := 30;
nREFRESH_BANK : integer := 8;
nRRD : integer := 4;
nWTR : integer := 4;
PERIODIC_RD_TIMER_DIV : integer := 20;
RANK_BM_BV_WIDTH : integer := 16;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
PHASE_DETECT : string := "OFF";
REFRESH_TIMER_DIV : integer := 39;
ZQ_TIMER_DIV : integer := 640000
);
port (
periodic_rd_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
periodic_rd_r : out std_logic;
maint_req_r : out std_logic;
inhbt_act_faw_r : out std_logic_vector(RANKS - 1 downto 0);
inhbt_rd_r : out std_logic_vector(RANKS - 1 downto 0);
wtr_inhbt_config_r : out std_logic_vector(RANKS - 1 downto 0);
maint_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
maint_zq_r : out std_logic;
wr_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
slot_0_present : in std_logic_vector(7 downto 0);
sending_row : in std_logic_vector(nBANK_MACHS - 1 downto 0);
sending_col : in std_logic_vector(nBANK_MACHS - 1 downto 0);
rst : in std_logic;
rd_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
rank_busy_r : in std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
periodic_rd_ack_r : in std_logic;
maint_wip_r : in std_logic;
insert_maint_r1 : in std_logic;
dfi_init_complete : in std_logic;
clk : in std_logic;
app_zq_req : in std_logic;
app_ref_req : in std_logic;
app_periodic_rd_req : in std_logic;
act_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0)
);
end component;
component col_mach is
generic (
TCQ : integer := 100;
BANK_WIDTH : integer := 3;
BURST_MODE : string := "8";
COL_WIDTH : integer := 12;
CS_WIDTH : integer := 4;
DATA_BUF_ADDR_WIDTH : integer := 8;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DELAY_WR_DATA_CNTRL : integer := 0;
DQS_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
EARLY_WR_DATA_ADDR : string := "OFF";
ECC : string := "OFF";
MC_ERR_ADDR_WIDTH : integer := 31;
nCK_PER_CLK : integer := 2;
nPHY_WRLAT : integer := 0;
nRD_EN2CNFG_WR : integer := 6;
nWR_EN2CNFG_RD : integer := 4;
nWR_EN2CNFG_WR : integer := 4;
RANK_WIDTH : integer := 2;
ROW_WIDTH : integer := 16
);
port (
dq_busy_data : out std_logic;
wr_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
dfi_wrdata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
wr_data_en : out std_logic;
wr_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
inhbt_wr_config : out std_logic;
inhbt_rd_config : out std_logic;
rd_rmw : out std_logic;
ecc_err_addr : out std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
ecc_status_valid : out std_logic;
wr_ecc_buf : out std_logic;
rd_data_end : out std_logic;
rd_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rd_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
rd_data_en : out std_logic;
clk : in std_logic;
rst : in std_logic;
sent_col : in std_logic;
col_size : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
col_wr_data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_valid : in std_logic;
col_periodic_rd : in std_logic;
col_data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col_rmw : in std_logic;
col_ra : in std_logic_vector(RANK_WIDTH - 1 downto 0);
col_ba : in std_logic_vector(BANK_WIDTH - 1 downto 0);
col_row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
col_a : in std_logic_vector(ROW_WIDTH - 1 downto 0)
);
end component;
signal act_this_rank_r : std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
signal col_a : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal col_ba : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal col_data_buf_addr : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal col_periodic_rd : std_logic;
signal col_ra : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal col_rmw : std_logic;
signal col_row : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal col_size : std_logic;
signal col_wr_data_buf_addr : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal dq_busy_data : std_logic;
signal ecc_status_valid : std_logic;
signal inhbt_act_faw_r : std_logic_vector(RANKS - 1 downto 0);
signal inhbt_rd_config : std_logic;
signal inhbt_rd_r : std_logic_vector(RANKS - 1 downto 0);
signal inhbt_wr_config : std_logic;
signal insert_maint_r1 : std_logic;
signal maint_rank_r : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal maint_req_r : std_logic;
signal maint_wip_r : std_logic;
signal maint_zq_r : std_logic;
signal periodic_rd_ack_r : std_logic;
signal periodic_rd_r : std_logic;
signal periodic_rd_rank_r : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal rank_busy_r : std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
signal rd_rmw : std_logic;
signal rd_this_rank_r : std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
signal sending_col : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal sending_row : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal sent_col : std_logic;
signal wr_ecc_buf : std_logic;
signal wr_this_rank_r : std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
signal wtr_inhbt_config_r : std_logic_vector(RANKS - 1 downto 0);
signal mc_rddata_valid : std_logic;
constant CODE_WIDTH : integer := DATA_WIDTH + ECC_WIDTH;
-- Declare intermediate signals for referenced outputs
signal wr_data_en_ns : std_logic;
signal rd_data_end_int31 : std_logic;
signal rd_data_en_int30 : std_logic;
signal io_config_strobe_ns : std_logic;
signal ecc_err_addr_int23 : std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
signal dfi_wrdata_en_ns : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dfi_we_n1_ns : std_logic;
signal dfi_we_n0_ns : std_logic;
signal dfi_rddata_en_ns : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dfi_ras_n1_ns : std_logic;
signal dfi_ras_n0_ns : std_logic;
signal dfi_odt_wr1_ns : std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
signal dfi_odt_wr0_ns : std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
signal dfi_odt_nom1_ns : std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
signal dfi_odt_nom0_ns : std_logic_vector((nSLOTS * nCS_PER_RANK) - 1 downto 0);
signal dfi_cs_n1_ns : std_logic_vector((CS_WIDTH * nCS_PER_RANK) - 1 downto 0);
signal dfi_cs_n0_ns : std_logic_vector((CS_WIDTH * nCS_PER_RANK) - 1 downto 0);
signal dfi_cas_n1_ns : std_logic;
signal dfi_cas_n0_ns : std_logic;
signal dfi_bank1_ns : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal dfi_bank0_ns : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal dfi_address1_ns : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal dfi_address0_ns : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal bank_mach_next_int2 : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
signal accept_ns_int1 : std_logic;
signal accept_int0 : std_logic;
signal io_config_ns : std_logic_vector(RANK_WIDTH downto 0);
signal rd_data_addr_int29 : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal rd_data_offset_int32 : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
signal wr_data_addr_ns : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal wr_data_offset_ns : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
signal dfi_wrdata_int20 : std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
signal dfi_wrdata_mask_int22 : std_logic_vector((4 * DQ_WIDTH / 8) - 1 downto 0);
signal rd_data_int28 : std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0);
signal ecc_single_int25 : std_logic_vector(3 downto 0);
signal ecc_multiple_int24 : std_logic_vector(3 downto 0);
signal rst_reg : std_logic_vector(9 downto 0);
signal rst_final : std_logic;
attribute max_fanout : string;
attribute max_fanout of rst_final : signal is "10";
begin
-- Drive referenced outputs
rd_data_end <= rd_data_end_int31;
rd_data_en <= rd_data_en_int30;
ecc_err_addr <= ecc_err_addr_int23;
bank_mach_next <= bank_mach_next_int2;
accept_ns <= accept_ns_int1;
accept <= accept_int0;
dfi_dram_clk_disable <= '0';
dfi_reset_n <= '1';
rd_data_addr <= rd_data_addr_int29;
rd_data_offset <= rd_data_offset_int32;
dfi_wrdata <= dfi_wrdata_int20;
dfi_wrdata_mask <= dfi_wrdata_mask_int22;
rd_data <= rd_data_int28;
ecc_single <= ecc_single_int25;
ecc_multiple <= ecc_multiple_int24;
PROCESS (clk)
BEGIN
IF ( clk'EVENT AND clk = '1') THEN
rst_reg <= (rst_reg(8 DOWNTO 0) & rst);
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF ( clk'EVENT AND clk = '1') THEN
rst_final <= rst_reg(9);
END IF;
END PROCESS;
rank_mach0 : rank_mach
generic map (
BURST_MODE => BURST_MODE,
CS_WIDTH => CS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
MAINT_PRESCALER_DIV => MAINT_PRESCALER_DIV,
nBANK_MACHS => nBANK_MACHS,
nCK_PER_CLK => nCK_PER_CLK,
CL => CL,
nFAW => nFAW,
nREFRESH_BANK => nREFRESH_BANK,
nRRD => nRRD,
nWTR => nWTR,
PERIODIC_RD_TIMER_DIV => PERIODIC_RD_TIMER_DIV,
RANK_BM_BV_WIDTH => RANK_BM_BV_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
PHASE_DETECT => PHASE_DETECT,
REFRESH_TIMER_DIV => REFRESH_TIMER_DIV,
ZQ_TIMER_DIV => ZQ_TIMER_DIV
)
port map (
maint_req_r => maint_req_r,
periodic_rd_r => periodic_rd_r,
periodic_rd_rank_r => periodic_rd_rank_r(RANK_WIDTH - 1 downto 0),
inhbt_act_faw_r => inhbt_act_faw_r(RANKS - 1 downto 0),
inhbt_rd_r => inhbt_rd_r(RANKS - 1 downto 0),
wtr_inhbt_config_r => wtr_inhbt_config_r(RANKS - 1 downto 0),
maint_rank_r => maint_rank_r(RANK_WIDTH - 1 downto 0),
maint_zq_r => maint_zq_r,
act_this_rank_r => act_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
app_periodic_rd_req => app_periodic_rd_req,
app_ref_req => app_ref_req,
app_zq_req => app_zq_req,
clk => clk,
dfi_init_complete => dfi_init_complete,
insert_maint_r1 => insert_maint_r1,
maint_wip_r => maint_wip_r,
periodic_rd_ack_r => periodic_rd_ack_r,
rank_busy_r => rank_busy_r((RANKS * nBANK_MACHS) - 1 downto 0),
rd_this_rank_r => rd_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
rst => rst_final,
sending_col => sending_col(nBANK_MACHS - 1 downto 0),
sending_row => sending_row(nBANK_MACHS - 1 downto 0),
slot_0_present => slot_0_present(7 downto 0),
slot_1_present => slot_1_present(7 downto 0),
wr_this_rank_r => wr_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0)
);
cmd_pipe_plus: if (CMD_PIPE_PLUS1 = "ON") generate
process (clk)
begin
if (clk'event and clk = '1') then
dfi_we_n1 <= dfi_we_n1_ns after (TCQ)*1 ps;
dfi_we_n0 <= dfi_we_n0_ns after (TCQ)*1 ps;
dfi_ras_n1 <= dfi_ras_n1_ns after (TCQ)*1 ps;
dfi_ras_n0 <= dfi_ras_n0_ns after (TCQ)*1 ps;
dfi_odt_wr1 <= dfi_odt_wr1_ns after (TCQ)*1 ps;
dfi_odt_wr0 <= dfi_odt_wr0_ns after (TCQ)*1 ps;
dfi_odt_nom1 <= dfi_odt_nom1_ns after (TCQ)*1 ps;
dfi_odt_nom0 <= dfi_odt_nom0_ns after (TCQ)*1 ps;
dfi_cs_n1 <= dfi_cs_n1_ns after (TCQ)*1 ps;
dfi_cs_n0 <= dfi_cs_n0_ns after (TCQ)*1 ps;
dfi_cas_n1 <= dfi_cas_n1_ns after (TCQ)*1 ps;
dfi_cas_n0 <= dfi_cas_n0_ns after (TCQ)*1 ps;
dfi_bank1 <= dfi_bank1_ns after (TCQ)*1 ps;
dfi_bank0 <= dfi_bank0_ns after (TCQ)*1 ps;
dfi_address1 <= dfi_address1_ns after (TCQ)*1 ps;
dfi_address0 <= dfi_address0_ns after (TCQ)*1 ps;
io_config <= io_config_ns after (TCQ)*1 ps;
io_config_strobe <= io_config_strobe_ns after (TCQ)*1 ps;
dfi_wrdata_en <= dfi_wrdata_en_ns after (TCQ)*1 ps;
dfi_rddata_en <= dfi_rddata_en_ns after (TCQ)*1 ps;
wr_data_en <= wr_data_en_ns after (TCQ)*1 ps;
wr_data_addr <= wr_data_addr_ns after (TCQ)*1 ps;
wr_data_offset <= wr_data_offset_ns after (TCQ)*1 ps;
end if;
end process;
end generate; --end cmd_pipe_plus
cmd_pipe_plus0: if (not(CMD_PIPE_PLUS1 = "ON")) generate
process (dfi_address0_ns , dfi_address1_ns
, dfi_bank0_ns , dfi_bank1_ns , dfi_cas_n0_ns
, dfi_cas_n1_ns , dfi_cs_n0_ns , dfi_cs_n1_ns
, dfi_odt_nom0_ns , dfi_odt_nom1_ns , dfi_odt_wr0_ns
, dfi_odt_wr1_ns , dfi_ras_n0_ns , dfi_ras_n1_ns
, dfi_rddata_en_ns , dfi_we_n0_ns , dfi_we_n1_ns
, dfi_wrdata_en_ns , io_config_ns
, io_config_strobe_ns , wr_data_addr_ns
, wr_data_en_ns , wr_data_offset_ns)
begin
dfi_we_n1 <= dfi_we_n1_ns after (TCQ)*1 ps;
dfi_we_n0 <= dfi_we_n0_ns after (TCQ)*1 ps;
dfi_ras_n1 <= dfi_ras_n1_ns after (TCQ)*1 ps;
dfi_ras_n0 <= dfi_ras_n0_ns after (TCQ)*1 ps;
dfi_odt_wr1 <= dfi_odt_wr1_ns after (TCQ)*1 ps;
dfi_odt_wr0 <= dfi_odt_wr0_ns after (TCQ)*1 ps;
dfi_odt_nom1 <= dfi_odt_nom1_ns after (TCQ)*1 ps;
dfi_odt_nom0 <= dfi_odt_nom0_ns after (TCQ)*1 ps;
dfi_cs_n1 <= dfi_cs_n1_ns after (TCQ)*1 ps;
dfi_cs_n0 <= dfi_cs_n0_ns after (TCQ)*1 ps;
dfi_cas_n1 <= dfi_cas_n1_ns after (TCQ)*1 ps;
dfi_cas_n0 <= dfi_cas_n0_ns after (TCQ)*1 ps;
dfi_bank1 <= dfi_bank1_ns after (TCQ)*1 ps;
dfi_bank0 <= dfi_bank0_ns after (TCQ)*1 ps;
dfi_address1 <= dfi_address1_ns after (TCQ)*1 ps;
dfi_address0 <= dfi_address0_ns after (TCQ)*1 ps;
io_config <= io_config_ns after (TCQ)*1 ps;
io_config_strobe <= io_config_strobe_ns after (TCQ)*1 ps;
dfi_wrdata_en <= dfi_wrdata_en_ns after (TCQ)*1 ps;
dfi_rddata_en <= dfi_rddata_en_ns after (TCQ)*1 ps;
wr_data_en <= wr_data_en_ns after (TCQ)*1 ps;
wr_data_addr <= wr_data_addr_ns after (TCQ)*1 ps;
wr_data_offset <= wr_data_offset_ns after (TCQ)*1 ps;
end process;
end generate; --block: cmd_pipe_plus0
bank_mach0 : bank_mach
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
COL_WIDTH => COL_WIDTH,
CS_WIDTH => CS_WIDTH,
CWL => CWL,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DRAM_TYPE => DRAM_TYPE,
EARLY_WR_DATA_ADDR => EARLY_WR_DATA_ADDR,
ECC => ECC,
LOW_IDLE_CNT => LOW_IDLE_CNT,
nBANK_MACHS => nBANK_MACHS,
nCK_PER_CLK => nCK_PER_CLK,
nCNFG2RD_EN => nCNFG2RD_EN,
nCNFG2WR => nCNFG2WR,
nCS_PER_RANK => nCS_PER_RANK,
nOP_WAIT => nOP_WAIT,
nRAS => nRAS,
nRCD => nRCD,
nRFC => nRFC,
nRTP => nRTP,
nRP => nRP,
nSLOTS => nSLOTS,
nWR => nWR,
ORDERING => ORDERING,
RANK_BM_BV_WIDTH => RANK_BM_BV_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ROW_WIDTH => ROW_WIDTH,
RTT_NOM => RTT_NOM,
RTT_WR => RTT_WR,
STARVE_LIMIT => STARVE_LIMIT,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
tZQCS => tZQCS
)
port map (
accept => accept_int0,
accept_ns => accept_ns_int1,
bank_mach_next => bank_mach_next_int2(BM_CNT_WIDTH - 1 downto 0),
col_a => col_a(ROW_WIDTH - 1 downto 0),
col_ba => col_ba(BANK_WIDTH - 1 downto 0),
col_data_buf_addr => col_data_buf_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0),
col_periodic_rd => col_periodic_rd,
col_ra => col_ra(RANK_WIDTH - 1 downto 0),
col_rmw => col_rmw,
col_row => col_row(ROW_WIDTH - 1 downto 0),
col_size => col_size,
col_wr_data_buf_addr => col_wr_data_buf_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0),
dfi_address0 => dfi_address0_ns(ROW_WIDTH - 1 downto 0),
dfi_address1 => dfi_address1_ns(ROW_WIDTH - 1 downto 0),
dfi_bank0 => dfi_bank0_ns(BANK_WIDTH - 1 downto 0),
dfi_bank1 => dfi_bank1_ns(BANK_WIDTH - 1 downto 0),
dfi_cas_n0 => dfi_cas_n0_ns,
dfi_cas_n1 => dfi_cas_n1_ns,
dfi_cs_n0 => dfi_cs_n0_ns((CS_WIDTH * nCS_PER_RANK) - 1 downto 0),
dfi_cs_n1 => dfi_cs_n1_ns((CS_WIDTH * nCS_PER_RANK) - 1 downto 0),
dfi_odt_nom0 => dfi_odt_nom0_ns((nSLOTS * nCS_PER_RANK) - 1 downto 0),
dfi_odt_nom1 => dfi_odt_nom1_ns((nSLOTS * nCS_PER_RANK) - 1 downto 0),
dfi_odt_wr0 => dfi_odt_wr0_ns((nSLOTS * nCS_PER_RANK) - 1 downto 0),
dfi_odt_wr1 => dfi_odt_wr1_ns((nSLOTS * nCS_PER_RANK) - 1 downto 0),
dfi_ras_n0 => dfi_ras_n0_ns,
dfi_ras_n1 => dfi_ras_n1_ns,
dfi_we_n0 => dfi_we_n0_ns,
dfi_we_n1 => dfi_we_n1_ns,
insert_maint_r1 => insert_maint_r1,
maint_wip_r => maint_wip_r,
io_config => io_config_ns(RANK_WIDTH downto 0),
io_config_strobe => io_config_strobe_ns,
sending_row => sending_row(nBANK_MACHS - 1 downto 0),
sending_col => sending_col(nBANK_MACHS - 1 downto 0),
sent_col => sent_col,
periodic_rd_ack_r => periodic_rd_ack_r,
act_this_rank_r => act_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
wr_this_rank_r => wr_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
rd_this_rank_r => rd_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
rank_busy_r => rank_busy_r((RANKS * nBANK_MACHS) - 1 downto 0),
bank => bank(BANK_WIDTH - 1 downto 0),
clk => clk,
cmd => cmd(2 downto 0),
col => col(COL_WIDTH - 1 downto 0),
data_buf_addr => data_buf_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0),
dfi_init_complete => dfi_init_complete,
dfi_rddata_valid => dfi_rddata_valid,
dq_busy_data => dq_busy_data,
hi_priority => hi_priority,
inhbt_act_faw_r => inhbt_act_faw_r(RANKS - 1 downto 0),
inhbt_rd_config => inhbt_rd_config,
inhbt_rd_r => inhbt_rd_r(RANKS - 1 downto 0),
inhbt_wr_config => inhbt_wr_config,
maint_rank_r => maint_rank_r(RANK_WIDTH - 1 downto 0),
maint_req_r => maint_req_r,
maint_zq_r => maint_zq_r,
periodic_rd_r => periodic_rd_r,
periodic_rd_rank_r => periodic_rd_rank_r(RANK_WIDTH - 1 downto 0),
rank => rank(RANK_WIDTH - 1 downto 0),
rd_data_addr => rd_data_addr_int29(DATA_BUF_ADDR_WIDTH - 1 downto 0),
rd_rmw => rd_rmw,
row => row(ROW_WIDTH - 1 downto 0),
rst => rst_final,
size => size,
slot_0_present => slot_0_present(7 downto 0),
slot_1_present => slot_1_present(7 downto 0),
use_addr => use_addr,
wtr_inhbt_config_r => wtr_inhbt_config_r(RANKS - 1 downto 0)
);
col_mach0 : col_mach
generic map (
TCQ => TCQ,
BANK_WIDTH => BANK_WIDTH,
BURST_MODE => BURST_MODE,
COL_WIDTH => COL_WIDTH,
CS_WIDTH => CS_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DATA_BUF_OFFSET_WIDTH => DATA_BUF_OFFSET_WIDTH,
DELAY_WR_DATA_CNTRL => DELAY_WR_DATA_CNTRL,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
EARLY_WR_DATA_ADDR => EARLY_WR_DATA_ADDR,
ECC => ECC,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
nCK_PER_CLK => nCK_PER_CLK,
nPHY_WRLAT => nPHY_WRLAT,
nRD_EN2CNFG_WR => nRD_EN2CNFG_WR,
nWR_EN2CNFG_RD => nWR_EN2CNFG_RD,
nWR_EN2CNFG_WR => nWR_EN2CNFG_WR,
RANK_WIDTH => RANK_WIDTH,
ROW_WIDTH => ROW_WIDTH
)
port map (
dq_busy_data => dq_busy_data,
wr_data_offset => wr_data_offset_ns(DATA_BUF_OFFSET_WIDTH - 1 downto 0),
dfi_wrdata_en => dfi_wrdata_en_ns(DQS_WIDTH - 1 downto 0),
wr_data_en => wr_data_en_ns,
wr_data_addr => wr_data_addr_ns(DATA_BUF_ADDR_WIDTH - 1 downto 0),
dfi_rddata_en => dfi_rddata_en_ns(DQS_WIDTH - 1 downto 0),
inhbt_wr_config => inhbt_wr_config,
inhbt_rd_config => inhbt_rd_config,
rd_rmw => rd_rmw,
ecc_err_addr => ecc_err_addr_int23(MC_ERR_ADDR_WIDTH - 1 downto 0),
ecc_status_valid => ecc_status_valid,
wr_ecc_buf => wr_ecc_buf,
rd_data_end => rd_data_end_int31,
rd_data_addr => rd_data_addr_int29(DATA_BUF_ADDR_WIDTH - 1 downto 0),
rd_data_offset => rd_data_offset_int32(DATA_BUF_OFFSET_WIDTH - 1 downto 0),
rd_data_en => rd_data_en_int30,
clk => clk,
rst => rst_final,
sent_col => sent_col,
col_size => col_size,
io_config => io_config_ns(RANK_WIDTH downto 0),
col_wr_data_buf_addr => col_wr_data_buf_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0),
dfi_rddata_valid => dfi_rddata_valid,
col_periodic_rd => col_periodic_rd,
col_data_buf_addr => col_data_buf_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0),
col_rmw => col_rmw,
col_ra => col_ra(RANK_WIDTH - 1 downto 0),
col_ba => col_ba(BANK_WIDTH - 1 downto 0),
col_row => col_row(ROW_WIDTH - 1 downto 0),
col_a => col_a(ROW_WIDTH - 1 downto 0)
);
int36 : if (ECC = "OFF") generate
rd_data_int28 <= dfi_rddata;
dfi_wrdata_int20 <= wr_data;
dfi_wrdata_mask_int22 <= wr_data_mask;
ecc_single_int25 <= "0000";
ecc_multiple_int24 <= "0000";
end generate;
int37 : if (not(ECC = "OFF")) generate
signal rd_merge_data : std_logic_vector (4*DATA_WIDTH - 1 downto 0);
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
-- Parameters
begin
ecc_merge_enc0 : ecc_merge_enc
generic map (
tcq => TCQ,
payload_width => PAYLOAD_WIDTH,
code_width => CODE_WIDTH,
data_buf_addr_width => DATA_BUF_ADDR_WIDTH,
data_buf_offset_width => DATA_BUF_OFFSET_WIDTH,
data_width => DATA_WIDTH,
dq_width => DQ_WIDTH,
ecc_width => ECC_WIDTH
)
port map (
-- Outputs
dfi_wrdata => dfi_wrdata_int20(4 * DQ_WIDTH - 1 downto 0),
dfi_wrdata_mask => dfi_wrdata_mask_int22(4 * DQ_WIDTH / 8 - 1 downto 0),
-- Inputs
clk => clk,
rst => rst_final,
wr_data => wr_data(4 * PAYLOAD_WIDTH - 1 downto 0),
wr_data_mask => wr_data_mask(4 * DATA_WIDTH / 8 - 1 downto 0),
rd_merge_data => rd_merge_data(4 * DATA_WIDTH - 1 downto 0),
h_rows => h_rows(CODE_WIDTH * ECC_WIDTH - 1 downto 0),
raw_not_ecc => raw_not_ecc(3 downto 0)
);
ecc_dec_fix0 : ecc_dec_fix
generic map (
tcq => TCQ,
payload_width => PAYLOAD_WIDTH,
code_width => CODE_WIDTH,
data_width => DATA_WIDTH,
dq_width => DQ_WIDTH,
ecc_width => ECC_WIDTH
)
port map (
-- Outputs
rd_data => rd_data_int28(4 * PAYLOAD_WIDTH - 1 downto 0),
ecc_single => ecc_single_int25(3 downto 0),
ecc_multiple => ecc_multiple_int24(3 downto 0),
-- Inputs
clk => clk,
rst => rst_final,
h_rows => h_rows(CODE_WIDTH * ECC_WIDTH - 1 downto 0),
dfi_rddata => dfi_rddata(4 * DQ_WIDTH - 1 downto 0),
correct_en => correct_en,
ecc_status_valid => ecc_status_valid
);
ecc_buf0 : ecc_buf
generic map (
tcq => TCQ,
payload_width => PAYLOAD_WIDTH,
data_buf_addr_width => DATA_BUF_ADDR_WIDTH,
data_buf_offset_width => DATA_BUF_OFFSET_WIDTH,
data_width => DATA_WIDTH
)
port map (
-- Outputs
rd_merge_data => rd_merge_data(4 * DATA_WIDTH - 1 downto 0),
-- Inputs
clk => clk,
rst => rst_final,
rd_data_addr => rd_data_addr_int29(DATA_BUF_ADDR_WIDTH - 1 downto 0),
rd_data_offset => rd_data_offset_int32(DATA_BUF_OFFSET_WIDTH - 1 downto 0),
wr_data_addr => wr_data_addr_ns(DATA_BUF_ADDR_WIDTH - 1 downto 0),
wr_data_offset => wr_data_offset_ns(DATA_BUF_OFFSET_WIDTH - 1 downto 0),
rd_data => rd_data_int28(4 * PAYLOAD_WIDTH - 1 downto 0),
wr_ecc_buf => wr_ecc_buf
);
ecc_gen0 : ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => DATA_WIDTH
)
port map (
-- Outputs
h_rows => h_rows(CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
end generate;
-- mc
end architecture trans;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:02:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0_1/system_ov7670_vga_1_0_stub.vhdl
-- Design : system_ov7670_vga_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_1_0 is
Port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_1_0;
architecture stub of system_ov7670_vga_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "pclk,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
|
entity test2 is end entity;
architecture arch of test2 is
signal b:bit;
-- alias bit_base is bit'base;
alias b_stable is b'stable;
begin
end architecture;
|
entity test2 is end entity;
architecture arch of test2 is
signal b:bit;
-- alias bit_base is bit'base;
alias b_stable is b'stable;
begin
end architecture;
|
entity test2 is end entity;
architecture arch of test2 is
signal b:bit;
-- alias bit_base is bit'base;
alias b_stable is b'stable;
begin
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity if_stage is
port(
clk : in vl_logic;
reset : in vl_logic;
spm_rd_data : in vl_logic_vector(31 downto 0);
spm_addr : out vl_logic_vector(29 downto 0);
spm_as_n : out vl_logic;
spm_rw : out vl_logic;
spm_wr_data : out vl_logic_vector(31 downto 0);
bus_rd_data : in vl_logic_vector(31 downto 0);
bus_rdy_n : in vl_logic;
bus_grant_n : in vl_logic;
bus_req_n : out vl_logic;
bus_addr : out vl_logic_vector(29 downto 0);
bus_as_n : out vl_logic;
bus_rw : out vl_logic;
bus_wr_data : out vl_logic_vector(31 downto 0);
stall : in vl_logic;
flush : in vl_logic;
new_pc : in vl_logic_vector(29 downto 0);
br_taken : in vl_logic;
br_addr : in vl_logic_vector(29 downto 0);
busy : out vl_logic;
if_pc : out vl_logic_vector(29 downto 0);
if_insn : out vl_logic_vector(31 downto 0);
if_en : out vl_logic
);
end if_stage;
|
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox_registers is
port(
Clk : in std_logic; -- Clock
Shift0In : in std_logic_vector(15 downto 0);
Shift1In : in std_logic_vector(15 downto 0);
Shift2In : in std_logic_vector(15 downto 0);
Shift3In : in std_logic_vector(15 downto 0);
Shift4In : in std_logic_vector(15 downto 0);
Shift0Out : out std_logic_vector(15 downto 0);
Shift1Out : out std_logic_vector(15 downto 0);
Shift2Out : out std_logic_vector(15 downto 0);
Shift3Out : out std_logic_vector(15 downto 0);
Shift4Out : out std_logic_vector(15 downto 0);
load0in : in std_logic_vector(63 downto 0);
load1in : in std_logic_vector(63 downto 0);
load2in : in std_logic_vector(63 downto 0);
load3in : in std_logic_vector(63 downto 0);
load4in : in std_logic_vector(63 downto 0);
load0out : out std_logic_vector(63 downto 0);
load1out : out std_logic_vector(63 downto 0);
load2out : out std_logic_vector(63 downto 0);
load3out : out std_logic_vector(63 downto 0);
load4out : out std_logic_vector(63 downto 0);
Sel : in std_logic_vector(1 downto 0);
ShiftEnable : in std_logic;
Reg0En : in std_logic;
Reg1En : in std_logic;
Reg2En : in std_logic;
Reg3En : in std_logic;
Reg4En : in std_logic
);
end entity Sbox_registers;
architecture structural of Sbox_registers is
signal Part0_0, Part0_1, Part0_2, Part0_3 : std_logic_vector(15 downto 0);
signal Part1_0, Part1_1, Part1_2, Part1_3 : std_logic_vector(15 downto 0);
signal Part2_0, Part2_1, Part2_2, Part2_3 : std_logic_vector(15 downto 0);
signal Part3_0, Part3_1, Part3_2, Part3_3 : std_logic_vector(15 downto 0);
signal Part4_0, Part4_1, Part4_2, Part4_3 : std_logic_vector(15 downto 0);
begin
----------------------------------
------ Combinatorial logic ------
----------------------------------
datapath: process(Part0_0, Part0_1, Part0_2, Part0_3, Part1_0, Part1_1, Part1_2, Part1_3, Part2_0, Part2_1, Part2_2, Part2_3,
Part3_0, Part3_1, Part3_2, Part3_3, Part4_0, Part4_1, Part4_2, Part4_3, Sel) is
begin
load0out <= Part0_0 & Part0_1 & Part0_2 & Part0_3;
load1out <= Part1_0 & Part1_1 & Part1_2 & Part1_3;
load2out <= Part2_0 & Part2_1 & Part2_2 & Part2_3;
load3out <= Part3_0 & Part3_1 & Part3_2 & Part3_3;
load4out <= Part4_0 & Part4_1 & Part4_2 & Part4_3;
if Sel = "00" then
Shift0Out <= Part0_0;
Shift1Out <= Part1_0;
Shift2Out <= Part2_0;
Shift3Out <= Part3_0;
Shift4Out <= Part4_0;
elsif Sel = "01" then
Shift0Out <= Part0_1;
Shift1Out <= Part1_1;
Shift2Out <= Part2_1;
Shift3Out <= Part3_1;
Shift4Out <= Part4_1;
elsif Sel = "10" then
Shift0Out <= Part0_2;
Shift1Out <= Part1_2;
Shift2Out <= Part2_2;
Shift3Out <= Part3_2;
Shift4Out <= Part4_2;
else
Shift0Out <= Part0_3;
Shift1Out <= Part1_3;
Shift2Out <= Part2_3;
Shift3Out <= Part3_3;
Shift4Out <= Part4_3;
end if;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk) is
begin
if(Clk = '1' and Clk'event) then
if ShiftEnable = '1' then
if Sel = "00" then
Part0_0 <= Shift0In;
Part1_0 <= Shift1In;
Part2_0 <= Shift2In;
Part3_0 <= Shift3In;
Part4_0 <= Shift4In;
elsif Sel = "01" then
Part0_1 <= Shift0In;
Part1_1 <= Shift1In;
Part2_1 <= Shift2In;
Part3_1 <= Shift3In;
Part4_1 <= Shift4In;
elsif Sel = "10" then
Part0_2 <= Shift0In;
Part1_2 <= Shift1In;
Part2_2 <= Shift2In;
Part3_2 <= Shift3In;
Part4_2 <= Shift4In;
elsif Sel = "11" then
Part0_3 <= Shift0In;
Part1_3 <= Shift1In;
Part2_3 <= Shift2In;
Part3_3 <= Shift3In;
Part4_3 <= Shift4In;
end if;
else
if Reg0En = '1' then
Part0_0 <= load0in(63 downto 48);
Part0_1 <= load0in(47 downto 32);
Part0_2 <= load0in(31 downto 16);
Part0_3 <= load0in(15 downto 0);
end if;
if Reg1En = '1' then
Part1_0 <= load1in(63 downto 48);
Part1_1 <= load1in(47 downto 32);
Part1_2 <= load1in(31 downto 16);
Part1_3 <= load1in(15 downto 0);
end if;
if Reg2En = '1' then
Part2_0 <= load2in(63 downto 48);
Part2_1 <= load2in(47 downto 32);
Part2_2 <= load2in(31 downto 16);
Part2_3 <= load2in(15 downto 0);
end if;
if Reg3En = '1' then
Part3_0 <= load3in(63 downto 48);
Part3_1 <= load3in(47 downto 32);
Part3_2 <= load3in(31 downto 16);
Part3_3 <= load3in(15 downto 0);
end if;
if Reg4En = '1' then
Part4_0 <= load4in(63 downto 48);
Part4_1 <= load4in(47 downto 32);
Part4_2 <= load4in(31 downto 16);
Part4_3 <= load4in(15 downto 0);
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdram is
port
(
sdata : inout std_logic_vector(15 downto 0);
sdaddr : out std_logic_vector(11 downto 0);
dqm : out std_logic_vector(1 downto 0);
sd_cs : out std_logic_vector(3 downto 0);
ba : buffer std_logic_vector(1 downto 0);
sd_we : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sysclk : in std_logic;
reset_in : in std_logic;
hostWR : in std_logic_vector(15 downto 0);
hostAddr : in std_logic_vector(23 downto 0);
hostState : in std_logic_vector(2 downto 0);
hostL : in std_logic;
hostU : in std_logic;
cpuWR : in std_logic_vector(15 downto 0);
cpuAddr : in std_logic_vector(24 downto 1);
cpuU : in std_logic;
cpuL : in std_logic;
cpustate : in std_logic_vector(5 downto 0);
cpu_dma : in std_logic;
chipWR : in std_logic_vector(15 downto 0);
chipAddr : in std_logic_vector(23 downto 1);
chipU : in std_logic;
chipL : in std_logic;
chipRW : in std_logic;
chip_dma : in std_logic;
c_7m : in std_logic;
hostRD : out std_logic_vector(15 downto 0);
hostena : buffer std_logic;
cpuRD : out std_logic_vector(15 downto 0);
cpuena : out std_logic;
chipRD : out std_logic_vector(15 downto 0);
reset_out : out std_logic;
enaRDreg : out std_logic;
enaWRreg : buffer std_logic;
ena7RDreg : out std_logic;
ena7WRreg : out std_logic
-- c_7m : out std_logic
);
end;
architecture rtl of sdram is
signal initstate :std_logic_vector(3 downto 0);
signal cas_sd_cs :std_logic_vector(3 downto 0);
signal cas_sd_ras :std_logic;
signal cas_sd_cas :std_logic;
signal cas_sd_we :std_logic;
signal cas_dqm :std_logic_vector(1 downto 0);
signal init_done :std_logic;
signal datain :std_logic_vector(15 downto 0);
signal datawr :std_logic_vector(15 downto 0);
signal casaddr :std_logic_vector(24 downto 0);
signal sdwrite :std_logic;
signal sdata_reg :std_logic_vector(15 downto 0);
signal hostCycle :std_logic;
signal zmAddr :std_logic_vector(24 downto 0);
signal zena :std_logic;
signal zcache :std_logic_vector(63 downto 0);
signal zcache_addr :std_logic_vector(23 downto 0);
signal zcache_fill :std_logic;
signal zcachehit :std_logic;
signal zvalid :std_logic_vector(3 downto 0);
signal zequal :std_logic;
signal hostStated :std_logic_vector(1 downto 0);
signal hostRDd :std_logic_vector(15 downto 0);
signal cena :std_logic;
signal ccache :std_logic_vector(63 downto 0);
signal ccache_addr :std_logic_vector(24 downto 0);
signal ccache_fill :std_logic;
signal ccachehit :std_logic;
signal cvalid :std_logic_vector(3 downto 0);
signal cequal :std_logic;
signal cpuStated :std_logic_vector(1 downto 0);
signal cpuRDd :std_logic_vector(15 downto 0);
signal hostSlot_cnt :std_logic_vector(7 downto 0);
signal reset_cnt :std_logic_vector(7 downto 0);
signal reset :std_logic;
signal reset_sdstate :std_logic;
signal c_7md :std_logic;
signal c_7mdd :std_logic;
signal c_7mdr :std_logic;
signal cpuCycle :std_logic;
signal chipCycle :std_logic;
signal slow :std_logic_vector(7 downto 0);
type sdram_states is (ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7,ph8,ph9,ph10,ph11,ph12,ph13,ph14,ph15);
signal sdram_state : sdram_states;
type pass_states is (nop,ras,cas);
signal pass : pass_states;
signal tst_adr1 :std_logic_vector(3 downto 0);
signal tst_adr2 :std_logic_vector(3 downto 0);
begin
process (sysclk, reset_in) begin
if reset_in = '0' THEN
reset_cnt <= "00000000";
reset <= '0';
reset_sdstate <= '0';
elsif (sysclk'event and sysclk='1') THEN
IF reset_cnt="00101010"THEN
reset_sdstate <= '1';
END IF;
IF reset_cnt="10101010"THEN
if sdram_state=ph15 then
reset <= '1';
end if;
ELSE
reset_cnt <= reset_cnt+1;
reset <= '0';
END IF;
end if;
end process;
-------------------------------------------------------------------------
-- SPIHOST cache
-------------------------------------------------------------------------
hostena <= '1' when zena='1' or hostState(1 downto 0)="01" OR zcachehit='1' else '0';
zmAddr <= '0'& NOT hostAddr(23) & hostAddr(22) & NOT hostAddr(21) & hostAddr(20 downto 0);
tst_adr1 <= hostAddr(2 downto 1)&zcache_addr(2 downto 1);
process (sysclk, zmAddr, hostAddr, zcache_addr, zcache, zequal, zvalid, hostRDd, hostStated, tst_adr1)
begin
if zmAddr(23 downto 3)=zcache_addr(23 downto 3) THEN
zequal <='1';
else
zequal <='0';
end if;
zcachehit <= '0';
if zequal='1' and zvalid(0)='1' and hostStated(1)='0' THEN
-- case (hostAddr(2 downto 1)-zcache_addr(2 downto 1)) is
-- when "00"=>
-- zcachehit <= zvalid(0);
-- hostRD <= zcache(63 downto 48);
-- when "01"=>
-- zcachehit <= zvalid(1);
-- hostRD <= zcache(47 downto 32);
-- when "10"=>
-- zcachehit <= zvalid(2);
-- hostRD <= zcache(31 downto 16);
-- when "11"=>
-- zcachehit <= zvalid(3);
-- hostRD <= zcache(15 downto 0);
-- when others=> null;
-- end case;
case (tst_adr1) is
when "0000"|"0101"|"1010"|"1111"=>
zcachehit <= zvalid(0);
hostRD <= zcache(63 downto 48);
when "0100"|"1001"|"1110"|"0011"=>
zcachehit <= zvalid(1);
hostRD <= zcache(47 downto 32);
when "1000"|"1101"|"0010"|"0111"=>
zcachehit <= zvalid(2);
hostRD <= zcache(31 downto 16);
when "1100"|"0001"|"0110"|"1011"=>
zcachehit <= zvalid(3);
hostRD <= zcache(15 downto 0);
when others=> null;
end case;
else
hostRD <= hostRDd;
end if;
end process;
--Datenübernahme
process (sysclk, reset) begin
if reset = '0' THEN
zcache_fill <= '0';
zena <= '0';
zvalid <= "0000";
elsif (sysclk'event and sysclk='1') THEN
if enaWRreg='1' THEN
zena <= '0';
end if;
if sdram_state=ph9 AND hostCycle='1' THEN
hostRDd <= sdata_reg;
-- if zmAddr=casaddr and cas_sd_cas='0' then
-- zena <= '1';
-- end if;
end if;
if sdram_state=ph11 AND hostCycle='1' THEN
-- hostRDd <= sdata_reg;
if zmAddr=casaddr and cas_sd_cas='0' then
zena <= '1';
end if;
end if;
hostStated <= hostState(1 downto 0);
if zequal='1' and hostState(1 downto 0)="11" THEN
zvalid <= "0000";
end if;
case sdram_state is
when ph7 =>
if hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostCycle='1' THEN
zcache_addr <= casaddr(23 downto 0);
zcache_fill <= '1';
zvalid <= "0000";
end if;
when ph9 =>
if zcache_fill='1' THEN
zcache(63 downto 48) <= sdata_reg;
-- zvalid(0) <= '1';
end if;
when ph10 =>
if zcache_fill='1' THEN
zcache(47 downto 32) <= sdata_reg;
-- zvalid(1) <= '1';
end if;
when ph11 =>
if zcache_fill='1' THEN
zcache(31 downto 16) <= sdata_reg;
-- zvalid(2) <= '1';
end if;
-- zena <= '0';
when ph12 =>
if zcache_fill='1' THEN
zcache(15 downto 0) <= sdata_reg;
-- zvalid(3) <= '1';
zvalid <= "1111";
end if;
zcache_fill <= '0';
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- cpu cache
-------------------------------------------------------------------------
cpuena <= '1' when cena='1' or ccachehit='1' else '0';
tst_adr2 <= cpuAddr(2 downto 1)&ccache_addr(2 downto 1);
process (sysclk, cpuAddr, ccache_addr, ccache, cequal, cvalid, cpuRDd, cpuStated, tst_adr2)
begin
if cpuAddr(24 downto 3)=ccache_addr(24 downto 3) THEN
cequal <='1';
else
cequal <='0';
end if;
ccachehit <= '0';
if cequal='1' and cvalid(0)='1' and cpuStated(1)='0' THEN
-- case (cpuAddr(2 downto 1)-ccache_addr(2 downto 1)) is
-- when "00"=>
-- ccachehit <= cvalid(0);
-- cpuRD <= ccache(63 downto 48);
-- when "01"=>
-- ccachehit <= cvalid(1);
-- cpuRD <= ccache(47 downto 32);
-- when "10"=>
-- ccachehit <= cvalid(2);
-- cpuRD <= ccache(31 downto 16);
-- when "11"=>
-- ccachehit <= cvalid(3);
-- cpuRD <= ccache(15 downto 0);
-- when others=> null;
-- end case;
case (tst_adr2) is
when "0000"|"0101"|"1010"|"1111"=>
ccachehit <= cvalid(0);
cpuRD <= ccache(63 downto 48);
when "0100"|"1001"|"1110"|"0011"=>
ccachehit <= cvalid(1);
cpuRD <= ccache(47 downto 32);
when "1000"|"1101"|"0010"|"0111"=>
ccachehit <= cvalid(2);
cpuRD <= ccache(31 downto 16);
when "1100"|"0001"|"0110"|"1011"=>
ccachehit <= cvalid(3);
cpuRD <= ccache(15 downto 0);
when others=> null;
end case;
else
cpuRD <= cpuRDd;
end if;
end process;
--Datenübernahme
process (sysclk, reset) begin
if reset = '0' THEN
ccache_fill <= '0';
cena <= '0';
cvalid <= "0000";
elsif (sysclk'event and sysclk='1') THEN
if cpuState(5)='1' THEN
cena <= '0';
end if;
if sdram_state=ph9 AND cpuCycle='1' THEN
cpuRDd <= sdata_reg;
-- if cpuAddr=casaddr(24 downto 1) and cas_sd_cas='0' then
-- cena <= '1';
-- end if;
end if;
if sdram_state=ph11 AND cpuCycle='1' THEN
-- cpuRDd <= sdata_reg;
if cpuAddr=casaddr(24 downto 1) and cas_sd_cas='0' then
cena <= '1';
end if;
end if;
cpuStated <= cpuState(1 downto 0);
if cequal='1' and cpuState(1 downto 0)="11" THEN
cvalid <= "0000";
end if;
case sdram_state is
when ph7 =>
if cpuStated(1)='0' AND cpuCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostCycle='1' THEN
ccache_addr <= casaddr;
ccache_fill <= '1';
cvalid <= "0000";
end if;
when ph9 =>
if ccache_fill='1' THEN
ccache(63 downto 48) <= sdata_reg;
-- cvalid(0) <= '1';
end if;
when ph10 =>
if ccache_fill='1' THEN
ccache(47 downto 32) <= sdata_reg;
-- cvalid(1) <= '1';
end if;
when ph11 =>
if ccache_fill='1' THEN
ccache(31 downto 16) <= sdata_reg;
-- cvalid(2) <= '1';
end if;
when ph12 =>
if ccache_fill='1' THEN
ccache(15 downto 0) <= sdata_reg;
-- cvalid(3) <= '1';
cvalid <= "1111";
end if;
ccache_fill <= '0';
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- chip cache
-------------------------------------------------------------------------
process (sysclk, sdata_reg)
begin
if (sysclk'event and sysclk='1') THEN
if sdram_state=ph9 AND chipCycle='1' THEN
chipRD <= sdata_reg;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- SDRAM Basic
-------------------------------------------------------------------------
reset_out <= init_done;
process (sysclk, reset, sdwrite, datain, datawr) begin
IF sdwrite='1' THEN
sdata <= datawr;
ELSE
sdata <= "ZZZZZZZZZZZZZZZZ";
END IF;
if (sysclk'event and sysclk='0') THEN
c_7md <= c_7m;
END IF;
if (sysclk'event and sysclk='1') THEN
if sdram_state=ph2 THEN
IF chipCycle='1' THEN
datawr <= chipWR;
ELSIF cpuCycle='1' THEN
datawr <= cpuWR;
ELSE
datawr <= hostWR;
END IF;
END IF;
sdata_reg <= sdata;
c_7mdd <= c_7md;
c_7mdr <= c_7md AND NOT c_7mdd;
if reset_sdstate = '0' then
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
ELSE
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
case sdram_state is --LATENCY=3
when ph2 => sdwrite <= '1';
enaWRreg <= '1';
when ph3 => sdwrite <= '1';
when ph4 => sdwrite <= '1';
when ph5 => sdwrite <= '1';
when ph6 => enaWRreg <= '1';
ena7RDreg <= '1';
-- when ph7 => c_7m <= '0';
when ph10 => enaWRreg <= '1';
when ph14 => enaWRreg <= '1';
ena7WRreg <= '1';
-- when ph15 => c_7m <= '1';
when others => null;
end case;
END IF;
if reset = '0' then
initstate <= (others => '0');
init_done <= '0';
ELSE
case sdram_state is --LATENCY=3
when ph15 => if initstate /= "1111" THEN
initstate <= initstate+1;
else
init_done <='1';
end if;
when others => null;
end case;
END IF;
IF c_7mdr='1' THEN
sdram_state <= ph2;
-- if reset_sdstate = '0' then
-- sdram_state <= ph0;
ELSE
case sdram_state is --LATENCY=3
when ph0 => sdram_state <= ph1;
when ph1 => sdram_state <= ph2;
-- when ph1 =>
-- IF c_28md='1' THEN
-- sdram_state <= ph2;
-- ELSE
-- sdram_state <= ph1;
-- END IF;
when ph2 => sdram_state <= ph3;
-- when ph2 => --sdram_state <= ph3;
-- IF c_28md='0' THEN
-- sdram_state <= ph3;
-- ELSE
-- sdram_state <= ph2;
-- END IF;
when ph3 => sdram_state <= ph4;
when ph4 => sdram_state <= ph5;
when ph5 => sdram_state <= ph6;
when ph6 => sdram_state <= ph7;
when ph7 => sdram_state <= ph8;
when ph8 => sdram_state <= ph9;
when ph9 => sdram_state <= ph10;
when ph10 => sdram_state <= ph11;
when ph11 => sdram_state <= ph12;
when ph12 => sdram_state <= ph13;
when ph13 => sdram_state <= ph14;
when ph14 => sdram_state <= ph15;
-- when ph15 => sdram_state <= ph0;
when others => sdram_state <= ph0;
end case;
END IF;
END IF;
end process;
process (sysclk, initstate, pass, hostAddr, datain, init_done, casaddr, cpuU, cpuL, hostCycle) begin
if (sysclk'event and sysclk='1') THEN
sd_cs <="1111";
sd_ras <= '1';
sd_cas <= '1';
sd_we <= '1';
sdaddr <= "XXXXXXXXXXXX";
ba <= "00";
dqm <= "00";
if init_done='0' then
if sdram_state =ph1 then
case initstate is
when "0010" => --PRECHARGE
sdaddr(10) <= '1'; --all banks
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '1';
sd_we <= '0';
when "0011"|"0100"|"0101"|"0110"|"0111"|"1000"|"1001"|"1010"|"1011"|"1100" => --AUTOREFRESH
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '1';
when "1101" => --LOAD MODE REGISTER
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '0';
-- ba <= "00";
-- sdaddr <= "001000100010"; --BURST=4 LATENCY=2
sdaddr <= "001000110010"; --BURST=4 LATENCY=3
when others => null; --NOP
end case;
END IF;
else
-- Time slot control
if sdram_state=ph1 THEN
cpuCycle <= '0';
chipCycle <= '0';
hostCycle <= '0';
cas_sd_cs <= "1110";
cas_sd_ras <= '1';
cas_sd_cas <= '1';
cas_sd_we <= '1';
IF slow(2 downto 0)=5 THEN
slow <= slow+3;
ELSE
slow <= slow+1;
END IF;
-- IF dma='0' OR cpu_dma='0' THEN
IF hostSlot_cnt /= "00000000" THEN
hostSlot_cnt <= hostSlot_cnt-1;
END IF;
-- IF chip_dma='1' THEN
IF chip_dma='0' OR chipRW='0' THEN
chipCycle <= '1';
sdaddr <= chipAddr(20 downto 9);
-- ba <= "00";
ba <= chipAddr(22 downto 21);
-- cas_dqm <= "00"; --only word access
cas_dqm <= chipU& chipL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= '0'&chipAddr&'0';
datain <= chipWR;
cas_sd_cas <= '0';
cas_sd_we <= chipRW;
-- ELSIF cpu_dma='1' AND hostSlot_cnt /= "00000000" THEN
-- ELSIF cpu_dma='0' OR cpuRW='0' THEN
ELSIF cpuState(2)='0' AND cpuState(5)='0' THEN
cpuCycle <= '1';
sdaddr <= cpuAddr(20 downto 9);
ba <= cpuAddr(22 downto 21);
cas_dqm <= cpuU& cpuL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= cpuAddr(24 downto 1)&'0';
datain <= cpuWR;
cas_sd_cas <= '0';
cas_sd_we <= NOT cpuState(1) OR NOT cpuState(0);
ELSE
hostSlot_cnt <= "00001111";
-- ELSIF hostState(2)='1' OR hostena='1' OR slow(3 downto 0)="0001" THEN --refresh cycle
IF hostState(2)='1' OR hostena='1' THEN --refresh cycle
-- ELSIF slow(3 downto 0)="0001" THEN --refresh cycle
sd_cs <="0000"; --AUTOREFRESH
sd_ras <= '0';
sd_cas <= '0';
ELSE
hostCycle <= '1';
sdaddr <= zmAddr(20 downto 9);
ba <= zmAddr(22 downto 21);
cas_dqm <= hostU& hostL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= zmAddr;
datain <= hostWR;
cas_sd_cas <= '0';
IF hostState="011" THEN
cas_sd_we <= '0';
-- dqm <= hostU& hostL;
END IF;
END IF;
END IF;
END IF;
if sdram_state=ph4 then
sdaddr <= '0' & '1' & '0' & casaddr(23)&casaddr(8 downto 1);--auto precharge
ba <= casaddr(22 downto 21);
sd_cs <= cas_sd_cs;
IF cas_sd_we='0' THEN
dqm <= cas_dqm;
END IF;
sd_ras <= cas_sd_ras;
sd_cas <= cas_sd_cas;
sd_we <= cas_sd_we;
END IF;
END IF;
END IF;
END process;
END;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdram is
port
(
sdata : inout std_logic_vector(15 downto 0);
sdaddr : out std_logic_vector(11 downto 0);
dqm : out std_logic_vector(1 downto 0);
sd_cs : out std_logic_vector(3 downto 0);
ba : buffer std_logic_vector(1 downto 0);
sd_we : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sysclk : in std_logic;
reset_in : in std_logic;
hostWR : in std_logic_vector(15 downto 0);
hostAddr : in std_logic_vector(23 downto 0);
hostState : in std_logic_vector(2 downto 0);
hostL : in std_logic;
hostU : in std_logic;
cpuWR : in std_logic_vector(15 downto 0);
cpuAddr : in std_logic_vector(24 downto 1);
cpuU : in std_logic;
cpuL : in std_logic;
cpustate : in std_logic_vector(5 downto 0);
cpu_dma : in std_logic;
chipWR : in std_logic_vector(15 downto 0);
chipAddr : in std_logic_vector(23 downto 1);
chipU : in std_logic;
chipL : in std_logic;
chipRW : in std_logic;
chip_dma : in std_logic;
c_7m : in std_logic;
hostRD : out std_logic_vector(15 downto 0);
hostena : buffer std_logic;
cpuRD : out std_logic_vector(15 downto 0);
cpuena : out std_logic;
chipRD : out std_logic_vector(15 downto 0);
reset_out : out std_logic;
enaRDreg : out std_logic;
enaWRreg : buffer std_logic;
ena7RDreg : out std_logic;
ena7WRreg : out std_logic
-- c_7m : out std_logic
);
end;
architecture rtl of sdram is
signal initstate :std_logic_vector(3 downto 0);
signal cas_sd_cs :std_logic_vector(3 downto 0);
signal cas_sd_ras :std_logic;
signal cas_sd_cas :std_logic;
signal cas_sd_we :std_logic;
signal cas_dqm :std_logic_vector(1 downto 0);
signal init_done :std_logic;
signal datain :std_logic_vector(15 downto 0);
signal datawr :std_logic_vector(15 downto 0);
signal casaddr :std_logic_vector(24 downto 0);
signal sdwrite :std_logic;
signal sdata_reg :std_logic_vector(15 downto 0);
signal hostCycle :std_logic;
signal zmAddr :std_logic_vector(24 downto 0);
signal zena :std_logic;
signal zcache :std_logic_vector(63 downto 0);
signal zcache_addr :std_logic_vector(23 downto 0);
signal zcache_fill :std_logic;
signal zcachehit :std_logic;
signal zvalid :std_logic_vector(3 downto 0);
signal zequal :std_logic;
signal hostStated :std_logic_vector(1 downto 0);
signal hostRDd :std_logic_vector(15 downto 0);
signal cena :std_logic;
signal ccache :std_logic_vector(63 downto 0);
signal ccache_addr :std_logic_vector(24 downto 0);
signal ccache_fill :std_logic;
signal ccachehit :std_logic;
signal cvalid :std_logic_vector(3 downto 0);
signal cequal :std_logic;
signal cpuStated :std_logic_vector(1 downto 0);
signal cpuRDd :std_logic_vector(15 downto 0);
signal hostSlot_cnt :std_logic_vector(7 downto 0);
signal reset_cnt :std_logic_vector(7 downto 0);
signal reset :std_logic;
signal reset_sdstate :std_logic;
signal c_7md :std_logic;
signal c_7mdd :std_logic;
signal c_7mdr :std_logic;
signal cpuCycle :std_logic;
signal chipCycle :std_logic;
signal slow :std_logic_vector(7 downto 0);
type sdram_states is (ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7,ph8,ph9,ph10,ph11,ph12,ph13,ph14,ph15);
signal sdram_state : sdram_states;
type pass_states is (nop,ras,cas);
signal pass : pass_states;
signal tst_adr1 :std_logic_vector(3 downto 0);
signal tst_adr2 :std_logic_vector(3 downto 0);
begin
process (sysclk, reset_in) begin
if reset_in = '0' THEN
reset_cnt <= "00000000";
reset <= '0';
reset_sdstate <= '0';
elsif (sysclk'event and sysclk='1') THEN
IF reset_cnt="00101010"THEN
reset_sdstate <= '1';
END IF;
IF reset_cnt="10101010"THEN
if sdram_state=ph15 then
reset <= '1';
end if;
ELSE
reset_cnt <= reset_cnt+1;
reset <= '0';
END IF;
end if;
end process;
-------------------------------------------------------------------------
-- SPIHOST cache
-------------------------------------------------------------------------
hostena <= '1' when zena='1' or hostState(1 downto 0)="01" OR zcachehit='1' else '0';
zmAddr <= '0'& NOT hostAddr(23) & hostAddr(22) & NOT hostAddr(21) & hostAddr(20 downto 0);
tst_adr1 <= hostAddr(2 downto 1)&zcache_addr(2 downto 1);
process (sysclk, zmAddr, hostAddr, zcache_addr, zcache, zequal, zvalid, hostRDd, hostStated, tst_adr1)
begin
if zmAddr(23 downto 3)=zcache_addr(23 downto 3) THEN
zequal <='1';
else
zequal <='0';
end if;
zcachehit <= '0';
if zequal='1' and zvalid(0)='1' and hostStated(1)='0' THEN
-- case (hostAddr(2 downto 1)-zcache_addr(2 downto 1)) is
-- when "00"=>
-- zcachehit <= zvalid(0);
-- hostRD <= zcache(63 downto 48);
-- when "01"=>
-- zcachehit <= zvalid(1);
-- hostRD <= zcache(47 downto 32);
-- when "10"=>
-- zcachehit <= zvalid(2);
-- hostRD <= zcache(31 downto 16);
-- when "11"=>
-- zcachehit <= zvalid(3);
-- hostRD <= zcache(15 downto 0);
-- when others=> null;
-- end case;
case (tst_adr1) is
when "0000"|"0101"|"1010"|"1111"=>
zcachehit <= zvalid(0);
hostRD <= zcache(63 downto 48);
when "0100"|"1001"|"1110"|"0011"=>
zcachehit <= zvalid(1);
hostRD <= zcache(47 downto 32);
when "1000"|"1101"|"0010"|"0111"=>
zcachehit <= zvalid(2);
hostRD <= zcache(31 downto 16);
when "1100"|"0001"|"0110"|"1011"=>
zcachehit <= zvalid(3);
hostRD <= zcache(15 downto 0);
when others=> null;
end case;
else
hostRD <= hostRDd;
end if;
end process;
--Datenübernahme
process (sysclk, reset) begin
if reset = '0' THEN
zcache_fill <= '0';
zena <= '0';
zvalid <= "0000";
elsif (sysclk'event and sysclk='1') THEN
if enaWRreg='1' THEN
zena <= '0';
end if;
if sdram_state=ph9 AND hostCycle='1' THEN
hostRDd <= sdata_reg;
-- if zmAddr=casaddr and cas_sd_cas='0' then
-- zena <= '1';
-- end if;
end if;
if sdram_state=ph11 AND hostCycle='1' THEN
-- hostRDd <= sdata_reg;
if zmAddr=casaddr and cas_sd_cas='0' then
zena <= '1';
end if;
end if;
hostStated <= hostState(1 downto 0);
if zequal='1' and hostState(1 downto 0)="11" THEN
zvalid <= "0000";
end if;
case sdram_state is
when ph7 =>
if hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostCycle='1' THEN
zcache_addr <= casaddr(23 downto 0);
zcache_fill <= '1';
zvalid <= "0000";
end if;
when ph9 =>
if zcache_fill='1' THEN
zcache(63 downto 48) <= sdata_reg;
-- zvalid(0) <= '1';
end if;
when ph10 =>
if zcache_fill='1' THEN
zcache(47 downto 32) <= sdata_reg;
-- zvalid(1) <= '1';
end if;
when ph11 =>
if zcache_fill='1' THEN
zcache(31 downto 16) <= sdata_reg;
-- zvalid(2) <= '1';
end if;
-- zena <= '0';
when ph12 =>
if zcache_fill='1' THEN
zcache(15 downto 0) <= sdata_reg;
-- zvalid(3) <= '1';
zvalid <= "1111";
end if;
zcache_fill <= '0';
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- cpu cache
-------------------------------------------------------------------------
cpuena <= '1' when cena='1' or ccachehit='1' else '0';
tst_adr2 <= cpuAddr(2 downto 1)&ccache_addr(2 downto 1);
process (sysclk, cpuAddr, ccache_addr, ccache, cequal, cvalid, cpuRDd, cpuStated, tst_adr2)
begin
if cpuAddr(24 downto 3)=ccache_addr(24 downto 3) THEN
cequal <='1';
else
cequal <='0';
end if;
ccachehit <= '0';
if cequal='1' and cvalid(0)='1' and cpuStated(1)='0' THEN
-- case (cpuAddr(2 downto 1)-ccache_addr(2 downto 1)) is
-- when "00"=>
-- ccachehit <= cvalid(0);
-- cpuRD <= ccache(63 downto 48);
-- when "01"=>
-- ccachehit <= cvalid(1);
-- cpuRD <= ccache(47 downto 32);
-- when "10"=>
-- ccachehit <= cvalid(2);
-- cpuRD <= ccache(31 downto 16);
-- when "11"=>
-- ccachehit <= cvalid(3);
-- cpuRD <= ccache(15 downto 0);
-- when others=> null;
-- end case;
case (tst_adr2) is
when "0000"|"0101"|"1010"|"1111"=>
ccachehit <= cvalid(0);
cpuRD <= ccache(63 downto 48);
when "0100"|"1001"|"1110"|"0011"=>
ccachehit <= cvalid(1);
cpuRD <= ccache(47 downto 32);
when "1000"|"1101"|"0010"|"0111"=>
ccachehit <= cvalid(2);
cpuRD <= ccache(31 downto 16);
when "1100"|"0001"|"0110"|"1011"=>
ccachehit <= cvalid(3);
cpuRD <= ccache(15 downto 0);
when others=> null;
end case;
else
cpuRD <= cpuRDd;
end if;
end process;
--Datenübernahme
process (sysclk, reset) begin
if reset = '0' THEN
ccache_fill <= '0';
cena <= '0';
cvalid <= "0000";
elsif (sysclk'event and sysclk='1') THEN
if cpuState(5)='1' THEN
cena <= '0';
end if;
if sdram_state=ph9 AND cpuCycle='1' THEN
cpuRDd <= sdata_reg;
-- if cpuAddr=casaddr(24 downto 1) and cas_sd_cas='0' then
-- cena <= '1';
-- end if;
end if;
if sdram_state=ph11 AND cpuCycle='1' THEN
-- cpuRDd <= sdata_reg;
if cpuAddr=casaddr(24 downto 1) and cas_sd_cas='0' then
cena <= '1';
end if;
end if;
cpuStated <= cpuState(1 downto 0);
if cequal='1' and cpuState(1 downto 0)="11" THEN
cvalid <= "0000";
end if;
case sdram_state is
when ph7 =>
if cpuStated(1)='0' AND cpuCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostCycle='1' THEN
ccache_addr <= casaddr;
ccache_fill <= '1';
cvalid <= "0000";
end if;
when ph9 =>
if ccache_fill='1' THEN
ccache(63 downto 48) <= sdata_reg;
-- cvalid(0) <= '1';
end if;
when ph10 =>
if ccache_fill='1' THEN
ccache(47 downto 32) <= sdata_reg;
-- cvalid(1) <= '1';
end if;
when ph11 =>
if ccache_fill='1' THEN
ccache(31 downto 16) <= sdata_reg;
-- cvalid(2) <= '1';
end if;
when ph12 =>
if ccache_fill='1' THEN
ccache(15 downto 0) <= sdata_reg;
-- cvalid(3) <= '1';
cvalid <= "1111";
end if;
ccache_fill <= '0';
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- chip cache
-------------------------------------------------------------------------
process (sysclk, sdata_reg)
begin
if (sysclk'event and sysclk='1') THEN
if sdram_state=ph9 AND chipCycle='1' THEN
chipRD <= sdata_reg;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- SDRAM Basic
-------------------------------------------------------------------------
reset_out <= init_done;
process (sysclk, reset, sdwrite, datain, datawr) begin
IF sdwrite='1' THEN
sdata <= datawr;
ELSE
sdata <= "ZZZZZZZZZZZZZZZZ";
END IF;
if (sysclk'event and sysclk='0') THEN
c_7md <= c_7m;
END IF;
if (sysclk'event and sysclk='1') THEN
if sdram_state=ph2 THEN
IF chipCycle='1' THEN
datawr <= chipWR;
ELSIF cpuCycle='1' THEN
datawr <= cpuWR;
ELSE
datawr <= hostWR;
END IF;
END IF;
sdata_reg <= sdata;
c_7mdd <= c_7md;
c_7mdr <= c_7md AND NOT c_7mdd;
if reset_sdstate = '0' then
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
ELSE
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
case sdram_state is --LATENCY=3
when ph2 => sdwrite <= '1';
enaWRreg <= '1';
when ph3 => sdwrite <= '1';
when ph4 => sdwrite <= '1';
when ph5 => sdwrite <= '1';
when ph6 => enaWRreg <= '1';
ena7RDreg <= '1';
-- when ph7 => c_7m <= '0';
when ph10 => enaWRreg <= '1';
when ph14 => enaWRreg <= '1';
ena7WRreg <= '1';
-- when ph15 => c_7m <= '1';
when others => null;
end case;
END IF;
if reset = '0' then
initstate <= (others => '0');
init_done <= '0';
ELSE
case sdram_state is --LATENCY=3
when ph15 => if initstate /= "1111" THEN
initstate <= initstate+1;
else
init_done <='1';
end if;
when others => null;
end case;
END IF;
IF c_7mdr='1' THEN
sdram_state <= ph2;
-- if reset_sdstate = '0' then
-- sdram_state <= ph0;
ELSE
case sdram_state is --LATENCY=3
when ph0 => sdram_state <= ph1;
when ph1 => sdram_state <= ph2;
-- when ph1 =>
-- IF c_28md='1' THEN
-- sdram_state <= ph2;
-- ELSE
-- sdram_state <= ph1;
-- END IF;
when ph2 => sdram_state <= ph3;
-- when ph2 => --sdram_state <= ph3;
-- IF c_28md='0' THEN
-- sdram_state <= ph3;
-- ELSE
-- sdram_state <= ph2;
-- END IF;
when ph3 => sdram_state <= ph4;
when ph4 => sdram_state <= ph5;
when ph5 => sdram_state <= ph6;
when ph6 => sdram_state <= ph7;
when ph7 => sdram_state <= ph8;
when ph8 => sdram_state <= ph9;
when ph9 => sdram_state <= ph10;
when ph10 => sdram_state <= ph11;
when ph11 => sdram_state <= ph12;
when ph12 => sdram_state <= ph13;
when ph13 => sdram_state <= ph14;
when ph14 => sdram_state <= ph15;
-- when ph15 => sdram_state <= ph0;
when others => sdram_state <= ph0;
end case;
END IF;
END IF;
end process;
process (sysclk, initstate, pass, hostAddr, datain, init_done, casaddr, cpuU, cpuL, hostCycle) begin
if (sysclk'event and sysclk='1') THEN
sd_cs <="1111";
sd_ras <= '1';
sd_cas <= '1';
sd_we <= '1';
sdaddr <= "XXXXXXXXXXXX";
ba <= "00";
dqm <= "00";
if init_done='0' then
if sdram_state =ph1 then
case initstate is
when "0010" => --PRECHARGE
sdaddr(10) <= '1'; --all banks
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '1';
sd_we <= '0';
when "0011"|"0100"|"0101"|"0110"|"0111"|"1000"|"1001"|"1010"|"1011"|"1100" => --AUTOREFRESH
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '1';
when "1101" => --LOAD MODE REGISTER
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '0';
-- ba <= "00";
-- sdaddr <= "001000100010"; --BURST=4 LATENCY=2
sdaddr <= "001000110010"; --BURST=4 LATENCY=3
when others => null; --NOP
end case;
END IF;
else
-- Time slot control
if sdram_state=ph1 THEN
cpuCycle <= '0';
chipCycle <= '0';
hostCycle <= '0';
cas_sd_cs <= "1110";
cas_sd_ras <= '1';
cas_sd_cas <= '1';
cas_sd_we <= '1';
IF slow(2 downto 0)=5 THEN
slow <= slow+3;
ELSE
slow <= slow+1;
END IF;
-- IF dma='0' OR cpu_dma='0' THEN
IF hostSlot_cnt /= "00000000" THEN
hostSlot_cnt <= hostSlot_cnt-1;
END IF;
-- IF chip_dma='1' THEN
IF chip_dma='0' OR chipRW='0' THEN
chipCycle <= '1';
sdaddr <= chipAddr(20 downto 9);
-- ba <= "00";
ba <= chipAddr(22 downto 21);
-- cas_dqm <= "00"; --only word access
cas_dqm <= chipU& chipL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= '0'&chipAddr&'0';
datain <= chipWR;
cas_sd_cas <= '0';
cas_sd_we <= chipRW;
-- ELSIF cpu_dma='1' AND hostSlot_cnt /= "00000000" THEN
-- ELSIF cpu_dma='0' OR cpuRW='0' THEN
ELSIF cpuState(2)='0' AND cpuState(5)='0' THEN
cpuCycle <= '1';
sdaddr <= cpuAddr(20 downto 9);
ba <= cpuAddr(22 downto 21);
cas_dqm <= cpuU& cpuL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= cpuAddr(24 downto 1)&'0';
datain <= cpuWR;
cas_sd_cas <= '0';
cas_sd_we <= NOT cpuState(1) OR NOT cpuState(0);
ELSE
hostSlot_cnt <= "00001111";
-- ELSIF hostState(2)='1' OR hostena='1' OR slow(3 downto 0)="0001" THEN --refresh cycle
IF hostState(2)='1' OR hostena='1' THEN --refresh cycle
-- ELSIF slow(3 downto 0)="0001" THEN --refresh cycle
sd_cs <="0000"; --AUTOREFRESH
sd_ras <= '0';
sd_cas <= '0';
ELSE
hostCycle <= '1';
sdaddr <= zmAddr(20 downto 9);
ba <= zmAddr(22 downto 21);
cas_dqm <= hostU& hostL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= zmAddr;
datain <= hostWR;
cas_sd_cas <= '0';
IF hostState="011" THEN
cas_sd_we <= '0';
-- dqm <= hostU& hostL;
END IF;
END IF;
END IF;
END IF;
if sdram_state=ph4 then
sdaddr <= '0' & '1' & '0' & casaddr(23)&casaddr(8 downto 1);--auto precharge
ba <= casaddr(22 downto 21);
sd_cs <= cas_sd_cs;
IF cas_sd_we='0' THEN
dqm <= cas_dqm;
END IF;
sd_ras <= cas_sd_ras;
sd_cas <= cas_sd_cas;
sd_we <= cas_sd_we;
END IF;
END IF;
END IF;
END process;
END;
|
entity sub is
generic ( def : integer;
g : integer := def );
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= g;
end architecture;
-------------------------------------------------------------------------------
entity elab30 is
end entity;
architecture test of elab30 is
signal x : integer;
begin
u: entity work.sub
generic map ( def => 42 )
port map ( x );
p1: process is
begin
wait for 1 ns;
assert x = 42;
wait;
end process;
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture verifier of dlx_test is
use work.dlx_types.all;
component clock_gen is
port ( phi1, phi2 : out std_logic;
reset : out std_logic );
end component clock_gen;
component memory is
port ( phi1, phi2 : in std_logic;
a : in dlx_address;
d : inout dlx_word;
width : in dlx_mem_width;
write_enable : in std_logic;
burst : in std_logic := '0';
mem_enable : in std_logic;
ready : out std_logic );
end component memory;
component dlx is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
a : out dlx_address;
d : inout dlx_word;
width : out dlx_mem_width;
write_enable : out std_logic;
ifetch : out std_logic;
mem_enable : out std_logic;
ready : in std_logic );
end component dlx;
signal phi1, phi2, reset : std_logic;
signal a_behav : dlx_address;
signal d_behav : dlx_word;
signal halt_behav : std_logic;
signal width_behav : dlx_mem_width;
signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
signal a_rtl : dlx_address;
signal d_rtl : dlx_word;
signal halt_rtl : std_logic;
signal width_rtl : dlx_mem_width;
signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
signal ready_mem : std_logic;
begin
cg : component clock_gen
port map ( phi1 => phi1, phi2 => phi2, reset => reset );
mem : component memory
port map ( phi1 => phi1, phi2 => phi2,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
burst => open,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_behav : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
ifetch => ifetch_behav,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_rtl : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
a => a_rtl, d => d_rtl,
width => width_rtl, write_enable => write_enable_rtl,
ifetch => ifetch_rtl,
mem_enable => mem_enable_rtl, ready => ready_mem );
verification_section : block is
begin
fwd_data_from_mem_to_rtl :
d_rtl <= d_behav when mem_enable_rtl = '1'
and write_enable_rtl = '0' else
disabled_dlx_word;
monitor : process
variable write_command_behav : boolean;
variable write_command_rtl : boolean;
begin
monitor_loop : loop
-- wait for a command, valid on leading edge of phi2
wait until rising_edge(phi2)
and mem_enable_behav = '1' and mem_enable_rtl = '1';
--
-- capture the command information
write_command_behav := write_enable_behav = '1';
write_command_rtl := write_enable_rtl = '1';
assert a_behav = a_rtl
report "addresses differ";
assert write_enable_behav = write_enable_rtl
report "write enable states differ";
assert ifetch_behav = ifetch_rtl
report "instruction fetch states differ";
assert width_behav = width_rtl
report "widths differ";
if write_command_behav and write_command_rtl then
assert d_behav = d_rtl
report "write data differs";
end if;
--
-- wait for the response from memory
ready_loop : loop
wait until falling_edge(phi2);
exit monitor_loop when reset = '1';
exit ready_loop when ready_mem = '1';
end loop ready_loop;
end loop monitor_loop;
--
-- get here when reset is asserted
wait until reset = '0';
--
-- process monitor now starts again from beginning
end process monitor;
end block verification_section;
end architecture verifier;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture verifier of dlx_test is
use work.dlx_types.all;
component clock_gen is
port ( phi1, phi2 : out std_logic;
reset : out std_logic );
end component clock_gen;
component memory is
port ( phi1, phi2 : in std_logic;
a : in dlx_address;
d : inout dlx_word;
width : in dlx_mem_width;
write_enable : in std_logic;
burst : in std_logic := '0';
mem_enable : in std_logic;
ready : out std_logic );
end component memory;
component dlx is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
a : out dlx_address;
d : inout dlx_word;
width : out dlx_mem_width;
write_enable : out std_logic;
ifetch : out std_logic;
mem_enable : out std_logic;
ready : in std_logic );
end component dlx;
signal phi1, phi2, reset : std_logic;
signal a_behav : dlx_address;
signal d_behav : dlx_word;
signal halt_behav : std_logic;
signal width_behav : dlx_mem_width;
signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
signal a_rtl : dlx_address;
signal d_rtl : dlx_word;
signal halt_rtl : std_logic;
signal width_rtl : dlx_mem_width;
signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
signal ready_mem : std_logic;
begin
cg : component clock_gen
port map ( phi1 => phi1, phi2 => phi2, reset => reset );
mem : component memory
port map ( phi1 => phi1, phi2 => phi2,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
burst => open,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_behav : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
ifetch => ifetch_behav,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_rtl : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
a => a_rtl, d => d_rtl,
width => width_rtl, write_enable => write_enable_rtl,
ifetch => ifetch_rtl,
mem_enable => mem_enable_rtl, ready => ready_mem );
verification_section : block is
begin
fwd_data_from_mem_to_rtl :
d_rtl <= d_behav when mem_enable_rtl = '1'
and write_enable_rtl = '0' else
disabled_dlx_word;
monitor : process
variable write_command_behav : boolean;
variable write_command_rtl : boolean;
begin
monitor_loop : loop
-- wait for a command, valid on leading edge of phi2
wait until rising_edge(phi2)
and mem_enable_behav = '1' and mem_enable_rtl = '1';
--
-- capture the command information
write_command_behav := write_enable_behav = '1';
write_command_rtl := write_enable_rtl = '1';
assert a_behav = a_rtl
report "addresses differ";
assert write_enable_behav = write_enable_rtl
report "write enable states differ";
assert ifetch_behav = ifetch_rtl
report "instruction fetch states differ";
assert width_behav = width_rtl
report "widths differ";
if write_command_behav and write_command_rtl then
assert d_behav = d_rtl
report "write data differs";
end if;
--
-- wait for the response from memory
ready_loop : loop
wait until falling_edge(phi2);
exit monitor_loop when reset = '1';
exit ready_loop when ready_mem = '1';
end loop ready_loop;
end loop monitor_loop;
--
-- get here when reset is asserted
wait until reset = '0';
--
-- process monitor now starts again from beginning
end process monitor;
end block verification_section;
end architecture verifier;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture verifier of dlx_test is
use work.dlx_types.all;
component clock_gen is
port ( phi1, phi2 : out std_logic;
reset : out std_logic );
end component clock_gen;
component memory is
port ( phi1, phi2 : in std_logic;
a : in dlx_address;
d : inout dlx_word;
width : in dlx_mem_width;
write_enable : in std_logic;
burst : in std_logic := '0';
mem_enable : in std_logic;
ready : out std_logic );
end component memory;
component dlx is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
a : out dlx_address;
d : inout dlx_word;
width : out dlx_mem_width;
write_enable : out std_logic;
ifetch : out std_logic;
mem_enable : out std_logic;
ready : in std_logic );
end component dlx;
signal phi1, phi2, reset : std_logic;
signal a_behav : dlx_address;
signal d_behav : dlx_word;
signal halt_behav : std_logic;
signal width_behav : dlx_mem_width;
signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
signal a_rtl : dlx_address;
signal d_rtl : dlx_word;
signal halt_rtl : std_logic;
signal width_rtl : dlx_mem_width;
signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
signal ready_mem : std_logic;
begin
cg : component clock_gen
port map ( phi1 => phi1, phi2 => phi2, reset => reset );
mem : component memory
port map ( phi1 => phi1, phi2 => phi2,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
burst => open,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_behav : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
ifetch => ifetch_behav,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_rtl : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
a => a_rtl, d => d_rtl,
width => width_rtl, write_enable => write_enable_rtl,
ifetch => ifetch_rtl,
mem_enable => mem_enable_rtl, ready => ready_mem );
verification_section : block is
begin
fwd_data_from_mem_to_rtl :
d_rtl <= d_behav when mem_enable_rtl = '1'
and write_enable_rtl = '0' else
disabled_dlx_word;
monitor : process
variable write_command_behav : boolean;
variable write_command_rtl : boolean;
begin
monitor_loop : loop
-- wait for a command, valid on leading edge of phi2
wait until rising_edge(phi2)
and mem_enable_behav = '1' and mem_enable_rtl = '1';
--
-- capture the command information
write_command_behav := write_enable_behav = '1';
write_command_rtl := write_enable_rtl = '1';
assert a_behav = a_rtl
report "addresses differ";
assert write_enable_behav = write_enable_rtl
report "write enable states differ";
assert ifetch_behav = ifetch_rtl
report "instruction fetch states differ";
assert width_behav = width_rtl
report "widths differ";
if write_command_behav and write_command_rtl then
assert d_behav = d_rtl
report "write data differs";
end if;
--
-- wait for the response from memory
ready_loop : loop
wait until falling_edge(phi2);
exit monitor_loop when reset = '1';
exit ready_loop when ready_mem = '1';
end loop ready_loop;
end loop monitor_loop;
--
-- get here when reset is asserted
wait until reset = '0';
--
-- process monitor now starts again from beginning
end process monitor;
end block verification_section;
end architecture verifier;
|
-------------------------------------------------------------------------------
--! @file debug_serial.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2015-01-20
--! @brief Debugging serial interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
--! @brief Entity declaration of debug_serial
--! @details
--! Provide a serial debugging interface over UART.
entity debug_serial is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Debugging interface
--! @{
--! TX start flag
start_i : in std_ulogic;
--! Data input
debug_i : in std_ulogic_vector(7 downto 0);
--! Data input enable
debug_en_i : in std_ulogic;
--! Data output
debug_o : out std_ulogic_vector(7 downto 0);
--! Data output enable
debug_en_o : out std_ulogic;
--! @}
--! @name Serial communication
--! @{
--! Serial receiver
rx_i : in std_ulogic;
--! Serial transmitter
tx_o : out std_ulogic);
--! @}
end entity debug_serial;
--! RTL implementation of debug_serial
architecture rtl of debug_serial is
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal tx_data : std_ulogic_vector(7 downto 0);
signal tx_data_en : std_ulogic;
signal tx_done : std_ulogic;
signal fifo_rd_en : std_ulogic;
signal fifo_empty : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
fifo_rd_en <= (start_i or tx_done) and (not fifo_empty);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! FIFO
fifo_inst : entity work.fifo_tmr
generic map (
depth_g => 256,
width_g => 8)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => debug_en_i,
data_i => debug_i,
done_o => open,
full_o => open,
wr_busy_o => open,
rd_en_i => fifo_rd_en,
data_o => tx_data,
data_en_o => tx_data_en,
empty_o => fifo_empty,
rd_busy_o => open);
--! Serial transmitter
uart_tx_inst : entity work.uart_tx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 156)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
data_i => tx_data,
data_en_i => tx_data_en,
busy_o => open,
done_o => tx_done,
tx_o => tx_o);
--! Serial receiver
uart_rx_inst : entity work.uart_rx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 156)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rx_i => rx_i,
data_o => debug_o,
data_en_o => debug_en_o,
error_o => open);
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PXData_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
PX_start_i : in std_logic;
PX_present_i : in std_logic;
PX_data_i: in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
PXwen_o : out std_logic);
end PXData_FSM;
architecture rtl of PXData_FSM is
type t_state is (waiting,
check_bus_busy,
send_START,
send_A7,
send_A6,
send_A5,
send_A4,
send_A3,
send_A2,
send_A1,
send_RW,
read_A_ACK,
send_D7,
send_D6,
send_D5,
send_D4,
send_D3,
send_D2,
send_D1,
send_D0,
read_D_ACK,
read_D7,
read_D6,
read_D5,
read_D4,
read_D3,
read_D2,
read_D1,
read_D0,
send_NOACK,
send_ACK,
restart_READ,
restart_DATA,
send_STOPCLKRD,
send_STOPCLK,
send_STOP,
write_sda);
signal s_state : t_state;
signal s_sdadir : std_logic; -- Signal buffer for sdadir_o !!
signal s_sda_response : std_logic;
signal s_count : unsigned(3 downto 0);
signal s_timeout: unsigned(4 downto 0);
signal s_d_serin : std_logic_vector(7 downto 0);
signal s_addrw : std_logic_vector(7 downto 0);
signal s_nbytes : unsigned(7 downto 0);
signal s_bytecount : unsigned(7 downto 0);
signal s_rwq : std_logic;
begin
p_format: process (clk_i, reset_n_i)
begin -- process p_serin
if (reset_n_i = '0') then -- asynchronous reset (active low)
s_state <= waiting;
s_count <= conv_unsigned(0,4);
s_d_serin <= "00000000";
pd_o <= "00000000";
error_o <= "00000000";
sclen_o <= '0';
readen_o <= '0';
sda_o <= '1';
sdadir_o <= '0'; s_sdadir <= '0';
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when check_bus_busy =>
if ( sda_i = '1' AND scl_i = '1' ) then
-- bus is free
s_state <= send_START;
else
-- bus isn't free
s_timeout <= s_timeout - conv_unsigned(1,1); -- decrement s_timeout
if (s_timeout = 0) then
error_o <= "00000001";
s_state <= waiting;
end if;
end if;
-------------------------------------------------------------------------
when send_START =>
sdadir_o <= '1'; s_sdadir <= '0';
sclen_o <= '1';
readen_o <= '0';
sda_o <= '0';
s_bytecount <= conv_unsigned(0,8);
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
s_state <= send_A7 ;
-------------------------------------------------------------------------
when send_A7 =>
sda_o <= s_addrw(7);
s_state <= send_A6;
-------------------------------------------------------------------------
when send_A6 =>
sda_o <= s_addrw(6);
s_state <= send_A5;
-------------------------------------------------------------------------
when send_A5 =>
sda_o <= s_addrw(5);
s_state <= send_A4;
-------------------------------------------------------------------------
when send_A4 =>
sda_o <= s_addrw(4);
s_state <= send_A3;
-------------------------------------------------------------------------
when send_A3 =>
sda_o <= s_addrw(3);
s_state <= send_A2;
-------------------------------------------------------------------------
when send_A2 =>
sda_o <= s_addrw(2);
s_state <= send_A1;
-------------------------------------------------------------------------
when send_A1 =>
sda_o <= s_addrw(1);
s_state <= send_RW;
-----------------------------------------------------------------------
when send_RW =>
sda_o <= s_addrw(0);
s_state <= read_A_ACK;
-------------------------------------------------------------------------
when read_A_ACK =>
sda_o <= '0';
sdadir_o <= '0'; s_sdadir <= '0';
s_state <= send_D7;
if ( s_rwq = '1') then -- read
s_state <= read_D7;
else -- write
s_state <= send_D7;
end if;
-------------------------------------------------------------------------
when send_D7 =>
sdadir_o <= '1'; s_sdadir <= '0';
if(s_sda_response = '0') then
-- ADDRESS acknowledged
sda_o <= data_i(7);
s_state <= send_D6;
else
-- A_ACK ERROR
error_o <= "00000010";
sda_o <= '1';
sclen_o <= '0';
s_state <= waiting;
end if;
-------------------------------------------------------------------------
when send_D6 =>
sda_o <= data_i(6);
s_bytecount <= s_bytecount + conv_unsigned(1,8);
s_state <= send_D5;
-------------------------------------------------------------------------
when send_D5 =>
sda_o <= data_i(5);
s_state <= send_D4;
-------------------------------------------------------------------------
when send_D4 =>
sda_o <= data_i(4);
s_state <= send_D3;
-------------------------------------------------------------------------
when send_D3 =>
sda_o <= data_i(3);
s_state <= send_D2;
-------------------------------------------------------------------------
when send_D2 =>
sda_o <= data_i(2);
s_state <= send_D1;
-------------------------------------------------------------------------
when send_D1 =>
sda_o <= data_i(1);
s_state <= send_D0;
-----------------------------------------------------------------------
when send_D0 =>
sda_o <= data_i(0);
s_state <= read_D_ACK;
-------------------------------------------------------------------------
when read_D_ACK =>
sda_o <= '0';
sdadir_o <= '0'; s_sdadir <= '0';
if(s_nbytes = s_bytecount) then
s_state <= send_STOPCLK;
else
s_state <= restart_DATA;
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
end if;
-------------------------------------------------------------------------
when read_D7 =>
if(s_sda_response = '0') then
-- ADDRESS acknowledged
s_state <= read_D6;
else
-- A_ACK ERROR
sdadir_o <= '1'; s_sdadir <= '0';
error_o <= "00000010";
sda_o <= '1';
sclen_o <= '0';
s_state <= waiting;
end if;
-------------------------------------------------------------------------
when read_D6 =>
readen_o <= '0';
s_d_serin(7)<= s_sda_response;
s_bytecount <= s_bytecount + conv_unsigned(1,8);
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
s_state <= read_D5;
-------------------------------------------------------------------------
when read_D5 =>
s_d_serin(6)<= s_sda_response;
s_state <= read_D4;
-------------------------------------------------------------------------
when read_D4 =>
s_d_serin(5)<= s_sda_response;
s_state <= read_D3;
-------------------------------------------------------------------------
when read_D3 =>
s_d_serin(4)<=s_sda_response;
s_state <= read_D2;
-------------------------------------------------------------------------
when read_D2 =>
s_d_serin(3)<= s_sda_response;
s_state <= read_D1;
-------------------------------------------------------------------------
when read_D1 =>
s_d_serin(2)<= s_sda_response;
s_state <= read_D0;
-------------------------------------------------------------------------
when read_D0 =>
s_d_serin(1)<= s_sda_response;
if(s_nbytes = s_bytecount) then
s_state <= send_NOACK;
else
s_state <= send_ACK;
end if;
-------------------------------------------------------------------------
when send_NOACK =>
s_d_serin(0)<= s_sda_response;
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= '1'; -- NOACK BY MASTER
s_state <= send_STOPCLKRD;
-------------------------------------------------------------------------
when send_ACK =>
s_d_serin(0)<= s_sda_response;
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= '0'; -- DTACK by Master
s_state <= restart_READ;
-------------------------------------------------------------------------
when restart_READ =>
sdadir_o <= '0'; s_sdadir <= '0';
readen_o <= '1';
pd_o <= s_d_serin;
s_d_serin(7)<= s_sda_response;
s_state <= read_D6;
-------------------------------------------------------------------------
when restart_DATA =>
if(s_sda_response = '0') then
-- DATA acknowledged
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= data_i(7);
s_state <= send_D6;
else
-- D_ACK ERROR
error_o <= "00000100";
s_state <= send_STOP;
end if;
-------------------------------------------------------------------------
when send_STOPCLKRD =>
sda_o <= '0';
sclen_o <= '0';
readen_o <= '1';
pd_o <= s_d_serin;
s_state <= send_STOP;
-------------------------------------------------------------------------
when send_STOPCLK =>
sda_o <= '0';
sclen_o <= '0';
if(s_sda_response = '0') then
-- DATA acknowledged
s_state <= send_STOP;
else
-- D_ACK ERROR
error_o <= "00000100";
s_state <= send_STOP;
end if;
-------------------------------------------------------------------------
when send_STOP =>
sda_o <= '1';
sclen_o <= '0';
readen_o <= '0';
s_state <= waiting;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if sub_i2c_i = '1' then
-- VME Start I2C Cycle command detected.
s_addrw <= addrw_i;
s_nbytes <= nbytes_i;
s_rwq <= addrw_i(0);
s_state <= check_bus_busy;
-- Initialize input counter
s_timeout <= conv_unsigned(10,5);
end if;
end case;
end if;
end process p_format;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PXData_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
PX_start_i : in std_logic;
PX_present_i : in std_logic;
PX_data_i: in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
PXwen_o : out std_logic);
end PXData_FSM;
architecture rtl of PXData_FSM is
type t_state is (waiting,
check_bus_busy,
send_START,
send_A7,
send_A6,
send_A5,
send_A4,
send_A3,
send_A2,
send_A1,
send_RW,
read_A_ACK,
send_D7,
send_D6,
send_D5,
send_D4,
send_D3,
send_D2,
send_D1,
send_D0,
read_D_ACK,
read_D7,
read_D6,
read_D5,
read_D4,
read_D3,
read_D2,
read_D1,
read_D0,
send_NOACK,
send_ACK,
restart_READ,
restart_DATA,
send_STOPCLKRD,
send_STOPCLK,
send_STOP,
write_sda);
signal s_state : t_state;
signal s_sdadir : std_logic; -- Signal buffer for sdadir_o !!
signal s_sda_response : std_logic;
signal s_count : unsigned(3 downto 0);
signal s_timeout: unsigned(4 downto 0);
signal s_d_serin : std_logic_vector(7 downto 0);
signal s_addrw : std_logic_vector(7 downto 0);
signal s_nbytes : unsigned(7 downto 0);
signal s_bytecount : unsigned(7 downto 0);
signal s_rwq : std_logic;
begin
p_format: process (clk_i, reset_n_i)
begin -- process p_serin
if (reset_n_i = '0') then -- asynchronous reset (active low)
s_state <= waiting;
s_count <= conv_unsigned(0,4);
s_d_serin <= "00000000";
pd_o <= "00000000";
error_o <= "00000000";
sclen_o <= '0';
readen_o <= '0';
sda_o <= '1';
sdadir_o <= '0'; s_sdadir <= '0';
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when check_bus_busy =>
if ( sda_i = '1' AND scl_i = '1' ) then
-- bus is free
s_state <= send_START;
else
-- bus isn't free
s_timeout <= s_timeout - conv_unsigned(1,1); -- decrement s_timeout
if (s_timeout = 0) then
error_o <= "00000001";
s_state <= waiting;
end if;
end if;
-------------------------------------------------------------------------
when send_START =>
sdadir_o <= '1'; s_sdadir <= '0';
sclen_o <= '1';
readen_o <= '0';
sda_o <= '0';
s_bytecount <= conv_unsigned(0,8);
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
s_state <= send_A7 ;
-------------------------------------------------------------------------
when send_A7 =>
sda_o <= s_addrw(7);
s_state <= send_A6;
-------------------------------------------------------------------------
when send_A6 =>
sda_o <= s_addrw(6);
s_state <= send_A5;
-------------------------------------------------------------------------
when send_A5 =>
sda_o <= s_addrw(5);
s_state <= send_A4;
-------------------------------------------------------------------------
when send_A4 =>
sda_o <= s_addrw(4);
s_state <= send_A3;
-------------------------------------------------------------------------
when send_A3 =>
sda_o <= s_addrw(3);
s_state <= send_A2;
-------------------------------------------------------------------------
when send_A2 =>
sda_o <= s_addrw(2);
s_state <= send_A1;
-------------------------------------------------------------------------
when send_A1 =>
sda_o <= s_addrw(1);
s_state <= send_RW;
-----------------------------------------------------------------------
when send_RW =>
sda_o <= s_addrw(0);
s_state <= read_A_ACK;
-------------------------------------------------------------------------
when read_A_ACK =>
sda_o <= '0';
sdadir_o <= '0'; s_sdadir <= '0';
s_state <= send_D7;
if ( s_rwq = '1') then -- read
s_state <= read_D7;
else -- write
s_state <= send_D7;
end if;
-------------------------------------------------------------------------
when send_D7 =>
sdadir_o <= '1'; s_sdadir <= '0';
if(s_sda_response = '0') then
-- ADDRESS acknowledged
sda_o <= data_i(7);
s_state <= send_D6;
else
-- A_ACK ERROR
error_o <= "00000010";
sda_o <= '1';
sclen_o <= '0';
s_state <= waiting;
end if;
-------------------------------------------------------------------------
when send_D6 =>
sda_o <= data_i(6);
s_bytecount <= s_bytecount + conv_unsigned(1,8);
s_state <= send_D5;
-------------------------------------------------------------------------
when send_D5 =>
sda_o <= data_i(5);
s_state <= send_D4;
-------------------------------------------------------------------------
when send_D4 =>
sda_o <= data_i(4);
s_state <= send_D3;
-------------------------------------------------------------------------
when send_D3 =>
sda_o <= data_i(3);
s_state <= send_D2;
-------------------------------------------------------------------------
when send_D2 =>
sda_o <= data_i(2);
s_state <= send_D1;
-------------------------------------------------------------------------
when send_D1 =>
sda_o <= data_i(1);
s_state <= send_D0;
-----------------------------------------------------------------------
when send_D0 =>
sda_o <= data_i(0);
s_state <= read_D_ACK;
-------------------------------------------------------------------------
when read_D_ACK =>
sda_o <= '0';
sdadir_o <= '0'; s_sdadir <= '0';
if(s_nbytes = s_bytecount) then
s_state <= send_STOPCLK;
else
s_state <= restart_DATA;
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
end if;
-------------------------------------------------------------------------
when read_D7 =>
if(s_sda_response = '0') then
-- ADDRESS acknowledged
s_state <= read_D6;
else
-- A_ACK ERROR
sdadir_o <= '1'; s_sdadir <= '0';
error_o <= "00000010";
sda_o <= '1';
sclen_o <= '0';
s_state <= waiting;
end if;
-------------------------------------------------------------------------
when read_D6 =>
readen_o <= '0';
s_d_serin(7)<= s_sda_response;
s_bytecount <= s_bytecount + conv_unsigned(1,8);
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
s_state <= read_D5;
-------------------------------------------------------------------------
when read_D5 =>
s_d_serin(6)<= s_sda_response;
s_state <= read_D4;
-------------------------------------------------------------------------
when read_D4 =>
s_d_serin(5)<= s_sda_response;
s_state <= read_D3;
-------------------------------------------------------------------------
when read_D3 =>
s_d_serin(4)<=s_sda_response;
s_state <= read_D2;
-------------------------------------------------------------------------
when read_D2 =>
s_d_serin(3)<= s_sda_response;
s_state <= read_D1;
-------------------------------------------------------------------------
when read_D1 =>
s_d_serin(2)<= s_sda_response;
s_state <= read_D0;
-------------------------------------------------------------------------
when read_D0 =>
s_d_serin(1)<= s_sda_response;
if(s_nbytes = s_bytecount) then
s_state <= send_NOACK;
else
s_state <= send_ACK;
end if;
-------------------------------------------------------------------------
when send_NOACK =>
s_d_serin(0)<= s_sda_response;
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= '1'; -- NOACK BY MASTER
s_state <= send_STOPCLKRD;
-------------------------------------------------------------------------
when send_ACK =>
s_d_serin(0)<= s_sda_response;
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= '0'; -- DTACK by Master
s_state <= restart_READ;
-------------------------------------------------------------------------
when restart_READ =>
sdadir_o <= '0'; s_sdadir <= '0';
readen_o <= '1';
pd_o <= s_d_serin;
s_d_serin(7)<= s_sda_response;
s_state <= read_D6;
-------------------------------------------------------------------------
when restart_DATA =>
if(s_sda_response = '0') then
-- DATA acknowledged
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= data_i(7);
s_state <= send_D6;
else
-- D_ACK ERROR
error_o <= "00000100";
s_state <= send_STOP;
end if;
-------------------------------------------------------------------------
when send_STOPCLKRD =>
sda_o <= '0';
sclen_o <= '0';
readen_o <= '1';
pd_o <= s_d_serin;
s_state <= send_STOP;
-------------------------------------------------------------------------
when send_STOPCLK =>
sda_o <= '0';
sclen_o <= '0';
if(s_sda_response = '0') then
-- DATA acknowledged
s_state <= send_STOP;
else
-- D_ACK ERROR
error_o <= "00000100";
s_state <= send_STOP;
end if;
-------------------------------------------------------------------------
when send_STOP =>
sda_o <= '1';
sclen_o <= '0';
readen_o <= '0';
s_state <= waiting;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if sub_i2c_i = '1' then
-- VME Start I2C Cycle command detected.
s_addrw <= addrw_i;
s_nbytes <= nbytes_i;
s_rwq <= addrw_i(0);
s_state <= check_bus_busy;
-- Initialize input counter
s_timeout <= conv_unsigned(10,5);
end if;
end case;
end if;
end process p_format;
end rtl;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:15:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesafp_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END mesafp_asap_entity;
ARCHITECTURE mesafp_asap_description OF mesafp_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register19: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register20: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register21: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
register3 := input3 + 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 + 6;
register7 := input7 * 7;
register8 := input8 * 8;
register9 := input9 + 9;
register10 := input10 * 10;
register11 := input11 * 11;
register12 := input12 + 12;
register13 := input13 * 13;
register14 := input14 * 14;
register15 := input15 * 15;
register16 := input16 * 16;
register17 := input17 * 17;
register18 := input18 * 18;
register19 := input19 * 19;
register20 := input20 * 20;
register21 := input21 * 21;
WHEN "00000010" =>
register1 := register1 + 23;
register2 := register21 + register2;
register3 := register17 + register3;
register4 := register4 + 25;
register5 := register5 + 27;
register6 := register19 + register6;
register7 := register7 + 29;
register8 := register8 + 31;
register9 := register15 + register9;
register10 := register10 + register12;
register12 := register13 + 33;
WHEN "00000011" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register20 + register2;
register3 := register16 + register3;
register5 := ((NOT register5) + 1) XOR register5;
register6 := register18 + register6;
register9 := register14 + register9;
register10 := register11 + register10;
WHEN "00000100" =>
IF (register5 = 38 or register1 = 38) THEN
output1 <= register5;
ELSE
output1 <= "00110";
END IF;
register1 := ((NOT register2) + 1) XOR register2;
register2 := ((NOT register3) + 1) XOR register3;
register3 := ((NOT register6) + 1) XOR register6;
register5 := ((NOT register9) + 1) XOR register9;
register6 := ((NOT register10) + 1) XOR register10;
WHEN "00000101" =>
output2 <= register1(0 TO 1) & register4(0 TO 2);
register1 := register6 / 2;
WHEN "00000110" =>
register3 := register1 * register3;
register2 := register1 * register2;
register1 := register1 * register5;
WHEN "00000111" =>
output3 <= register3(0 TO 1) & register8(0 TO 2);
output4 <= register2(0 TO 1) & register7(0 TO 2);
output5 <= register1(0 TO 1) & register12(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesafp_asap_description; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libddr
-- File: libddr.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: DDR input/output registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allddr is
component unisim_iddr_reg is
generic ( tech : integer := virtex4);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component gen_iddr_reg
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ec_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component unisim_oddr_reg
generic ( tech : integer := virtex4);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component gen_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component spartan3e_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex4_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex2_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component stratixii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component cycloneiii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex5_ddr2_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; tech : integer := virtex5);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libddr
-- File: libddr.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: DDR input/output registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allddr is
component unisim_iddr_reg is
generic ( tech : integer := virtex4);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component gen_iddr_reg
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ec_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component unisim_oddr_reg
generic ( tech : integer := virtex4);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component gen_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component spartan3e_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex4_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex2_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component stratixii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component cycloneiii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex5_ddr2_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; tech : integer := virtex5);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
end;
|
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Debouncer is
generic (N : positive);
port (clk : in std_logic;
dirty_In : in std_logic;
cleanOut : out std_logic);
end Debouncer;
architecture Behavioral of Debouncer is
signal s_dirty_In : std_logic_vector(N downto 1);
begin
process(clk, dirty_In)
begin
if(dirty_In='1') then
s_dirty_In <= (others => '0');
elsif(rising_edge(clk)) then
--s_dirty_In <= (others => '1');
s_dirty_In <= '1' & s_dirty_In(N downto 2);
end if;
cleanOut <= s_dirty_In(N);
end process;
end Behavioral; |
--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1993
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <REFERENCES>
--!
--! \copyright <COPYRIGHT_OR_LICENSE>
--!
--! Revision history:
--!
--! \version <VERSION>
--! \date <YYYY-MM-DD>
--! \author <AUTHOR_NAME>
--! \brief Create file.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package template_package is
end package template_package;
package body template_package is
end package body template_package;
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mezzanotte is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
dout : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end entity;
architecture beh of mezzanotte is
type stati is (idle, getOP, getA, getB, exe1, exe2, exe3);
signal st : stati;
signal A, B, REG : std_logic_vector(15 downto 0);
signal OP : std_logic_vector(1 downto 0);
signal enOP, enA, enB, enEXE1, enEXE2, enEXE3 : std_logic;
signal counter : integer range 2 downto 0;
function next_state (st : stati; start : std_logic; op : std_logic_vector(1 downto 0); counter : integer range 2 downto 0)
return stati is
variable nxt : stati;
begin
case st is
when idle =>
if start = '1' then
nxt := getOp;
else
nxt :=idle;
end if;
when getOP =>
nxt := getA;
when getA =>
if op = "01" then
nxt := exe3;
else
nxt := getB;
end if;
when getB =>
case op is
when "00" =>
nxt := exe1;
when "10" =>
nxt := exe3;
when others => -- "11"
nxt := exe2;
end case;
when exe1 =>
nxt := idle;
when exe2 =>
if counter < 1 then
nxt := exe2;
else
nxt := idle;
end if;
when exe3 =>
if counter < 2 then
nxt := exe3;
else
nxt := idle;
end if;
end case;
return nxt;
end next_state;
begin
-- CU
process (clk)
begin
if clk'event and clk = '0' then
st <= next_state(st, start, op, counter);
end if;
end process;
enOP <= '1' when st = getOP else '0';
enA <= '1' when st = getA else '0';
enB <= '1' when st = getB else '0';
enEXE1 <= '1' when st = exe1 else '0';
enEXE2 <= '1' when st = exe2 else '0';
enEXE3 <= '1' when st = exe3 else '0';
-- DATAPATH
process (clk)
variable tmp : std_logic_vector(15 downto 0);
begin
if enOP = '1' then
OP <= din(1 downto 0);
counter <= 0;
end if;
if enA = '1' then
A <= din;
end if;
if enB = '1' then
B <= din;
end if;
if enEXE1 = '1' then
REG <= A and B;
dout <= REG;
end if;
if enEXE2 = '1' then
if counter = 1 then
if A < B then
tmp := A;
else
tmp := B;
end if;
if tmp < REG then
REG <= tmp;
dout <= REG;
else
dout <= REG;
end if;
else
counter <= counter + 1;
end if;
end if;
if enEXE3 = '1' then
if counter = 2 then
if op = "01" then
tmp := A + REG;
REG <= tmp;
dout <= REG;
else -- OP "10"
REG <= A + B;
dout <= REG;
end if;
else
counter <= counter + 1;
end if;
end if;
if enEXE1 = '1' or (enEXE2 = '1' and counter = 1) or (enEXE3 = '1' and counter = 2) then
fine <= '1';
else
fine <= '0';
end if;
end process;
end architecture; |
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mezzanotte is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
dout : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end entity;
architecture beh of mezzanotte is
type stati is (idle, getOP, getA, getB, exe1, exe2, exe3);
signal st : stati;
signal A, B, REG : std_logic_vector(15 downto 0);
signal OP : std_logic_vector(1 downto 0);
signal enOP, enA, enB, enEXE1, enEXE2, enEXE3 : std_logic;
signal counter : integer range 2 downto 0;
function next_state (st : stati; start : std_logic; op : std_logic_vector(1 downto 0); counter : integer range 2 downto 0)
return stati is
variable nxt : stati;
begin
case st is
when idle =>
if start = '1' then
nxt := getOp;
else
nxt :=idle;
end if;
when getOP =>
nxt := getA;
when getA =>
if op = "01" then
nxt := exe3;
else
nxt := getB;
end if;
when getB =>
case op is
when "00" =>
nxt := exe1;
when "10" =>
nxt := exe3;
when others => -- "11"
nxt := exe2;
end case;
when exe1 =>
nxt := idle;
when exe2 =>
if counter < 1 then
nxt := exe2;
else
nxt := idle;
end if;
when exe3 =>
if counter < 2 then
nxt := exe3;
else
nxt := idle;
end if;
end case;
return nxt;
end next_state;
begin
-- CU
process (clk)
begin
if clk'event and clk = '0' then
st <= next_state(st, start, op, counter);
end if;
end process;
enOP <= '1' when st = getOP else '0';
enA <= '1' when st = getA else '0';
enB <= '1' when st = getB else '0';
enEXE1 <= '1' when st = exe1 else '0';
enEXE2 <= '1' when st = exe2 else '0';
enEXE3 <= '1' when st = exe3 else '0';
-- DATAPATH
process (clk)
variable tmp : std_logic_vector(15 downto 0);
begin
if enOP = '1' then
OP <= din(1 downto 0);
counter <= 0;
end if;
if enA = '1' then
A <= din;
end if;
if enB = '1' then
B <= din;
end if;
if enEXE1 = '1' then
REG <= A and B;
dout <= REG;
end if;
if enEXE2 = '1' then
if counter = 1 then
if A < B then
tmp := A;
else
tmp := B;
end if;
if tmp < REG then
REG <= tmp;
dout <= REG;
else
dout <= REG;
end if;
else
counter <= counter + 1;
end if;
end if;
if enEXE3 = '1' then
if counter = 2 then
if op = "01" then
tmp := A + REG;
REG <= tmp;
dout <= REG;
else -- OP "10"
REG <= A + B;
dout <= REG;
end if;
else
counter <= counter + 1;
end if;
end if;
if enEXE1 = '1' or (enEXE2 = '1' and counter = 1) or (enEXE3 = '1' and counter = 2) then
fine <= '1';
else
fine <= '0';
end if;
end process;
end architecture; |
-------------------------------------------------------------------------------
--
-- File: DMA_Transfer_Manager.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module manages all transfers from main memory to local buffers through
-- DMA, both control data (Queue Heads, Transfer Descriptors)and packet data.
-- Control registers are visible to this module.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
entity DMA_Transfer_Manager is
generic (
-- The master will start generating data from the C_M_START_DATA_VALUE value
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
-- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := "0100000000";
-- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M_AXI_ADDR_WIDTH : integer := 10;
-- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M_AXI_DATA_WIDTH : integer := 32;
-- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
C_M_TRANSACTIONS_NUM : integer := 4;
C_FIFO_SIZE : integer := 64
);
port (
Axi_Clk : IN std_logic;
Axi_Resetn : IN std_logic;
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0); --debug purposes
state_ind_arb : out std_logic_vector(5 downto 0); --debug purposes
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0); --debug purposes
ind_statte_axistream : out std_logic_vector(4 downto 0); --debug purposes
--AXI Lite Master for DMA control
a_M_Axi_Awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Awprot : out std_logic_vector(2 downto 0);
a_M_Axi_Awvalid : out std_logic;
a_M_Axi_Awready : in std_logic;
a_M_Axi_Wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Wstrb : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
a_M_Axi_Wvalid : out std_logic;
a_M_Axi_Wready : in std_logic;
a_M_Axi_Bresp : in std_logic_vector(1 downto 0);
a_M_Axi_Bvalid : in std_logic;
a_M_Axi_Bready : out std_logic;
a_M_Axi_Araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Arprot : out std_logic_vector(2 downto 0);
a_M_Axi_Arvalid : out std_logic;
a_M_Axi_Arready : in std_logic;
a_M_Axi_Rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Rresp : in std_logic_vector(1 downto 0);
a_M_Axi_Rvalid : in std_logic;
a_M_Axi_Rready : out std_logic;
--AXI Stream interface taht enables the DMA to write/read to/from the Context Memory
a_S_Axis_MM2S_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_S_Axis_MM2S_Tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a_S_Axis_MM2S_Tvalid : IN STD_LOGIC;
a_S_Axis_MM2S_Tready : OUT STD_LOGIC;
a_S_Axis_MM2S_Tlast : IN STD_LOGIC;
a_M_Axis_S2MM_Tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_M_Axis_S2MM_Tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a_M_Axis_S2MM_Tvalid : OUT STD_LOGIC;
a_M_Axis_S2MM_Tready : IN STD_LOGIC;
a_M_Axis_S2MM_Tlast : OUT STD_LOGIC;
--Command FIFO; used to keep track of received OUT transactions
RX_COMMAND_FIFO_RD_EN : OUT std_logic;
RX_COMMAND_FIFO_DOUT : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
RX_COMMAND_FIFO_EMPTY : IN std_logic;
RX_COMMAND_FIFO_VALID : IN std_logic;
--FIFO control signals
arb_tx_fifo_s_aresetn : OUT std_logic;
--multiplex between FIFO access and Context memory access
a_Axis_MM2S_Mux_Ctrl : OUT STD_LOGIC;
a_Axis_S2MM_Mux_Ctrl : OUT STD_LOGIC;
--Protocol_Engine interface
a_Send_Zero_Length_Packet_Set : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Set_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_In_Packet_Complete_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --a bit is set when the corresponding endpoint has completed an IN transaction
a_In_Packet_Complete_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Packet_Complete_Clear_En : OUT STD_LOGIC; --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Rd : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- a bit is set when the corresponding endpoint has received an IN token
a_In_Token_Received_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Clear_En : OUT STD_LOGIC; --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Cnt_Bytes_Sent : in std_logic_vector(12 downto 0); --number of bytes sent in response to an IN token
a_Cnt_Bytes_Sent_oValid : IN std_logic;
a_Resend : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --indicates that the endpoint corresponding to set bits need to resend a packet
a_Resend_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Resend_Clear_En : OUT STD_LOGIC; --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Pe_Endpt_Nr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the lower layers (ULPI, Packet_Decoder)
a_Arb_Endpt_Nr : OUT std_logic_vector(4 downto 0); --endpoint accessed by the DMA_Transfer_Manager
--Control_Registers interface
a_USBSTS_Wr_UI : OUT std_logic;
a_USBSTS_Wr_en_UI : OUT std_logic;
a_USBMODE_Rd : in std_logic_vector(31 downto 0);
a_USBCMD_SUTW_Wr : out std_logic;
a_USBCMD_SUTW_Wr_En : out std_logic;
a_USBCMD_ATDTW_Wr : out std_logic;
a_USBCMD_ATDTW_Wr_En : out std_logic;
a_EMDPTFLUSH_Rd : in std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set : out std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set_En : out std_logic;
a_ENDPTPRIME_Rd : in std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear_En : out std_logic;
a_ENDPTPRIME_Set : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Set_En : out std_logic;
a_ENDPTSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr_En : out std_logic;
a_ENDPTSETUPSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTSETUPSTAT_Wr_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Rd : in std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear : out std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Ack : in std_logic;
a_ENDPOINTLISTADDR_Rd : in std_logic_vector(31 downto 0)
);
end DMA_Transfer_Manager;
architecture implementation of DMA_Transfer_Manager is
COMPONENT DMA_Operations
PORT(
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
M_AXI_AWREADY : IN std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BRESP : IN std_logic_vector(1 downto 0);
M_AXI_BVALID : IN std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RDATA : IN std_logic_vector(31 downto 0);
M_AXI_RRESP : IN std_logic_vector(1 downto 0);
M_AXI_RVALID : IN std_logic;
M_AXI_AWADDR : OUT std_logic_vector(9 downto 0);
M_AXI_AWPROT : OUT std_logic_vector(2 downto 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_WDATA : OUT std_logic_vector(31 downto 0);
M_AXI_WSTRB : OUT std_logic_vector(3 downto 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_BREADY : OUT std_logic;
M_AXI_ARADDR : OUT std_logic_vector(9 downto 0);
M_AXI_ARPROT : OUT std_logic_vector(2 downto 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_RREADY : OUT std_logic;
dma_transfer_complete : OUT std_logic;
start_dma_s2mm : IN std_logic;
start_dma_mm2s : IN std_logic;
dma_transfer_length : in STD_LOGIC_VECTOR(31 downto 0);
dma_source_dest_address : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Context
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ENDPT_NR : in integer range 0 to 22;
-- ENDPT_NR_PD : in integer range 0 to 22;
RD_EN : IN std_logic;
WR_EN : IN std_logic;
dTD_TOTAL_BYTES_WR_EN : IN std_logic;
dTD_STATUS_WR_EN : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_NEXT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_SETUP_BUFFER_wr_EN : in STD_LOGIC;
dQH_MULT_wr : IN std_logic_vector(1 downto 0);
dQH_ZLT_wr : IN std_logic;
dQH_MAX_PACKET_LENGTH_wr : IN std_logic_vector(10 downto 0);
dQH_IOS_wr : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_T_wr : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : IN std_logic_vector(14 downto 0);
dTD_IOC_wr : IN std_logic;
dTD_C_PAGE_wr : IN std_logic_vector(2 downto 0);
dTD_MULT_wr : IN std_logic_vector(1 downto 0);
dTD_STATUS_wr : IN std_logic_vector(7 downto 0);
dTD_PAGE0_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE1_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE2_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE3_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE4_wr : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : IN std_logic_vector(11 downto 0);
dQH_MULT_rd : OUT std_logic_vector(1 downto 0);
dQH_ZLT_rd : OUT std_logic;
-- pe_dQH_ZLT_rd : OUT STD_LOGIC;
dQH_MAX_PACKET_LENGTH_rd : OUT std_logic_vector(10 downto 0);
dQH_IOS_rd : OUT std_logic;
dQH_CURRENT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_T_rd : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : OUT std_logic_vector(14 downto 0);
dTD_IOC_rd : OUT std_logic;
dTD_C_PAGE_rd : OUT std_logic_vector(2 downto 0);
dTD_MULT_rd : OUT std_logic_vector(1 downto 0);
dTD_STATUS_rd : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_rd : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT Context_to_Stream
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ind_statte_axistream : out std_logic_vector(4 downto 0);
dQH_RD : IN std_logic;
dQH_WR : IN std_logic;
dTD_RD : IN std_logic;
dTD_WR : IN std_logic;
SETUP_WR : IN STD_LOGIC;
dQH_WR_EN : out STD_LOGIC;
s_axis_mm2s_tdata : IN std_logic_vector(31 downto 0);
s_axis_mm2s_tkeep : IN std_logic_vector(3 downto 0);
s_axis_mm2s_tvalid : IN std_logic;
s_axis_mm2s_tlast : IN std_logic;
m_axis_s2mm_tready : IN std_logic;
dQH_MULT_rd : IN std_logic_vector(1 downto 0);
dQH_ZLT_rd : IN std_logic;
dQH_MAX_PACKET_LENGTH_rd : IN std_logic_vector(10 downto 0);
dQH_IOS_rd : IN std_logic;
dQH_CURRENT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_T_rd : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : IN std_logic_vector(14 downto 0);
dTD_IOC_rd : IN std_logic;
dTD_C_PAGE_rd : IN std_logic_vector(2 downto 0);
dTD_MULT_rd : IN std_logic_vector(1 downto 0);
dTD_STATUS_rd : IN std_logic_vector(7 downto 0);
dTD_PAGE0_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE1_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE2_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE3_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE4_rd : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : IN std_logic_vector(11 downto 0);
s_axis_mm2s_tready : OUT std_logic;
m_axis_s2mm_tdata : OUT std_logic_vector(31 downto 0);
m_axis_s2mm_tkeep : OUT std_logic_vector(3 downto 0);
m_axis_s2mm_tvalid : OUT std_logic;
m_axis_s2mm_tlast : OUT std_logic;
dQH_MULT_wr : OUT std_logic_vector(1 downto 0);
dQH_ZLT_wr : OUT std_logic;
dQH_MAX_PACKET_LENGTH_wr : OUT std_logic_vector(10 downto 0);
dQH_IOS_wr : OUT std_logic;
dQH_CURRENT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_T_wr : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : OUT std_logic_vector(14 downto 0);
dTD_IOC_wr : OUT std_logic;
dTD_C_PAGE_wr : OUT std_logic_vector(2 downto 0);
dTD_MULT_wr : OUT std_logic_vector(1 downto 0);
dTD_STATUS_wr : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_wr : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
constant ATDTW : integer := 14;
constant SUTW : integer := 13;
constant SLOM : integer := 3;
type state_type is (IDLE, PRIME_MM2S_DQH, PRIME_WAIT0, PRIME_MM2S_DTD, PRIME_WAIT1, PRIME_WAIT2, PRIME_FILL_FIFO, PRIME_FILL_FIFO_1, IN_HANDSHAKE, PRIME_FILL_FIFO_2, SETUP_LOCKOUT_TRIPWIRE, SETUP_UPDATE_SETUP_BYTES, SETUP_WAIT1, SETUP_S2MM, SETUP_UPDATE_ENDPTSETUP_RECEIVED, SETUP_WAIT2, START_OUT_FRAMEWORK, OUT_START_TRANSFER, OUT_TRANSFER_S2MM, OUT_WAIT1, OUT_CHECK_COMPLETE, OUT_TRANSFER_COMPLETE, OUT_FETCH_NEXT_DTD, OUT_WAIT2,START_IN_FRAMEWORK, IN_TRANSFER_MM2S, IN_RELOAD_BUFFER, IN_WAIT0, IN_WAIT1, IN_CHECK_COMPLETE, IN_TRANSACTION_COMPLETE, IN_FETCH_NEXT_DTD, IN_WAIT2);
signal state, next_state : state_type;
type DMA_CURRENT_TRANSFER_ADDRESS is array (11 downto 0) of std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Array, a_DMA_Current_Transfer_Addr_Array_q : DMA_CURRENT_TRANSFER_ADDRESS;
signal a_Context_Mux_Ctrl : std_logic;
signal a_Read_dQH : std_logic;
signal a_Read_dQH_Fsm : std_logic;
signal a_Read_dQH_q : std_logic;
signal a_Write_dQH : std_logic;
signal a_Write_dQH_Fsm : std_logic;
signal a_Write_dQH_q : std_logic;
signal a_Read_dTD : std_logic;
signal a_Read_dTD_Fsm : std_logic;
signal a_Read_dTD_q : std_logic;
signal write_dTD : std_logic;
signal a_Write_Setup_Bytes, a_Write_Setup_Bytes_q, a_Write_Setup_Bytes_FSM : std_logic;
signal a_dQH_Wr_En_Mux_Stream : std_logic;
signal a_dQH_Wr_En_Mux_Out : std_logic;
signal a_dQH_Wr_En_Mux_Arb : std_logic;
signal a_Start_DMA_S2MM : std_logic;
signal a_Start_DMA_MM2S : std_logic;
signal a_DMA_Source_Dest_Addr : std_logic_vector(31 downto 0);
signal a_DMA_Transfer_Length : std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Fsm : std_logic_vector (31 downto 0);
signal a_DMA_Current_Transfer_Addr_Le : std_logic;
signal a_DMA_Transfer_Complete : STD_LOGIC;
signal a_Aux_Addr_Register : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length_Le : std_logic;
signal a_Axis_MM2S_Mux_Ctrl_Fsm , a_Axis_S2MM_Mux_Ctrl_Fsm : STD_LOGIC;
signal a_Arb_dQH_MULT_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dQH_ZLT_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0); --not used
signal a_Arb_dQH_IOS_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Arb_dQH_Current_dTD_Pointer_Wr_En : STD_LOGIC;
signal a_Arb_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0); --not used
signal a_Arb_dQH_Next_dTD_Pointer_Wr_En : STD_LOGIC; --not used
signal a_Arb_dQH_T_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Arb_dTD_Total_Bytes_Wr_En : STD_LOGIC;
signal a_Arb_dTD_IOC_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0); --not used
signal a_Arb_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0); --not used
signal a_Arb_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page4_wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0); --not used
signal a_Stream_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dQH_Zlt_Wr : STD_LOGIC;
signal a_Stream_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_Stream_dQH_IOS_Wr : STD_LOGIC;
signal a_Stream_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_Next_dTD_Pointer_wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_T_Wr : STD_LOGIC;
signal a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Stream_dTD_IOC_Wr : STD_LOGIC;
signal a_Stream_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_Stream_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_Stream_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Wr : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Wr : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Wr : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Wr : STD_LOGIC;
signal a_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Setup_Buffer_Wr_En : std_logic;
signal a_dTD_Status_Wr_En : STD_LOGIC;
signal a_dQH_MULT_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Rd : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Rd : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Rd : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Rd : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Rd : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Rd : STD_LOGIC;
signal a_dTD_C_Page_Rd : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Rd : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Rd : STD_LOGIC_VECTOR (11 downto 0);
signal a_Out_Transfer_Byte_Count_Le1 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count_Le2 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count : std_logic_vector (12 downto 0);
signal a_Endpointlistaddr_Loc : std_logic_vector(20 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En_Fsm : std_logic;
signal a_ENDPTSETUPSTAT_Wr_Fsm : std_logic_vector(31 downto 0);
signal a_USBSTS_Wr_UI_Fsm : std_logic;
signal a_USBSTS_Wr_En_UI_Fsm : std_logic;
signal a_ENDPTSTAT_Set : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Set_En : std_logic;
signal a_ENDPTSTAT_clear : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Clear_En : std_logic;
signal a_ENDPTSTAT_Wr_Loc : std_logic_vector(31 downto 0);
signal tx_fifo_resetn : std_logic;
signal a_Prime : STD_LOGIC;
signal a_Setup_Received : STD_LOGIC;
signal a_In_Token_Received : STD_LOGIC;
signal a_Endpt_Nr_Int : integer range 0 to 23;
signal a_Endpt_Nr_Fsm : integer range 0 to 23;
signal a_Endpt_Nr_Le : STD_LOGIC;
signal a_Endpt_Nr : std_logic_vector(4 downto 0);
signal a_Endpt_Nr_4b : integer range 0 to 27;
signal a_Endpt_Nr_Prime : integer range 0 to 23;
signal a_Endpt_Nr_Setup : integer range 0 to 23;
signal a_Endpt_Nr_In_Token : integer range 0 to 23;
signal a_Endpt_In_Out : STD_LOGIC;
signal a_Bit_Index : integer range 0 to 27;
signal a_Cnt_Bytes_Sent_Loc : std_logic_vector (12 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of state_ind_arb : signal is "true";
-- attribute keep of state_ind_arb : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute mark_debug of a_Setup_Received : signal is "true";
-- attribute keep of a_Setup_Received : signal is "true";
-- attribute mark_debug of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute keep of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute mark_debug of a_In_Packet_Complete_Rd : signal is "true";
-- attribute keep of a_In_Packet_Complete_Rd : signal is "true";
-- attribute mark_debug of a_In_Token_Received : signal is "true";
-- attribute keep of a_In_Token_Received : signal is "true";
-- attribute mark_debug of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute keep of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute mark_debug of a_Bit_Index : signal is "true";
-- attribute keep of a_Bit_Index : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Prime : signal is "true";
-- attribute keep of a_Endpt_Nr_Prime : signal is "true";
-- attribute mark_debug of a_Endpt_Nr : signal is "true";
-- attribute keep of a_Endpt_Nr : signal is "true";
-- attribute mark_debug of a_Endpt_In_Out : signal is "true";
-- attribute keep of a_Endpt_In_Out : signal is "true";
-- attribute mark_debug of a_In_Token_Received_Rd : signal is "true";
-- attribute keep of a_In_Token_Received_Rd : signal is "true";
-- attribute mark_debug of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute keep of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute mark_debug of a_Prime : signal is "true";
-- attribute keep of a_Prime : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute keep of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set : signal is "true";
-- attribute mark_debug of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute keep of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Int : signal is "true";
-- attribute keep of a_Endpt_Nr_Int : signal is "true";
begin
a_Aux_Addr_Register <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd;
arb_tx_fifo_s_aresetn <= tx_fifo_resetn;
a_Axis_MM2S_Mux_Ctrl <= a_Axis_MM2S_Mux_Ctrl_Fsm;
a_Axis_S2MM_Mux_Ctrl <= a_Axis_S2MM_Mux_Ctrl_Fsm;
a_Endpointlistaddr_Loc <= a_ENDPOINTLISTADDR_Rd(31 downto 11);
-- This module is responsible with implementing the S2MM and MM2S frameworks for the DMA engine
Inst_DMA_Operations: DMA_Operations PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
state_ind_dma => state_ind_dma,
DEBUG_REG_DATA => DEBUG_REG_DATA,
M_AXI_AWADDR => a_M_Axi_Awaddr,
M_AXI_AWPROT => a_M_Axi_Awprot,
M_AXI_AWVALID => a_M_Axi_Awvalid,
M_AXI_AWREADY => a_M_Axi_Awready,
M_AXI_WDATA => a_M_Axi_Wdata,
M_AXI_WSTRB => a_M_Axi_Wstrb,
M_AXI_WVALID => a_M_Axi_Wvalid,
M_AXI_WREADY => a_M_Axi_Wready,
M_AXI_BRESP => a_M_Axi_Bresp,
M_AXI_BVALID => a_M_Axi_Bvalid,
M_AXI_BREADY => a_M_Axi_Bready,
M_AXI_ARADDR => a_M_Axi_Araddr,
M_AXI_ARPROT => a_M_Axi_Arprot,
M_AXI_ARVALID => a_M_Axi_Arvalid,
M_AXI_ARREADY => a_M_Axi_Arready,
M_AXI_RDATA => a_M_Axi_Rdata,
M_AXI_RRESP => a_M_Axi_Rresp,
M_AXI_RVALID => a_M_Axi_Rvalid,
M_AXI_RREADY => a_M_Axi_Rready,
dma_transfer_complete => a_DMA_Transfer_Complete,
start_dma_s2mm => a_Start_DMA_S2MM,
start_dma_mm2s => a_Start_DMA_MM2S,
dma_source_dest_address => a_DMA_Source_Dest_Addr,
dma_transfer_length => a_DMA_Transfer_Length
);
-- This module implements the context memory (Queue Heads, Transfer Descriptors)
Inst_Context: Context PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ENDPT_NR => a_Endpt_Nr_Int,
RD_EN => '0',
WR_EN => a_dQH_Wr_En_Mux_Out,
dQH_CURRENT_dTD_POINTER_wr_EN => a_Arb_dQH_Current_dTD_Pointer_Wr_En,
dQH_NEXT_dTD_POINTER_wr_en => a_Arb_dQH_Next_dTD_Pointer_Wr_En,
dTD_TOTAL_BYTES_WR_EN => a_Arb_dTD_Total_Bytes_Wr_En,
dTD_STATUS_WR_EN => a_dTD_Status_Wr_En,
dQH_SETUP_BUFFER_wr_EN => a_dQH_Setup_Buffer_Wr_En,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd ,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_dQH_Mult_Wr,
dQH_ZLT_wr => a_dQH_ZLT_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_dQH_Next_dTD_Pointer_Wr,
dQH_T_wr => a_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_dTD_C_Page_Wr,
dTD_MULT_wr => a_dTD_Mult_Wr,
dTD_STATUS_wr => a_dTD_Status_Wr,
dTD_PAGE0_wr => a_dTD_Page0_Wr,
dTD_PAGE1_wr => a_dTD_Page1_Wr,
dTD_PAGE2_wr => a_dTD_Page2_Wr,
dTD_PAGE3_wr => a_dTD_Page3_Wr,
dTD_PAGE4_wr => a_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_dTD_Current_Offset_Wr
);
-- This module handles control data transfers (Setup packets, dTD, dQH, Status) through the DMA module
Inst_Context_to_Stream: Context_to_Stream PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ind_statte_axistream => ind_statte_axistream,
dQH_RD => a_Read_dQH,
dQH_WR => a_Write_dQH,
dTD_RD => a_Read_dTD,
dTD_WR => write_dTD,
SETUP_WR => a_Write_Setup_Bytes,
dQH_WR_EN => a_dQH_Wr_En_Mux_Stream,
s_axis_mm2s_tdata => a_S_Axis_MM2S_Tdata,
s_axis_mm2s_tkeep => a_S_Axis_MM2S_Tkeep,
s_axis_mm2s_tvalid => a_S_Axis_MM2S_Tvalid,
s_axis_mm2s_tready => a_S_Axis_MM2S_Tready,
s_axis_mm2s_tlast => a_S_Axis_MM2S_Tlast,
m_axis_s2mm_tdata => a_M_Axis_S2MM_Tdata,
m_axis_s2mm_tkeep => a_M_Axis_S2MM_Tkeep,
m_axis_s2mm_tvalid => a_M_Axis_S2MM_Tvalid,
m_axis_s2mm_tready => a_M_Axis_S2MM_Tready,
m_axis_s2mm_tlast => a_M_Axis_S2MM_Tlast,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_Stream_dQH_Mult_Wr,
dQH_ZLT_wr => a_Stream_dQH_Zlt_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_Stream_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_Stream_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_Stream_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_Stream_dQH_Next_dTD_Pointer_wr,
dQH_T_wr => a_Stream_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_Stream_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_Stream_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_Stream_dTD_C_Page_Wr,
dTD_MULT_wr => a_Stream_dTD_Mult_Wr,
dTD_STATUS_wr => a_Stream_dTD_Status_Wr,
dTD_PAGE0_wr => a_Stream_dTD_Page0_Wr,
dTD_PAGE1_wr => a_Stream_dTD_Page1_Wr,
dTD_PAGE2_wr => a_Stream_dTD_Page2_Wr,
dTD_PAGE3_wr => a_Stream_dTD_Page3_Wr,
dTD_PAGE4_wr => a_Stream_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_Stream_dTD_Current_Offset_Wr
);
--Both DMA Engine and the DMA_Transfer_MAnager can read/write to the context memory. The MUX is implemented below
--DMA_Transfer_MAnager controls this MUX
a_dQH_Mult_Wr <= a_Stream_dQH_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_MULT_Wr ;
a_dQH_ZLT_Wr <= a_Stream_dQH_Zlt_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_ZLT_Wr;
a_dQH_Max_Packet_Length_Wr <= a_Stream_dQH_Max_Packet_Length_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Max_Packet_Length_Wr;
a_dQH_IOS_Wr <= a_Stream_dQH_IOS_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_IOS_Wr;
a_dQH_Current_dTD_Pointer_Wr <= a_Stream_dQH_Current_dTD_Pointer_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Current_dTD_Pointer_Wr;
a_dQH_Next_dTD_Pointer_Wr <= a_Stream_dQH_Next_dTD_Pointer_wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Next_dTD_Pointer_Wr;
a_dQH_T_Wr <= a_Stream_dQH_T_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_T_Wr;
a_dQH_Setup_Buffer_Bytes_3_0_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr;
a_dQH_Setup_Buffer_Bytes_7_4_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr;
a_dTD_Total_Bytes_Wr <= a_Stream_dTD_Total_Bytes_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Total_Bytes_Wr;
a_dTD_IOC_Wr <= a_Stream_dTD_IOC_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_IOC_Wr;
a_dTD_C_Page_Wr <= a_Stream_dTD_C_Page_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_C_Page_Wr;
a_dTD_Mult_Wr <= a_Stream_dTD_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Mult_Wr;
a_dTD_Status_Wr <= a_Stream_dTD_Status_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Status_Wr;
a_dTD_Page0_Wr <= a_Stream_dTD_Page0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page0_Wr;
a_dTD_Page1_Wr <= a_Stream_dTD_Page1_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page1_Wr;
a_dTD_Page2_Wr <= a_Stream_dTD_Page2_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page2_Wr;
a_dTD_Page3_Wr <= a_Stream_dTD_Page3_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page3_Wr;
a_dTD_Page4_Wr <= a_Stream_dTD_Page4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page4_wr;
a_dTD_Current_Offset_Wr <= a_Stream_dTD_Current_Offset_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Current_Offset_Wr;
a_dQH_Wr_En_Mux_Out <= a_dQH_Wr_En_Mux_Stream when (a_Context_Mux_Ctrl = '0') else
a_dQH_Wr_En_Mux_Arb;
--Generate control signals for Context_to_Stream module. Control signals
--must be pulses
IMPULSE_WRITE_DQH: process (Axi_Clk, a_Write_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_dQH <= '0';
a_Write_dQH_q <= '0';
else
a_Write_dQH_q <= a_Write_dQH_Fsm;
a_Write_dQH <= a_Write_dQH_Fsm and (not a_Write_dQH_q);
end if;
end if;
end process;
IMPULSE_WRITE_SETUP: process (Axi_Clk, a_Write_Setup_Bytes_FSM)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_Setup_Bytes <= '0';
a_Write_Setup_Bytes_q <= '0';
else
a_Write_Setup_Bytes_q <= a_Write_Setup_Bytes_FSM;
a_Write_Setup_Bytes <= a_Write_Setup_Bytes_FSM and (not a_Write_Setup_Bytes_q);
end if;
end if;
end process;
IMPULSE_READ_DQH: process (Axi_Clk, a_Read_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dQH <= '0';
a_Read_dQH_q <= '0';
else
a_Read_dQH_q <= a_Read_dQH_Fsm;
a_Read_dQH <= a_Read_dQH_Fsm and (not a_Read_dQH_q);
end if;
end if;
end process;
IMPULSE_READ_DTD_PROC: process (Axi_Clk, a_Read_dTD_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dTD <= '0';
a_Read_dTD_q <= '0';
else
a_Read_dTD_q <= a_Read_dTD_Fsm;
a_Read_dTD <= a_Read_dTD_Fsm and (not a_Read_dTD_q);
end if;
end if;
end process;
--combinational signals generated by the state machine are registered
REGISTER_Q_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSETUPSTAT_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr <= (others => '0');
a_USBSTS_Wr_UI <= '0';
a_USBSTS_Wr_en_UI <= '0';
else
a_ENDPTSETUPSTAT_Wr_En <= a_ENDPTSETUPSTAT_Wr_En_Fsm;
a_ENDPTSETUPSTAT_Wr <= a_ENDPTSETUPSTAT_Wr_Fsm;
a_USBSTS_Wr_UI <= a_USBSTS_Wr_UI_Fsm;
a_USBSTS_Wr_en_UI <= a_USBSTS_Wr_En_UI_Fsm;
end if;
end if;
end process;
a_ENDPTSTAT_Wr <= a_ENDPTSTAT_Wr_Loc;
--generate the ENDPTSTAT register
ENDPTSTAT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSTAT_Wr_Loc <= (others => '0');
elsif (a_ENDPTSTAT_Set_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc or a_ENDPTSTAT_Set;
elsif (a_ENDPTSTAT_Clear_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and a_ENDPTSTAT_clear;
elsif (a_EMDPTFLUSH_Rd /= "00000000000000000000000000000000") then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and (not(a_EMDPTFLUSH_Rd));
end if;
end if;
end process;
a_Cnt_Bytes_Sent_Loc <= a_Cnt_Bytes_Sent;
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on in integer format
ENDPT_NR_INT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Int <= 0;
elsif (a_Endpt_Nr_Le = '1') then
a_Endpt_Nr_Int <= a_Endpt_Nr_Fsm;
end if;
end if;
end process;
a_Endpt_Nr <= std_logic_vector(to_unsigned(a_Endpt_Nr_Int,5));
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on. Lower layers need to be aware of this
ARB_ENDPT_NR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Arb_Endpt_Nr <= (others => '0');
else
a_Arb_Endpt_Nr <= a_Endpt_Nr;
end if;
end if;
end process;
--determin the endpoint type
DET_ENDPTTYPE: process (Axi_Resetn, a_Endpt_Nr)
begin
if (a_Endpt_Nr(0) = '0') then
a_Endpt_In_Out <= '0';
else
a_Endpt_In_Out <= '1';
end if;
end process;
a_Endpt_Nr_4b <= to_integer(unsigned(a_Endpt_Nr(4 downto 1)));
-- Control registers usually have bits [27:16] referring to IN endpoints asnd bits[11:0] referring to OUT endpoint
DET_INDEX: process (Axi_Resetn, a_Endpt_Nr_4b, a_Endpt_In_Out)
begin
if (a_Endpt_In_Out = '0') then
a_Bit_Index <= a_Endpt_Nr_4b;
else
a_Bit_Index <= a_Endpt_Nr_4b + 16;
end if;
end process;
-- Determin the endpoint selected for priming from endptprime register
DET_PRIME_ENDPTNR_PROC: process (Axi_Clk, a_ENDPTPRIME_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
elsif(a_ENDPTPRIME_Rd /= "00000000000000000000000000000000") then
a_Prime <= '1';
for endptprime_index in 0 to 27 loop
if (endptprime_index < 12) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= endptprime_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (endptprime_index >= 16) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= (endptprime_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
end if;
end if;
end process;
--Determin the endpoint number from setup_received register
DET_SETUP_ENDPTNR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
elsif(a_Arb_ENDPTSETUP_RECEIVED_Rd /= "00000000000000000000000000000000") then
a_Setup_Received <= '1';
for setup_index in 0 to 27 loop
if (setup_index < 12) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= setup_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (setup_index >= 16) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= (setup_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
end if;
end if;
end process;
--Determin the endpoint number from token_in_received register
DET_TOKEN_IN_ENDPTNR_PROC: process (Axi_Clk, a_In_Token_Received_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
elsif((a_In_Token_Received_Rd and a_ENDPTSTAT_Wr_Loc) /= "00000000000000000000000000000000") then
a_In_Token_Received <= '1';
for token_in_index in 0 to 27 loop
if (token_in_index < 12) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= token_in_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (token_in_index >= 16) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= (token_in_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
end if;
end if;
end process;
OUT_TRANSFER_BYTE_COUNT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Out_Transfer_Byte_Count <= (others => '0');
elsif (a_Out_Transfer_Byte_Count_Le1 = '1') then
a_Out_Transfer_Byte_Count <= RX_COMMAND_FIFO_DOUT(23 downto 11);
elsif (a_Out_Transfer_Byte_Count_Le2 = '1') then
a_Out_Transfer_Byte_Count <= std_logic_vector( to_unsigned((to_integer(unsigned(RX_COMMAND_FIFO_DOUT(23 downto 11))) - to_integer(unsigned(a_dTD_Total_Bytes_Rd))),13) );
end if;
end if;
end process;
DMA_TRANSFER_ADDR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_Current_Transfer_Addr_Array <= (others =>(others => '0'));
a_DMA_Current_Transfer_Addr_Array_q <= (others =>(others => '0'));
elsif (a_DMA_Current_Transfer_Addr_Le = '1') then
a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Fsm;
a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------
DECIDE_LENGTH_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_In_Transfer_Length <= (others => '0');
else
if (a_DMA_In_Transfer_Length_Le = '1') then
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
a_DMA_In_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
else
a_DMA_In_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
end if;
end if;
end if;
end if;
end process;
--DMA_Transfer_Manager State Machine
SYNC_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, a_dQH_Next_dTD_Pointer_Rd, a_Arb_ENDPTSETUP_RECEIVED_Ack, a_Cnt_Bytes_Sent_oValid, a_Send_Zero_Length_Packet_Ack_Rd, a_DMA_Current_Transfer_Addr_Array, a_Prime, RX_COMMAND_FIFO_VALID, a_dTD_Page0_Rd, a_dTD_Current_Offset_Rd,a_Endpt_Nr_4b, a_Endpt_Nr_Int, a_Aux_Addr_Register, a_In_Packet_Complete_Rd, a_Endpt_Nr_In_Token, RX_COMMAND_FIFO_EMPTY, a_Endpt_Nr_Setup, a_USBMODE_Rd, a_Bit_Index, RX_COMMAND_FIFO_DOUT, a_Out_Transfer_Byte_Count, a_Cnt_Bytes_Sent_Loc, a_dTD_Total_Bytes_Rd, a_dQH_Current_dTD_Pointer_Rd, a_dQH_T_Rd, a_Endpt_Nr_Prime, a_In_Token_Received, a_Endpt_In_Out, a_Setup_Received, a_DMA_Transfer_Complete, a_Endpointlistaddr_Loc)
begin
--declare default state for next_state to avoid latches
next_state <= state;
state_ind_arb <= "000000";
a_Context_Mux_Ctrl <= '0';
a_dQH_Wr_En_Mux_Arb <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '0';
a_Arb_dTD_Total_Bytes_Wr_En <= '0';
a_Arb_dQH_Next_dTD_Pointer_Wr_En <= '0';
a_dQH_Setup_Buffer_Wr_En <= '0';
a_dTD_Status_Wr_En <= '0';
a_Read_dQH_Fsm <= '0';
a_Write_dQH_Fsm <= '0';
a_Read_dTD_Fsm <= '0';
write_dTD <= '0';
a_Write_Setup_Bytes_FSM <= '0';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO as a DEFAULT; FIFO connected to DMA only when data ready
a_Axis_S2MM_Mux_Ctrl_Fsm <= '1';
a_Start_DMA_S2MM <= '0';
a_Start_DMA_MM2S <= '0';
a_DMA_Source_Dest_Addr <= (others => '0');
a_DMA_Transfer_Length <= (others => '0');
tx_fifo_resetn <= '1';
a_Endpt_Nr_Fsm <= 0;
a_Endpt_Nr_Le <= '0';
RX_COMMAND_FIFO_RD_EN <= '0';
a_Out_Transfer_Byte_Count_Le1 <= '0';
a_Out_Transfer_Byte_Count_Le2 <= '0';
a_DMA_Current_Transfer_Addr_Fsm <= (others => '0');
a_DMA_Current_Transfer_Addr_Le <= '0';
-- pe_setup_received_rst <= '1';
a_Arb_dQH_MULT_Wr <= (others => '0');
a_Arb_dQH_ZLT_Wr <= '0';
a_Arb_dQH_Max_Packet_Length_Wr <= (others => '0');
a_Arb_dQH_IOS_Wr <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_Next_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_T_Wr <= '0';
a_Arb_dTD_Total_Bytes_Wr <= (others => '0');
a_Arb_dTD_IOC_Wr <= '0';
a_Arb_dTD_C_Page_Wr <= (others => '0');
a_Arb_dTD_Mult_Wr <= (others => '0');
a_Arb_dTD_Status_Wr <= (others => '0');
a_Arb_dTD_Page0_Wr <= (others => '0');
a_Arb_dTD_Page1_Wr <= (others => '0');
a_Arb_dTD_Page2_Wr <= (others => '0');
a_Arb_dTD_Page3_Wr <= (others => '0');
a_Arb_dTD_Page4_wr <= (others => '0');
a_Arb_dTD_Current_Offset_Wr <= (others => '0');
a_USBSTS_Wr_UI_Fsm <= '0';
a_USBSTS_Wr_En_UI_Fsm <= '0';
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '0';
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '0';
a_ENDPTPRIME_Clear <= (others => '1');
a_ENDPTPRIME_Clear_En <= '0';
a_ENDPTPRIME_Set <= (others => '0');
a_ENDPTPRIME_Set_En <= '0';
a_ENDPTCOMPLETE_Wr <= (others => '0');
a_ENDPTCOMPLETE_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm <= (others => '0');
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear <= (others => '1');
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '0';
a_ENDPTSTAT_Set <= (others => '0');
a_ENDPTSTAT_Set_En <= '0';
a_ENDPTSTAT_clear <= (others => '1');
a_ENDPTSTAT_Clear_En <= '0';
a_EMDPTFLUSH_Set <= (others => '0');
a_EMDPTFLUSH_Set_En <= '0';
a_In_Packet_Complete_Clear_En <= '0';
a_In_Packet_Complete_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Set <= (others => '0');
a_Send_Zero_Length_Packet_Set_En <= '0';
a_Send_Zero_Length_Packet_Ack_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Ack_Clear_En <= '0';
a_In_Token_Received_Clear <= (others => '1');
a_In_Token_Received_Clear_En <= '0';
a_Resend_Clear_En <= '0';
a_Resend_Clear <= (others => '1');
a_DMA_In_Transfer_Length_Le <= '0';
case state is -- state machine triggered by 2 conditions: priming of an endpoint or setup packet arrival; setup packets processed separately; OUT framework not tested
when IDLE =>
state_ind_arb <= "000000";
if (a_Prime = '1') then
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Prime;
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Le <= '1';
next_state <= PRIME_MM2S_DQH;
elsif (a_Setup_Received = '1') then
a_Context_Mux_Ctrl <= '1';
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Setup;
a_Endpt_Nr_Le <= '1';
next_state <= SETUP_LOCKOUT_TRIPWIRE;
elsif (a_In_Token_Received = '1') then
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Fsm <= a_Endpt_Nr_In_Token;
a_Endpt_Nr_Le <= '1';
next_state <= START_IN_FRAMEWORK;
elsif (RX_COMMAND_FIFO_EMPTY /= '1' and RX_COMMAND_FIFO_VALID = '1') then
RX_COMMAND_FIFO_RD_EN <= '1';
next_state <= START_OUT_FRAMEWORK;
end if;
------------------SETUP PACKET PROCESSING--------------------------
when SETUP_LOCKOUT_TRIPWIRE =>
state_ind_arb <= "000001";
a_Context_Mux_Ctrl <= '1';
if (a_USBMODE_Rd(SLOM) = '0') then
next_state <= IDLE;
else
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_In_Token_Received_Clear(a_Bit_Index + 16) <= '0';
a_In_Token_Received_Clear_En <= '1';
a_EMDPTFLUSH_Set(a_Bit_Index + 16) <= '1';
a_EMDPTFLUSH_Set_En <= '1';
next_state <= SETUP_UPDATE_SETUP_BYTES;
end if;
when SETUP_UPDATE_SETUP_BYTES =>
state_ind_arb <= "000010";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_dQH_Setup_Buffer_Wr_En <= '1';
next_state <= SETUP_WAIT1;
when SETUP_WAIT1 => --wait for dqh to be updated in context memory
state_ind_arb <= "000011";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
next_state <= SETUP_S2MM;
when SETUP_S2MM =>
state_ind_arb <= "000100";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_Setup_Bytes_FSM <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned(((a_Endpt_Nr_Int*64)+40),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(8,32)); --dQH = 2*4 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_Setup_Bytes_FSM <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm(a_Bit_Index) <= '1';
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= SETUP_UPDATE_ENDPTSETUP_RECEIVED;
end if;
when SETUP_UPDATE_ENDPTSETUP_RECEIVED =>
state_ind_arb <= "000101";
a_Arb_ENDPTSETUP_RECEIVED_Clear(a_Bit_Index) <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '1';
if (a_Arb_ENDPTSETUP_RECEIVED_Ack = '1') then
next_state <= SETUP_WAIT2;
end if;
when SETUP_WAIT2 =>
next_state <= IDLE;
------------------------------ PRIME FRAMEWORK -----------------------------------------
when PRIME_MM2S_DQH => --read DQH from main memory
state_ind_arb <= "000110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dQH_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= PRIME_WAIT0;
end if;
when PRIME_WAIT0 =>
state_ind_arb <= "000000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
next_state <= PRIME_MM2S_DTD;
when PRIME_MM2S_DTD => --read DQH from main memory
state_ind_arb <= "100110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dTD = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_DMA_Current_Transfer_Addr_Fsm <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd; --initialize the transfer address with PAGE0
a_DMA_Current_Transfer_Addr_Le <= '1';
if (a_Endpt_In_Out = '1') then --IN endpoint, FIFO needs to be prepared with transmit data
tx_fifo_resetn <= '0'; -- flush fifo;
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
next_state <= PRIME_FILL_FIFO;
else --OUT endpoint
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
next_state <= PRIME_WAIT1;
end if;
end if;
when PRIME_FILL_FIFO => --extract necessary data to fill TX fifo
state_ind_arb <= "000111";
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Send_Zero_Length_Packet_Set(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Set_En <= '1';
next_state <= PRIME_WAIT1;
else
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
next_state <= PRIME_FILL_FIFO_1;
else
next_state <= PRIME_FILL_FIFO_2;
end if;
end if;
when PRIME_FILL_FIFO_1 =>
state_ind_arb <= "001000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_dTD_Total_Bytes_Rd)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_FILL_FIFO_2 =>
state_ind_arb <= "001001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + (C_FIFO_SIZE));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + (C_FIFO_SIZE)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_WAIT1 =>
state_ind_arb <= "001010";
next_state <= PRIME_WAIT2;
when PRIME_WAIT2 =>
state_ind_arb <= "001011";
next_state <= IDLE;
---------OUT_TOKEN_FRAMEWORK (RX_PACKET)---------------------------------------------------------------------------
when START_OUT_FRAMEWORK =>
state_ind_arb <= "001100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Out_Transfer_Byte_Count_Le1 <= '1';
a_Endpt_Nr_Fsm <= to_integer(unsigned(RX_COMMAND_FIFO_DOUT(10 downto 7)));
a_Endpt_Nr_Le <= '1';
next_state <= OUT_START_TRANSFER;
when OUT_START_TRANSFER =>
state_ind_arb <= "001101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
if (a_Out_Transfer_Byte_Count <= a_dTD_Total_Bytes_Rd)then
next_state <= OUT_TRANSFER_S2MM;
else
next_state <= IDLE; --ERROR
end if;
when OUT_TRANSFER_S2MM =>
state_ind_arb <= "001110";
a_Axis_S2MM_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= "0000000000000000000" & a_Out_Transfer_Byte_Count; --transfer the received packet in main memory
a_Start_DMA_S2MM <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Out_Transfer_Byte_Count)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b)) + unsigned(a_Out_Transfer_Byte_Count)); --update the memory address for the s2mm transfer
a_DMA_Current_Transfer_Addr_Le <= '1';
next_state <= OUT_WAIT1;
end if;
when OUT_WAIT1 =>
state_ind_arb <= "001111";
next_state <= OUT_CHECK_COMPLETE;
when OUT_CHECK_COMPLETE =>
state_ind_arb <= "010000";
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= OUT_TRANSFER_COMPLETE;
else
next_state <= IDLE;
end if;
when OUT_TRANSFER_COMPLETE =>
state_ind_arb <= "010001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_dQH_Fsm <= '0';
if (a_dQH_T_Rd = '0') then
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= OUT_FETCH_NEXT_DTD;
else
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
next_state <= IDLE;
end if;
end if;
when OUT_FETCH_NEXT_DTD =>
state_ind_arb <= "010010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= OUT_WAIT2;
end if;
when OUT_WAIT2 =>
state_ind_arb <= "010011";
next_state <= IDLE;
---------IN_TOKEN_FRAMEWORK (TX_PACKET)---------------------------------------------------------------------------
when START_IN_FRAMEWORK =>
state_ind_arb <= "010100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; --context memory connected to DMA stream port, not FIFO if 0 fifo will assert tvalid for 1 ck cycle
a_Context_Mux_Ctrl <= '0';
a_In_Token_Received_Clear(a_Bit_Index) <= '0';
a_In_Token_Received_Clear_En <= '1';
if (a_In_Packet_Complete_Rd(a_Bit_Index) = '1') then
a_In_Packet_Complete_Clear(a_Bit_Index) <= '0';
a_In_Packet_Complete_Clear_En <= '1';
next_state <= IN_HANDSHAKE;
elsif (a_Resend(a_Bit_Index) = '1') then
tx_fifo_resetn <= '0'; -- flush fifo;
next_state <= IN_HANDSHAKE;
end if;
when IN_HANDSHAKE =>
state_ind_arb <= "010101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1';
if (a_Cnt_Bytes_Sent_oValid = '1') then
if (a_Resend(a_Bit_Index) = '0') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Cnt_Bytes_Sent_Loc)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
end if;
next_state <= IN_WAIT0;
end if;
when IN_WAIT0 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
if (a_Resend(a_Bit_Index) = '0') then
next_state <= IN_CHECK_COMPLETE;
else
a_Resend_Clear(a_Bit_Index) <= '0';
a_Resend_Clear_En <= '1';
next_state <= IN_RELOAD_BUFFER;
end if;
when IN_CHECK_COMPLETE =>
state_ind_arb <= "011000";
a_DMA_In_Transfer_Length_Le <= '1';
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_dTD_Status_Wr_En <= '1'; --write 0 to active bit
next_state <= IN_TRANSACTION_COMPLETE;
else
next_state <= IN_TRANSFER_MM2S;
end if;
when IN_TRANSFER_MM2S =>
state_ind_arb <= "010110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + unsigned(a_Cnt_Bytes_Sent_Loc));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_Cnt_Bytes_Sent_Loc)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
end if;
when IN_RELOAD_BUFFER =>
state_ind_arb <= "111011";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
end if;
when IN_WAIT1 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
next_state <= IDLE;
when IN_TRANSACTION_COMPLETE => --copy dQH back to main memory with status updated
state_ind_arb <= "011001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1' or a_Send_Zero_Length_Packet_Ack_Rd(a_Bit_Index) = '1') then
a_Write_dQH_Fsm <= '0';
a_Send_Zero_Length_Packet_Ack_Clear(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Ack_Clear_En <= '1';
if (a_dQH_T_Rd = '1') then
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
a_ENDPTSTAT_clear(a_Bit_Index) <= '0';
a_ENDPTSTAT_Clear_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= IDLE;
else
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= IN_FETCH_NEXT_DTD;
end if;
end if;
when IN_FETCH_NEXT_DTD =>
state_ind_arb <= "011010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= IN_WAIT2;
end if;
when IN_WAIT2 =>
state_ind_arb <= "011011";
next_state <= IDLE;
when others =>
state_ind_arb <= "011100";
next_state <= IDLE;
end case;
end process;
end implementation;
|
-------------------------------------------------------------------------------
--
-- File: DMA_Transfer_Manager.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module manages all transfers from main memory to local buffers through
-- DMA, both control data (Queue Heads, Transfer Descriptors)and packet data.
-- Control registers are visible to this module.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
entity DMA_Transfer_Manager is
generic (
-- The master will start generating data from the C_M_START_DATA_VALUE value
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
-- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := "0100000000";
-- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M_AXI_ADDR_WIDTH : integer := 10;
-- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M_AXI_DATA_WIDTH : integer := 32;
-- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
C_M_TRANSACTIONS_NUM : integer := 4;
C_FIFO_SIZE : integer := 64
);
port (
Axi_Clk : IN std_logic;
Axi_Resetn : IN std_logic;
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0); --debug purposes
state_ind_arb : out std_logic_vector(5 downto 0); --debug purposes
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0); --debug purposes
ind_statte_axistream : out std_logic_vector(4 downto 0); --debug purposes
--AXI Lite Master for DMA control
a_M_Axi_Awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Awprot : out std_logic_vector(2 downto 0);
a_M_Axi_Awvalid : out std_logic;
a_M_Axi_Awready : in std_logic;
a_M_Axi_Wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Wstrb : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
a_M_Axi_Wvalid : out std_logic;
a_M_Axi_Wready : in std_logic;
a_M_Axi_Bresp : in std_logic_vector(1 downto 0);
a_M_Axi_Bvalid : in std_logic;
a_M_Axi_Bready : out std_logic;
a_M_Axi_Araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Arprot : out std_logic_vector(2 downto 0);
a_M_Axi_Arvalid : out std_logic;
a_M_Axi_Arready : in std_logic;
a_M_Axi_Rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Rresp : in std_logic_vector(1 downto 0);
a_M_Axi_Rvalid : in std_logic;
a_M_Axi_Rready : out std_logic;
--AXI Stream interface taht enables the DMA to write/read to/from the Context Memory
a_S_Axis_MM2S_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_S_Axis_MM2S_Tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a_S_Axis_MM2S_Tvalid : IN STD_LOGIC;
a_S_Axis_MM2S_Tready : OUT STD_LOGIC;
a_S_Axis_MM2S_Tlast : IN STD_LOGIC;
a_M_Axis_S2MM_Tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_M_Axis_S2MM_Tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a_M_Axis_S2MM_Tvalid : OUT STD_LOGIC;
a_M_Axis_S2MM_Tready : IN STD_LOGIC;
a_M_Axis_S2MM_Tlast : OUT STD_LOGIC;
--Command FIFO; used to keep track of received OUT transactions
RX_COMMAND_FIFO_RD_EN : OUT std_logic;
RX_COMMAND_FIFO_DOUT : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
RX_COMMAND_FIFO_EMPTY : IN std_logic;
RX_COMMAND_FIFO_VALID : IN std_logic;
--FIFO control signals
arb_tx_fifo_s_aresetn : OUT std_logic;
--multiplex between FIFO access and Context memory access
a_Axis_MM2S_Mux_Ctrl : OUT STD_LOGIC;
a_Axis_S2MM_Mux_Ctrl : OUT STD_LOGIC;
--Protocol_Engine interface
a_Send_Zero_Length_Packet_Set : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Set_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_In_Packet_Complete_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --a bit is set when the corresponding endpoint has completed an IN transaction
a_In_Packet_Complete_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Packet_Complete_Clear_En : OUT STD_LOGIC; --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Rd : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- a bit is set when the corresponding endpoint has received an IN token
a_In_Token_Received_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Clear_En : OUT STD_LOGIC; --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Cnt_Bytes_Sent : in std_logic_vector(12 downto 0); --number of bytes sent in response to an IN token
a_Cnt_Bytes_Sent_oValid : IN std_logic;
a_Resend : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --indicates that the endpoint corresponding to set bits need to resend a packet
a_Resend_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Resend_Clear_En : OUT STD_LOGIC; --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Pe_Endpt_Nr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the lower layers (ULPI, Packet_Decoder)
a_Arb_Endpt_Nr : OUT std_logic_vector(4 downto 0); --endpoint accessed by the DMA_Transfer_Manager
--Control_Registers interface
a_USBSTS_Wr_UI : OUT std_logic;
a_USBSTS_Wr_en_UI : OUT std_logic;
a_USBMODE_Rd : in std_logic_vector(31 downto 0);
a_USBCMD_SUTW_Wr : out std_logic;
a_USBCMD_SUTW_Wr_En : out std_logic;
a_USBCMD_ATDTW_Wr : out std_logic;
a_USBCMD_ATDTW_Wr_En : out std_logic;
a_EMDPTFLUSH_Rd : in std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set : out std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set_En : out std_logic;
a_ENDPTPRIME_Rd : in std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear_En : out std_logic;
a_ENDPTPRIME_Set : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Set_En : out std_logic;
a_ENDPTSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr_En : out std_logic;
a_ENDPTSETUPSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTSETUPSTAT_Wr_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Rd : in std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear : out std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Ack : in std_logic;
a_ENDPOINTLISTADDR_Rd : in std_logic_vector(31 downto 0)
);
end DMA_Transfer_Manager;
architecture implementation of DMA_Transfer_Manager is
COMPONENT DMA_Operations
PORT(
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
M_AXI_AWREADY : IN std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BRESP : IN std_logic_vector(1 downto 0);
M_AXI_BVALID : IN std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RDATA : IN std_logic_vector(31 downto 0);
M_AXI_RRESP : IN std_logic_vector(1 downto 0);
M_AXI_RVALID : IN std_logic;
M_AXI_AWADDR : OUT std_logic_vector(9 downto 0);
M_AXI_AWPROT : OUT std_logic_vector(2 downto 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_WDATA : OUT std_logic_vector(31 downto 0);
M_AXI_WSTRB : OUT std_logic_vector(3 downto 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_BREADY : OUT std_logic;
M_AXI_ARADDR : OUT std_logic_vector(9 downto 0);
M_AXI_ARPROT : OUT std_logic_vector(2 downto 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_RREADY : OUT std_logic;
dma_transfer_complete : OUT std_logic;
start_dma_s2mm : IN std_logic;
start_dma_mm2s : IN std_logic;
dma_transfer_length : in STD_LOGIC_VECTOR(31 downto 0);
dma_source_dest_address : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Context
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ENDPT_NR : in integer range 0 to 22;
-- ENDPT_NR_PD : in integer range 0 to 22;
RD_EN : IN std_logic;
WR_EN : IN std_logic;
dTD_TOTAL_BYTES_WR_EN : IN std_logic;
dTD_STATUS_WR_EN : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_NEXT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_SETUP_BUFFER_wr_EN : in STD_LOGIC;
dQH_MULT_wr : IN std_logic_vector(1 downto 0);
dQH_ZLT_wr : IN std_logic;
dQH_MAX_PACKET_LENGTH_wr : IN std_logic_vector(10 downto 0);
dQH_IOS_wr : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_T_wr : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : IN std_logic_vector(14 downto 0);
dTD_IOC_wr : IN std_logic;
dTD_C_PAGE_wr : IN std_logic_vector(2 downto 0);
dTD_MULT_wr : IN std_logic_vector(1 downto 0);
dTD_STATUS_wr : IN std_logic_vector(7 downto 0);
dTD_PAGE0_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE1_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE2_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE3_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE4_wr : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : IN std_logic_vector(11 downto 0);
dQH_MULT_rd : OUT std_logic_vector(1 downto 0);
dQH_ZLT_rd : OUT std_logic;
-- pe_dQH_ZLT_rd : OUT STD_LOGIC;
dQH_MAX_PACKET_LENGTH_rd : OUT std_logic_vector(10 downto 0);
dQH_IOS_rd : OUT std_logic;
dQH_CURRENT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_T_rd : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : OUT std_logic_vector(14 downto 0);
dTD_IOC_rd : OUT std_logic;
dTD_C_PAGE_rd : OUT std_logic_vector(2 downto 0);
dTD_MULT_rd : OUT std_logic_vector(1 downto 0);
dTD_STATUS_rd : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_rd : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT Context_to_Stream
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ind_statte_axistream : out std_logic_vector(4 downto 0);
dQH_RD : IN std_logic;
dQH_WR : IN std_logic;
dTD_RD : IN std_logic;
dTD_WR : IN std_logic;
SETUP_WR : IN STD_LOGIC;
dQH_WR_EN : out STD_LOGIC;
s_axis_mm2s_tdata : IN std_logic_vector(31 downto 0);
s_axis_mm2s_tkeep : IN std_logic_vector(3 downto 0);
s_axis_mm2s_tvalid : IN std_logic;
s_axis_mm2s_tlast : IN std_logic;
m_axis_s2mm_tready : IN std_logic;
dQH_MULT_rd : IN std_logic_vector(1 downto 0);
dQH_ZLT_rd : IN std_logic;
dQH_MAX_PACKET_LENGTH_rd : IN std_logic_vector(10 downto 0);
dQH_IOS_rd : IN std_logic;
dQH_CURRENT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_T_rd : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : IN std_logic_vector(14 downto 0);
dTD_IOC_rd : IN std_logic;
dTD_C_PAGE_rd : IN std_logic_vector(2 downto 0);
dTD_MULT_rd : IN std_logic_vector(1 downto 0);
dTD_STATUS_rd : IN std_logic_vector(7 downto 0);
dTD_PAGE0_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE1_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE2_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE3_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE4_rd : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : IN std_logic_vector(11 downto 0);
s_axis_mm2s_tready : OUT std_logic;
m_axis_s2mm_tdata : OUT std_logic_vector(31 downto 0);
m_axis_s2mm_tkeep : OUT std_logic_vector(3 downto 0);
m_axis_s2mm_tvalid : OUT std_logic;
m_axis_s2mm_tlast : OUT std_logic;
dQH_MULT_wr : OUT std_logic_vector(1 downto 0);
dQH_ZLT_wr : OUT std_logic;
dQH_MAX_PACKET_LENGTH_wr : OUT std_logic_vector(10 downto 0);
dQH_IOS_wr : OUT std_logic;
dQH_CURRENT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_T_wr : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : OUT std_logic_vector(14 downto 0);
dTD_IOC_wr : OUT std_logic;
dTD_C_PAGE_wr : OUT std_logic_vector(2 downto 0);
dTD_MULT_wr : OUT std_logic_vector(1 downto 0);
dTD_STATUS_wr : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_wr : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
constant ATDTW : integer := 14;
constant SUTW : integer := 13;
constant SLOM : integer := 3;
type state_type is (IDLE, PRIME_MM2S_DQH, PRIME_WAIT0, PRIME_MM2S_DTD, PRIME_WAIT1, PRIME_WAIT2, PRIME_FILL_FIFO, PRIME_FILL_FIFO_1, IN_HANDSHAKE, PRIME_FILL_FIFO_2, SETUP_LOCKOUT_TRIPWIRE, SETUP_UPDATE_SETUP_BYTES, SETUP_WAIT1, SETUP_S2MM, SETUP_UPDATE_ENDPTSETUP_RECEIVED, SETUP_WAIT2, START_OUT_FRAMEWORK, OUT_START_TRANSFER, OUT_TRANSFER_S2MM, OUT_WAIT1, OUT_CHECK_COMPLETE, OUT_TRANSFER_COMPLETE, OUT_FETCH_NEXT_DTD, OUT_WAIT2,START_IN_FRAMEWORK, IN_TRANSFER_MM2S, IN_RELOAD_BUFFER, IN_WAIT0, IN_WAIT1, IN_CHECK_COMPLETE, IN_TRANSACTION_COMPLETE, IN_FETCH_NEXT_DTD, IN_WAIT2);
signal state, next_state : state_type;
type DMA_CURRENT_TRANSFER_ADDRESS is array (11 downto 0) of std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Array, a_DMA_Current_Transfer_Addr_Array_q : DMA_CURRENT_TRANSFER_ADDRESS;
signal a_Context_Mux_Ctrl : std_logic;
signal a_Read_dQH : std_logic;
signal a_Read_dQH_Fsm : std_logic;
signal a_Read_dQH_q : std_logic;
signal a_Write_dQH : std_logic;
signal a_Write_dQH_Fsm : std_logic;
signal a_Write_dQH_q : std_logic;
signal a_Read_dTD : std_logic;
signal a_Read_dTD_Fsm : std_logic;
signal a_Read_dTD_q : std_logic;
signal write_dTD : std_logic;
signal a_Write_Setup_Bytes, a_Write_Setup_Bytes_q, a_Write_Setup_Bytes_FSM : std_logic;
signal a_dQH_Wr_En_Mux_Stream : std_logic;
signal a_dQH_Wr_En_Mux_Out : std_logic;
signal a_dQH_Wr_En_Mux_Arb : std_logic;
signal a_Start_DMA_S2MM : std_logic;
signal a_Start_DMA_MM2S : std_logic;
signal a_DMA_Source_Dest_Addr : std_logic_vector(31 downto 0);
signal a_DMA_Transfer_Length : std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Fsm : std_logic_vector (31 downto 0);
signal a_DMA_Current_Transfer_Addr_Le : std_logic;
signal a_DMA_Transfer_Complete : STD_LOGIC;
signal a_Aux_Addr_Register : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length_Le : std_logic;
signal a_Axis_MM2S_Mux_Ctrl_Fsm , a_Axis_S2MM_Mux_Ctrl_Fsm : STD_LOGIC;
signal a_Arb_dQH_MULT_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dQH_ZLT_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0); --not used
signal a_Arb_dQH_IOS_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Arb_dQH_Current_dTD_Pointer_Wr_En : STD_LOGIC;
signal a_Arb_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0); --not used
signal a_Arb_dQH_Next_dTD_Pointer_Wr_En : STD_LOGIC; --not used
signal a_Arb_dQH_T_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Arb_dTD_Total_Bytes_Wr_En : STD_LOGIC;
signal a_Arb_dTD_IOC_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0); --not used
signal a_Arb_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0); --not used
signal a_Arb_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page4_wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0); --not used
signal a_Stream_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dQH_Zlt_Wr : STD_LOGIC;
signal a_Stream_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_Stream_dQH_IOS_Wr : STD_LOGIC;
signal a_Stream_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_Next_dTD_Pointer_wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_T_Wr : STD_LOGIC;
signal a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Stream_dTD_IOC_Wr : STD_LOGIC;
signal a_Stream_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_Stream_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_Stream_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Wr : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Wr : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Wr : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Wr : STD_LOGIC;
signal a_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Setup_Buffer_Wr_En : std_logic;
signal a_dTD_Status_Wr_En : STD_LOGIC;
signal a_dQH_MULT_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Rd : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Rd : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Rd : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Rd : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Rd : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Rd : STD_LOGIC;
signal a_dTD_C_Page_Rd : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Rd : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Rd : STD_LOGIC_VECTOR (11 downto 0);
signal a_Out_Transfer_Byte_Count_Le1 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count_Le2 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count : std_logic_vector (12 downto 0);
signal a_Endpointlistaddr_Loc : std_logic_vector(20 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En_Fsm : std_logic;
signal a_ENDPTSETUPSTAT_Wr_Fsm : std_logic_vector(31 downto 0);
signal a_USBSTS_Wr_UI_Fsm : std_logic;
signal a_USBSTS_Wr_En_UI_Fsm : std_logic;
signal a_ENDPTSTAT_Set : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Set_En : std_logic;
signal a_ENDPTSTAT_clear : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Clear_En : std_logic;
signal a_ENDPTSTAT_Wr_Loc : std_logic_vector(31 downto 0);
signal tx_fifo_resetn : std_logic;
signal a_Prime : STD_LOGIC;
signal a_Setup_Received : STD_LOGIC;
signal a_In_Token_Received : STD_LOGIC;
signal a_Endpt_Nr_Int : integer range 0 to 23;
signal a_Endpt_Nr_Fsm : integer range 0 to 23;
signal a_Endpt_Nr_Le : STD_LOGIC;
signal a_Endpt_Nr : std_logic_vector(4 downto 0);
signal a_Endpt_Nr_4b : integer range 0 to 27;
signal a_Endpt_Nr_Prime : integer range 0 to 23;
signal a_Endpt_Nr_Setup : integer range 0 to 23;
signal a_Endpt_Nr_In_Token : integer range 0 to 23;
signal a_Endpt_In_Out : STD_LOGIC;
signal a_Bit_Index : integer range 0 to 27;
signal a_Cnt_Bytes_Sent_Loc : std_logic_vector (12 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of state_ind_arb : signal is "true";
-- attribute keep of state_ind_arb : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute mark_debug of a_Setup_Received : signal is "true";
-- attribute keep of a_Setup_Received : signal is "true";
-- attribute mark_debug of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute keep of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute mark_debug of a_In_Packet_Complete_Rd : signal is "true";
-- attribute keep of a_In_Packet_Complete_Rd : signal is "true";
-- attribute mark_debug of a_In_Token_Received : signal is "true";
-- attribute keep of a_In_Token_Received : signal is "true";
-- attribute mark_debug of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute keep of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute mark_debug of a_Bit_Index : signal is "true";
-- attribute keep of a_Bit_Index : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Prime : signal is "true";
-- attribute keep of a_Endpt_Nr_Prime : signal is "true";
-- attribute mark_debug of a_Endpt_Nr : signal is "true";
-- attribute keep of a_Endpt_Nr : signal is "true";
-- attribute mark_debug of a_Endpt_In_Out : signal is "true";
-- attribute keep of a_Endpt_In_Out : signal is "true";
-- attribute mark_debug of a_In_Token_Received_Rd : signal is "true";
-- attribute keep of a_In_Token_Received_Rd : signal is "true";
-- attribute mark_debug of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute keep of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute mark_debug of a_Prime : signal is "true";
-- attribute keep of a_Prime : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute keep of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set : signal is "true";
-- attribute mark_debug of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute keep of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Int : signal is "true";
-- attribute keep of a_Endpt_Nr_Int : signal is "true";
begin
a_Aux_Addr_Register <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd;
arb_tx_fifo_s_aresetn <= tx_fifo_resetn;
a_Axis_MM2S_Mux_Ctrl <= a_Axis_MM2S_Mux_Ctrl_Fsm;
a_Axis_S2MM_Mux_Ctrl <= a_Axis_S2MM_Mux_Ctrl_Fsm;
a_Endpointlistaddr_Loc <= a_ENDPOINTLISTADDR_Rd(31 downto 11);
-- This module is responsible with implementing the S2MM and MM2S frameworks for the DMA engine
Inst_DMA_Operations: DMA_Operations PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
state_ind_dma => state_ind_dma,
DEBUG_REG_DATA => DEBUG_REG_DATA,
M_AXI_AWADDR => a_M_Axi_Awaddr,
M_AXI_AWPROT => a_M_Axi_Awprot,
M_AXI_AWVALID => a_M_Axi_Awvalid,
M_AXI_AWREADY => a_M_Axi_Awready,
M_AXI_WDATA => a_M_Axi_Wdata,
M_AXI_WSTRB => a_M_Axi_Wstrb,
M_AXI_WVALID => a_M_Axi_Wvalid,
M_AXI_WREADY => a_M_Axi_Wready,
M_AXI_BRESP => a_M_Axi_Bresp,
M_AXI_BVALID => a_M_Axi_Bvalid,
M_AXI_BREADY => a_M_Axi_Bready,
M_AXI_ARADDR => a_M_Axi_Araddr,
M_AXI_ARPROT => a_M_Axi_Arprot,
M_AXI_ARVALID => a_M_Axi_Arvalid,
M_AXI_ARREADY => a_M_Axi_Arready,
M_AXI_RDATA => a_M_Axi_Rdata,
M_AXI_RRESP => a_M_Axi_Rresp,
M_AXI_RVALID => a_M_Axi_Rvalid,
M_AXI_RREADY => a_M_Axi_Rready,
dma_transfer_complete => a_DMA_Transfer_Complete,
start_dma_s2mm => a_Start_DMA_S2MM,
start_dma_mm2s => a_Start_DMA_MM2S,
dma_source_dest_address => a_DMA_Source_Dest_Addr,
dma_transfer_length => a_DMA_Transfer_Length
);
-- This module implements the context memory (Queue Heads, Transfer Descriptors)
Inst_Context: Context PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ENDPT_NR => a_Endpt_Nr_Int,
RD_EN => '0',
WR_EN => a_dQH_Wr_En_Mux_Out,
dQH_CURRENT_dTD_POINTER_wr_EN => a_Arb_dQH_Current_dTD_Pointer_Wr_En,
dQH_NEXT_dTD_POINTER_wr_en => a_Arb_dQH_Next_dTD_Pointer_Wr_En,
dTD_TOTAL_BYTES_WR_EN => a_Arb_dTD_Total_Bytes_Wr_En,
dTD_STATUS_WR_EN => a_dTD_Status_Wr_En,
dQH_SETUP_BUFFER_wr_EN => a_dQH_Setup_Buffer_Wr_En,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd ,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_dQH_Mult_Wr,
dQH_ZLT_wr => a_dQH_ZLT_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_dQH_Next_dTD_Pointer_Wr,
dQH_T_wr => a_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_dTD_C_Page_Wr,
dTD_MULT_wr => a_dTD_Mult_Wr,
dTD_STATUS_wr => a_dTD_Status_Wr,
dTD_PAGE0_wr => a_dTD_Page0_Wr,
dTD_PAGE1_wr => a_dTD_Page1_Wr,
dTD_PAGE2_wr => a_dTD_Page2_Wr,
dTD_PAGE3_wr => a_dTD_Page3_Wr,
dTD_PAGE4_wr => a_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_dTD_Current_Offset_Wr
);
-- This module handles control data transfers (Setup packets, dTD, dQH, Status) through the DMA module
Inst_Context_to_Stream: Context_to_Stream PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ind_statte_axistream => ind_statte_axistream,
dQH_RD => a_Read_dQH,
dQH_WR => a_Write_dQH,
dTD_RD => a_Read_dTD,
dTD_WR => write_dTD,
SETUP_WR => a_Write_Setup_Bytes,
dQH_WR_EN => a_dQH_Wr_En_Mux_Stream,
s_axis_mm2s_tdata => a_S_Axis_MM2S_Tdata,
s_axis_mm2s_tkeep => a_S_Axis_MM2S_Tkeep,
s_axis_mm2s_tvalid => a_S_Axis_MM2S_Tvalid,
s_axis_mm2s_tready => a_S_Axis_MM2S_Tready,
s_axis_mm2s_tlast => a_S_Axis_MM2S_Tlast,
m_axis_s2mm_tdata => a_M_Axis_S2MM_Tdata,
m_axis_s2mm_tkeep => a_M_Axis_S2MM_Tkeep,
m_axis_s2mm_tvalid => a_M_Axis_S2MM_Tvalid,
m_axis_s2mm_tready => a_M_Axis_S2MM_Tready,
m_axis_s2mm_tlast => a_M_Axis_S2MM_Tlast,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_Stream_dQH_Mult_Wr,
dQH_ZLT_wr => a_Stream_dQH_Zlt_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_Stream_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_Stream_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_Stream_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_Stream_dQH_Next_dTD_Pointer_wr,
dQH_T_wr => a_Stream_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_Stream_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_Stream_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_Stream_dTD_C_Page_Wr,
dTD_MULT_wr => a_Stream_dTD_Mult_Wr,
dTD_STATUS_wr => a_Stream_dTD_Status_Wr,
dTD_PAGE0_wr => a_Stream_dTD_Page0_Wr,
dTD_PAGE1_wr => a_Stream_dTD_Page1_Wr,
dTD_PAGE2_wr => a_Stream_dTD_Page2_Wr,
dTD_PAGE3_wr => a_Stream_dTD_Page3_Wr,
dTD_PAGE4_wr => a_Stream_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_Stream_dTD_Current_Offset_Wr
);
--Both DMA Engine and the DMA_Transfer_MAnager can read/write to the context memory. The MUX is implemented below
--DMA_Transfer_MAnager controls this MUX
a_dQH_Mult_Wr <= a_Stream_dQH_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_MULT_Wr ;
a_dQH_ZLT_Wr <= a_Stream_dQH_Zlt_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_ZLT_Wr;
a_dQH_Max_Packet_Length_Wr <= a_Stream_dQH_Max_Packet_Length_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Max_Packet_Length_Wr;
a_dQH_IOS_Wr <= a_Stream_dQH_IOS_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_IOS_Wr;
a_dQH_Current_dTD_Pointer_Wr <= a_Stream_dQH_Current_dTD_Pointer_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Current_dTD_Pointer_Wr;
a_dQH_Next_dTD_Pointer_Wr <= a_Stream_dQH_Next_dTD_Pointer_wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Next_dTD_Pointer_Wr;
a_dQH_T_Wr <= a_Stream_dQH_T_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_T_Wr;
a_dQH_Setup_Buffer_Bytes_3_0_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr;
a_dQH_Setup_Buffer_Bytes_7_4_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr;
a_dTD_Total_Bytes_Wr <= a_Stream_dTD_Total_Bytes_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Total_Bytes_Wr;
a_dTD_IOC_Wr <= a_Stream_dTD_IOC_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_IOC_Wr;
a_dTD_C_Page_Wr <= a_Stream_dTD_C_Page_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_C_Page_Wr;
a_dTD_Mult_Wr <= a_Stream_dTD_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Mult_Wr;
a_dTD_Status_Wr <= a_Stream_dTD_Status_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Status_Wr;
a_dTD_Page0_Wr <= a_Stream_dTD_Page0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page0_Wr;
a_dTD_Page1_Wr <= a_Stream_dTD_Page1_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page1_Wr;
a_dTD_Page2_Wr <= a_Stream_dTD_Page2_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page2_Wr;
a_dTD_Page3_Wr <= a_Stream_dTD_Page3_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page3_Wr;
a_dTD_Page4_Wr <= a_Stream_dTD_Page4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page4_wr;
a_dTD_Current_Offset_Wr <= a_Stream_dTD_Current_Offset_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Current_Offset_Wr;
a_dQH_Wr_En_Mux_Out <= a_dQH_Wr_En_Mux_Stream when (a_Context_Mux_Ctrl = '0') else
a_dQH_Wr_En_Mux_Arb;
--Generate control signals for Context_to_Stream module. Control signals
--must be pulses
IMPULSE_WRITE_DQH: process (Axi_Clk, a_Write_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_dQH <= '0';
a_Write_dQH_q <= '0';
else
a_Write_dQH_q <= a_Write_dQH_Fsm;
a_Write_dQH <= a_Write_dQH_Fsm and (not a_Write_dQH_q);
end if;
end if;
end process;
IMPULSE_WRITE_SETUP: process (Axi_Clk, a_Write_Setup_Bytes_FSM)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_Setup_Bytes <= '0';
a_Write_Setup_Bytes_q <= '0';
else
a_Write_Setup_Bytes_q <= a_Write_Setup_Bytes_FSM;
a_Write_Setup_Bytes <= a_Write_Setup_Bytes_FSM and (not a_Write_Setup_Bytes_q);
end if;
end if;
end process;
IMPULSE_READ_DQH: process (Axi_Clk, a_Read_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dQH <= '0';
a_Read_dQH_q <= '0';
else
a_Read_dQH_q <= a_Read_dQH_Fsm;
a_Read_dQH <= a_Read_dQH_Fsm and (not a_Read_dQH_q);
end if;
end if;
end process;
IMPULSE_READ_DTD_PROC: process (Axi_Clk, a_Read_dTD_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dTD <= '0';
a_Read_dTD_q <= '0';
else
a_Read_dTD_q <= a_Read_dTD_Fsm;
a_Read_dTD <= a_Read_dTD_Fsm and (not a_Read_dTD_q);
end if;
end if;
end process;
--combinational signals generated by the state machine are registered
REGISTER_Q_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSETUPSTAT_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr <= (others => '0');
a_USBSTS_Wr_UI <= '0';
a_USBSTS_Wr_en_UI <= '0';
else
a_ENDPTSETUPSTAT_Wr_En <= a_ENDPTSETUPSTAT_Wr_En_Fsm;
a_ENDPTSETUPSTAT_Wr <= a_ENDPTSETUPSTAT_Wr_Fsm;
a_USBSTS_Wr_UI <= a_USBSTS_Wr_UI_Fsm;
a_USBSTS_Wr_en_UI <= a_USBSTS_Wr_En_UI_Fsm;
end if;
end if;
end process;
a_ENDPTSTAT_Wr <= a_ENDPTSTAT_Wr_Loc;
--generate the ENDPTSTAT register
ENDPTSTAT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSTAT_Wr_Loc <= (others => '0');
elsif (a_ENDPTSTAT_Set_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc or a_ENDPTSTAT_Set;
elsif (a_ENDPTSTAT_Clear_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and a_ENDPTSTAT_clear;
elsif (a_EMDPTFLUSH_Rd /= "00000000000000000000000000000000") then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and (not(a_EMDPTFLUSH_Rd));
end if;
end if;
end process;
a_Cnt_Bytes_Sent_Loc <= a_Cnt_Bytes_Sent;
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on in integer format
ENDPT_NR_INT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Int <= 0;
elsif (a_Endpt_Nr_Le = '1') then
a_Endpt_Nr_Int <= a_Endpt_Nr_Fsm;
end if;
end if;
end process;
a_Endpt_Nr <= std_logic_vector(to_unsigned(a_Endpt_Nr_Int,5));
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on. Lower layers need to be aware of this
ARB_ENDPT_NR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Arb_Endpt_Nr <= (others => '0');
else
a_Arb_Endpt_Nr <= a_Endpt_Nr;
end if;
end if;
end process;
--determin the endpoint type
DET_ENDPTTYPE: process (Axi_Resetn, a_Endpt_Nr)
begin
if (a_Endpt_Nr(0) = '0') then
a_Endpt_In_Out <= '0';
else
a_Endpt_In_Out <= '1';
end if;
end process;
a_Endpt_Nr_4b <= to_integer(unsigned(a_Endpt_Nr(4 downto 1)));
-- Control registers usually have bits [27:16] referring to IN endpoints asnd bits[11:0] referring to OUT endpoint
DET_INDEX: process (Axi_Resetn, a_Endpt_Nr_4b, a_Endpt_In_Out)
begin
if (a_Endpt_In_Out = '0') then
a_Bit_Index <= a_Endpt_Nr_4b;
else
a_Bit_Index <= a_Endpt_Nr_4b + 16;
end if;
end process;
-- Determin the endpoint selected for priming from endptprime register
DET_PRIME_ENDPTNR_PROC: process (Axi_Clk, a_ENDPTPRIME_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
elsif(a_ENDPTPRIME_Rd /= "00000000000000000000000000000000") then
a_Prime <= '1';
for endptprime_index in 0 to 27 loop
if (endptprime_index < 12) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= endptprime_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (endptprime_index >= 16) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= (endptprime_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
end if;
end if;
end process;
--Determin the endpoint number from setup_received register
DET_SETUP_ENDPTNR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
elsif(a_Arb_ENDPTSETUP_RECEIVED_Rd /= "00000000000000000000000000000000") then
a_Setup_Received <= '1';
for setup_index in 0 to 27 loop
if (setup_index < 12) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= setup_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (setup_index >= 16) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= (setup_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
end if;
end if;
end process;
--Determin the endpoint number from token_in_received register
DET_TOKEN_IN_ENDPTNR_PROC: process (Axi_Clk, a_In_Token_Received_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
elsif((a_In_Token_Received_Rd and a_ENDPTSTAT_Wr_Loc) /= "00000000000000000000000000000000") then
a_In_Token_Received <= '1';
for token_in_index in 0 to 27 loop
if (token_in_index < 12) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= token_in_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (token_in_index >= 16) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= (token_in_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
end if;
end if;
end process;
OUT_TRANSFER_BYTE_COUNT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Out_Transfer_Byte_Count <= (others => '0');
elsif (a_Out_Transfer_Byte_Count_Le1 = '1') then
a_Out_Transfer_Byte_Count <= RX_COMMAND_FIFO_DOUT(23 downto 11);
elsif (a_Out_Transfer_Byte_Count_Le2 = '1') then
a_Out_Transfer_Byte_Count <= std_logic_vector( to_unsigned((to_integer(unsigned(RX_COMMAND_FIFO_DOUT(23 downto 11))) - to_integer(unsigned(a_dTD_Total_Bytes_Rd))),13) );
end if;
end if;
end process;
DMA_TRANSFER_ADDR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_Current_Transfer_Addr_Array <= (others =>(others => '0'));
a_DMA_Current_Transfer_Addr_Array_q <= (others =>(others => '0'));
elsif (a_DMA_Current_Transfer_Addr_Le = '1') then
a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Fsm;
a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------
DECIDE_LENGTH_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_In_Transfer_Length <= (others => '0');
else
if (a_DMA_In_Transfer_Length_Le = '1') then
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
a_DMA_In_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
else
a_DMA_In_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
end if;
end if;
end if;
end if;
end process;
--DMA_Transfer_Manager State Machine
SYNC_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, a_dQH_Next_dTD_Pointer_Rd, a_Arb_ENDPTSETUP_RECEIVED_Ack, a_Cnt_Bytes_Sent_oValid, a_Send_Zero_Length_Packet_Ack_Rd, a_DMA_Current_Transfer_Addr_Array, a_Prime, RX_COMMAND_FIFO_VALID, a_dTD_Page0_Rd, a_dTD_Current_Offset_Rd,a_Endpt_Nr_4b, a_Endpt_Nr_Int, a_Aux_Addr_Register, a_In_Packet_Complete_Rd, a_Endpt_Nr_In_Token, RX_COMMAND_FIFO_EMPTY, a_Endpt_Nr_Setup, a_USBMODE_Rd, a_Bit_Index, RX_COMMAND_FIFO_DOUT, a_Out_Transfer_Byte_Count, a_Cnt_Bytes_Sent_Loc, a_dTD_Total_Bytes_Rd, a_dQH_Current_dTD_Pointer_Rd, a_dQH_T_Rd, a_Endpt_Nr_Prime, a_In_Token_Received, a_Endpt_In_Out, a_Setup_Received, a_DMA_Transfer_Complete, a_Endpointlistaddr_Loc)
begin
--declare default state for next_state to avoid latches
next_state <= state;
state_ind_arb <= "000000";
a_Context_Mux_Ctrl <= '0';
a_dQH_Wr_En_Mux_Arb <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '0';
a_Arb_dTD_Total_Bytes_Wr_En <= '0';
a_Arb_dQH_Next_dTD_Pointer_Wr_En <= '0';
a_dQH_Setup_Buffer_Wr_En <= '0';
a_dTD_Status_Wr_En <= '0';
a_Read_dQH_Fsm <= '0';
a_Write_dQH_Fsm <= '0';
a_Read_dTD_Fsm <= '0';
write_dTD <= '0';
a_Write_Setup_Bytes_FSM <= '0';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO as a DEFAULT; FIFO connected to DMA only when data ready
a_Axis_S2MM_Mux_Ctrl_Fsm <= '1';
a_Start_DMA_S2MM <= '0';
a_Start_DMA_MM2S <= '0';
a_DMA_Source_Dest_Addr <= (others => '0');
a_DMA_Transfer_Length <= (others => '0');
tx_fifo_resetn <= '1';
a_Endpt_Nr_Fsm <= 0;
a_Endpt_Nr_Le <= '0';
RX_COMMAND_FIFO_RD_EN <= '0';
a_Out_Transfer_Byte_Count_Le1 <= '0';
a_Out_Transfer_Byte_Count_Le2 <= '0';
a_DMA_Current_Transfer_Addr_Fsm <= (others => '0');
a_DMA_Current_Transfer_Addr_Le <= '0';
-- pe_setup_received_rst <= '1';
a_Arb_dQH_MULT_Wr <= (others => '0');
a_Arb_dQH_ZLT_Wr <= '0';
a_Arb_dQH_Max_Packet_Length_Wr <= (others => '0');
a_Arb_dQH_IOS_Wr <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_Next_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_T_Wr <= '0';
a_Arb_dTD_Total_Bytes_Wr <= (others => '0');
a_Arb_dTD_IOC_Wr <= '0';
a_Arb_dTD_C_Page_Wr <= (others => '0');
a_Arb_dTD_Mult_Wr <= (others => '0');
a_Arb_dTD_Status_Wr <= (others => '0');
a_Arb_dTD_Page0_Wr <= (others => '0');
a_Arb_dTD_Page1_Wr <= (others => '0');
a_Arb_dTD_Page2_Wr <= (others => '0');
a_Arb_dTD_Page3_Wr <= (others => '0');
a_Arb_dTD_Page4_wr <= (others => '0');
a_Arb_dTD_Current_Offset_Wr <= (others => '0');
a_USBSTS_Wr_UI_Fsm <= '0';
a_USBSTS_Wr_En_UI_Fsm <= '0';
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '0';
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '0';
a_ENDPTPRIME_Clear <= (others => '1');
a_ENDPTPRIME_Clear_En <= '0';
a_ENDPTPRIME_Set <= (others => '0');
a_ENDPTPRIME_Set_En <= '0';
a_ENDPTCOMPLETE_Wr <= (others => '0');
a_ENDPTCOMPLETE_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm <= (others => '0');
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear <= (others => '1');
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '0';
a_ENDPTSTAT_Set <= (others => '0');
a_ENDPTSTAT_Set_En <= '0';
a_ENDPTSTAT_clear <= (others => '1');
a_ENDPTSTAT_Clear_En <= '0';
a_EMDPTFLUSH_Set <= (others => '0');
a_EMDPTFLUSH_Set_En <= '0';
a_In_Packet_Complete_Clear_En <= '0';
a_In_Packet_Complete_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Set <= (others => '0');
a_Send_Zero_Length_Packet_Set_En <= '0';
a_Send_Zero_Length_Packet_Ack_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Ack_Clear_En <= '0';
a_In_Token_Received_Clear <= (others => '1');
a_In_Token_Received_Clear_En <= '0';
a_Resend_Clear_En <= '0';
a_Resend_Clear <= (others => '1');
a_DMA_In_Transfer_Length_Le <= '0';
case state is -- state machine triggered by 2 conditions: priming of an endpoint or setup packet arrival; setup packets processed separately; OUT framework not tested
when IDLE =>
state_ind_arb <= "000000";
if (a_Prime = '1') then
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Prime;
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Le <= '1';
next_state <= PRIME_MM2S_DQH;
elsif (a_Setup_Received = '1') then
a_Context_Mux_Ctrl <= '1';
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Setup;
a_Endpt_Nr_Le <= '1';
next_state <= SETUP_LOCKOUT_TRIPWIRE;
elsif (a_In_Token_Received = '1') then
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Fsm <= a_Endpt_Nr_In_Token;
a_Endpt_Nr_Le <= '1';
next_state <= START_IN_FRAMEWORK;
elsif (RX_COMMAND_FIFO_EMPTY /= '1' and RX_COMMAND_FIFO_VALID = '1') then
RX_COMMAND_FIFO_RD_EN <= '1';
next_state <= START_OUT_FRAMEWORK;
end if;
------------------SETUP PACKET PROCESSING--------------------------
when SETUP_LOCKOUT_TRIPWIRE =>
state_ind_arb <= "000001";
a_Context_Mux_Ctrl <= '1';
if (a_USBMODE_Rd(SLOM) = '0') then
next_state <= IDLE;
else
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_In_Token_Received_Clear(a_Bit_Index + 16) <= '0';
a_In_Token_Received_Clear_En <= '1';
a_EMDPTFLUSH_Set(a_Bit_Index + 16) <= '1';
a_EMDPTFLUSH_Set_En <= '1';
next_state <= SETUP_UPDATE_SETUP_BYTES;
end if;
when SETUP_UPDATE_SETUP_BYTES =>
state_ind_arb <= "000010";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_dQH_Setup_Buffer_Wr_En <= '1';
next_state <= SETUP_WAIT1;
when SETUP_WAIT1 => --wait for dqh to be updated in context memory
state_ind_arb <= "000011";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
next_state <= SETUP_S2MM;
when SETUP_S2MM =>
state_ind_arb <= "000100";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_Setup_Bytes_FSM <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned(((a_Endpt_Nr_Int*64)+40),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(8,32)); --dQH = 2*4 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_Setup_Bytes_FSM <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm(a_Bit_Index) <= '1';
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= SETUP_UPDATE_ENDPTSETUP_RECEIVED;
end if;
when SETUP_UPDATE_ENDPTSETUP_RECEIVED =>
state_ind_arb <= "000101";
a_Arb_ENDPTSETUP_RECEIVED_Clear(a_Bit_Index) <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '1';
if (a_Arb_ENDPTSETUP_RECEIVED_Ack = '1') then
next_state <= SETUP_WAIT2;
end if;
when SETUP_WAIT2 =>
next_state <= IDLE;
------------------------------ PRIME FRAMEWORK -----------------------------------------
when PRIME_MM2S_DQH => --read DQH from main memory
state_ind_arb <= "000110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dQH_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= PRIME_WAIT0;
end if;
when PRIME_WAIT0 =>
state_ind_arb <= "000000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
next_state <= PRIME_MM2S_DTD;
when PRIME_MM2S_DTD => --read DQH from main memory
state_ind_arb <= "100110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dTD = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_DMA_Current_Transfer_Addr_Fsm <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd; --initialize the transfer address with PAGE0
a_DMA_Current_Transfer_Addr_Le <= '1';
if (a_Endpt_In_Out = '1') then --IN endpoint, FIFO needs to be prepared with transmit data
tx_fifo_resetn <= '0'; -- flush fifo;
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
next_state <= PRIME_FILL_FIFO;
else --OUT endpoint
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
next_state <= PRIME_WAIT1;
end if;
end if;
when PRIME_FILL_FIFO => --extract necessary data to fill TX fifo
state_ind_arb <= "000111";
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Send_Zero_Length_Packet_Set(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Set_En <= '1';
next_state <= PRIME_WAIT1;
else
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
next_state <= PRIME_FILL_FIFO_1;
else
next_state <= PRIME_FILL_FIFO_2;
end if;
end if;
when PRIME_FILL_FIFO_1 =>
state_ind_arb <= "001000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_dTD_Total_Bytes_Rd)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_FILL_FIFO_2 =>
state_ind_arb <= "001001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + (C_FIFO_SIZE));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + (C_FIFO_SIZE)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_WAIT1 =>
state_ind_arb <= "001010";
next_state <= PRIME_WAIT2;
when PRIME_WAIT2 =>
state_ind_arb <= "001011";
next_state <= IDLE;
---------OUT_TOKEN_FRAMEWORK (RX_PACKET)---------------------------------------------------------------------------
when START_OUT_FRAMEWORK =>
state_ind_arb <= "001100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Out_Transfer_Byte_Count_Le1 <= '1';
a_Endpt_Nr_Fsm <= to_integer(unsigned(RX_COMMAND_FIFO_DOUT(10 downto 7)));
a_Endpt_Nr_Le <= '1';
next_state <= OUT_START_TRANSFER;
when OUT_START_TRANSFER =>
state_ind_arb <= "001101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
if (a_Out_Transfer_Byte_Count <= a_dTD_Total_Bytes_Rd)then
next_state <= OUT_TRANSFER_S2MM;
else
next_state <= IDLE; --ERROR
end if;
when OUT_TRANSFER_S2MM =>
state_ind_arb <= "001110";
a_Axis_S2MM_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= "0000000000000000000" & a_Out_Transfer_Byte_Count; --transfer the received packet in main memory
a_Start_DMA_S2MM <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Out_Transfer_Byte_Count)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b)) + unsigned(a_Out_Transfer_Byte_Count)); --update the memory address for the s2mm transfer
a_DMA_Current_Transfer_Addr_Le <= '1';
next_state <= OUT_WAIT1;
end if;
when OUT_WAIT1 =>
state_ind_arb <= "001111";
next_state <= OUT_CHECK_COMPLETE;
when OUT_CHECK_COMPLETE =>
state_ind_arb <= "010000";
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= OUT_TRANSFER_COMPLETE;
else
next_state <= IDLE;
end if;
when OUT_TRANSFER_COMPLETE =>
state_ind_arb <= "010001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_dQH_Fsm <= '0';
if (a_dQH_T_Rd = '0') then
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= OUT_FETCH_NEXT_DTD;
else
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
next_state <= IDLE;
end if;
end if;
when OUT_FETCH_NEXT_DTD =>
state_ind_arb <= "010010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= OUT_WAIT2;
end if;
when OUT_WAIT2 =>
state_ind_arb <= "010011";
next_state <= IDLE;
---------IN_TOKEN_FRAMEWORK (TX_PACKET)---------------------------------------------------------------------------
when START_IN_FRAMEWORK =>
state_ind_arb <= "010100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; --context memory connected to DMA stream port, not FIFO if 0 fifo will assert tvalid for 1 ck cycle
a_Context_Mux_Ctrl <= '0';
a_In_Token_Received_Clear(a_Bit_Index) <= '0';
a_In_Token_Received_Clear_En <= '1';
if (a_In_Packet_Complete_Rd(a_Bit_Index) = '1') then
a_In_Packet_Complete_Clear(a_Bit_Index) <= '0';
a_In_Packet_Complete_Clear_En <= '1';
next_state <= IN_HANDSHAKE;
elsif (a_Resend(a_Bit_Index) = '1') then
tx_fifo_resetn <= '0'; -- flush fifo;
next_state <= IN_HANDSHAKE;
end if;
when IN_HANDSHAKE =>
state_ind_arb <= "010101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1';
if (a_Cnt_Bytes_Sent_oValid = '1') then
if (a_Resend(a_Bit_Index) = '0') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Cnt_Bytes_Sent_Loc)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
end if;
next_state <= IN_WAIT0;
end if;
when IN_WAIT0 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
if (a_Resend(a_Bit_Index) = '0') then
next_state <= IN_CHECK_COMPLETE;
else
a_Resend_Clear(a_Bit_Index) <= '0';
a_Resend_Clear_En <= '1';
next_state <= IN_RELOAD_BUFFER;
end if;
when IN_CHECK_COMPLETE =>
state_ind_arb <= "011000";
a_DMA_In_Transfer_Length_Le <= '1';
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_dTD_Status_Wr_En <= '1'; --write 0 to active bit
next_state <= IN_TRANSACTION_COMPLETE;
else
next_state <= IN_TRANSFER_MM2S;
end if;
when IN_TRANSFER_MM2S =>
state_ind_arb <= "010110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + unsigned(a_Cnt_Bytes_Sent_Loc));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_Cnt_Bytes_Sent_Loc)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
end if;
when IN_RELOAD_BUFFER =>
state_ind_arb <= "111011";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
end if;
when IN_WAIT1 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
next_state <= IDLE;
when IN_TRANSACTION_COMPLETE => --copy dQH back to main memory with status updated
state_ind_arb <= "011001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1' or a_Send_Zero_Length_Packet_Ack_Rd(a_Bit_Index) = '1') then
a_Write_dQH_Fsm <= '0';
a_Send_Zero_Length_Packet_Ack_Clear(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Ack_Clear_En <= '1';
if (a_dQH_T_Rd = '1') then
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
a_ENDPTSTAT_clear(a_Bit_Index) <= '0';
a_ENDPTSTAT_Clear_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= IDLE;
else
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= IN_FETCH_NEXT_DTD;
end if;
end if;
when IN_FETCH_NEXT_DTD =>
state_ind_arb <= "011010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= IN_WAIT2;
end if;
when IN_WAIT2 =>
state_ind_arb <= "011011";
next_state <= IDLE;
when others =>
state_ind_arb <= "011100";
next_state <= IDLE;
end case;
end process;
end implementation;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Wed Oct 18 15:15:21 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_processing_system7_0_0_stub.vhdl
-- Design : ip_design_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.3";
begin
end;
|
library verilog;
use verilog.vl_types.all;
entity Etapa2_vlg_sample_tst is
port(
SW : in vl_logic_vector(2 downto 1);
sampler_tx : out vl_logic
);
end Etapa2_vlg_sample_tst;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_in_8b_sync_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_in_8b_sync_0 is
port (
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave_0.byteenable
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
rd_en : in std_logic := '0'; -- .read
wait_req : out std_logic; -- .waitrequest
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- .address
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
st_valid : in std_logic := '0'; -- .valid
st_ready : out std_logic; -- .ready
irq : out std_logic -- conduit_end.export
);
end entity fifo_in_8b_sync_0;
architecture rtl of fifo_in_8b_sync_0 is
component fifo_in_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
rd_en : in std_logic := 'X'; -- read
wait_req : out std_logic; -- waitrequest
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
st_valid : in std_logic := 'X'; -- valid
st_ready : out std_logic; -- ready
irq : out std_logic -- export
);
end component fifo_in_8b_sync;
begin
fifo_in_8b_sync_0 : component fifo_in_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
byte_en => byte_en, -- avalon_slave_0.byteenable
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
rd_en => rd_en, -- .read
wait_req => wait_req, -- .waitrequest
addr => addr, -- .address
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_sink.data
st_valid => st_valid, -- .valid
st_ready => st_ready, -- .ready
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_in_8b_sync_0
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.filter_shared_package.all;
entity filter_coeff_controller is
generic
(
MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation
RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled.
MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled.
CHANNELS : natural := C
);
port
(
cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0);
cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0);
valid : in std_logic;
coeff_rdaddr : out COEFF_ADD_T;
coeff_rden : out std_logic
);
end filter_coeff_controller;
architecture behaviour of filter_coeff_controller is
begin
-- read interface
coeff_rdaddr <= std_logic_vector(resize(unsigned(cnt_mac) * to_unsigned(CHANNELS,cnt_ch'length), coeff_rdaddr'length) + unsigned(cnt_ch));
coeff_rden <= valid;
end behaviour;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_1 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_1 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(63 downto 0);
variable rTemp2 : SIGNED(31 downto 0);
variable rTemp3 : SIGNED(31 downto 0);
begin
rTemp1 := (signed(INPUT_1) * signed(INPUT_2));
OUTPUT_1 <= std_logic_vector(rTemp1(42 downto 11));
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
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