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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_B_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_B_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_B_prod;
ARCHITECTURE xilinx OF RAM_B_prod IS
COMPONENT RAM_B_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_B_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
---------------------------------------------------------
-- JAM CPU
-- Integer Unit
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--This integer unit uses a basic ALU with shift
--and adds a multicycle multiplier.
--The multiplier uses Booth's algorithm.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
entity IU is
port(
a_in, b_in : in std_logic_vector(31 downto 0); -- IU input
do_mult : in std_logic; -- Do multicycle mult?
mult_op : in std_logic; -- Return [0=LSW] or [1=MSW) of mult result
alu_op : in std_logic_vector(2 downto 0); -- ALU op
inv_in2 : in std_logic; -- Invert operator in2 in ALU
clk : in std_logic; -- Global clock
reset : in std_logic; -- Global reset
ovf : out std_logic; -- Overflow
result : out std_logic_vector(31 downto 0); -- IU result
mc : out std_logic); -- Goes high during the last cycle of multicycle ops
end;
architecture rev1 of IU is
component ALU
port(
op : in std_logic_vector(2 downto 0); -- ALU operation
inv_in2 : in std_logic; -- Invert operator in2
in1, in2 : in std_logic_vector(31 downto 0); -- ALU input
ovf : out std_logic; -- ALU overflow
alu_out : out std_logic_vector(31 downto 0)); -- ALU result
end component;
for alu_unit : ALU use entity work.ALU(rev2);
signal a, b, alu_data : std_logic_vector(31 downto 0);
signal b_reg : std_logic_vector(31 downto 0);
signal op : std_logic_vector(2 downto 0);
signal running : std_logic;
signal finished : std_logic;
signal from_latch : std_logic_vector(64 downto 0);
begin
alu_unit : ALU port map(op, inv_in2, a, b, ovf, alu_data);
result <=
alu_data when do_mult = '0' else
from_latch(32 downto 1) when mult_op = '0' else
from_latch(64 downto 33);
a <=
a_in when do_mult = '0' else
from_latch(64 downto 33);
b <=
b_in when do_mult = '0' else
b_reg;
op <=
alu_op when do_mult = '0' else
"001" when from_latch(1 downto 0) = "01" else
"010" when from_latch(1 downto 0) = "10" else
"000";
--65bit register + 32 bit buffer for b_in
process(clk)
constant zero32: std_logic_vector(31 downto 0) := (others => '0');
begin
if clk'event and clk='1' then
if do_mult = '1' and running = '0' then
from_latch <= zero32 & a_in & '0';
b_reg <= b_in;
elsif do_mult ='1' then
from_latch <= alu_data(31) & alu_data & from_latch(32 downto 1);
end if;
end if;
end process;
process(clk)
variable loop_nr: std_logic_vector(5 downto 0);
begin
if clk'event and clk='1' then
if reset='1' then
running <= '0';
finished <= '0';
mc <= '0';
else
if do_mult = '1' then
--multicycle mult
if running = '0' then
--setup
running <= '1';
loop_nr := (others => '0');
end if;
if loop_nr(5) = '1' then --last cycle?
finished <= '1';
loop_nr := (others => '0');
mc <= '1';
else
mc <= '0';
loop_nr := loop_nr + '1';
end if;
if finished = '1' then
finished <= '0';
running <= '0';
end if;
else
mc <= '0';
running <= '0';
end if;
end if;
end if;
end process;
end;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:39:16 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_stub.vhdl
-- Design : zynq_design_1_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zynq_design_1_auto_pc_0 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end zynq_design_1_auto_pc_0;
architecture stub of zynq_design_1_auto_pc_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
begin
end;
|
architecture RTL of FIFO is
attribute coordinate of others : COMPONENT is (0.0, 17.5);
attribute coordinate of others : COMPONENT is (0.0, 17.5);
begin
end architecture RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0' after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(pad) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3)
or (tech = spartan3e) or (tech = virtex4) or (tech = virtex5)
generate
x0 : virtex_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0' after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(pad) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3)
or (tech = spartan3e) or (tech = virtex4) or (tech = virtex5)
generate
x0 : virtex_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
|
--
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity driver_sharp is
port (
clk : in std_logic; -- Clock input
rst : in std_logic; -- Reset input
-- Signals to drive the screen
vsync : out std_logic;
hsync : out std_logic;
enable : out std_logic;
-- Signals to communicate with block giving color
x_out : out std_logic_vector ( 9 downto 0);
y_out : out std_logic_vector ( 8 downto 0)
);
end driver_sharp;
architecture v1_0 of driver_sharp is
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 800; -- Horizontal sync signal cycle width in clock cycle
constant THp : positive := 96; -- Horizontal sync signal pulse width in clock cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
constant TV : positive := 525; -- Vertical sync signal period in clock cycle
begin -- behavorial
process(clk,rst)
variable x_counter : positive range 1 to TH := 1; -- counter for x axis
variable y_counter : positive range 1 to TV := 1; -- counter for y axis
variable x : natural range 0 to THd := 0; -- x coordinate of active pixel
variable y : natural range 0 to TVd := 0; -- x coordinate of active pixel
begin
if rst = '1' then
x_counter := 1;
y_counter := 1;
vsync <= '0';
hsync <= '0';
enable <= '0';
x_out <= (others => '0');
y_out <= (others => '0');
x := 0;
y := 0;
elsif rising_edge(clk) then
if y_counter < 2 then
vsync <= '0';
else
vsync <= '1';
end if;
if x_counter < TH then
x_counter := x_counter + 1;
else
x_counter := 1;
if y_counter < TV then
y_counter := y_counter + 1;
else
y_counter := 1;
y := 0;
y_out <= (others => '0');
end if;
if y_counter > TVs and y < TVd then
y_out <= std_logic_vector(to_unsigned(y,9));
y := y +1;
end if;
end if;
if x_counter <= THp then
hsync <= '0';
x := 0;
x_out <= (others => '0');
else
hsync <= '1';
if x < THd and y_counter > TVs and y_counter <= TVd + TVs then
x_out <= std_logic_vector(to_unsigned(x,10));
x := x + 1;
enable <= '1';
else
enable <= '0';
x_out <= (others => '0');
end if;
end if;
end if;
end process;
end v1_0;
architecture v1_1 of driver_sharp is
-- Constants defined by specification
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 799; -- Horizontal sync signal cycle width in clock cycle
constant TV : positive := 524; -- Vertical sync signal period in clock cycle
constant THp : positive := 95; -- Horizontal sync signal pulse width in clock cyle
constant TVp : positive := 1; -- Vertical sync signal pulse width in hsync cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
-- Internal signals
signal x_counter : std_logic_vector( 9 downto 0) := (others => '0'); -- counter for x axis
signal y_counter : std_logic_vector( 9 downto 0) := (others => '0'); -- counter for x axis
signal x : std_logic_vector( 9 downto 0) := (others => '0');
signal y : std_logic_vector( 8 downto 0) := (others => '0');
-- FSM for hsync
type hsync_state_type is (low,high);
signal hsync_state : hsync_state_type := low;
signal hsync_next_state : hsync_state_type := low ;
-- FSM for vsync
type vsync_state_type is (low,high,ready_to_low);
signal vsync_state : vsync_state_type := low;
signal vsync_next_state : vsync_state_type := low ;
signal ycounter_next : std_logic_vector (9 downto 0):= (others => '0');
-- FSM for enable
type line_state_type is (virtual,real); -- State indicating if we are in non real lines or real lines
signal line_state : line_state_type := virtual; -- State of line
signal line_next_state : line_state_type := virtual; -- State of line
type enable_state_type is (active,inactive,done);
signal enable_state : enable_state_type := inactive;
signal enable_next_state : enable_state_type := inactive;
-- FSM for y
type y_state_type is (active,inactive,done,ready,ready_to_reset);
signal y_state : y_state_type := inactive;
signal y_next_state : y_state_type := inactive;
begin -- behavorial
x_counter_process: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' or unsigned(x_counter) = TH then
x_counter <= (others => '0');
else
x_counter <= std_logic_vector(unsigned(x_counter) + 1);
end if;
end if;
end process;
-- ycounter state register process
ycounter_state_register_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
y_counter <= (others => '0');
elsif unsigned(x_counter) = TH then
y_counter <= ycounter_next;
else
y_counter <= y_counter;
end if;
end if;
end process;
--ycounter state transition
y_counter_state_transition_process : process(y_counter)
begin
if unsigned(y_counter) = TV then
ycounter_next <= (others => '0');
else
ycounter_next <= std_logic_vector(unsigned(y_counter) + 1);
end if;
end process;
--hsync state register
hsync_state_register_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
hsync_state <= low;
else
hsync_state <= hsync_next_state;
end if;
end if;
end process;
--hsync state transition
hsync_state_transition_process : process(hsync_state,x_counter)
begin
case hsync_state is
when low => if unsigned(x_counter) = THp then
hsync_next_state <= high;
else
hsync_next_state <= low ;
end if;
when high => if unsigned(x_counter) = TH then
hsync_next_state <= low;
else
hsync_next_state <= high;
end if;
when others => hsync_next_state <= low ;
end case;
end process;
--hsync output function
hsync <= '1' when hsync_state = high else '0';
--vsync state register
vsync_state_register_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
vsync_state <= low;
else
vsync_state <= vsync_next_state;
end if;
end if;
end process;
--vsync state transition
vsync_state_transition_process : process(vsync_state,y_counter,x_counter)
begin
case vsync_state is
when low => if unsigned(y_counter) = TVp then
vsync_next_state <= high;
else
vsync_next_state <= low ;
end if;
when high => if unsigned(y_counter) = TV then
vsync_next_state <= ready_to_low;
else
vsync_next_state <= high;
end if;
when ready_to_low => if unsigned(x_counter) = TH then
vsync_next_state <= low;
else
vsync_next_state <= ready_to_low;
end if;
when others => vsync_next_state <= low ;
end case;
end process;
--vsync output function
vsync <= '0' when vsync_state = low else '1';
-- Process managing line state
line_state_register_process: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
line_state <= virtual;
else
line_state <= line_next_state;
end if;
end if;
end process;
--line_state transition
line_state_transition_process : process(line_state,y_counter)
begin
case line_state is
when virtual => if unsigned(y_counter) = TVs then
line_next_state <= real;
else
line_next_state <= virtual ;
end if;
when real => if unsigned(y_counter) = (TVd + TVs) then
line_next_state <= virtual;
else
line_next_state <= real;
end if;
when others => line_next_state <= virtual;
end case;
end process;
-- enable process management
enable_state_register_process: process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
enable_state <= inactive;
else
enable_state <= enable_next_state;
end if;
end if;
end process;
--enable_state transition
enable_state_transition_process : process(enable_state,hsync_next_state,x,line_state)
begin
case enable_state is
when inactive => if hsync_next_state = high and line_state = real then
enable_next_state <= active;
else
enable_next_state <= inactive ;
end if;
when active => if unsigned(x) = (THd -1) then
enable_next_state <= done;
else
enable_next_state <= active;
end if;
when done => if hsync_next_state = low then
enable_next_state <= inactive;
else
enable_next_state <= done;
end if;
when others => enable_next_state <= inactive;
end case;
end process;
enable <= '1' when enable_state = active else '0';
x_out_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' or unsigned(x) = (THd -1) then
x <= (others => '0');
elsif enable_state = active then
x <= std_logic_vector(unsigned(x) + 1);
else
x <= x;
end if;
end if;
end process;
y_out_process : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
y_state <= inactive;
else
y_state <= y_next_state;
end if;
end if;
end process;
--y state transition
process(y_state,y_counter,hsync_state,hsync_next_state,vsync_state)
begin
case y_state is
when inactive => if unsigned(y_counter) = TVs then
y_next_state <= ready;
else
y_next_state <= inactive ;
end if;
when active => if hsync_state = low then
y_next_state <= done;
y <= std_logic_vector(unsigned(y) + 1);
else
y <= y;
y_next_state <= active;
end if;
when done => if unsigned(y) = (TVd - 1) then
y_next_state <= ready_to_reset;
else
y_next_state <= ready;
y <= y;
end if;
when ready_to_reset => if vsync_state = low then
y_next_state <= inactive;
y <= (others => '0');
else
y_next_state <= ready_to_reset;
y <= y;
end if;
when ready => if hsync_next_state = high then
y_next_state <= active;
else
y_next_state <= ready;
end if;
when others => y_next_state <= inactive ;
end case;
end process;
x_out <= x;
y_out <= y;
end v1_1;
architecture v1_2 of driver_sharp is
-- Constants defined by specification
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 799; -- Horizontal sync signal cycle width in clock cycle
constant TV : positive := 524; -- Vertical sync signal period in clock cycle
constant THp : positive := 95; -- Horizontal sync signal pulse width in clock cyle
constant TVp : positive := 1; -- Vertical sync signal pulse width in hsync cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
-- Constants for internal use
constant x_counter_low : positive := 1024 - THp ;
constant x_counter_low_start : positive := x_counter_low + 1;
constant x_counter_high : positive := 1024 - (TH - THp) + 1;
constant y_counter_low : positive := 1024 - TVp;
constant y_counter_high : positive := 1024 - (TV - TVp) + 1;
-- Internal signals
signal x_counter: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(x_counter_low_start,11)); -- counter for x axis
signal x_counter_init: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(x_counter_high,11)); -- counter for x axis
signal hsyncP : std_logic := '0';
signal hsyncN : std_logic := '1';
signal y_counterP: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(y_counter_low,11)); -- counter for x axis
signal y_counter_init: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(y_counter_high,11)); -- counter for x axis
-- FSM for vsync
type vsync_state_type is (low,after_low,high,ready_to_low,before_low);
signal vsyncP : vsync_state_type := low;
signal vsyncN : vsync_state_type := low ;
-- counter to determine if line is active or not
constant line_counter_low_start : positive := 512 - TVs;
constant line_counter_low : positive := 512 - (TV - TVd);
constant line_counter_high : positive := 512 - TVd + 1;
signal line_counter : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(line_counter_low_start,10));
signal line_counter_init : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(line_counter_low_start,10));
type line_state_type is(virtual,first_real,real,after_real);
signal line_stateP : line_state_type := virtual;
signal line_stateN : line_state_type := virtual;
begin -- behavorial
-- Process managing outputs
output_management : process(clk,rst)
begin
if rst = '1' then
-- vsync <= '0';
hsync <= '0';
enable <= '0';
x_out <= (others => '0');
y_out <= (others => '0');
elsif rising_edge(clk) then
-- vsync <= vsyncP;
hsync <= hsyncP;
-- enable <= enableP;
-- x_out <= x_outP;
-- y_out <= x_outP;
end if;
end process;
-- process managing xcounter increment
xcounter_increment : process(clk,rst)
begin
if rst = '1' then
x_counter <= std_logic_vector(to_unsigned(x_counter_low_start,11));
hsyncP <= '0';
elsif rising_edge(clk) then
if x_counter(10) = '1' then
x_counter <= x_counter_init;
hsyncP <= hsyncN;
else
x_counter <= std_logic_vector(unsigned(x_counter)+1);
end if;
end if;
end process;
-- process preparing next hsync_value
prepare_next_hsync : process(hsyncP)
begin
case hsyncP is
when '0' => hsyncN <= '1';
when '1' => hsyncN <= '0';
when others => hsyncN <= '0';
end case;
end process;
-- process computing next x_counter_init
prepare_next_counter_init : process (hsyncP)
begin
case hsyncP is
when '0' => x_counter_init <= std_logic_vector(to_unsigned(x_counter_high,11));
when '1' => x_counter_init <= std_logic_vector(to_unsigned(x_counter_low,11));
when others => x_counter_init <= std_logic_vector(to_unsigned(x_counter_high,11));
end case;
end process;
-- process managing ycounter increment
ycounter_increment : process(clk,rst)
begin
if rst = '1' then
y_counterP <= std_logic_vector(to_unsigned(y_counter_low,11));
elsif rising_edge(clk) then
if x_counter(10) = '1' and hsyncP = '1' then
if y_counterP(10) = '1' then
y_counterP <= y_counter_init;
else
y_counterP <= std_logic_vector(unsigned(y_counterP) + 1);
end if;
else
y_counterP <= y_counterP;
end if;
end if;
end process;
-- prepare the init value for ycounter
prepare_ycounter_init : process(vsyncP)
begin
case vsyncP is
when low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_high,11));
when after_low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_high,11));
when high => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,11));
when ready_to_low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,11));
when others => y_counter_init <= std_logic_vector(to_unsigned(y_counter_high,11));
end case;
end process;
--vsync state register
vsync_state_register_process : process(clk,rst)
begin
if rst = '1' then
vsyncP <= low;
elsif rising_edge(clk) then
vsyncP <= vsyncN;
end if;
end process;
--vsync state transition
vsync_state_transition_process : process(vsyncP,hsyncP,y_counterP,x_counter)
begin
case vsyncP is
when low => if y_counterP(10) = '1' then
vsyncN <= after_low;
else
vsyncN <= low ;
end if;
when after_low => if y_counterP(10) = '1' then
vsyncN <= after_low;
else
vsyncN <= high ;
end if;
when high => if y_counterP(10) = '1' and vsyncP = high then
vsyncN <= ready_to_low;
else
vsyncN <= high;
end if;
when ready_to_low => if x_counter(10) = '1' and hsyncP = '1' then
vsyncN <= before_low;
else
vsyncN <= ready_to_low;
end if;
when before_low => vsyncN <= low;
when others => vsyncN <= low ;
end case;
end process;
--vsync output function
apply_vsync : vsync <= '0' when vsyncP = low else '1';
-- Process managing line state
line_state_register: process(clk,rst)
begin
if rst = '1' then
line_stateP <= virtual;
elsif rising_edge(clk) then
line_stateP <= line_stateN;
end if;
end process;
--line_state transition
line_state_transition : process(line_stateP,line_counter(9))
begin
case line_stateP is
when virtual => if line_counter(9) = '1' then
line_stateN <= first_real ;
else
line_stateN <= virtual;
end if;
when first_real => if line_counter(9) = '0' then
line_stateN <= real;
else
line_stateN <= first_real;
end if;
when real => if line_counter(9) = '1' then
line_stateN <= after_real;
else
line_stateN <= real;
end if;
when after_real => if line_counter(9) = '0' then
line_stateN <= virtual;
else
line_stateN <= after_real;
end if;
when others => line_stateN <= virtual;
end case;
end process;
-- line counter increment
line_couter_increment : process(clk,rst)
begin
if rst = '1' then
line_counter <= std_logic_vector(to_unsigned(line_counter_low_start,10));
elsif rising_edge(clk) then
if x_counter(10) = '1' and hsyncP = '1' then
if line_counter(9) = '1' then
line_counter <= line_counter_init;
else
line_counter <= std_logic_vector(unsigned(line_counter) + 1);
end if;
end if;
end if;
end process;
prepare_line_counter_init : process(line_stateP)
begin
case line_stateP is
when virtual => line_counter_init <= std_logic_vector(to_unsigned(line_counter_high,10));
when first_real => line_counter_init <= std_logic_vector(to_unsigned(line_counter_high,10));
when real => line_counter_init <= std_logic_vector(to_unsigned(line_counter_low,10));
when after_real => line_counter_init <= std_logic_vector(to_unsigned(line_counter_low,10));
when others => line_counter_init <= std_logic_vector(to_unsigned(line_counter_high,10));
end case;
end process;
end v1_2;
architecture v1_3 of driver_sharp is
-- Constants defined by specification
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 799; -- Horizontal sync signal cycle width in clock cycle
constant TV : positive := 524; -- Vertical sync signal period in clock cycle
constant THp : positive := 95; -- Horizontal sync signal pulse width in clock cyle
constant TVp : positive := 1; -- Vertical sync signal pulse width in hsync cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
-- Constants for internal use
-- X axis
constant x_counter_low : positive := 1024 - THp ;
constant x_counter_low_start : positive := x_counter_low+1;
-- constant x_counter_low_start : positive := x_counter_low;
constant x_counter_valid : positive := 1024 - THd + 1;
constant x_counter_fill : positive := 1024 - (TH - THp - THd) + 1;
-- Y axis
constant y_counter_low : positive := 512 - TVp + 1;
constant y_counter_low_start : positive := y_counter_low;
constant y_counter_pre_fill : positive := 512 - (TVs - TVp) + 1;
constant y_counter_valid : positive := 512 - TVd + 1;
constant y_counter_post_fill : positive := 512 - (TV - TVp - TVs - TVd + 1) ;
-- Internal signals related to X axis
signal x_counter: std_logic_vector( 10 downto 0) := std_logic_vector(to_unsigned(x_counter_low_start,11)); -- counter for x axis
signal x_counter_init: std_logic_vector( 10 downto 0) := (others => '0');
signal hsyncP : std_logic := '0';
signal enableP : std_logic := '0';
type x_fsm_state_type is (x_low,x_valid,x_fill);
signal x_fsm_stateP : x_fsm_state_type := x_low;
signal x_fsm_stateN : x_fsm_state_type := x_valid;
signal x : std_logic_vector(9 downto 0) := (others => '0');
-- Internal signals related to Y axis
signal y_counter: std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(y_counter_low_start,10)); -- counter for x axis
signal y_counter_init: std_logic_vector(9 downto 0) := (others => '0');
signal vsyncP : std_logic := '0';
type y_fsm_state_type is (y_low,y_pre_fill,y_valid,y_post_fill);
signal y_fsm_stateP : y_fsm_state_type;
signal y_fsm_stateN : y_fsm_state_type;
signal y : std_logic_vector(8 downto 0) := (others => '0');
begin -- behavorial
-- Process managing outputs
output_management : process(clk,rst)
begin
if rst = '1' then
hsync <= '0';
vsync <= '0';
enable <= '0';
x_out <= (others => '0');
y_out <= (others => '0');
elsif rising_edge(clk) then
vsync <= vsyncP;
hsync <= hsyncP;
enable <= enableP;
x_out <= x;
y_out <= y;
end if;
end process;
-- process managing x_counter increment
x_counter_increment : process(clk,rst)
begin
if rst = '1' then
x_counter <= std_logic_vector(to_unsigned(x_counter_low_start,11));
elsif rising_edge(clk) then
if x_counter(10) = '1' then
x_counter <= x_counter_init;
else
x_counter <= std_logic_vector(unsigned(x_counter)+1);
end if;
end if;
end process;
-- process computing x_counter_init
prepare_x_counter_init : process (x_fsm_stateP)
begin
case x_fsm_stateP is
when x_low => x_counter_init <= std_logic_vector(to_unsigned(x_counter_valid,11));
when x_valid => x_counter_init <= std_logic_vector(to_unsigned(x_counter_fill,11));
when x_fill => x_counter_init <= std_logic_vector(to_unsigned(x_counter_low,11));
when others => x_counter_init <= (others => '0');
end case;
end process;
-- process computing next x_fsm_state
prepare_next_x_fsm_state : process (x_fsm_stateP)
begin
case x_fsm_stateP is
when x_low => x_fsm_stateN <= x_valid;
when x_valid => x_fsm_stateN <= x_fill;
when x_fill => x_fsm_stateN <= x_low;
when others => x_fsm_stateN <= x_low;
end case;
end process;
-- process managing x_fsm_state register
x_fsm_state_register : process(clk,rst)
begin
if rst = '1' then
x_fsm_stateP <= x_low;
elsif rising_edge(clk) then
if x_counter(10) = '1' then
x_fsm_stateP <= x_fsm_stateN;
else
x_fsm_stateP <= x_fsm_stateP;
end if;
end if;
end process;
apply_hsync : hsyncP <= '0' when x_fsm_stateP = x_low else '1';
-- process managing ycounter increment
ycounter_increment : process(clk,rst)
begin
if rst = '1' then
y_counter <= std_logic_vector(to_unsigned(y_counter_low_start,10));
elsif rising_edge(clk) then
if x_counter(10) = '1' and x_fsm_stateP = x_fill then
if y_counter(9) = '1' then
y_counter <= y_counter_init;
else
y_counter <= std_logic_vector(unsigned(y_counter) + 1);
end if;
else
y_counter <= y_counter;
end if;
end if;
end process;
-- prepare the init value for ycounter
prepare_ycounter_init : process(y_fsm_stateP)
begin
case y_fsm_stateP is
when y_low => y_counter_init <= std_logic_vector(to_unsigned(y_counter_pre_fill,10));
when y_pre_fill => y_counter_init <= std_logic_vector(to_unsigned(y_counter_valid,10));
when y_valid => y_counter_init <= std_logic_vector(to_unsigned(y_counter_post_fill,10));
when y_post_fill => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,10));
when others => y_counter_init <= std_logic_vector(to_unsigned(y_counter_low,10));
end case;
end process;
-- process computing next y_fsm_state
vsync_state_transition_process : process(y_fsm_stateP)
begin
case y_fsm_stateP is
when y_low => y_fsm_stateN <= y_pre_fill;
when y_pre_fill => y_fsm_stateN <= y_valid;
when y_valid => y_fsm_stateN <= y_post_fill;
when y_post_fill => y_fsm_stateN <= y_low;
when others => y_fsm_stateN <= y_low;
end case;
end process;
-- process managing y_fsm_state_register
y_fsm_state_register : process(clk,rst)
begin
if rst = '1' then
y_fsm_stateP <= y_low;
elsif rising_edge(clk) then
if y_counter(9) = '1' and x_counter(10) = '1' and x_fsm_stateP = x_fill then
y_fsm_stateP <= y_fsm_stateN;
else
y_fsm_stateP <= y_fsm_stateP;
end if;
end if;
end process;
--vsync output function
apply_vsync : vsyncP <= '0' when y_fsm_stateP = y_low else '1';
-- enable output function
apply_enable : enableP <= '1' when y_fsm_stateP = y_valid and x_fsm_stateP = x_valid else '0';
--process managing x increment
x_increment : process(clk,rst)
begin
if rst = '1' then
x <= (others => '0');
elsif rising_edge(clk) then
if x_fsm_stateP = x_valid and y_fsm_statep = y_valid then
if x_counter(10) = '0' then
x <= std_logic_vector(unsigned(x) + 1);
else
x <= (others => '0');
end if;
else
x <= x;
end if;
end if;
end process;
-- process managing y increment
y_increment : process(clk,rst)
begin
if rst = '1' then
y <= (others => '0');
elsif rising_edge(clk) then
if y_fsm_stateP = y_valid and x_fsm_stateP = x_fill then
if x_counter(10) = '1'then
if y_counter(9) = '0' then
y <= std_logic_vector(unsigned(y) + 1);
else
y <= (others => '0');
end if;
end if;
else
y <= y;
end if;
end if;
end process;
end v1_3;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_atx_pll is
generic (
avmm_group_channel_index : integer := 0 ;
output_clock_frequency : string := "" ;
reference_clock_frequency : string := "" ;
use_default_base_address : string := "true" ;
user_base_address0 : integer := 0 ;
user_base_address1 : integer := 0 ;
user_base_address2 : integer := 0 ;
cp_current_ctrl : integer := 300 ;
cp_current_test : string := "enable_ch_pump_normal" ;
cp_hs_levshift_power_supply_setting : integer := 1 ;
cp_replica_bias_ctrl : string := "disable_replica_bias_ctrl" ;
cp_rgla_bypass : string := "false" ;
cp_rgla_volt_inc : string := "boost_30pct" ;
l_counter : integer := 1 ;
lcpll_atb_select : string := "atb_disable" ;
lcpll_d2a_sel : string := "volt_1p02v" ;
lcpll_hclk_driver_enable : string := "driver_off" ;
lcvco_gear_sel : string := "high_gear" ;
lcvco_sel : string := "high_freq_14g" ;
lpf_ripple_cap_ctrl : string := "none" ;
lpf_rxpll_pfd_bw_ctrl : integer := 2400 ;
m_counter : integer := 4 ;
ref_clk_div : integer := 1 ;
refclk_sel : string := "refclk" ;
vreg1_lcvco_volt_inc : string := "volt_1p1v" ;
vreg1_vccehlow : string := "normal_operation" ;
vreg2_lcpll_volt_sel : string := "vreg2_volt_1p0v" ;
vreg3_lcpll_volt_sel : string := "vreg3_volt_1p0v"
);
port (
avmmaddress : in std_logic_vector( 10 downto 0 );
avmmbyteen : in std_logic_vector( 1 downto 0 );
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector( 15 downto 0 );
avmmreaddata : out std_logic_vector( 15 downto 0 );
blockselect : out std_logic;
ch0rcsrlc : in std_logic_vector( 31 downto 0 );
ch1rcsrlc : in std_logic_vector( 31 downto 0 );
ch2rcsrlc : in std_logic_vector( 31 downto 0 );
cmurstn : in std_logic;
cmurstnlpf : in std_logic;
extfbclk : in std_logic;
iqclklc : in std_logic;
pldclklc : in std_logic;
pllfbswblc : in std_logic;
pllfbswtlc : in std_logic;
refclklc : in std_logic;
clk010g : out std_logic;
clk025g : out std_logic;
clk18010g : out std_logic;
clk18025g : out std_logic;
clk33cmu : out std_logic;
clklowcmu : out std_logic;
frefcmu : out std_logic;
iqclkatt : out std_logic;
pfdmodelockcmu : out std_logic;
pldclkatt : out std_logic;
refclkatt : out std_logic;
txpllhclk : out std_logic
);
end stratixv_atx_pll;
architecture behavior of stratixv_atx_pll is
component stratixv_atx_pll_encrypted
generic (
avmm_group_channel_index : integer := 0 ;
output_clock_frequency : string := "" ;
reference_clock_frequency : string := "" ;
use_default_base_address : string := "true" ;
user_base_address0 : integer := 0 ;
user_base_address1 : integer := 0 ;
user_base_address2 : integer := 0 ;
cp_current_ctrl : integer := 300 ;
cp_current_test : string := "enable_ch_pump_normal" ;
cp_hs_levshift_power_supply_setting : integer := 1 ;
cp_replica_bias_ctrl : string := "disable_replica_bias_ctrl" ;
cp_rgla_bypass : string := "false" ;
cp_rgla_volt_inc : string := "boost_30pct" ;
l_counter : integer := 1 ;
lcpll_atb_select : string := "atb_disable" ;
lcpll_d2a_sel : string := "volt_1p02v" ;
lcpll_hclk_driver_enable : string := "driver_off" ;
lcvco_gear_sel : string := "high_gear" ;
lcvco_sel : string := "high_freq_14g" ;
lpf_ripple_cap_ctrl : string := "none" ;
lpf_rxpll_pfd_bw_ctrl : integer := 2400 ;
m_counter : integer := 4 ;
ref_clk_div : integer := 1 ;
refclk_sel : string := "refclk" ;
vreg1_lcvco_volt_inc : string := "volt_1p1v" ;
vreg1_vccehlow : string := "normal_operation" ;
vreg2_lcpll_volt_sel : string := "vreg2_volt_1p0v" ;
vreg3_lcpll_volt_sel : string := "vreg3_volt_1p0v"
);
port (
avmmaddress : in std_logic_vector( 10 downto 0 );
avmmbyteen : in std_logic_vector( 1 downto 0 );
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector( 15 downto 0 );
avmmreaddata : out std_logic_vector( 15 downto 0 );
blockselect : out std_logic;
ch0rcsrlc : in std_logic_vector( 31 downto 0 );
ch1rcsrlc : in std_logic_vector( 31 downto 0 );
ch2rcsrlc : in std_logic_vector( 31 downto 0 );
cmurstn : in std_logic;
cmurstnlpf : in std_logic;
extfbclk : in std_logic;
iqclklc : in std_logic;
pldclklc : in std_logic;
pllfbswblc : in std_logic;
pllfbswtlc : in std_logic;
refclklc : in std_logic;
clk010g : out std_logic;
clk025g : out std_logic;
clk18010g : out std_logic;
clk18025g : out std_logic;
clk33cmu : out std_logic;
clklowcmu : out std_logic;
frefcmu : out std_logic;
iqclkatt : out std_logic;
pfdmodelockcmu : out std_logic;
pldclkatt : out std_logic;
refclkatt : out std_logic;
txpllhclk : out std_logic
);
end component;
begin
inst : stratixv_atx_pll_encrypted
generic map (
avmm_group_channel_index => avmm_group_channel_index ,
output_clock_frequency => output_clock_frequency ,
reference_clock_frequency => reference_clock_frequency ,
use_default_base_address => use_default_base_address ,
user_base_address0 => user_base_address0 ,
user_base_address1 => user_base_address1 ,
user_base_address2 => user_base_address2 ,
cp_current_ctrl => cp_current_ctrl ,
cp_current_test => cp_current_test ,
cp_hs_levshift_power_supply_setting => cp_hs_levshift_power_supply_setting ,
cp_replica_bias_ctrl => cp_replica_bias_ctrl ,
cp_rgla_bypass => cp_rgla_bypass ,
cp_rgla_volt_inc => cp_rgla_volt_inc ,
l_counter => l_counter ,
lcpll_atb_select => lcpll_atb_select ,
lcpll_d2a_sel => lcpll_d2a_sel ,
lcpll_hclk_driver_enable => lcpll_hclk_driver_enable ,
lcvco_gear_sel => lcvco_gear_sel ,
lcvco_sel => lcvco_sel ,
lpf_ripple_cap_ctrl => lpf_ripple_cap_ctrl ,
lpf_rxpll_pfd_bw_ctrl => lpf_rxpll_pfd_bw_ctrl ,
m_counter => m_counter ,
ref_clk_div => ref_clk_div ,
refclk_sel => refclk_sel ,
vreg1_lcvco_volt_inc => vreg1_lcvco_volt_inc ,
vreg1_vccehlow => vreg1_vccehlow ,
vreg2_lcpll_volt_sel => vreg2_lcpll_volt_sel ,
vreg3_lcpll_volt_sel => vreg3_lcpll_volt_sel
)
port map (
avmmaddress => avmmaddress ,
avmmbyteen => avmmbyteen ,
avmmclk => avmmclk ,
avmmread => avmmread ,
avmmrstn => avmmrstn ,
avmmwrite => avmmwrite ,
avmmwritedata => avmmwritedata ,
avmmreaddata => avmmreaddata ,
blockselect => blockselect ,
ch0rcsrlc => ch0rcsrlc ,
ch1rcsrlc => ch1rcsrlc ,
ch2rcsrlc => ch2rcsrlc ,
cmurstn => cmurstn ,
cmurstnlpf => cmurstnlpf ,
extfbclk => extfbclk ,
iqclklc => iqclklc ,
pldclklc => pldclklc ,
pllfbswblc => pllfbswblc ,
pllfbswtlc => pllfbswtlc ,
refclklc => refclklc ,
clk010g => clk010g ,
clk025g => clk025g ,
clk18010g => clk18010g ,
clk18025g => clk18025g ,
clk33cmu => clk33cmu ,
clklowcmu => clklowcmu ,
frefcmu => frefcmu ,
iqclkatt => iqclkatt ,
pfdmodelockcmu => pfdmodelockcmu ,
pldclkatt => pldclkatt ,
refclkatt => refclkatt ,
txpllhclk => txpllhclk
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_channel_pll is
generic
(
avmm_group_channel_index : integer := 0;
output_clock_frequency : string := "0 ps";
reference_clock_frequency : string := "0 ps";
sim_use_fast_model : string := "true";
use_default_base_address : string := "true";
user_base_address : integer := 0;
bbpd_salatch_offset_ctrl_clk0 : string := "clk0_offset_0mv";
bbpd_salatch_offset_ctrl_clk180 : string := "clk180_offset_0mv";
bbpd_salatch_offset_ctrl_clk270 : string := "clk270_offset_0mv";
bbpd_salatch_offset_ctrl_clk90 : string := "clk90_offset_0mv";
bbpd_salatch_sel : string := "normal";
bypass_cp_rgla : string := "false";
cdr_atb_select : string := "atb_disable";
cgb_clk_enable : string := "false";
charge_pump_current_test : string := "enable_ch_pump_normal";
clklow_fref_to_ppm_div_sel : integer := 1;
clock_monitor : string := "lpbk_data";
diag_rev_lpbk : string := "false";
eye_monitor_bbpd_data_ctrl : string := "cdr_data";
fast_lock_mode : string := "false";
fb_sel : string := "vcoclk";
gpon_lock2ref_ctrl : string := "lck2ref";
hs_levshift_power_supply_setting : integer := 1;
ignore_phslock : string := "false";
l_counter_pd_clock_disable : string := "false";
m_counter : integer := 25;
pcie_freq_control : string := "pcie_100mhz";
pd_charge_pump_current_ctrl : integer := 5;
pd_l_counter : integer := 1;
pfd_charge_pump_current_ctrl : integer := 20;
pfd_l_counter : integer := 1;
powerdown : string := "false";
ref_clk_div : integer := 1;
regulator_volt_inc : string := "volt_inc_0pct";
replica_bias_ctrl : string := "true";
reverse_serial_lpbk : string := "false";
ripple_cap_ctrl : string := "none";
rxpll_pd_bw_ctrl : integer := 300;
rxpll_pfd_bw_ctrl : integer := 3200;
txpll_hclk_driver_enable : string := "false";
vco_overange_ref : string := "off";
vco_range_ctrl_en : string := "false"
);
port
(
avmmaddress : in std_logic_vector(10 downto 0);
avmmbyteen : in std_logic;
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector(15 downto 0);
clk270eye : in std_logic;
clk270beyerm : in std_logic;
clk90eye : in std_logic;
clk90beyerm : in std_logic;
clkindeser : in std_logic;
crurstb : in std_logic;
deeye : in std_logic;
deeyerm : in std_logic;
doeye : in std_logic;
doeyerm : in std_logic;
earlyeios : in std_logic;
extclk : in std_logic;
extfbctrla : in std_logic;
extfbctrlb : in std_logic;
gpblck2refb : in std_logic;
lpbkpreen : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
occalen : in std_logic;
pciel : in std_logic;
pciem : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
ppmlock : in std_logic;
refclk : in std_logic;
rstn : in std_logic;
rxp : in std_logic;
sd : in std_logic;
avmmreaddata : out std_logic_vector(15 downto 0);
blockselect : out std_logic;
ck0pd : out std_logic;
ck180pd : out std_logic;
ck270pd : out std_logic;
ck90pd : out std_logic;
clk270bcdr : out std_logic;
clk270bdes : out std_logic;
clk90bcdr : out std_logic;
clk90bdes : out std_logic;
clkcdr : out std_logic;
clklow : out std_logic;
decdr : out std_logic;
deven : out std_logic;
docdr : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pdof : out std_logic_vector(3 downto 0);
pfdmodelock : out std_logic;
rxlpbdp : out std_logic;
rxlpbp : out std_logic;
rxplllock : out std_logic;
txpllhclk : out std_logic;
txrlpbk : out std_logic;
vctrloverrange : out std_logic
);
end stratixv_channel_pll;
architecture behavior of stratixv_channel_pll is
component stratixv_channel_pll_encrypted
generic (
avmm_group_channel_index : integer := 0;
output_clock_frequency : string := "0 ps";
reference_clock_frequency : string := "0 ps";
sim_use_fast_model : string := "true";
use_default_base_address : string := "true";
user_base_address : integer := 0;
bbpd_salatch_offset_ctrl_clk0 : string := "clk0_offset_0mv";
bbpd_salatch_offset_ctrl_clk180 : string := "clk180_offset_0mv";
bbpd_salatch_offset_ctrl_clk270 : string := "clk270_offset_0mv";
bbpd_salatch_offset_ctrl_clk90 : string := "clk90_offset_0mv";
bbpd_salatch_sel : string := "normal";
bypass_cp_rgla : string := "false";
cdr_atb_select : string := "atb_disable";
cgb_clk_enable : string := "false";
charge_pump_current_test : string := "enable_ch_pump_normal";
clklow_fref_to_ppm_div_sel : integer := 1;
clock_monitor : string := "lpbk_data";
diag_rev_lpbk : string := "false";
eye_monitor_bbpd_data_ctrl : string := "cdr_data";
fast_lock_mode : string := "false";
fb_sel : string := "vcoclk";
gpon_lock2ref_ctrl : string := "lck2ref";
hs_levshift_power_supply_setting : integer := 1;
ignore_phslock : string := "false";
l_counter_pd_clock_disable : string := "false";
m_counter : integer := 25;
pcie_freq_control : string := "pcie_100mhz";
pd_charge_pump_current_ctrl : integer := 5;
pd_l_counter : integer := 1;
pfd_charge_pump_current_ctrl : integer := 20;
pfd_l_counter : integer := 1;
powerdown : string := "false";
ref_clk_div : integer := 1;
regulator_volt_inc : string := "volt_inc_0pct";
replica_bias_ctrl : string := "true";
reverse_serial_lpbk : string := "false";
ripple_cap_ctrl : string := "none";
rxpll_pd_bw_ctrl : integer := 300;
rxpll_pfd_bw_ctrl : integer := 3200;
txpll_hclk_driver_enable : string := "false";
vco_overange_ref : string := "off";
vco_range_ctrl_en : string := "false"
);
port (
avmmaddress : in std_logic_vector(10 downto 0);
avmmbyteen : in std_logic;
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector(15 downto 0);
clk270eye : in std_logic;
clk270beyerm : in std_logic;
clk90eye : in std_logic;
clk90beyerm : in std_logic;
clkindeser : in std_logic;
crurstb : in std_logic;
deeye : in std_logic;
deeyerm : in std_logic;
doeye : in std_logic;
doeyerm : in std_logic;
earlyeios : in std_logic;
extclk : in std_logic;
extfbctrla : in std_logic;
extfbctrlb : in std_logic;
gpblck2refb : in std_logic;
lpbkpreen : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
occalen : in std_logic;
pciel : in std_logic;
pciem : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
ppmlock : in std_logic;
refclk : in std_logic;
rstn : in std_logic;
rxp : in std_logic;
sd : in std_logic;
avmmreaddata : out std_logic_vector(15 downto 0);
blockselect : out std_logic;
ck0pd : out std_logic;
ck180pd : out std_logic;
ck270pd : out std_logic;
ck90pd : out std_logic;
clk270bcdr : out std_logic;
clk270bdes : out std_logic;
clk90bcdr : out std_logic;
clk90bdes : out std_logic;
clkcdr : out std_logic;
clklow : out std_logic;
decdr : out std_logic;
deven : out std_logic;
docdr : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pdof : out std_logic_vector(3 downto 0);
pfdmodelock : out std_logic;
rxlpbdp : out std_logic;
rxlpbp : out std_logic;
rxplllock : out std_logic;
txpllhclk : out std_logic;
txrlpbk : out std_logic;
vctrloverrange : out std_logic
);
end component;
begin
inst : stratixv_channel_pll_encrypted
generic map
(
avmm_group_channel_index => avmm_group_channel_index,
output_clock_frequency => output_clock_frequency,
reference_clock_frequency => reference_clock_frequency,
sim_use_fast_model => sim_use_fast_model,
use_default_base_address => use_default_base_address,
user_base_address => user_base_address,
bbpd_salatch_offset_ctrl_clk0 => bbpd_salatch_offset_ctrl_clk0,
bbpd_salatch_offset_ctrl_clk180 => bbpd_salatch_offset_ctrl_clk180,
bbpd_salatch_offset_ctrl_clk270 => bbpd_salatch_offset_ctrl_clk270,
bbpd_salatch_offset_ctrl_clk90 => bbpd_salatch_offset_ctrl_clk90,
bbpd_salatch_sel => bbpd_salatch_sel,
bypass_cp_rgla => bypass_cp_rgla,
cdr_atb_select => cdr_atb_select,
cgb_clk_enable => cgb_clk_enable,
charge_pump_current_test => charge_pump_current_test,
clklow_fref_to_ppm_div_sel => clklow_fref_to_ppm_div_sel,
clock_monitor => clock_monitor,
diag_rev_lpbk => diag_rev_lpbk,
eye_monitor_bbpd_data_ctrl => eye_monitor_bbpd_data_ctrl,
fast_lock_mode => fast_lock_mode,
fb_sel => fb_sel,
gpon_lock2ref_ctrl => gpon_lock2ref_ctrl,
hs_levshift_power_supply_setting => hs_levshift_power_supply_setting,
ignore_phslock => ignore_phslock,
l_counter_pd_clock_disable => l_counter_pd_clock_disable,
m_counter => m_counter,
pcie_freq_control => pcie_freq_control,
pd_charge_pump_current_ctrl => pd_charge_pump_current_ctrl,
pd_l_counter => pd_l_counter,
pfd_charge_pump_current_ctrl => pfd_charge_pump_current_ctrl,
pfd_l_counter => pfd_l_counter,
powerdown => powerdown,
ref_clk_div => ref_clk_div,
regulator_volt_inc => regulator_volt_inc,
replica_bias_ctrl => replica_bias_ctrl,
reverse_serial_lpbk => reverse_serial_lpbk,
ripple_cap_ctrl => ripple_cap_ctrl,
rxpll_pd_bw_ctrl => rxpll_pd_bw_ctrl,
rxpll_pfd_bw_ctrl => rxpll_pfd_bw_ctrl,
txpll_hclk_driver_enable => txpll_hclk_driver_enable,
vco_overange_ref => vco_overange_ref,
vco_range_ctrl_en => vco_range_ctrl_en
)
port map
(
avmmaddress => avmmaddress,
avmmbyteen => avmmbyteen,
avmmclk => avmmclk,
avmmread => avmmread,
avmmrstn => avmmrstn,
avmmwrite => avmmwrite,
avmmwritedata => avmmwritedata,
clk270eye => clk270eye,
clk270beyerm => clk270beyerm,
clk90eye => clk90eye,
clk90beyerm => clk90beyerm,
clkindeser => clkindeser,
crurstb => crurstb,
deeye => deeye,
deeyerm => deeyerm,
doeye => doeye,
doeyerm => doeyerm,
earlyeios => earlyeios,
extclk => extclk,
extfbctrla => extfbctrla,
extfbctrlb => extfbctrlb,
gpblck2refb => gpblck2refb,
lpbkpreen => lpbkpreen,
ltd => ltd,
ltr => ltr,
occalen => occalen,
pciel => pciel,
pciem => pciem,
pciesw => pciesw,
ppmlock => ppmlock,
refclk => refclk,
rstn => rstn,
rxp => rxp,
sd => sd,
avmmreaddata => avmmreaddata,
blockselect => blockselect,
ck0pd => ck0pd,
ck180pd => ck180pd,
ck270pd => ck270pd,
ck90pd => ck90pd,
clk270bcdr => clk270bcdr,
clk270bdes => clk270bdes,
clk90bcdr => clk90bcdr,
clk90bdes => clk90bdes,
clkcdr => clkcdr,
clklow => clklow,
decdr => decdr,
deven => deven,
docdr => docdr,
dodd => dodd,
fref => fref,
pdof => pdof,
pfdmodelock => pfdmodelock,
rxlpbdp => rxlpbdp,
rxlpbp => rxlpbp,
rxplllock => rxplllock,
txpllhclk => txpllhclk,
txrlpbk => txrlpbk,
vctrloverrange => vctrloverrange
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_pcs_aggregate is
generic (
xaui_sm_operation : string := "en_xaui_sm";
dskw_sm_operation : string := "dskw_xaui_sm";
data_agg_bonding : string := "agg_disable";
prot_mode_tx : string := "pipe_g1_tx";
pcs_dw_datapath : string := "sw_data_path";
dskw_control : string := "dskw_write_control";
refclkdig_sel : string := "dis_refclk_dig_sel"
);
port (
refclkdig : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rcvdclkch0 : in std_logic_vector(0 downto 0);
rcvdclkch1 : in std_logic_vector(0 downto 0);
hardrst : in std_logic_vector(0 downto 0);
txpcsrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
dprioagg : in std_logic_vector(63 downto 0);
rcvdclkout : out std_logic_vector(0 downto 0);
rcvdclkouttop : out std_logic_vector(0 downto 0);
rcvdclkoutbot : out std_logic_vector(0 downto 0);
rdenablesynctopch1 : in std_logic_vector(0 downto 0);
txdatatctopch1 : in std_logic_vector(7 downto 0);
txctltctopch1 : in std_logic_vector(0 downto 0);
syncstatustopch1 : in std_logic_vector(0 downto 0);
rdaligntopch1 : in std_logic_vector(1 downto 0);
aligndetsynctopch1 : in std_logic_vector(1 downto 0);
fifordintopch1 : in std_logic_vector(0 downto 0);
alignstatussynctopch1 : in std_logic_vector(0 downto 0);
cgcomprddintopch1 : in std_logic_vector(1 downto 0);
cgcompwrintopch1 : in std_logic_vector(1 downto 0);
delcondmetintopch1 : in std_logic_vector(0 downto 0);
fifoovrintopch1 : in std_logic_vector(0 downto 0);
latencycompintopch1 : in std_logic_vector(0 downto 0);
insertincompleteintopch1 : in std_logic_vector(0 downto 0);
decdatatopch1 : in std_logic_vector(7 downto 0);
decctltopch1 : in std_logic_vector(0 downto 0);
decdatavalidtopch1 : in std_logic_vector(0 downto 0);
runningdisptopch1 : in std_logic_vector(1 downto 0);
txdatatstopch1 : out std_logic_vector(7 downto 0);
txctltstopch1 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch1 : out std_logic_vector(0 downto 0);
endskwqdtopch1 : out std_logic_vector(0 downto 0);
endskwrdptrstopch1 : out std_logic_vector(0 downto 0);
alignstatustopch1 : out std_logic_vector(0 downto 0);
alignstatussync0topch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch1 : out std_logic_vector(0 downto 0);
cgcomprddalltopch1 : out std_logic_vector(0 downto 0);
cgcompwralltopch1 : out std_logic_vector(0 downto 0);
delcondmet0topch1 : out std_logic_vector(0 downto 0);
insertincomplete0topch1 : out std_logic_vector(0 downto 0);
fifoovr0topch1 : out std_logic_vector(0 downto 0);
latencycomp0topch1 : out std_logic_vector(0 downto 0);
rxdatarstopch1 : out std_logic_vector(7 downto 0);
rxctlrstopch1 : out std_logic_vector(0 downto 0);
rdenablesynctopch0 : in std_logic_vector(0 downto 0);
txdatatctopch0 : in std_logic_vector(7 downto 0);
txctltctopch0 : in std_logic_vector(0 downto 0);
syncstatustopch0 : in std_logic_vector(0 downto 0);
rdaligntopch0 : in std_logic_vector(1 downto 0);
aligndetsynctopch0 : in std_logic_vector(1 downto 0);
fifordintopch0 : in std_logic_vector(0 downto 0);
alignstatussynctopch0 : in std_logic_vector(0 downto 0);
cgcomprddintopch0 : in std_logic_vector(1 downto 0);
cgcompwrintopch0 : in std_logic_vector(1 downto 0);
delcondmetintopch0 : in std_logic_vector(0 downto 0);
fifoovrintopch0 : in std_logic_vector(0 downto 0);
latencycompintopch0 : in std_logic_vector(0 downto 0);
insertincompleteintopch0 : in std_logic_vector(0 downto 0);
decdatatopch0 : in std_logic_vector(7 downto 0);
decctltopch0 : in std_logic_vector(0 downto 0);
decdatavalidtopch0 : in std_logic_vector(0 downto 0);
runningdisptopch0 : in std_logic_vector(1 downto 0);
txdatatstopch0 : out std_logic_vector(7 downto 0);
txctltstopch0 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch0 : out std_logic_vector(0 downto 0);
endskwqdtopch0 : out std_logic_vector(0 downto 0);
endskwrdptrstopch0 : out std_logic_vector(0 downto 0);
alignstatustopch0 : out std_logic_vector(0 downto 0);
alignstatussync0topch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch0 : out std_logic_vector(0 downto 0);
cgcomprddalltopch0 : out std_logic_vector(0 downto 0);
cgcompwralltopch0 : out std_logic_vector(0 downto 0);
delcondmet0topch0 : out std_logic_vector(0 downto 0);
insertincomplete0topch0 : out std_logic_vector(0 downto 0);
fifoovr0topch0 : out std_logic_vector(0 downto 0);
latencycomp0topch0 : out std_logic_vector(0 downto 0);
rxdatarstopch0 : out std_logic_vector(7 downto 0);
rxctlrstopch0 : out std_logic_vector(0 downto 0);
rdenablesyncch2 : in std_logic_vector(0 downto 0);
txdatatcch2 : in std_logic_vector(7 downto 0);
txctltcch2 : in std_logic_vector(0 downto 0);
syncstatusch2 : in std_logic_vector(0 downto 0);
rdalignch2 : in std_logic_vector(1 downto 0);
aligndetsyncch2 : in std_logic_vector(1 downto 0);
fifordinch2 : in std_logic_vector(0 downto 0);
alignstatussyncch2 : in std_logic_vector(0 downto 0);
cgcomprddinch2 : in std_logic_vector(1 downto 0);
cgcompwrinch2 : in std_logic_vector(1 downto 0);
delcondmetinch2 : in std_logic_vector(0 downto 0);
fifoovrinch2 : in std_logic_vector(0 downto 0);
latencycompinch2 : in std_logic_vector(0 downto 0);
insertincompleteinch2 : in std_logic_vector(0 downto 0);
decdatach2 : in std_logic_vector(7 downto 0);
decctlch2 : in std_logic_vector(0 downto 0);
decdatavalidch2 : in std_logic_vector(0 downto 0);
runningdispch2 : in std_logic_vector(1 downto 0);
txdatatsch2 : out std_logic_vector(7 downto 0);
txctltsch2 : out std_logic_vector(0 downto 0);
fiforstrdqdch2 : out std_logic_vector(0 downto 0);
endskwqdch2 : out std_logic_vector(0 downto 0);
endskwrdptrsch2 : out std_logic_vector(0 downto 0);
alignstatusch2 : out std_logic_vector(0 downto 0);
alignstatussync0ch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch2 : out std_logic_vector(0 downto 0);
cgcomprddallch2 : out std_logic_vector(0 downto 0);
cgcompwrallch2 : out std_logic_vector(0 downto 0);
delcondmet0ch2 : out std_logic_vector(0 downto 0);
insertincomplete0ch2 : out std_logic_vector(0 downto 0);
fifoovr0ch2 : out std_logic_vector(0 downto 0);
latencycomp0ch2 : out std_logic_vector(0 downto 0);
rxdatarsch2 : out std_logic_vector(7 downto 0);
rxctlrsch2 : out std_logic_vector(0 downto 0);
rdenablesyncch1 : in std_logic_vector(0 downto 0);
txdatatcch1 : in std_logic_vector(7 downto 0);
txctltcch1 : in std_logic_vector(0 downto 0);
syncstatusch1 : in std_logic_vector(0 downto 0);
rdalignch1 : in std_logic_vector(1 downto 0);
aligndetsyncch1 : in std_logic_vector(1 downto 0);
fifordinch1 : in std_logic_vector(0 downto 0);
alignstatussyncch1 : in std_logic_vector(0 downto 0);
cgcomprddinch1 : in std_logic_vector(1 downto 0);
cgcompwrinch1 : in std_logic_vector(1 downto 0);
delcondmetinch1 : in std_logic_vector(0 downto 0);
fifoovrinch1 : in std_logic_vector(0 downto 0);
latencycompinch1 : in std_logic_vector(0 downto 0);
insertincompleteinch1 : in std_logic_vector(0 downto 0);
decdatach1 : in std_logic_vector(7 downto 0);
decctlch1 : in std_logic_vector(0 downto 0);
decdatavalidch1 : in std_logic_vector(0 downto 0);
runningdispch1 : in std_logic_vector(1 downto 0);
txdatatsch1 : out std_logic_vector(7 downto 0);
txctltsch1 : out std_logic_vector(0 downto 0);
fiforstrdqdch1 : out std_logic_vector(0 downto 0);
endskwqdch1 : out std_logic_vector(0 downto 0);
endskwrdptrsch1 : out std_logic_vector(0 downto 0);
alignstatusch1 : out std_logic_vector(0 downto 0);
alignstatussync0ch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch1 : out std_logic_vector(0 downto 0);
cgcomprddallch1 : out std_logic_vector(0 downto 0);
cgcompwrallch1 : out std_logic_vector(0 downto 0);
delcondmet0ch1 : out std_logic_vector(0 downto 0);
insertincomplete0ch1 : out std_logic_vector(0 downto 0);
fifoovr0ch1 : out std_logic_vector(0 downto 0);
latencycomp0ch1 : out std_logic_vector(0 downto 0);
rxdatarsch1 : out std_logic_vector(7 downto 0);
rxctlrsch1 : out std_logic_vector(0 downto 0);
rdenablesyncch0 : in std_logic_vector(0 downto 0);
txdatatcch0 : in std_logic_vector(7 downto 0);
txctltcch0 : in std_logic_vector(0 downto 0);
syncstatusch0 : in std_logic_vector(0 downto 0);
rdalignch0 : in std_logic_vector(1 downto 0);
aligndetsyncch0 : in std_logic_vector(1 downto 0);
fifordinch0 : in std_logic_vector(0 downto 0);
alignstatussyncch0 : in std_logic_vector(0 downto 0);
cgcomprddinch0 : in std_logic_vector(1 downto 0);
cgcompwrinch0 : in std_logic_vector(1 downto 0);
delcondmetinch0 : in std_logic_vector(0 downto 0);
fifoovrinch0 : in std_logic_vector(0 downto 0);
latencycompinch0 : in std_logic_vector(0 downto 0);
insertincompleteinch0 : in std_logic_vector(0 downto 0);
decdatach0 : in std_logic_vector(7 downto 0);
decctlch0 : in std_logic_vector(0 downto 0);
decdatavalidch0 : in std_logic_vector(0 downto 0);
runningdispch0 : in std_logic_vector(1 downto 0);
txdatatsch0 : out std_logic_vector(7 downto 0);
txctltsch0 : out std_logic_vector(0 downto 0);
fiforstrdqdch0 : out std_logic_vector(0 downto 0);
endskwqdch0 : out std_logic_vector(0 downto 0);
endskwrdptrsch0 : out std_logic_vector(0 downto 0);
alignstatusch0 : out std_logic_vector(0 downto 0);
alignstatussync0ch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch0 : out std_logic_vector(0 downto 0);
cgcomprddallch0 : out std_logic_vector(0 downto 0);
cgcompwrallch0 : out std_logic_vector(0 downto 0);
delcondmet0ch0 : out std_logic_vector(0 downto 0);
insertincomplete0ch0 : out std_logic_vector(0 downto 0);
fifoovr0ch0 : out std_logic_vector(0 downto 0);
latencycomp0ch0 : out std_logic_vector(0 downto 0);
rxdatarsch0 : out std_logic_vector(7 downto 0);
rxctlrsch0 : out std_logic_vector(0 downto 0);
rdenablesyncbotch2 : in std_logic_vector(0 downto 0);
txdatatcbotch2 : in std_logic_vector(7 downto 0);
txctltcbotch2 : in std_logic_vector(0 downto 0);
syncstatusbotch2 : in std_logic_vector(0 downto 0);
rdalignbotch2 : in std_logic_vector(1 downto 0);
aligndetsyncbotch2 : in std_logic_vector(1 downto 0);
fifordinbotch2 : in std_logic_vector(0 downto 0);
alignstatussyncbotch2 : in std_logic_vector(0 downto 0);
cgcomprddinbotch2 : in std_logic_vector(1 downto 0);
cgcompwrinbotch2 : in std_logic_vector(1 downto 0);
delcondmetinbotch2 : in std_logic_vector(0 downto 0);
fifoovrinbotch2 : in std_logic_vector(0 downto 0);
latencycompinbotch2 : in std_logic_vector(0 downto 0);
insertincompleteinbotch2 : in std_logic_vector(0 downto 0);
decdatabotch2 : in std_logic_vector(7 downto 0);
decctlbotch2 : in std_logic_vector(0 downto 0);
decdatavalidbotch2 : in std_logic_vector(0 downto 0);
runningdispbotch2 : in std_logic_vector(1 downto 0);
txdatatsbotch2 : out std_logic_vector(7 downto 0);
txctltsbotch2 : out std_logic_vector(0 downto 0);
fiforstrdqdbotch2 : out std_logic_vector(0 downto 0);
endskwqdbotch2 : out std_logic_vector(0 downto 0);
endskwrdptrsbotch2 : out std_logic_vector(0 downto 0);
alignstatusbotch2 : out std_logic_vector(0 downto 0);
alignstatussync0botch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0botch2 : out std_logic_vector(0 downto 0);
cgcomprddallbotch2 : out std_logic_vector(0 downto 0);
cgcompwrallbotch2 : out std_logic_vector(0 downto 0);
delcondmet0botch2 : out std_logic_vector(0 downto 0);
insertincomplete0botch2 : out std_logic_vector(0 downto 0);
fifoovr0botch2 : out std_logic_vector(0 downto 0);
latencycomp0botch2 : out std_logic_vector(0 downto 0);
rxdatarsbotch2 : out std_logic_vector(7 downto 0);
rxctlrsbotch2 : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_pcs_aggregate;
architecture behavior of stratixv_hssi_8g_pcs_aggregate is
component stratixv_hssi_8g_pcs_aggregate_encrypted
generic (
xaui_sm_operation : string := "en_xaui_sm";
dskw_sm_operation : string := "dskw_xaui_sm";
data_agg_bonding : string := "agg_disable";
prot_mode_tx : string := "pipe_g1_tx";
pcs_dw_datapath : string := "sw_data_path";
dskw_control : string := "dskw_write_control";
refclkdig_sel : string := "dis_refclk_dig_sel"
);
port (
refclkdig : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rcvdclkch0 : in std_logic_vector(0 downto 0);
rcvdclkch1 : in std_logic_vector(0 downto 0);
hardrst : in std_logic_vector(0 downto 0);
txpcsrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
dprioagg : in std_logic_vector(63 downto 0);
rcvdclkout : out std_logic_vector(0 downto 0);
rcvdclkouttop : out std_logic_vector(0 downto 0);
rcvdclkoutbot : out std_logic_vector(0 downto 0);
rdenablesynctopch1 : in std_logic_vector(0 downto 0);
txdatatctopch1 : in std_logic_vector(7 downto 0);
txctltctopch1 : in std_logic_vector(0 downto 0);
syncstatustopch1 : in std_logic_vector(0 downto 0);
rdaligntopch1 : in std_logic_vector(1 downto 0);
aligndetsynctopch1 : in std_logic_vector(1 downto 0);
fifordintopch1 : in std_logic_vector(0 downto 0);
alignstatussynctopch1 : in std_logic_vector(0 downto 0);
cgcomprddintopch1 : in std_logic_vector(1 downto 0);
cgcompwrintopch1 : in std_logic_vector(1 downto 0);
delcondmetintopch1 : in std_logic_vector(0 downto 0);
fifoovrintopch1 : in std_logic_vector(0 downto 0);
latencycompintopch1 : in std_logic_vector(0 downto 0);
insertincompleteintopch1 : in std_logic_vector(0 downto 0);
decdatatopch1 : in std_logic_vector(7 downto 0);
decctltopch1 : in std_logic_vector(0 downto 0);
decdatavalidtopch1 : in std_logic_vector(0 downto 0);
runningdisptopch1 : in std_logic_vector(1 downto 0);
txdatatstopch1 : out std_logic_vector(7 downto 0);
txctltstopch1 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch1 : out std_logic_vector(0 downto 0);
endskwqdtopch1 : out std_logic_vector(0 downto 0);
endskwrdptrstopch1 : out std_logic_vector(0 downto 0);
alignstatustopch1 : out std_logic_vector(0 downto 0);
alignstatussync0topch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch1 : out std_logic_vector(0 downto 0);
cgcomprddalltopch1 : out std_logic_vector(0 downto 0);
cgcompwralltopch1 : out std_logic_vector(0 downto 0);
delcondmet0topch1 : out std_logic_vector(0 downto 0);
insertincomplete0topch1 : out std_logic_vector(0 downto 0);
fifoovr0topch1 : out std_logic_vector(0 downto 0);
latencycomp0topch1 : out std_logic_vector(0 downto 0);
rxdatarstopch1 : out std_logic_vector(7 downto 0);
rxctlrstopch1 : out std_logic_vector(0 downto 0);
rdenablesynctopch0 : in std_logic_vector(0 downto 0);
txdatatctopch0 : in std_logic_vector(7 downto 0);
txctltctopch0 : in std_logic_vector(0 downto 0);
syncstatustopch0 : in std_logic_vector(0 downto 0);
rdaligntopch0 : in std_logic_vector(1 downto 0);
aligndetsynctopch0 : in std_logic_vector(1 downto 0);
fifordintopch0 : in std_logic_vector(0 downto 0);
alignstatussynctopch0 : in std_logic_vector(0 downto 0);
cgcomprddintopch0 : in std_logic_vector(1 downto 0);
cgcompwrintopch0 : in std_logic_vector(1 downto 0);
delcondmetintopch0 : in std_logic_vector(0 downto 0);
fifoovrintopch0 : in std_logic_vector(0 downto 0);
latencycompintopch0 : in std_logic_vector(0 downto 0);
insertincompleteintopch0 : in std_logic_vector(0 downto 0);
decdatatopch0 : in std_logic_vector(7 downto 0);
decctltopch0 : in std_logic_vector(0 downto 0);
decdatavalidtopch0 : in std_logic_vector(0 downto 0);
runningdisptopch0 : in std_logic_vector(1 downto 0);
txdatatstopch0 : out std_logic_vector(7 downto 0);
txctltstopch0 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch0 : out std_logic_vector(0 downto 0);
endskwqdtopch0 : out std_logic_vector(0 downto 0);
endskwrdptrstopch0 : out std_logic_vector(0 downto 0);
alignstatustopch0 : out std_logic_vector(0 downto 0);
alignstatussync0topch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch0 : out std_logic_vector(0 downto 0);
cgcomprddalltopch0 : out std_logic_vector(0 downto 0);
cgcompwralltopch0 : out std_logic_vector(0 downto 0);
delcondmet0topch0 : out std_logic_vector(0 downto 0);
insertincomplete0topch0 : out std_logic_vector(0 downto 0);
fifoovr0topch0 : out std_logic_vector(0 downto 0);
latencycomp0topch0 : out std_logic_vector(0 downto 0);
rxdatarstopch0 : out std_logic_vector(7 downto 0);
rxctlrstopch0 : out std_logic_vector(0 downto 0);
rdenablesyncch2 : in std_logic_vector(0 downto 0);
txdatatcch2 : in std_logic_vector(7 downto 0);
txctltcch2 : in std_logic_vector(0 downto 0);
syncstatusch2 : in std_logic_vector(0 downto 0);
rdalignch2 : in std_logic_vector(1 downto 0);
aligndetsyncch2 : in std_logic_vector(1 downto 0);
fifordinch2 : in std_logic_vector(0 downto 0);
alignstatussyncch2 : in std_logic_vector(0 downto 0);
cgcomprddinch2 : in std_logic_vector(1 downto 0);
cgcompwrinch2 : in std_logic_vector(1 downto 0);
delcondmetinch2 : in std_logic_vector(0 downto 0);
fifoovrinch2 : in std_logic_vector(0 downto 0);
latencycompinch2 : in std_logic_vector(0 downto 0);
insertincompleteinch2 : in std_logic_vector(0 downto 0);
decdatach2 : in std_logic_vector(7 downto 0);
decctlch2 : in std_logic_vector(0 downto 0);
decdatavalidch2 : in std_logic_vector(0 downto 0);
runningdispch2 : in std_logic_vector(1 downto 0);
txdatatsch2 : out std_logic_vector(7 downto 0);
txctltsch2 : out std_logic_vector(0 downto 0);
fiforstrdqdch2 : out std_logic_vector(0 downto 0);
endskwqdch2 : out std_logic_vector(0 downto 0);
endskwrdptrsch2 : out std_logic_vector(0 downto 0);
alignstatusch2 : out std_logic_vector(0 downto 0);
alignstatussync0ch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch2 : out std_logic_vector(0 downto 0);
cgcomprddallch2 : out std_logic_vector(0 downto 0);
cgcompwrallch2 : out std_logic_vector(0 downto 0);
delcondmet0ch2 : out std_logic_vector(0 downto 0);
insertincomplete0ch2 : out std_logic_vector(0 downto 0);
fifoovr0ch2 : out std_logic_vector(0 downto 0);
latencycomp0ch2 : out std_logic_vector(0 downto 0);
rxdatarsch2 : out std_logic_vector(7 downto 0);
rxctlrsch2 : out std_logic_vector(0 downto 0);
rdenablesyncch1 : in std_logic_vector(0 downto 0);
txdatatcch1 : in std_logic_vector(7 downto 0);
txctltcch1 : in std_logic_vector(0 downto 0);
syncstatusch1 : in std_logic_vector(0 downto 0);
rdalignch1 : in std_logic_vector(1 downto 0);
aligndetsyncch1 : in std_logic_vector(1 downto 0);
fifordinch1 : in std_logic_vector(0 downto 0);
alignstatussyncch1 : in std_logic_vector(0 downto 0);
cgcomprddinch1 : in std_logic_vector(1 downto 0);
cgcompwrinch1 : in std_logic_vector(1 downto 0);
delcondmetinch1 : in std_logic_vector(0 downto 0);
fifoovrinch1 : in std_logic_vector(0 downto 0);
latencycompinch1 : in std_logic_vector(0 downto 0);
insertincompleteinch1 : in std_logic_vector(0 downto 0);
decdatach1 : in std_logic_vector(7 downto 0);
decctlch1 : in std_logic_vector(0 downto 0);
decdatavalidch1 : in std_logic_vector(0 downto 0);
runningdispch1 : in std_logic_vector(1 downto 0);
txdatatsch1 : out std_logic_vector(7 downto 0);
txctltsch1 : out std_logic_vector(0 downto 0);
fiforstrdqdch1 : out std_logic_vector(0 downto 0);
endskwqdch1 : out std_logic_vector(0 downto 0);
endskwrdptrsch1 : out std_logic_vector(0 downto 0);
alignstatusch1 : out std_logic_vector(0 downto 0);
alignstatussync0ch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch1 : out std_logic_vector(0 downto 0);
cgcomprddallch1 : out std_logic_vector(0 downto 0);
cgcompwrallch1 : out std_logic_vector(0 downto 0);
delcondmet0ch1 : out std_logic_vector(0 downto 0);
insertincomplete0ch1 : out std_logic_vector(0 downto 0);
fifoovr0ch1 : out std_logic_vector(0 downto 0);
latencycomp0ch1 : out std_logic_vector(0 downto 0);
rxdatarsch1 : out std_logic_vector(7 downto 0);
rxctlrsch1 : out std_logic_vector(0 downto 0);
rdenablesyncch0 : in std_logic_vector(0 downto 0);
txdatatcch0 : in std_logic_vector(7 downto 0);
txctltcch0 : in std_logic_vector(0 downto 0);
syncstatusch0 : in std_logic_vector(0 downto 0);
rdalignch0 : in std_logic_vector(1 downto 0);
aligndetsyncch0 : in std_logic_vector(1 downto 0);
fifordinch0 : in std_logic_vector(0 downto 0);
alignstatussyncch0 : in std_logic_vector(0 downto 0);
cgcomprddinch0 : in std_logic_vector(1 downto 0);
cgcompwrinch0 : in std_logic_vector(1 downto 0);
delcondmetinch0 : in std_logic_vector(0 downto 0);
fifoovrinch0 : in std_logic_vector(0 downto 0);
latencycompinch0 : in std_logic_vector(0 downto 0);
insertincompleteinch0 : in std_logic_vector(0 downto 0);
decdatach0 : in std_logic_vector(7 downto 0);
decctlch0 : in std_logic_vector(0 downto 0);
decdatavalidch0 : in std_logic_vector(0 downto 0);
runningdispch0 : in std_logic_vector(1 downto 0);
txdatatsch0 : out std_logic_vector(7 downto 0);
txctltsch0 : out std_logic_vector(0 downto 0);
fiforstrdqdch0 : out std_logic_vector(0 downto 0);
endskwqdch0 : out std_logic_vector(0 downto 0);
endskwrdptrsch0 : out std_logic_vector(0 downto 0);
alignstatusch0 : out std_logic_vector(0 downto 0);
alignstatussync0ch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch0 : out std_logic_vector(0 downto 0);
cgcomprddallch0 : out std_logic_vector(0 downto 0);
cgcompwrallch0 : out std_logic_vector(0 downto 0);
delcondmet0ch0 : out std_logic_vector(0 downto 0);
insertincomplete0ch0 : out std_logic_vector(0 downto 0);
fifoovr0ch0 : out std_logic_vector(0 downto 0);
latencycomp0ch0 : out std_logic_vector(0 downto 0);
rxdatarsch0 : out std_logic_vector(7 downto 0);
rxctlrsch0 : out std_logic_vector(0 downto 0);
rdenablesyncbotch2 : in std_logic_vector(0 downto 0);
txdatatcbotch2 : in std_logic_vector(7 downto 0);
txctltcbotch2 : in std_logic_vector(0 downto 0);
syncstatusbotch2 : in std_logic_vector(0 downto 0);
rdalignbotch2 : in std_logic_vector(1 downto 0);
aligndetsyncbotch2 : in std_logic_vector(1 downto 0);
fifordinbotch2 : in std_logic_vector(0 downto 0);
alignstatussyncbotch2 : in std_logic_vector(0 downto 0);
cgcomprddinbotch2 : in std_logic_vector(1 downto 0);
cgcompwrinbotch2 : in std_logic_vector(1 downto 0);
delcondmetinbotch2 : in std_logic_vector(0 downto 0);
fifoovrinbotch2 : in std_logic_vector(0 downto 0);
latencycompinbotch2 : in std_logic_vector(0 downto 0);
insertincompleteinbotch2 : in std_logic_vector(0 downto 0);
decdatabotch2 : in std_logic_vector(7 downto 0);
decctlbotch2 : in std_logic_vector(0 downto 0);
decdatavalidbotch2 : in std_logic_vector(0 downto 0);
runningdispbotch2 : in std_logic_vector(1 downto 0);
txdatatsbotch2 : out std_logic_vector(7 downto 0);
txctltsbotch2 : out std_logic_vector(0 downto 0);
fiforstrdqdbotch2 : out std_logic_vector(0 downto 0);
endskwqdbotch2 : out std_logic_vector(0 downto 0);
endskwrdptrsbotch2 : out std_logic_vector(0 downto 0);
alignstatusbotch2 : out std_logic_vector(0 downto 0);
alignstatussync0botch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0botch2 : out std_logic_vector(0 downto 0);
cgcomprddallbotch2 : out std_logic_vector(0 downto 0);
cgcompwrallbotch2 : out std_logic_vector(0 downto 0);
delcondmet0botch2 : out std_logic_vector(0 downto 0);
insertincomplete0botch2 : out std_logic_vector(0 downto 0);
fifoovr0botch2 : out std_logic_vector(0 downto 0);
latencycomp0botch2 : out std_logic_vector(0 downto 0);
rxdatarsbotch2 : out std_logic_vector(7 downto 0);
rxctlrsbotch2 : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_pcs_aggregate_encrypted
generic map (
xaui_sm_operation => xaui_sm_operation,
dskw_sm_operation => dskw_sm_operation,
data_agg_bonding => data_agg_bonding,
prot_mode_tx => prot_mode_tx,
pcs_dw_datapath => pcs_dw_datapath,
dskw_control => dskw_control,
refclkdig_sel => refclkdig_sel
)
port map (
refclkdig => refclkdig,
scanmoden => scanmoden,
scanshiftn => scanshiftn,
txpmaclk => txpmaclk,
rcvdclkch0 => rcvdclkch0,
rcvdclkch1 => rcvdclkch1,
hardrst => hardrst,
txpcsrst => txpcsrst,
rxpcsrst => rxpcsrst,
dprioagg => dprioagg,
rcvdclkout => rcvdclkout,
rcvdclkouttop => rcvdclkouttop,
rcvdclkoutbot => rcvdclkoutbot,
rdenablesynctopch1 => rdenablesynctopch1,
txdatatctopch1 => txdatatctopch1,
txctltctopch1 => txctltctopch1,
syncstatustopch1 => syncstatustopch1,
rdaligntopch1 => rdaligntopch1,
aligndetsynctopch1 => aligndetsynctopch1,
fifordintopch1 => fifordintopch1,
alignstatussynctopch1 => alignstatussynctopch1,
cgcomprddintopch1 => cgcomprddintopch1,
cgcompwrintopch1 => cgcompwrintopch1,
delcondmetintopch1 => delcondmetintopch1,
fifoovrintopch1 => fifoovrintopch1,
latencycompintopch1 => latencycompintopch1,
insertincompleteintopch1 => insertincompleteintopch1,
decdatatopch1 => decdatatopch1,
decctltopch1 => decctltopch1,
decdatavalidtopch1 => decdatavalidtopch1,
runningdisptopch1 => runningdisptopch1,
txdatatstopch1 => txdatatstopch1,
txctltstopch1 => txctltstopch1,
fiforstrdqdtopch1 => fiforstrdqdtopch1,
endskwqdtopch1 => endskwqdtopch1,
endskwrdptrstopch1 => endskwrdptrstopch1,
alignstatustopch1 => alignstatustopch1,
alignstatussync0topch1 => alignstatussync0topch1,
fifordoutcomp0topch1 => fifordoutcomp0topch1,
cgcomprddalltopch1 => cgcomprddalltopch1,
cgcompwralltopch1 => cgcompwralltopch1,
delcondmet0topch1 => delcondmet0topch1,
insertincomplete0topch1 => insertincomplete0topch1,
fifoovr0topch1 => fifoovr0topch1,
latencycomp0topch1 => latencycomp0topch1,
rxdatarstopch1 => rxdatarstopch1,
rxctlrstopch1 => rxctlrstopch1,
rdenablesynctopch0 => rdenablesynctopch0,
txdatatctopch0 => txdatatctopch0,
txctltctopch0 => txctltctopch0,
syncstatustopch0 => syncstatustopch0,
rdaligntopch0 => rdaligntopch0,
aligndetsynctopch0 => aligndetsynctopch0,
fifordintopch0 => fifordintopch0,
alignstatussynctopch0 => alignstatussynctopch0,
cgcomprddintopch0 => cgcomprddintopch0,
cgcompwrintopch0 => cgcompwrintopch0,
delcondmetintopch0 => delcondmetintopch0,
fifoovrintopch0 => fifoovrintopch0,
latencycompintopch0 => latencycompintopch0,
insertincompleteintopch0 => insertincompleteintopch0,
decdatatopch0 => decdatatopch0,
decctltopch0 => decctltopch0,
decdatavalidtopch0 => decdatavalidtopch0,
runningdisptopch0 => runningdisptopch0,
txdatatstopch0 => txdatatstopch0,
txctltstopch0 => txctltstopch0,
fiforstrdqdtopch0 => fiforstrdqdtopch0,
endskwqdtopch0 => endskwqdtopch0,
endskwrdptrstopch0 => endskwrdptrstopch0,
alignstatustopch0 => alignstatustopch0,
alignstatussync0topch0 => alignstatussync0topch0,
fifordoutcomp0topch0 => fifordoutcomp0topch0,
cgcomprddalltopch0 => cgcomprddalltopch0,
cgcompwralltopch0 => cgcompwralltopch0,
delcondmet0topch0 => delcondmet0topch0,
insertincomplete0topch0 => insertincomplete0topch0,
fifoovr0topch0 => fifoovr0topch0,
latencycomp0topch0 => latencycomp0topch0,
rxdatarstopch0 => rxdatarstopch0,
rxctlrstopch0 => rxctlrstopch0,
rdenablesyncch2 => rdenablesyncch2,
txdatatcch2 => txdatatcch2,
txctltcch2 => txctltcch2,
syncstatusch2 => syncstatusch2,
rdalignch2 => rdalignch2,
aligndetsyncch2 => aligndetsyncch2,
fifordinch2 => fifordinch2,
alignstatussyncch2 => alignstatussyncch2,
cgcomprddinch2 => cgcomprddinch2,
cgcompwrinch2 => cgcompwrinch2,
delcondmetinch2 => delcondmetinch2,
fifoovrinch2 => fifoovrinch2,
latencycompinch2 => latencycompinch2,
insertincompleteinch2 => insertincompleteinch2,
decdatach2 => decdatach2,
decctlch2 => decctlch2,
decdatavalidch2 => decdatavalidch2,
runningdispch2 => runningdispch2,
txdatatsch2 => txdatatsch2,
txctltsch2 => txctltsch2,
fiforstrdqdch2 => fiforstrdqdch2,
endskwqdch2 => endskwqdch2,
endskwrdptrsch2 => endskwrdptrsch2,
alignstatusch2 => alignstatusch2,
alignstatussync0ch2 => alignstatussync0ch2,
fifordoutcomp0ch2 => fifordoutcomp0ch2,
cgcomprddallch2 => cgcomprddallch2,
cgcompwrallch2 => cgcompwrallch2,
delcondmet0ch2 => delcondmet0ch2,
insertincomplete0ch2 => insertincomplete0ch2,
fifoovr0ch2 => fifoovr0ch2,
latencycomp0ch2 => latencycomp0ch2,
rxdatarsch2 => rxdatarsch2,
rxctlrsch2 => rxctlrsch2,
rdenablesyncch1 => rdenablesyncch1,
txdatatcch1 => txdatatcch1,
txctltcch1 => txctltcch1,
syncstatusch1 => syncstatusch1,
rdalignch1 => rdalignch1,
aligndetsyncch1 => aligndetsyncch1,
fifordinch1 => fifordinch1,
alignstatussyncch1 => alignstatussyncch1,
cgcomprddinch1 => cgcomprddinch1,
cgcompwrinch1 => cgcompwrinch1,
delcondmetinch1 => delcondmetinch1,
fifoovrinch1 => fifoovrinch1,
latencycompinch1 => latencycompinch1,
insertincompleteinch1 => insertincompleteinch1,
decdatach1 => decdatach1,
decctlch1 => decctlch1,
decdatavalidch1 => decdatavalidch1,
runningdispch1 => runningdispch1,
txdatatsch1 => txdatatsch1,
txctltsch1 => txctltsch1,
fiforstrdqdch1 => fiforstrdqdch1,
endskwqdch1 => endskwqdch1,
endskwrdptrsch1 => endskwrdptrsch1,
alignstatusch1 => alignstatusch1,
alignstatussync0ch1 => alignstatussync0ch1,
fifordoutcomp0ch1 => fifordoutcomp0ch1,
cgcomprddallch1 => cgcomprddallch1,
cgcompwrallch1 => cgcompwrallch1,
delcondmet0ch1 => delcondmet0ch1,
insertincomplete0ch1 => insertincomplete0ch1,
fifoovr0ch1 => fifoovr0ch1,
latencycomp0ch1 => latencycomp0ch1,
rxdatarsch1 => rxdatarsch1,
rxctlrsch1 => rxctlrsch1,
rdenablesyncch0 => rdenablesyncch0,
txdatatcch0 => txdatatcch0,
txctltcch0 => txctltcch0,
syncstatusch0 => syncstatusch0,
rdalignch0 => rdalignch0,
aligndetsyncch0 => aligndetsyncch0,
fifordinch0 => fifordinch0,
alignstatussyncch0 => alignstatussyncch0,
cgcomprddinch0 => cgcomprddinch0,
cgcompwrinch0 => cgcompwrinch0,
delcondmetinch0 => delcondmetinch0,
fifoovrinch0 => fifoovrinch0,
latencycompinch0 => latencycompinch0,
insertincompleteinch0 => insertincompleteinch0,
decdatach0 => decdatach0,
decctlch0 => decctlch0,
decdatavalidch0 => decdatavalidch0,
runningdispch0 => runningdispch0,
txdatatsch0 => txdatatsch0,
txctltsch0 => txctltsch0,
fiforstrdqdch0 => fiforstrdqdch0,
endskwqdch0 => endskwqdch0,
endskwrdptrsch0 => endskwrdptrsch0,
alignstatusch0 => alignstatusch0,
alignstatussync0ch0 => alignstatussync0ch0,
fifordoutcomp0ch0 => fifordoutcomp0ch0,
cgcomprddallch0 => cgcomprddallch0,
cgcompwrallch0 => cgcompwrallch0,
delcondmet0ch0 => delcondmet0ch0,
insertincomplete0ch0 => insertincomplete0ch0,
fifoovr0ch0 => fifoovr0ch0,
latencycomp0ch0 => latencycomp0ch0,
rxdatarsch0 => rxdatarsch0,
rxctlrsch0 => rxctlrsch0,
rdenablesyncbotch2 => rdenablesyncbotch2,
txdatatcbotch2 => txdatatcbotch2,
txctltcbotch2 => txctltcbotch2,
syncstatusbotch2 => syncstatusbotch2,
rdalignbotch2 => rdalignbotch2,
aligndetsyncbotch2 => aligndetsyncbotch2,
fifordinbotch2 => fifordinbotch2,
alignstatussyncbotch2 => alignstatussyncbotch2,
cgcomprddinbotch2 => cgcomprddinbotch2,
cgcompwrinbotch2 => cgcompwrinbotch2,
delcondmetinbotch2 => delcondmetinbotch2,
fifoovrinbotch2 => fifoovrinbotch2,
latencycompinbotch2 => latencycompinbotch2,
insertincompleteinbotch2 => insertincompleteinbotch2,
decdatabotch2 => decdatabotch2,
decctlbotch2 => decctlbotch2,
decdatavalidbotch2 => decdatavalidbotch2,
runningdispbotch2 => runningdispbotch2,
txdatatsbotch2 => txdatatsbotch2,
txctltsbotch2 => txctltsbotch2,
fiforstrdqdbotch2 => fiforstrdqdbotch2,
endskwqdbotch2 => endskwqdbotch2,
endskwrdptrsbotch2 => endskwrdptrsbotch2,
alignstatusbotch2 => alignstatusbotch2,
alignstatussync0botch2 => alignstatussync0botch2,
fifordoutcomp0botch2 => fifordoutcomp0botch2,
cgcomprddallbotch2 => cgcomprddallbotch2,
cgcompwrallbotch2 => cgcompwrallbotch2,
delcondmet0botch2 => delcondmet0botch2,
insertincomplete0botch2 => insertincomplete0botch2,
fifoovr0botch2 => fifoovr0botch2,
latencycomp0botch2 => latencycomp0botch2,
rxdatarsbotch2 => rxdatarsbotch2,
rxctlrsbotch2 => rxctlrsbotch2
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_rx_pcs is
generic (
prot_mode : string := "gige";
tx_rx_parallel_loopback : string := "dis_plpbk";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
polarity_inversion : string := "dis_pol_inv";
wa_pd : string := "wa_pd_10";
wa_pd_data : bit_vector := B"0000000000000000000000000000000000000000";
wa_boundary_lock_ctrl : string := "bit_slip";
wa_pld_controlled : string := "dis_pld_ctrl";
wa_sync_sm_ctrl : string := "gige_sync_sm";
wa_rknumber_data : bit_vector := B"00000000";
wa_renumber_data : bit_vector := B"000000";
wa_rgnumber_data : bit_vector := B"00000000";
wa_rosnumber_data : bit_vector := B"00";
wa_kchar : string := "dis_kchar";
wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm";
wa_clk_slip_spacing : string := "min_clk_slip_spacing";
wa_clk_slip_spacing_data : bit_vector := B"0000010000";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
deskew_pattern : bit_vector := B"1101101000";
deskew_prog_pattern_only : string := "en_deskew_prog_pat_only";
rate_match : string := "dis_rm";
eightb_tenb_decoder : string := "dis_8b10b";
err_flags_sel : string := "err_flags_wa";
polinv_8b10b_dec : string := "dis_polinv_8b10b_dec";
eightbtenb_decoder_output_sel : string := "data_8b10b_decoder";
invalid_code_flag_only : string := "dis_invalid_code_only";
auto_error_replacement : string := "dis_err_replace";
pad_or_edb_error_replace : string := "replace_edb";
byte_deserializer : string := "dis_bds";
byte_order : string := "dis_bo";
re_bo_on_wa : string := "dis_re_bo_on_wa";
bo_pattern : bit_vector := B"00000000000000000000";
bo_pad : bit_vector := B"0000000000";
phase_compensation_fifo : string := "low_latency";
prbs_ver : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_ver : string := "dis_bist";
cdr_ctrl : string := "dis_cdr_ctrl";
cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask";
wait_cnt : bit_vector := B"00000000";
mask_cnt : bit_vector := B"1111111111";
auto_deassert_pc_rst_cnt_data : bit_vector := B"00000";
auto_pc_en_cnt_data : bit_vector := B"0000000";
eidle_entry_sd : string := "dis_eidle_sd";
eidle_entry_eios : string := "dis_eidle_eios";
eidle_entry_iei : string := "dis_eidle_iei";
rx_rcvd_clk : string := "rcvd_clk_rcvd_clk";
rx_clk1 : string := "rcvd_clk_clk1";
rx_clk2 : string := "rcvd_clk_clk2";
rx_rd_clk : string := "pld_rx_clk";
dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo";
comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
agg_block_sel : string := "same_smrt_pack";
test_bus_sel : string := "test_bus_sel";
wa_rvnumber_data : bit_vector := B"0000000000000";
ctrl_plane_bonding_compensation : string := "dis_compensation";
clock_gate_rx : string := "dis_clk_gating";
prbs_ver_clr_flag : string := "dis_prbs_clr_flag";
hip_mode : string := "dis_hip";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
ctrl_plane_bonding_consumption : string := "individual";
pma_done_count : bit_vector := B"000000000000000000";
test_mode : string := "prbs";
bist_ver_clr_flag : string := "dis_bist_clr_flag";
wa_disp_err_flag : string := "dis_disp_err_flag";
wait_for_phfifo_cnt_data : bit_vector := B"000000";
runlength_check : string := "en_runlength_sw";
test_bus_sel_val : bit_vector := B"0000";
runlength_val : bit_vector := B"000000";
force_signal_detect : string := "en_force_signal_detect";
deskew : string := "dis_deskew";
rx_wr_clk : string := "rx_clk2_div_1_2_4";
rx_clk_free_running : string := "en_rx_clk_free_run";
rx_pcs_urst : string := "en_rx_pcs_urst";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
pipe_if_enable : string := "dis_pipe_rx";
pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
ibm_invalid_code : string := "dis_ibm_invalid_code";
channel_number : string := "int";
rx_refclk : string := "dis_refclk_sel"
);
port (
hrdrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
rmfifouserrst : in std_logic_vector(0 downto 0);
phfifouserrst : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
enablecommadetect : in std_logic_vector(0 downto 0);
a1a2size : in std_logic_vector(0 downto 0);
bitslip : in std_logic_vector(0 downto 0);
rmfiforeadenable : in std_logic_vector(0 downto 0);
rmfifowriteenable : in std_logic_vector(0 downto 0);
pldrxclk : in std_logic_vector(0 downto 0);
softresetrclk1 : out std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
bitreversalenable : in std_logic_vector(0 downto 0);
bytereversalenable : in std_logic_vector(0 downto 0);
rcvdclkpma : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(19 downto 0);
sigdetfrompma : in std_logic_vector(0 downto 0);
fiforstrdqd : in std_logic_vector(0 downto 0);
endskwqd : in std_logic_vector(0 downto 0);
endskwrdptrs : in std_logic_vector(0 downto 0);
alignstatus : in std_logic_vector(0 downto 0);
fiforstrdqdtoporbot : in std_logic_vector(0 downto 0);
endskwqdtoporbot : in std_logic_vector(0 downto 0);
endskwrdptrstoporbot : in std_logic_vector(0 downto 0);
alignstatustoporbot : in std_logic_vector(0 downto 0);
datafrinaggblock : in std_logic_vector(7 downto 0);
ctrlfromaggblock : in std_logic_vector(0 downto 0);
rxdatarstoporbot : in std_logic_vector(7 downto 0);
rxcontrolrstoporbot : in std_logic_vector(0 downto 0);
rcvdclk0pma : in std_logic_vector(0 downto 0);
parallelloopback : in std_logic_vector(19 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
byteorder : in std_logic_vector(0 downto 0);
pxfifowrdisable : in std_logic_vector(0 downto 0);
pcfifordenable : in std_logic_vector(0 downto 0);
pmatestbus : in std_logic_vector(7 downto 0);
encodertestbus : in std_logic_vector(9 downto 0);
txctrltestbus : in std_logic_vector(9 downto 0);
phystatusinternal : in std_logic_vector(0 downto 0);
rxvalidinternal : in std_logic_vector(0 downto 0);
rxstatusinternal : in std_logic_vector(2 downto 0);
phystatuspcsgen3 : in std_logic_vector(0 downto 0);
rxvalidpcsgen3 : in std_logic_vector(0 downto 0);
rxstatuspcsgen3 : in std_logic_vector(2 downto 0);
rxdatavalidpcsgen3 : in std_logic_vector(3 downto 0);
rxblkstartpcsgen3 : in std_logic_vector(3 downto 0);
rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0);
rxdatapcsgen3 : in std_logic_vector(63 downto 0);
pipepowerdown : in std_logic_vector(1 downto 0);
rateswitchcontrol : in std_logic_vector(0 downto 0);
gen2ngen1 : in std_logic_vector(0 downto 0);
gen2ngen1bundle : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
pipeloopbk : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
txdiv2syncoutpipeup : in std_logic_vector(0 downto 0);
fifoselectoutpipeup : in std_logic_vector(0 downto 0);
txwrenableoutpipeup : in std_logic_vector(0 downto 0);
txrdenableoutpipeup : in std_logic_vector(0 downto 0);
txdiv2syncoutpipedown : in std_logic_vector(0 downto 0);
fifoselectoutpipedown : in std_logic_vector(0 downto 0);
txwrenableoutpipedown : in std_logic_vector(0 downto 0);
txrdenableoutpipedown : in std_logic_vector(0 downto 0);
alignstatussync0 : in std_logic_vector(0 downto 0);
rmfifordincomp0 : in std_logic_vector(0 downto 0);
cgcomprddall : in std_logic_vector(0 downto 0);
cgcompwrall : in std_logic_vector(0 downto 0);
delcondmet0 : in std_logic_vector(0 downto 0);
fifoovr0 : in std_logic_vector(0 downto 0);
latencycomp0 : in std_logic_vector(0 downto 0);
insertincomplete0 : in std_logic_vector(0 downto 0);
alignstatussync0toporbot : in std_logic_vector(0 downto 0);
fifordincomp0toporbot : in std_logic_vector(0 downto 0);
cgcomprddalltoporbot : in std_logic_vector(0 downto 0);
cgcompwralltoporbot : in std_logic_vector(0 downto 0);
delcondmet0toporbot : in std_logic_vector(0 downto 0);
fifoovr0toporbot : in std_logic_vector(0 downto 0);
latencycomp0toporbot : in std_logic_vector(0 downto 0);
insertincomplete0toporbot : in std_logic_vector(0 downto 0);
alignstatussync : out std_logic_vector(0 downto 0);
fifordoutcomp : out std_logic_vector(0 downto 0);
cgcomprddout : out std_logic_vector(1 downto 0);
cgcompwrout : out std_logic_vector(1 downto 0);
delcondmetout : out std_logic_vector(0 downto 0);
fifoovrout : out std_logic_vector(0 downto 0);
latencycompout : out std_logic_vector(0 downto 0);
insertincompleteout : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(63 downto 0);
parallelrevloopback : out std_logic_vector(19 downto 0);
clocktopld : out std_logic_vector(0 downto 0);
bisterr : out std_logic_vector(0 downto 0);
clk2b : out std_logic_vector(0 downto 0);
rcvdclkpmab : out std_logic_vector(0 downto 0);
syncstatus : out std_logic_vector(0 downto 0);
decoderdatavalid : out std_logic_vector(0 downto 0);
decoderdata : out std_logic_vector(7 downto 0);
decoderctrl : out std_logic_vector(0 downto 0);
runningdisparity : out std_logic_vector(1 downto 0);
selftestdone : out std_logic_vector(0 downto 0);
selftesterr : out std_logic_vector(0 downto 0);
errdata : out std_logic_vector(15 downto 0);
errctrl : out std_logic_vector(1 downto 0);
prbsdone : out std_logic_vector(0 downto 0);
prbserrlt : out std_logic_vector(0 downto 0);
signaldetectout : out std_logic_vector(0 downto 0);
aligndetsync : out std_logic_vector(1 downto 0);
rdalign : out std_logic_vector(1 downto 0);
bistdone : out std_logic_vector(0 downto 0);
runlengthviolation : out std_logic_vector(0 downto 0);
rlvlt : out std_logic_vector(0 downto 0);
rmfifopartialfull : out std_logic_vector(0 downto 0);
rmfifofull : out std_logic_vector(0 downto 0);
rmfifopartialempty : out std_logic_vector(0 downto 0);
rmfifoempty : out std_logic_vector(0 downto 0);
pcfifofull : out std_logic_vector(0 downto 0);
pcfifoempty : out std_logic_vector(0 downto 0);
a1a2k1k2flag : out std_logic_vector(3 downto 0);
byteordflag : out std_logic_vector(0 downto 0);
rxpipeclk : out std_logic_vector(0 downto 0);
channeltestbusout : out std_logic_vector(9 downto 0);
rxpipesoftreset : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
pipedata : out std_logic_vector(63 downto 0);
rxdatavalid : out std_logic_vector(3 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
speedchange : out std_logic_vector(0 downto 0);
eidledetected : out std_logic_vector(0 downto 0);
wordalignboundary : out std_logic_vector(4 downto 0);
rxclkslip : out std_logic_vector(0 downto 0);
eidleexit : out std_logic_vector(0 downto 0);
earlyeios : out std_logic_vector(0 downto 0);
ltr : out std_logic_vector(0 downto 0);
pcswrapbackin : in std_logic_vector(69 downto 0);
rxdivsyncinchnlup : in std_logic_vector(1 downto 0);
rxdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
rxweinchnlup : in std_logic_vector(1 downto 0);
rxweinchnldown : in std_logic_vector(1 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
configselinchnlup : in std_logic_vector(0 downto 0);
configselinchnldown : in std_logic_vector(0 downto 0);
speedchangeinchnlup : in std_logic_vector(0 downto 0);
speedchangeinchnldown : in std_logic_vector(0 downto 0);
pcieswitch : out std_logic_vector(0 downto 0);
rxdivsyncoutchnlup : out std_logic_vector(1 downto 0);
rxweoutchnlup : out std_logic_vector(1 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
resetpcptrsoutchnlup : out std_logic_vector(0 downto 0);
speedchangeoutchnlup : out std_logic_vector(0 downto 0);
configseloutchnlup : out std_logic_vector(0 downto 0);
rxdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rxweoutchnldown : out std_logic_vector(1 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsoutchnldown : out std_logic_vector(0 downto 0);
speedchangeoutchnldown : out std_logic_vector(0 downto 0);
configseloutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsinchnluppipe : out std_logic_vector(0 downto 0);
resetpcptrsinchnldownpipe : out std_logic_vector(0 downto 0);
speedchangeinchnluppipe : out std_logic_vector(0 downto 0);
speedchangeinchnldownpipe : out std_logic_vector(0 downto 0);
disablepcfifobyteserdes : out std_logic_vector(0 downto 0);
resetpcptrs : out std_logic_vector(0 downto 0);
rcvdclkagg : in std_logic_vector(0 downto 0);
rcvdclkaggtoporbot : in std_logic_vector(0 downto 0);
dispcbytegen3 : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txfifordclkraw : in std_logic_vector(0 downto 0);
resetpcptrsgen3 : in std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_rx_pcs;
architecture behavior of stratixv_hssi_8g_rx_pcs is
component stratixv_hssi_8g_rx_pcs_encrypted
generic (
prot_mode : string := "gige";
tx_rx_parallel_loopback : string := "dis_plpbk";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
polarity_inversion : string := "dis_pol_inv";
wa_pd : string := "wa_pd_10";
wa_pd_data : bit_vector := B"0000000000000000000000000000000000000000";
wa_boundary_lock_ctrl : string := "bit_slip";
wa_pld_controlled : string := "dis_pld_ctrl";
wa_sync_sm_ctrl : string := "gige_sync_sm";
wa_rknumber_data : bit_vector := B"00000000";
wa_renumber_data : bit_vector := B"000000";
wa_rgnumber_data : bit_vector := B"00000000";
wa_rosnumber_data : bit_vector := B"00";
wa_kchar : string := "dis_kchar";
wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm";
wa_clk_slip_spacing : string := "min_clk_slip_spacing";
wa_clk_slip_spacing_data : bit_vector := B"0000010000";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
deskew_pattern : bit_vector := B"1101101000";
deskew_prog_pattern_only : string := "en_deskew_prog_pat_only";
rate_match : string := "dis_rm";
eightb_tenb_decoder : string := "dis_8b10b";
err_flags_sel : string := "err_flags_wa";
polinv_8b10b_dec : string := "dis_polinv_8b10b_dec";
eightbtenb_decoder_output_sel : string := "data_8b10b_decoder";
invalid_code_flag_only : string := "dis_invalid_code_only";
auto_error_replacement : string := "dis_err_replace";
pad_or_edb_error_replace : string := "replace_edb";
byte_deserializer : string := "dis_bds";
byte_order : string := "dis_bo";
re_bo_on_wa : string := "dis_re_bo_on_wa";
bo_pattern : bit_vector := B"00000000000000000000";
bo_pad : bit_vector := B"0000000000";
phase_compensation_fifo : string := "low_latency";
prbs_ver : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_ver : string := "dis_bist";
cdr_ctrl : string := "dis_cdr_ctrl";
cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask";
wait_cnt : bit_vector := B"00000000";
mask_cnt : bit_vector := B"1111111111";
auto_deassert_pc_rst_cnt_data : bit_vector := B"00000";
auto_pc_en_cnt_data : bit_vector := B"0000000";
eidle_entry_sd : string := "dis_eidle_sd";
eidle_entry_eios : string := "dis_eidle_eios";
eidle_entry_iei : string := "dis_eidle_iei";
rx_rcvd_clk : string := "rcvd_clk_rcvd_clk";
rx_clk1 : string := "rcvd_clk_clk1";
rx_clk2 : string := "rcvd_clk_clk2";
rx_rd_clk : string := "pld_rx_clk";
dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo";
comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
agg_block_sel : string := "same_smrt_pack";
test_bus_sel : string := "test_bus_sel";
wa_rvnumber_data : bit_vector := B"0000000000000";
ctrl_plane_bonding_compensation : string := "dis_compensation";
clock_gate_rx : string := "dis_clk_gating";
prbs_ver_clr_flag : string := "dis_prbs_clr_flag";
hip_mode : string := "dis_hip";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
ctrl_plane_bonding_consumption : string := "individual";
pma_done_count : bit_vector := B"000000000000000000";
test_mode : string := "prbs";
bist_ver_clr_flag : string := "dis_bist_clr_flag";
wa_disp_err_flag : string := "dis_disp_err_flag";
wait_for_phfifo_cnt_data : bit_vector := B"000000";
runlength_check : string := "en_runlength_sw";
test_bus_sel_val : bit_vector := B"0000";
runlength_val : bit_vector := B"000000";
force_signal_detect : string := "en_force_signal_detect";
deskew : string := "dis_deskew";
rx_wr_clk : string := "rx_clk2_div_1_2_4";
rx_clk_free_running : string := "en_rx_clk_free_run";
rx_pcs_urst : string := "en_rx_pcs_urst";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
pipe_if_enable : string := "dis_pipe_rx";
pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
ibm_invalid_code : string := "dis_ibm_invalid_code";
channel_number : string := "int";
rx_refclk : string := "dis_refclk_sel"
);
port (
hrdrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
rmfifouserrst : in std_logic_vector(0 downto 0);
phfifouserrst : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
enablecommadetect : in std_logic_vector(0 downto 0);
a1a2size : in std_logic_vector(0 downto 0);
bitslip : in std_logic_vector(0 downto 0);
rmfiforeadenable : in std_logic_vector(0 downto 0);
rmfifowriteenable : in std_logic_vector(0 downto 0);
pldrxclk : in std_logic_vector(0 downto 0);
softresetrclk1 : out std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
bitreversalenable : in std_logic_vector(0 downto 0);
bytereversalenable : in std_logic_vector(0 downto 0);
rcvdclkpma : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(19 downto 0);
sigdetfrompma : in std_logic_vector(0 downto 0);
fiforstrdqd : in std_logic_vector(0 downto 0);
endskwqd : in std_logic_vector(0 downto 0);
endskwrdptrs : in std_logic_vector(0 downto 0);
alignstatus : in std_logic_vector(0 downto 0);
fiforstrdqdtoporbot : in std_logic_vector(0 downto 0);
endskwqdtoporbot : in std_logic_vector(0 downto 0);
endskwrdptrstoporbot : in std_logic_vector(0 downto 0);
alignstatustoporbot : in std_logic_vector(0 downto 0);
datafrinaggblock : in std_logic_vector(7 downto 0);
ctrlfromaggblock : in std_logic_vector(0 downto 0);
rxdatarstoporbot : in std_logic_vector(7 downto 0);
rxcontrolrstoporbot : in std_logic_vector(0 downto 0);
rcvdclk0pma : in std_logic_vector(0 downto 0);
parallelloopback : in std_logic_vector(19 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
byteorder : in std_logic_vector(0 downto 0);
pxfifowrdisable : in std_logic_vector(0 downto 0);
pcfifordenable : in std_logic_vector(0 downto 0);
pmatestbus : in std_logic_vector(7 downto 0);
encodertestbus : in std_logic_vector(9 downto 0);
txctrltestbus : in std_logic_vector(9 downto 0);
phystatusinternal : in std_logic_vector(0 downto 0);
rxvalidinternal : in std_logic_vector(0 downto 0);
rxstatusinternal : in std_logic_vector(2 downto 0);
phystatuspcsgen3 : in std_logic_vector(0 downto 0);
rxvalidpcsgen3 : in std_logic_vector(0 downto 0);
rxstatuspcsgen3 : in std_logic_vector(2 downto 0);
rxdatavalidpcsgen3 : in std_logic_vector(3 downto 0);
rxblkstartpcsgen3 : in std_logic_vector(3 downto 0);
rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0);
rxdatapcsgen3 : in std_logic_vector(63 downto 0);
pipepowerdown : in std_logic_vector(1 downto 0);
rateswitchcontrol : in std_logic_vector(0 downto 0);
gen2ngen1 : in std_logic_vector(0 downto 0);
gen2ngen1bundle : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
pipeloopbk : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
txdiv2syncoutpipeup : in std_logic_vector(0 downto 0);
fifoselectoutpipeup : in std_logic_vector(0 downto 0);
txwrenableoutpipeup : in std_logic_vector(0 downto 0);
txrdenableoutpipeup : in std_logic_vector(0 downto 0);
txdiv2syncoutpipedown : in std_logic_vector(0 downto 0);
fifoselectoutpipedown : in std_logic_vector(0 downto 0);
txwrenableoutpipedown : in std_logic_vector(0 downto 0);
txrdenableoutpipedown : in std_logic_vector(0 downto 0);
alignstatussync0 : in std_logic_vector(0 downto 0);
rmfifordincomp0 : in std_logic_vector(0 downto 0);
cgcomprddall : in std_logic_vector(0 downto 0);
cgcompwrall : in std_logic_vector(0 downto 0);
delcondmet0 : in std_logic_vector(0 downto 0);
fifoovr0 : in std_logic_vector(0 downto 0);
latencycomp0 : in std_logic_vector(0 downto 0);
insertincomplete0 : in std_logic_vector(0 downto 0);
alignstatussync0toporbot : in std_logic_vector(0 downto 0);
fifordincomp0toporbot : in std_logic_vector(0 downto 0);
cgcomprddalltoporbot : in std_logic_vector(0 downto 0);
cgcompwralltoporbot : in std_logic_vector(0 downto 0);
delcondmet0toporbot : in std_logic_vector(0 downto 0);
fifoovr0toporbot : in std_logic_vector(0 downto 0);
latencycomp0toporbot : in std_logic_vector(0 downto 0);
insertincomplete0toporbot : in std_logic_vector(0 downto 0);
alignstatussync : out std_logic_vector(0 downto 0);
fifordoutcomp : out std_logic_vector(0 downto 0);
cgcomprddout : out std_logic_vector(1 downto 0);
cgcompwrout : out std_logic_vector(1 downto 0);
delcondmetout : out std_logic_vector(0 downto 0);
fifoovrout : out std_logic_vector(0 downto 0);
latencycompout : out std_logic_vector(0 downto 0);
insertincompleteout : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(63 downto 0);
parallelrevloopback : out std_logic_vector(19 downto 0);
clocktopld : out std_logic_vector(0 downto 0);
bisterr : out std_logic_vector(0 downto 0);
clk2b : out std_logic_vector(0 downto 0);
rcvdclkpmab : out std_logic_vector(0 downto 0);
syncstatus : out std_logic_vector(0 downto 0);
decoderdatavalid : out std_logic_vector(0 downto 0);
decoderdata : out std_logic_vector(7 downto 0);
decoderctrl : out std_logic_vector(0 downto 0);
runningdisparity : out std_logic_vector(1 downto 0);
selftestdone : out std_logic_vector(0 downto 0);
selftesterr : out std_logic_vector(0 downto 0);
errdata : out std_logic_vector(15 downto 0);
errctrl : out std_logic_vector(1 downto 0);
prbsdone : out std_logic_vector(0 downto 0);
prbserrlt : out std_logic_vector(0 downto 0);
signaldetectout : out std_logic_vector(0 downto 0);
aligndetsync : out std_logic_vector(1 downto 0);
rdalign : out std_logic_vector(1 downto 0);
bistdone : out std_logic_vector(0 downto 0);
runlengthviolation : out std_logic_vector(0 downto 0);
rlvlt : out std_logic_vector(0 downto 0);
rmfifopartialfull : out std_logic_vector(0 downto 0);
rmfifofull : out std_logic_vector(0 downto 0);
rmfifopartialempty : out std_logic_vector(0 downto 0);
rmfifoempty : out std_logic_vector(0 downto 0);
pcfifofull : out std_logic_vector(0 downto 0);
pcfifoempty : out std_logic_vector(0 downto 0);
a1a2k1k2flag : out std_logic_vector(3 downto 0);
byteordflag : out std_logic_vector(0 downto 0);
rxpipeclk : out std_logic_vector(0 downto 0);
channeltestbusout : out std_logic_vector(9 downto 0);
rxpipesoftreset : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
pipedata : out std_logic_vector(63 downto 0);
rxdatavalid : out std_logic_vector(3 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
speedchange : out std_logic_vector(0 downto 0);
eidledetected : out std_logic_vector(0 downto 0);
wordalignboundary : out std_logic_vector(4 downto 0);
rxclkslip : out std_logic_vector(0 downto 0);
eidleexit : out std_logic_vector(0 downto 0);
earlyeios : out std_logic_vector(0 downto 0);
ltr : out std_logic_vector(0 downto 0);
pcswrapbackin : in std_logic_vector(69 downto 0);
rxdivsyncinchnlup : in std_logic_vector(1 downto 0);
rxdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
rxweinchnlup : in std_logic_vector(1 downto 0);
rxweinchnldown : in std_logic_vector(1 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
configselinchnlup : in std_logic_vector(0 downto 0);
configselinchnldown : in std_logic_vector(0 downto 0);
speedchangeinchnlup : in std_logic_vector(0 downto 0);
speedchangeinchnldown : in std_logic_vector(0 downto 0);
pcieswitch : out std_logic_vector(0 downto 0);
rxdivsyncoutchnlup : out std_logic_vector(1 downto 0);
rxweoutchnlup : out std_logic_vector(1 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
resetpcptrsoutchnlup : out std_logic_vector(0 downto 0);
speedchangeoutchnlup : out std_logic_vector(0 downto 0);
configseloutchnlup : out std_logic_vector(0 downto 0);
rxdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rxweoutchnldown : out std_logic_vector(1 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsoutchnldown : out std_logic_vector(0 downto 0);
speedchangeoutchnldown : out std_logic_vector(0 downto 0);
configseloutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsinchnluppipe : out std_logic_vector(0 downto 0);
resetpcptrsinchnldownpipe : out std_logic_vector(0 downto 0);
speedchangeinchnluppipe : out std_logic_vector(0 downto 0);
speedchangeinchnldownpipe : out std_logic_vector(0 downto 0);
disablepcfifobyteserdes : out std_logic_vector(0 downto 0);
resetpcptrs : out std_logic_vector(0 downto 0);
rcvdclkagg : in std_logic_vector(0 downto 0);
rcvdclkaggtoporbot : in std_logic_vector(0 downto 0);
dispcbytegen3 : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txfifordclkraw : in std_logic_vector(0 downto 0);
resetpcptrsgen3 : in std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_rx_pcs_encrypted
generic map (
prot_mode => prot_mode,
tx_rx_parallel_loopback => tx_rx_parallel_loopback,
pma_dw => pma_dw,
pcs_bypass => pcs_bypass,
polarity_inversion => polarity_inversion,
wa_pd => wa_pd,
wa_pd_data => wa_pd_data,
wa_boundary_lock_ctrl => wa_boundary_lock_ctrl,
wa_pld_controlled => wa_pld_controlled,
wa_sync_sm_ctrl => wa_sync_sm_ctrl,
wa_rknumber_data => wa_rknumber_data,
wa_renumber_data => wa_renumber_data,
wa_rgnumber_data => wa_rgnumber_data,
wa_rosnumber_data => wa_rosnumber_data,
wa_kchar => wa_kchar,
wa_det_latency_sync_status_beh => wa_det_latency_sync_status_beh,
wa_clk_slip_spacing => wa_clk_slip_spacing,
wa_clk_slip_spacing_data => wa_clk_slip_spacing_data,
bit_reversal => bit_reversal,
symbol_swap => symbol_swap,
deskew_pattern => deskew_pattern,
deskew_prog_pattern_only => deskew_prog_pattern_only,
rate_match => rate_match,
eightb_tenb_decoder => eightb_tenb_decoder,
err_flags_sel => err_flags_sel,
polinv_8b10b_dec => polinv_8b10b_dec,
eightbtenb_decoder_output_sel => eightbtenb_decoder_output_sel,
invalid_code_flag_only => invalid_code_flag_only,
auto_error_replacement => auto_error_replacement,
pad_or_edb_error_replace => pad_or_edb_error_replace,
byte_deserializer => byte_deserializer,
byte_order => byte_order,
re_bo_on_wa => re_bo_on_wa,
bo_pattern => bo_pattern,
bo_pad => bo_pad,
phase_compensation_fifo => phase_compensation_fifo,
prbs_ver => prbs_ver,
cid_pattern => cid_pattern,
cid_pattern_len => cid_pattern_len,
bist_ver => bist_ver,
cdr_ctrl => cdr_ctrl,
cdr_ctrl_rxvalid_mask => cdr_ctrl_rxvalid_mask,
wait_cnt => wait_cnt,
mask_cnt => mask_cnt,
auto_deassert_pc_rst_cnt_data => auto_deassert_pc_rst_cnt_data,
auto_pc_en_cnt_data => auto_pc_en_cnt_data,
eidle_entry_sd => eidle_entry_sd,
eidle_entry_eios => eidle_entry_eios,
eidle_entry_iei => eidle_entry_iei,
rx_rcvd_clk => rx_rcvd_clk,
rx_clk1 => rx_clk1,
rx_clk2 => rx_clk2,
rx_rd_clk => rx_rd_clk,
dw_one_or_two_symbol_bo => dw_one_or_two_symbol_bo,
comp_fifo_rst_pld_ctrl => comp_fifo_rst_pld_ctrl,
bypass_pipeline_reg => bypass_pipeline_reg,
agg_block_sel => agg_block_sel,
test_bus_sel => test_bus_sel,
wa_rvnumber_data => wa_rvnumber_data,
ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation,
clock_gate_rx => clock_gate_rx,
prbs_ver_clr_flag => prbs_ver_clr_flag,
hip_mode => hip_mode,
ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
pma_done_count => pma_done_count,
test_mode => test_mode,
bist_ver_clr_flag => bist_ver_clr_flag,
wa_disp_err_flag => wa_disp_err_flag,
wait_for_phfifo_cnt_data => wait_for_phfifo_cnt_data,
runlength_check => runlength_check,
test_bus_sel_val => test_bus_sel_val,
runlength_val => runlength_val,
force_signal_detect => force_signal_detect,
deskew => deskew,
rx_wr_clk => rx_wr_clk,
rx_clk_free_running => rx_clk_free_running,
rx_pcs_urst => rx_pcs_urst,
self_switch_dw_scaling => self_switch_dw_scaling,
pipe_if_enable => pipe_if_enable,
pc_fifo_rst_pld_ctrl => pc_fifo_rst_pld_ctrl,
auto_speed_nego_gen2 => auto_speed_nego_gen2,
auto_speed_nego_gen3 => auto_speed_nego_gen3,
ibm_invalid_code => ibm_invalid_code,
channel_number => channel_number,
rx_refclk => rx_refclk
)
port map (
hrdrst => hrdrst,
rxpcsrst => rxpcsrst,
rmfifouserrst => rmfifouserrst,
phfifouserrst => phfifouserrst,
scanmode => scanmode,
enablecommadetect => enablecommadetect,
a1a2size => a1a2size,
bitslip => bitslip,
rmfiforeadenable => rmfiforeadenable,
rmfifowriteenable => rmfifowriteenable,
pldrxclk => pldrxclk,
softresetrclk1 => softresetrclk1,
polinvrx => polinvrx,
bitreversalenable => bitreversalenable,
bytereversalenable => bytereversalenable,
rcvdclkpma => rcvdclkpma,
datain => datain,
sigdetfrompma => sigdetfrompma,
fiforstrdqd => fiforstrdqd,
endskwqd => endskwqd,
endskwrdptrs => endskwrdptrs,
alignstatus => alignstatus,
fiforstrdqdtoporbot => fiforstrdqdtoporbot,
endskwqdtoporbot => endskwqdtoporbot,
endskwrdptrstoporbot => endskwrdptrstoporbot,
alignstatustoporbot => alignstatustoporbot,
datafrinaggblock => datafrinaggblock,
ctrlfromaggblock => ctrlfromaggblock,
rxdatarstoporbot => rxdatarstoporbot,
rxcontrolrstoporbot => rxcontrolrstoporbot,
rcvdclk0pma => rcvdclk0pma,
parallelloopback => parallelloopback,
txpmaclk => txpmaclk,
byteorder => byteorder,
pxfifowrdisable => pxfifowrdisable,
pcfifordenable => pcfifordenable,
pmatestbus => pmatestbus,
encodertestbus => encodertestbus,
txctrltestbus => txctrltestbus,
phystatusinternal => phystatusinternal,
rxvalidinternal => rxvalidinternal,
rxstatusinternal => rxstatusinternal,
phystatuspcsgen3 => phystatuspcsgen3,
rxvalidpcsgen3 => rxvalidpcsgen3,
rxstatuspcsgen3 => rxstatuspcsgen3,
rxdatavalidpcsgen3 => rxdatavalidpcsgen3,
rxblkstartpcsgen3 => rxblkstartpcsgen3,
rxsynchdrpcsgen3 => rxsynchdrpcsgen3,
rxdatapcsgen3 => rxdatapcsgen3,
pipepowerdown => pipepowerdown,
rateswitchcontrol => rateswitchcontrol,
gen2ngen1 => gen2ngen1,
gen2ngen1bundle => gen2ngen1bundle,
eidleinfersel => eidleinfersel,
pipeloopbk => pipeloopbk,
pldltr => pldltr,
prbscidenable => prbscidenable,
txdiv2syncoutpipeup => txdiv2syncoutpipeup,
fifoselectoutpipeup => fifoselectoutpipeup,
txwrenableoutpipeup => txwrenableoutpipeup,
txrdenableoutpipeup => txrdenableoutpipeup,
txdiv2syncoutpipedown => txdiv2syncoutpipedown,
fifoselectoutpipedown => fifoselectoutpipedown,
txwrenableoutpipedown => txwrenableoutpipedown,
txrdenableoutpipedown => txrdenableoutpipedown,
alignstatussync0 => alignstatussync0,
rmfifordincomp0 => rmfifordincomp0,
cgcomprddall => cgcomprddall,
cgcompwrall => cgcompwrall,
delcondmet0 => delcondmet0,
fifoovr0 => fifoovr0,
latencycomp0 => latencycomp0,
insertincomplete0 => insertincomplete0,
alignstatussync0toporbot => alignstatussync0toporbot,
fifordincomp0toporbot => fifordincomp0toporbot,
cgcomprddalltoporbot => cgcomprddalltoporbot,
cgcompwralltoporbot => cgcompwralltoporbot,
delcondmet0toporbot => delcondmet0toporbot,
fifoovr0toporbot => fifoovr0toporbot,
latencycomp0toporbot => latencycomp0toporbot,
insertincomplete0toporbot => insertincomplete0toporbot,
alignstatussync => alignstatussync,
fifordoutcomp => fifordoutcomp,
cgcomprddout => cgcomprddout,
cgcompwrout => cgcompwrout,
delcondmetout => delcondmetout,
fifoovrout => fifoovrout,
latencycompout => latencycompout,
insertincompleteout => insertincompleteout,
dataout => dataout,
parallelrevloopback => parallelrevloopback,
clocktopld => clocktopld,
bisterr => bisterr,
clk2b => clk2b,
rcvdclkpmab => rcvdclkpmab,
syncstatus => syncstatus,
decoderdatavalid => decoderdatavalid,
decoderdata => decoderdata,
decoderctrl => decoderctrl,
runningdisparity => runningdisparity,
selftestdone => selftestdone,
selftesterr => selftesterr,
errdata => errdata,
errctrl => errctrl,
prbsdone => prbsdone,
prbserrlt => prbserrlt,
signaldetectout => signaldetectout,
aligndetsync => aligndetsync,
rdalign => rdalign,
bistdone => bistdone,
runlengthviolation => runlengthviolation,
rlvlt => rlvlt,
rmfifopartialfull => rmfifopartialfull,
rmfifofull => rmfifofull,
rmfifopartialempty => rmfifopartialempty,
rmfifoempty => rmfifoempty,
pcfifofull => pcfifofull,
pcfifoempty => pcfifoempty,
a1a2k1k2flag => a1a2k1k2flag,
byteordflag => byteordflag,
rxpipeclk => rxpipeclk,
channeltestbusout => channeltestbusout,
rxpipesoftreset => rxpipesoftreset,
phystatus => phystatus,
rxvalid => rxvalid,
rxstatus => rxstatus,
pipedata => pipedata,
rxdatavalid => rxdatavalid,
rxblkstart => rxblkstart,
rxsynchdr => rxsynchdr,
speedchange => speedchange,
eidledetected => eidledetected,
wordalignboundary => wordalignboundary,
rxclkslip => rxclkslip,
eidleexit => eidleexit,
earlyeios => earlyeios,
ltr => ltr,
pcswrapbackin => pcswrapbackin,
rxdivsyncinchnlup => rxdivsyncinchnlup,
rxdivsyncinchnldown => rxdivsyncinchnldown,
wrenableinchnlup => wrenableinchnlup,
wrenableinchnldown => wrenableinchnldown,
rdenableinchnlup => rdenableinchnlup,
rdenableinchnldown => rdenableinchnldown,
rxweinchnlup => rxweinchnlup,
rxweinchnldown => rxweinchnldown,
resetpcptrsinchnlup => resetpcptrsinchnlup,
resetpcptrsinchnldown => resetpcptrsinchnldown,
configselinchnlup => configselinchnlup,
configselinchnldown => configselinchnldown,
speedchangeinchnlup => speedchangeinchnlup,
speedchangeinchnldown => speedchangeinchnldown,
pcieswitch => pcieswitch,
rxdivsyncoutchnlup => rxdivsyncoutchnlup,
rxweoutchnlup => rxweoutchnlup,
wrenableoutchnlup => wrenableoutchnlup,
rdenableoutchnlup => rdenableoutchnlup,
resetpcptrsoutchnlup => resetpcptrsoutchnlup,
speedchangeoutchnlup => speedchangeoutchnlup,
configseloutchnlup => configseloutchnlup,
rxdivsyncoutchnldown => rxdivsyncoutchnldown,
rxweoutchnldown => rxweoutchnldown,
wrenableoutchnldown => wrenableoutchnldown,
rdenableoutchnldown => rdenableoutchnldown,
resetpcptrsoutchnldown => resetpcptrsoutchnldown,
speedchangeoutchnldown => speedchangeoutchnldown,
configseloutchnldown => configseloutchnldown,
resetpcptrsinchnluppipe => resetpcptrsinchnluppipe,
resetpcptrsinchnldownpipe => resetpcptrsinchnldownpipe,
speedchangeinchnluppipe => speedchangeinchnluppipe,
speedchangeinchnldownpipe => speedchangeinchnldownpipe,
disablepcfifobyteserdes => disablepcfifobyteserdes,
resetpcptrs => resetpcptrs,
rcvdclkagg => rcvdclkagg,
rcvdclkaggtoporbot => rcvdclkaggtoporbot,
dispcbytegen3 => dispcbytegen3,
refclkdig => refclkdig,
txfifordclkraw => txfifordclkraw,
resetpcptrsgen3 => resetpcptrsgen3,
syncdatain => syncdatain,
observablebyteserdesclock => observablebyteserdesclock
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_tx_pcs is
generic (
prot_mode : string := "basic";
hip_mode : string := "dis_hip";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
phase_compensation_fifo : string := "low_latency";
tx_compliance_controlled_disparity : string := "dis_txcompliance";
force_kchar : string := "dis_force_kchar";
force_echar : string := "dis_force_echar";
byte_serializer : string := "dis_bs";
data_selection_8b10b_encoder_input : string := "normal_data_path";
eightb_tenb_disp_ctrl : string := "dis_disp_ctrl";
eightb_tenb_encoder : string := "dis_8b10b";
prbs_gen : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_gen : string := "dis_bist";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
polarity_inversion : string := "dis_polinv";
tx_bitslip : string := "dis_tx_bitslip";
agg_block_sel : string := "same_smrt_pack";
revloop_back_rm : string := "dis_rev_loopback_rx_rm";
phfifo_write_clk_sel : string := "pld_tx_clk";
ctrl_plane_bonding_consumption : string := "individual";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
test_mode : string := "prbs";
clock_gate_tx : string := "dis_clk_gating";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
ctrl_plane_bonding_compensation : string := "dis_compensation";
refclk_b_clk_sel : string := "tx_pma_clock";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
channel_number : string := "int"
);
port (
txpcsreset : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(43 downto 0);
coreclk : in std_logic_vector(0 downto 0);
invpol : in std_logic_vector(0 downto 0);
xgmdatain : in std_logic_vector(7 downto 0);
xgmctrl : in std_logic_vector(0 downto 0);
xgmdataintoporbottom : in std_logic_vector(7 downto 0);
xgmctrltoporbottom : in std_logic_vector(0 downto 0);
txpmalocalclk : in std_logic_vector(0 downto 0);
enrevparallellpbk : in std_logic_vector(0 downto 0);
revparallellpbkdata : in std_logic_vector(19 downto 0);
phfifowrenable : in std_logic_vector(0 downto 0);
phfiforddisable : in std_logic_vector(0 downto 0);
phfiforeset : in std_logic_vector(0 downto 0);
detectrxloopin : in std_logic_vector(0 downto 0);
powerdn : in std_logic_vector(1 downto 0);
pipeenrevparallellpbkin : in std_logic_vector(0 downto 0);
pipetxswing : in std_logic_vector(0 downto 0);
pipetxdeemph : in std_logic_vector(0 downto 0);
pipetxmargin : in std_logic_vector(2 downto 0);
rxpolarityin : in std_logic_vector(0 downto 0);
polinvrxin : in std_logic_vector(0 downto 0);
elecidleinfersel : in std_logic_vector(2 downto 0);
rateswitch : in std_logic_vector(0 downto 0);
rateswitchbundle : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
bitslipboundaryselect : in std_logic_vector(4 downto 0);
phfifooverflow : out std_logic_vector(0 downto 0);
phfifounderflow : out std_logic_vector(0 downto 0);
clkout : out std_logic_vector(0 downto 0);
clkoutgen3 : out std_logic_vector(0 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(19 downto 0);
rdenablesync : out std_logic_vector(0 downto 0);
refclkb : out std_logic_vector(0 downto 0);
parallelfdbkout : out std_logic_vector(19 downto 0);
txpipeclk : out std_logic_vector(0 downto 0);
encodertestbus : out std_logic_vector(9 downto 0);
txctrltestbus : out std_logic_vector(9 downto 0);
txpipesoftreset : out std_logic_vector(0 downto 0);
txpipeelectidle : out std_logic_vector(0 downto 0);
detectrxloopout : out std_logic_vector(0 downto 0);
pipepowerdownout : out std_logic_vector(1 downto 0);
pipeenrevparallellpbkout : out std_logic_vector(0 downto 0);
phfifotxswing : out std_logic_vector(0 downto 0);
phfifotxdeemph : out std_logic_vector(0 downto 0);
phfifotxmargin : out std_logic_vector(2 downto 0);
txdataouttogen3 : out std_logic_vector(31 downto 0);
txdatakouttogen3 : out std_logic_vector(3 downto 0);
txdatavalidouttogen3 : out std_logic_vector(3 downto 0);
txblkstartout : out std_logic_vector(3 downto 0);
txsynchdrout : out std_logic_vector(1 downto 0);
txcomplianceout : out std_logic_vector(0 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
rxpolarityout : out std_logic_vector(0 downto 0);
polinvrxout : out std_logic_vector(0 downto 0);
grayelecidleinferselout : out std_logic_vector(2 downto 0);
txdivsyncinchnlup : in std_logic_vector(1 downto 0);
txdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
fifoselectinchnlup : in std_logic_vector(1 downto 0);
fifoselectinchnldown : in std_logic_vector(1 downto 0);
resetpcptrs : in std_logic_vector(0 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
dispcbyte : in std_logic_vector(0 downto 0);
txdivsyncoutchnlup : out std_logic_vector(1 downto 0);
txdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
fifoselectoutchnlup : out std_logic_vector(1 downto 0);
fifoselectoutchnldown : out std_logic_vector(1 downto 0);
txfifordclkraw : out std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_tx_pcs;
architecture behavior of stratixv_hssi_8g_tx_pcs is
component stratixv_hssi_8g_tx_pcs_encrypted
generic (
prot_mode : string := "basic";
hip_mode : string := "dis_hip";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
phase_compensation_fifo : string := "low_latency";
tx_compliance_controlled_disparity : string := "dis_txcompliance";
force_kchar : string := "dis_force_kchar";
force_echar : string := "dis_force_echar";
byte_serializer : string := "dis_bs";
data_selection_8b10b_encoder_input : string := "normal_data_path";
eightb_tenb_disp_ctrl : string := "dis_disp_ctrl";
eightb_tenb_encoder : string := "dis_8b10b";
prbs_gen : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_gen : string := "dis_bist";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
polarity_inversion : string := "dis_polinv";
tx_bitslip : string := "dis_tx_bitslip";
agg_block_sel : string := "same_smrt_pack";
revloop_back_rm : string := "dis_rev_loopback_rx_rm";
phfifo_write_clk_sel : string := "pld_tx_clk";
ctrl_plane_bonding_consumption : string := "individual";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
test_mode : string := "prbs";
clock_gate_tx : string := "dis_clk_gating";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
ctrl_plane_bonding_compensation : string := "dis_compensation";
refclk_b_clk_sel : string := "tx_pma_clock";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
channel_number : string := "int"
);
port (
txpcsreset : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(43 downto 0);
coreclk : in std_logic_vector(0 downto 0);
invpol : in std_logic_vector(0 downto 0);
xgmdatain : in std_logic_vector(7 downto 0);
xgmctrl : in std_logic_vector(0 downto 0);
xgmdataintoporbottom : in std_logic_vector(7 downto 0);
xgmctrltoporbottom : in std_logic_vector(0 downto 0);
txpmalocalclk : in std_logic_vector(0 downto 0);
enrevparallellpbk : in std_logic_vector(0 downto 0);
revparallellpbkdata : in std_logic_vector(19 downto 0);
phfifowrenable : in std_logic_vector(0 downto 0);
phfiforddisable : in std_logic_vector(0 downto 0);
phfiforeset : in std_logic_vector(0 downto 0);
detectrxloopin : in std_logic_vector(0 downto 0);
powerdn : in std_logic_vector(1 downto 0);
pipeenrevparallellpbkin : in std_logic_vector(0 downto 0);
pipetxswing : in std_logic_vector(0 downto 0);
pipetxdeemph : in std_logic_vector(0 downto 0);
pipetxmargin : in std_logic_vector(2 downto 0);
rxpolarityin : in std_logic_vector(0 downto 0);
polinvrxin : in std_logic_vector(0 downto 0);
elecidleinfersel : in std_logic_vector(2 downto 0);
rateswitch : in std_logic_vector(0 downto 0);
rateswitchbundle : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
bitslipboundaryselect : in std_logic_vector(4 downto 0);
phfifooverflow : out std_logic_vector(0 downto 0);
phfifounderflow : out std_logic_vector(0 downto 0);
clkout : out std_logic_vector(0 downto 0);
clkoutgen3 : out std_logic_vector(0 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(19 downto 0);
rdenablesync : out std_logic_vector(0 downto 0);
refclkb : out std_logic_vector(0 downto 0);
parallelfdbkout : out std_logic_vector(19 downto 0);
txpipeclk : out std_logic_vector(0 downto 0);
encodertestbus : out std_logic_vector(9 downto 0);
txctrltestbus : out std_logic_vector(9 downto 0);
txpipesoftreset : out std_logic_vector(0 downto 0);
txpipeelectidle : out std_logic_vector(0 downto 0);
detectrxloopout : out std_logic_vector(0 downto 0);
pipepowerdownout : out std_logic_vector(1 downto 0);
pipeenrevparallellpbkout : out std_logic_vector(0 downto 0);
phfifotxswing : out std_logic_vector(0 downto 0);
phfifotxdeemph : out std_logic_vector(0 downto 0);
phfifotxmargin : out std_logic_vector(2 downto 0);
txdataouttogen3 : out std_logic_vector(31 downto 0);
txdatakouttogen3 : out std_logic_vector(3 downto 0);
txdatavalidouttogen3 : out std_logic_vector(3 downto 0);
txblkstartout : out std_logic_vector(3 downto 0);
txsynchdrout : out std_logic_vector(1 downto 0);
txcomplianceout : out std_logic_vector(0 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
rxpolarityout : out std_logic_vector(0 downto 0);
polinvrxout : out std_logic_vector(0 downto 0);
grayelecidleinferselout : out std_logic_vector(2 downto 0);
txdivsyncinchnlup : in std_logic_vector(1 downto 0);
txdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
fifoselectinchnlup : in std_logic_vector(1 downto 0);
fifoselectinchnldown : in std_logic_vector(1 downto 0);
resetpcptrs : in std_logic_vector(0 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
dispcbyte : in std_logic_vector(0 downto 0);
txdivsyncoutchnlup : out std_logic_vector(1 downto 0);
txdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
fifoselectoutchnlup : out std_logic_vector(1 downto 0);
fifoselectoutchnldown : out std_logic_vector(1 downto 0);
txfifordclkraw : out std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_tx_pcs_encrypted
generic map (
prot_mode => prot_mode,
hip_mode => hip_mode,
pma_dw => pma_dw,
pcs_bypass => pcs_bypass,
phase_compensation_fifo => phase_compensation_fifo,
tx_compliance_controlled_disparity => tx_compliance_controlled_disparity,
force_kchar => force_kchar,
force_echar => force_echar,
byte_serializer => byte_serializer,
data_selection_8b10b_encoder_input => data_selection_8b10b_encoder_input,
eightb_tenb_disp_ctrl => eightb_tenb_disp_ctrl,
eightb_tenb_encoder => eightb_tenb_encoder,
prbs_gen => prbs_gen,
cid_pattern => cid_pattern,
cid_pattern_len => cid_pattern_len,
bist_gen => bist_gen,
bit_reversal => bit_reversal,
symbol_swap => symbol_swap,
polarity_inversion => polarity_inversion,
tx_bitslip => tx_bitslip,
agg_block_sel => agg_block_sel,
revloop_back_rm => revloop_back_rm,
phfifo_write_clk_sel => phfifo_write_clk_sel,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
bypass_pipeline_reg => bypass_pipeline_reg,
ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution,
test_mode => test_mode,
clock_gate_tx => clock_gate_tx,
self_switch_dw_scaling => self_switch_dw_scaling,
ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation,
refclk_b_clk_sel => refclk_b_clk_sel,
auto_speed_nego_gen2 => auto_speed_nego_gen2,
auto_speed_nego_gen3 => auto_speed_nego_gen3,
channel_number => channel_number
)
port map (
txpcsreset => txpcsreset,
refclkdig => refclkdig,
scanmode => scanmode,
datain => datain,
coreclk => coreclk,
invpol => invpol,
xgmdatain => xgmdatain,
xgmctrl => xgmctrl,
xgmdataintoporbottom => xgmdataintoporbottom,
xgmctrltoporbottom => xgmctrltoporbottom,
txpmalocalclk => txpmalocalclk,
enrevparallellpbk => enrevparallellpbk,
revparallellpbkdata => revparallellpbkdata,
phfifowrenable => phfifowrenable,
phfiforddisable => phfiforddisable,
phfiforeset => phfiforeset,
detectrxloopin => detectrxloopin,
powerdn => powerdn,
pipeenrevparallellpbkin => pipeenrevparallellpbkin,
pipetxswing => pipetxswing,
pipetxdeemph => pipetxdeemph,
pipetxmargin => pipetxmargin,
rxpolarityin => rxpolarityin,
polinvrxin => polinvrxin,
elecidleinfersel => elecidleinfersel,
rateswitch => rateswitch,
rateswitchbundle => rateswitchbundle,
prbscidenable => prbscidenable,
bitslipboundaryselect => bitslipboundaryselect,
phfifooverflow => phfifooverflow,
phfifounderflow => phfifounderflow,
clkout => clkout,
clkoutgen3 => clkoutgen3,
xgmdataout => xgmdataout,
xgmctrlenable => xgmctrlenable,
dataout => dataout,
rdenablesync => rdenablesync,
refclkb => refclkb,
parallelfdbkout => parallelfdbkout,
txpipeclk => txpipeclk,
encodertestbus => encodertestbus,
txctrltestbus => txctrltestbus,
txpipesoftreset => txpipesoftreset,
txpipeelectidle => txpipeelectidle,
detectrxloopout => detectrxloopout,
pipepowerdownout => pipepowerdownout,
pipeenrevparallellpbkout => pipeenrevparallellpbkout,
phfifotxswing => phfifotxswing,
phfifotxdeemph => phfifotxdeemph,
phfifotxmargin => phfifotxmargin,
txdataouttogen3 => txdataouttogen3,
txdatakouttogen3 => txdatakouttogen3,
txdatavalidouttogen3 => txdatavalidouttogen3,
txblkstartout => txblkstartout,
txsynchdrout => txsynchdrout,
txcomplianceout => txcomplianceout,
txelecidleout => txelecidleout,
rxpolarityout => rxpolarityout,
polinvrxout => polinvrxout,
grayelecidleinferselout => grayelecidleinferselout,
txdivsyncinchnlup => txdivsyncinchnlup,
txdivsyncinchnldown => txdivsyncinchnldown,
wrenableinchnlup => wrenableinchnlup,
wrenableinchnldown => wrenableinchnldown,
rdenableinchnlup => rdenableinchnlup,
rdenableinchnldown => rdenableinchnldown,
fifoselectinchnlup => fifoselectinchnlup,
fifoselectinchnldown => fifoselectinchnldown,
resetpcptrs => resetpcptrs,
resetpcptrsinchnlup => resetpcptrsinchnlup,
resetpcptrsinchnldown => resetpcptrsinchnldown,
dispcbyte => dispcbyte,
txdivsyncoutchnlup => txdivsyncoutchnlup,
txdivsyncoutchnldown => txdivsyncoutchnldown,
rdenableoutchnlup => rdenableoutchnlup,
rdenableoutchnldown => rdenableoutchnldown,
wrenableoutchnlup => wrenableoutchnlup,
wrenableoutchnldown => wrenableoutchnldown,
fifoselectoutchnlup => fifoselectoutchnlup,
fifoselectoutchnldown => fifoselectoutchnldown,
txfifordclkraw => txfifordclkraw,
syncdatain => syncdatain,
observablebyteserdesclock => observablebyteserdesclock
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pipe_gen1_2 is
generic (
prot_mode : string := "pipe_g1";
hip_mode : string := "dis_hip";
tx_pipe_enable : string := "dis_pipe_tx";
rx_pipe_enable : string := "dis_pipe_rx";
pipe_byte_de_serializer_en : string := "dont_care_bds";
txswing : string := "dis_txswing";
rxdetect_bypass : string := "dis_rxdetect_bypass";
error_replace_pad : string := "replace_edb";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle : string := "dis_phystatus_rst_toggle";
elecidle_delay : string := "elec_idle_delay";
elec_idle_delay_val : bit_vector := B"000";
phy_status_delay : string := "phystatus_delay";
phystatus_delay_val : bit_vector := B"000";
ctrl_plane_bonding_consumption : string := "individual";
byte_deserializer : string := "dis_bds"
);
port (
pipetxclk : in std_logic_vector(0 downto 0);
piperxclk : in std_logic_vector(0 downto 0);
refclkb : in std_logic_vector(0 downto 0);
txpipereset : in std_logic_vector(0 downto 0);
rxpipereset : in std_logic_vector(0 downto 0);
refclkbreset : in std_logic_vector(0 downto 0);
rrdwidthrx : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txelecidlein : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txswingport : in std_logic_vector(0 downto 0);
txdch : in std_logic_vector(43 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
sigdetni : in std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdch : out std_logic_vector(63 downto 0);
phystatus : out std_logic_vector(0 downto 0);
revloopback : in std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
txd : out std_logic_vector(43 downto 0);
revloopbk : out std_logic_vector(0 downto 0);
revloopbkpcsgen3 : in std_logic_vector(0 downto 0);
rxelectricalidlepcsgen3 : in std_logic_vector(0 downto 0);
txelecidlecomp : in std_logic_vector(0 downto 0);
rindvrx : in std_logic_vector(0 downto 0);
rmasterrx : in std_logic_vector(1 downto 0);
speedchange : in std_logic_vector(0 downto 0);
speedchangechnlup : in std_logic_vector(0 downto 0);
speedchangechnldown : in std_logic_vector(0 downto 0);
rxd : in std_logic_vector(63 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
txdetectrx : out std_logic_vector(0 downto 0);
powerstate : out std_logic_vector(3 downto 0);
rxfound : in std_logic_vector(0 downto 0);
rxdetectvalid : in std_logic_vector(0 downto 0);
rxelectricalidle : in std_logic_vector(0 downto 0);
powerstatetransitiondone : in std_logic_vector(0 downto 0);
powerstatetransitiondoneena : in std_logic_vector(0 downto 0);
txdeemphint : out std_logic_vector(0 downto 0);
txmarginint : out std_logic_vector(2 downto 0);
txswingint : out std_logic_vector(0 downto 0);
rxelectricalidleout : out std_logic_vector(0 downto 0);
rxpolaritypcsgen3 : in std_logic_vector(0 downto 0);
polinvrxint : out std_logic_vector(0 downto 0);
speedchangeout : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_pipe_gen1_2;
architecture behavior of stratixv_hssi_pipe_gen1_2 is
component stratixv_hssi_pipe_gen1_2_encrypted
generic (
prot_mode : string := "pipe_g1";
hip_mode : string := "dis_hip";
tx_pipe_enable : string := "dis_pipe_tx";
rx_pipe_enable : string := "dis_pipe_rx";
pipe_byte_de_serializer_en : string := "dont_care_bds";
txswing : string := "dis_txswing";
rxdetect_bypass : string := "dis_rxdetect_bypass";
error_replace_pad : string := "replace_edb";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle : string := "dis_phystatus_rst_toggle";
elecidle_delay : string := "elec_idle_delay";
elec_idle_delay_val : bit_vector := B"000";
phy_status_delay : string := "phystatus_delay";
phystatus_delay_val : bit_vector := B"000";
ctrl_plane_bonding_consumption : string := "individual";
byte_deserializer : string := "dis_bds"
);
port (
pipetxclk : in std_logic_vector(0 downto 0);
piperxclk : in std_logic_vector(0 downto 0);
refclkb : in std_logic_vector(0 downto 0);
txpipereset : in std_logic_vector(0 downto 0);
rxpipereset : in std_logic_vector(0 downto 0);
refclkbreset : in std_logic_vector(0 downto 0);
rrdwidthrx : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txelecidlein : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txswingport : in std_logic_vector(0 downto 0);
txdch : in std_logic_vector(43 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
sigdetni : in std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdch : out std_logic_vector(63 downto 0);
phystatus : out std_logic_vector(0 downto 0);
revloopback : in std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
txd : out std_logic_vector(43 downto 0);
revloopbk : out std_logic_vector(0 downto 0);
revloopbkpcsgen3 : in std_logic_vector(0 downto 0);
rxelectricalidlepcsgen3 : in std_logic_vector(0 downto 0);
txelecidlecomp : in std_logic_vector(0 downto 0);
rindvrx : in std_logic_vector(0 downto 0);
rmasterrx : in std_logic_vector(1 downto 0);
speedchange : in std_logic_vector(0 downto 0);
speedchangechnlup : in std_logic_vector(0 downto 0);
speedchangechnldown : in std_logic_vector(0 downto 0);
rxd : in std_logic_vector(63 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
txdetectrx : out std_logic_vector(0 downto 0);
powerstate : out std_logic_vector(3 downto 0);
rxfound : in std_logic_vector(0 downto 0);
rxdetectvalid : in std_logic_vector(0 downto 0);
rxelectricalidle : in std_logic_vector(0 downto 0);
powerstatetransitiondone : in std_logic_vector(0 downto 0);
powerstatetransitiondoneena : in std_logic_vector(0 downto 0);
txdeemphint : out std_logic_vector(0 downto 0);
txmarginint : out std_logic_vector(2 downto 0);
txswingint : out std_logic_vector(0 downto 0);
rxelectricalidleout : out std_logic_vector(0 downto 0);
rxpolaritypcsgen3 : in std_logic_vector(0 downto 0);
polinvrxint : out std_logic_vector(0 downto 0);
speedchangeout : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_pipe_gen1_2_encrypted
generic map (
prot_mode => prot_mode,
hip_mode => hip_mode,
tx_pipe_enable => tx_pipe_enable,
rx_pipe_enable => rx_pipe_enable,
pipe_byte_de_serializer_en => pipe_byte_de_serializer_en,
txswing => txswing,
rxdetect_bypass => rxdetect_bypass,
error_replace_pad => error_replace_pad,
ind_error_reporting => ind_error_reporting,
phystatus_rst_toggle => phystatus_rst_toggle,
elecidle_delay => elecidle_delay,
elec_idle_delay_val => elec_idle_delay_val,
phy_status_delay => phy_status_delay,
phystatus_delay_val => phystatus_delay_val,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
byte_deserializer => byte_deserializer
)
port map (
pipetxclk => pipetxclk,
piperxclk => piperxclk,
refclkb => refclkb,
txpipereset => txpipereset,
rxpipereset => rxpipereset,
refclkbreset => refclkbreset,
rrdwidthrx => rrdwidthrx,
txdetectrxloopback => txdetectrxloopback,
txelecidlein => txelecidlein,
powerdown => powerdown,
txdeemph => txdeemph,
txmargin => txmargin,
txswingport => txswingport,
txdch => txdch,
rxpolarity => rxpolarity,
sigdetni => sigdetni,
rxvalid => rxvalid,
rxelecidle => rxelecidle,
rxstatus => rxstatus,
rxdch => rxdch,
phystatus => phystatus,
revloopback => revloopback,
polinvrx => polinvrx,
txd => txd,
revloopbk => revloopbk,
revloopbkpcsgen3 => revloopbkpcsgen3,
rxelectricalidlepcsgen3 => rxelectricalidlepcsgen3,
txelecidlecomp => txelecidlecomp,
rindvrx => rindvrx,
rmasterrx => rmasterrx,
speedchange => speedchange,
speedchangechnlup => speedchangechnlup,
speedchangechnldown => speedchangechnldown,
rxd => rxd,
txelecidleout => txelecidleout,
txdetectrx => txdetectrx,
powerstate => powerstate,
rxfound => rxfound,
rxdetectvalid => rxdetectvalid,
rxelectricalidle => rxelectricalidle,
powerstatetransitiondone => powerstatetransitiondone,
powerstatetransitiondoneena => powerstatetransitiondoneena,
txdeemphint => txdeemphint,
txmarginint => txmarginint,
txswingint => txswingint,
rxelectricalidleout => rxelectricalidleout,
rxpolaritypcsgen3 => rxpolaritypcsgen3,
polinvrxint => polinvrxint,
speedchangeout => speedchangeout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pipe_gen3 is
generic (
mode : string := "pipe_g1";
ctrl_plane_bonding : string := "individual";
pipe_clk_sel : string := "func_clk";
rate_match_pad_insertion : string := "dis_rm_fifo_pad_ins";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle_g3 : string := "dis_phystatus_rst_toggle_g3";
phystatus_rst_toggle_g12 : string := "dis_phystatus_rst_toggle";
cdr_control : string := "en_cdr_ctrl";
cid_enable : string := "en_cid_mode";
parity_chk_ts1 : string := "en_ts1_parity_chk";
rxvalid_mask : string := "rxvalid_mask_en";
ph_fifo_reg_mode : string := "phfifo_reg_mode_dis";
test_mode_timers : string := "dis_test_mode_timers";
inf_ei_enable : string := "dis_inf_ei";
spd_chnge_g2_sel : string := "false";
cp_up_mstr : string := "false";
cp_dwn_mstr : string := "false";
cp_cons_sel : string := "cp_cons_default";
elecidle_delay_g12_data : bit_vector := B"000";
elecidle_delay_g12 : string := "elecidle_delay_g12";
elecidle_delay_g3_data : bit_vector := B"000";
elecidle_delay_g3 : string := "elecidle_delay_g3";
phy_status_delay_g12_data : bit_vector := B"000";
phy_status_delay_g12 : string := "phy_status_delay_g12";
phy_status_delay_g3_data : bit_vector := B"000";
phy_status_delay_g3 : string := "phy_status_delay_g3";
sigdet_wait_counter_data : bit_vector := B"00000000";
sigdet_wait_counter : string := "sigdet_wait_counter";
data_mask_count_val : bit_vector := B"0000000000";
data_mask_count : string := "data_mask_count";
pma_done_counter_data : bit_vector := B"000000000000000000";
pma_done_counter : string := "pma_done_count";
pc_en_counter_data : bit_vector := B"00000";
pc_en_counter : string := "pc_en_count";
pc_rst_counter_data : bit_vector := B"0000";
pc_rst_counter : string := "pc_rst_count";
phfifo_flush_wait_data : bit_vector := B"000000";
phfifo_flush_wait : string := "phfifo_flush_wait";
asn_clk_enable : string := "false";
free_run_clk_enable : string := "true";
asn_enable : string := "dis_asn"
);
port (
rcvdclk : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
pcsdigclk : in std_logic_vector(0 downto 0);
pllfixedclk : in std_logic_vector(0 downto 0);
rtxgen3capen : in std_logic_vector(0 downto 0);
rrxgen3capen : in std_logic_vector(0 downto 0);
rtxdigclksel : in std_logic_vector(0 downto 0);
rrxdigclksel : in std_logic_vector(0 downto 0);
rxrstn : in std_logic_vector(0 downto 0);
txrstn : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
pldasyncstatus : out std_logic_vector(5 downto 0);
testout : out std_logic_vector(19 downto 0);
gen3datasel : out std_logic_vector(0 downto 0);
gen3clksel : out std_logic_vector(0 downto 0);
pcsrst : out std_logic_vector(0 downto 0);
dispcbyte : out std_logic_vector(0 downto 0);
resetpcprts : out std_logic_vector(0 downto 0);
shutdownclk : out std_logic_vector(0 downto 0);
txdata : in std_logic_vector(31 downto 0);
txdatak : in std_logic_vector(3 downto 0);
txdataskip : in std_logic_vector(0 downto 0);
txsynchdr : in std_logic_vector(1 downto 0);
txblkstart : in std_logic_vector(0 downto 0);
txelecidle : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txcompliance : in std_logic_vector(0 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
rate : in std_logic_vector(1 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txswing : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
currentcoeff : in std_logic_vector(17 downto 0);
currentrxpreset : in std_logic_vector(2 downto 0);
rxupdatefc : in std_logic_vector(0 downto 0);
rxdataskip : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdataint : in std_logic_vector(31 downto 0);
rxdatakint : in std_logic_vector(3 downto 0);
rxdataskipint : in std_logic_vector(0 downto 0);
rxsynchdrint : in std_logic_vector(1 downto 0);
rxblkstartint : in std_logic_vector(0 downto 0);
txdataint : out std_logic_vector(31 downto 0);
txdatakint : out std_logic_vector(3 downto 0);
txdataskipint : out std_logic_vector(0 downto 0);
txsynchdrint : out std_logic_vector(1 downto 0);
txblkstartint : out std_logic_vector(0 downto 0);
testinfei : out std_logic_vector(18 downto 0);
eidetint : in std_logic_vector(0 downto 0);
eipartialdetint : in std_logic_vector(0 downto 0);
idetint : in std_logic_vector(0 downto 0);
blkalgndint : in std_logic_vector(0 downto 0);
clkcompinsertint : in std_logic_vector(0 downto 0);
clkcompdeleteint : in std_logic_vector(0 downto 0);
clkcompoverflint : in std_logic_vector(0 downto 0);
clkcompundflint : in std_logic_vector(0 downto 0);
errdecodeint : in std_logic_vector(0 downto 0);
rcvlfsrchkint : in std_logic_vector(0 downto 0);
errencodeint : in std_logic_vector(0 downto 0);
rxpolarityint : out std_logic_vector(0 downto 0);
revlpbkint : out std_logic_vector(0 downto 0);
inferredrxvalidint : out std_logic_vector(0 downto 0);
rxd8gpcsin : in std_logic_vector(63 downto 0);
rxelecidle8gpcsin : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
rxd8gpcsout : out std_logic_vector(63 downto 0);
revlpbk8gpcsout : out std_logic_vector(0 downto 0);
pmarxdetectvalid : in std_logic_vector(0 downto 0);
pmarxfound : in std_logic_vector(0 downto 0);
pmasignaldet : in std_logic_vector(0 downto 0);
pmapcieswdone : in std_logic_vector(1 downto 0);
pmapcieswitch : out std_logic_vector(1 downto 0);
pmatxmargin : out std_logic_vector(2 downto 0);
pmatxdeemph : out std_logic_vector(0 downto 0);
pmatxswing : out std_logic_vector(0 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmatxelecidle : out std_logic_vector(0 downto 0);
pmatxdetectrx : out std_logic_vector(0 downto 0);
ppmeidleexit : out std_logic_vector(0 downto 0);
pmaltr : out std_logic_vector(0 downto 0);
pmaearlyeios : out std_logic_vector(0 downto 0);
pmarxdetpd : out std_logic_vector(0 downto 0);
bundlingindown : in std_logic_vector(9 downto 0);
bundlingoutdown : out std_logic_vector(9 downto 0);
rxpolarity8gpcsout : out std_logic_vector(0 downto 0);
speedchangeg2 : in std_logic_vector(0 downto 0);
bundlingoutup : out std_logic_vector(9 downto 0);
bundlinginup : in std_logic_vector(9 downto 0);
masktxpll : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_pipe_gen3;
architecture behavior of stratixv_hssi_pipe_gen3 is
component stratixv_hssi_pipe_gen3_encrypted
generic (
mode : string := "pipe_g1";
ctrl_plane_bonding : string := "individual";
pipe_clk_sel : string := "func_clk";
rate_match_pad_insertion : string := "dis_rm_fifo_pad_ins";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle_g3 : string := "dis_phystatus_rst_toggle_g3";
phystatus_rst_toggle_g12 : string := "dis_phystatus_rst_toggle";
cdr_control : string := "en_cdr_ctrl";
cid_enable : string := "en_cid_mode";
parity_chk_ts1 : string := "en_ts1_parity_chk";
rxvalid_mask : string := "rxvalid_mask_en";
ph_fifo_reg_mode : string := "phfifo_reg_mode_dis";
test_mode_timers : string := "dis_test_mode_timers";
inf_ei_enable : string := "dis_inf_ei";
spd_chnge_g2_sel : string := "false";
cp_up_mstr : string := "false";
cp_dwn_mstr : string := "false";
cp_cons_sel : string := "cp_cons_default";
elecidle_delay_g12_data : bit_vector := B"000";
elecidle_delay_g12 : string := "elecidle_delay_g12";
elecidle_delay_g3_data : bit_vector := B"000";
elecidle_delay_g3 : string := "elecidle_delay_g3";
phy_status_delay_g12_data : bit_vector := B"000";
phy_status_delay_g12 : string := "phy_status_delay_g12";
phy_status_delay_g3_data : bit_vector := B"000";
phy_status_delay_g3 : string := "phy_status_delay_g3";
sigdet_wait_counter_data : bit_vector := B"00000000";
sigdet_wait_counter : string := "sigdet_wait_counter";
data_mask_count_val : bit_vector := B"0000000000";
data_mask_count : string := "data_mask_count";
pma_done_counter_data : bit_vector := B"000000000000000000";
pma_done_counter : string := "pma_done_count";
pc_en_counter_data : bit_vector := B"00000";
pc_en_counter : string := "pc_en_count";
pc_rst_counter_data : bit_vector := B"0000";
pc_rst_counter : string := "pc_rst_count";
phfifo_flush_wait_data : bit_vector := B"000000";
phfifo_flush_wait : string := "phfifo_flush_wait";
asn_clk_enable : string := "false";
free_run_clk_enable : string := "true";
asn_enable : string := "dis_asn"
);
port (
rcvdclk : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
pcsdigclk : in std_logic_vector(0 downto 0);
pllfixedclk : in std_logic_vector(0 downto 0);
rtxgen3capen : in std_logic_vector(0 downto 0);
rrxgen3capen : in std_logic_vector(0 downto 0);
rtxdigclksel : in std_logic_vector(0 downto 0);
rrxdigclksel : in std_logic_vector(0 downto 0);
rxrstn : in std_logic_vector(0 downto 0);
txrstn : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
pldasyncstatus : out std_logic_vector(5 downto 0);
testout : out std_logic_vector(19 downto 0);
gen3datasel : out std_logic_vector(0 downto 0);
gen3clksel : out std_logic_vector(0 downto 0);
pcsrst : out std_logic_vector(0 downto 0);
dispcbyte : out std_logic_vector(0 downto 0);
resetpcprts : out std_logic_vector(0 downto 0);
shutdownclk : out std_logic_vector(0 downto 0);
txdata : in std_logic_vector(31 downto 0);
txdatak : in std_logic_vector(3 downto 0);
txdataskip : in std_logic_vector(0 downto 0);
txsynchdr : in std_logic_vector(1 downto 0);
txblkstart : in std_logic_vector(0 downto 0);
txelecidle : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txcompliance : in std_logic_vector(0 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
rate : in std_logic_vector(1 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txswing : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
currentcoeff : in std_logic_vector(17 downto 0);
currentrxpreset : in std_logic_vector(2 downto 0);
rxupdatefc : in std_logic_vector(0 downto 0);
rxdataskip : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdataint : in std_logic_vector(31 downto 0);
rxdatakint : in std_logic_vector(3 downto 0);
rxdataskipint : in std_logic_vector(0 downto 0);
rxsynchdrint : in std_logic_vector(1 downto 0);
rxblkstartint : in std_logic_vector(0 downto 0);
txdataint : out std_logic_vector(31 downto 0);
txdatakint : out std_logic_vector(3 downto 0);
txdataskipint : out std_logic_vector(0 downto 0);
txsynchdrint : out std_logic_vector(1 downto 0);
txblkstartint : out std_logic_vector(0 downto 0);
testinfei : out std_logic_vector(18 downto 0);
eidetint : in std_logic_vector(0 downto 0);
eipartialdetint : in std_logic_vector(0 downto 0);
idetint : in std_logic_vector(0 downto 0);
blkalgndint : in std_logic_vector(0 downto 0);
clkcompinsertint : in std_logic_vector(0 downto 0);
clkcompdeleteint : in std_logic_vector(0 downto 0);
clkcompoverflint : in std_logic_vector(0 downto 0);
clkcompundflint : in std_logic_vector(0 downto 0);
errdecodeint : in std_logic_vector(0 downto 0);
rcvlfsrchkint : in std_logic_vector(0 downto 0);
errencodeint : in std_logic_vector(0 downto 0);
rxpolarityint : out std_logic_vector(0 downto 0);
revlpbkint : out std_logic_vector(0 downto 0);
inferredrxvalidint : out std_logic_vector(0 downto 0);
rxd8gpcsin : in std_logic_vector(63 downto 0);
rxelecidle8gpcsin : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
rxd8gpcsout : out std_logic_vector(63 downto 0);
revlpbk8gpcsout : out std_logic_vector(0 downto 0);
pmarxdetectvalid : in std_logic_vector(0 downto 0);
pmarxfound : in std_logic_vector(0 downto 0);
pmasignaldet : in std_logic_vector(0 downto 0);
pmapcieswdone : in std_logic_vector(1 downto 0);
pmapcieswitch : out std_logic_vector(1 downto 0);
pmatxmargin : out std_logic_vector(2 downto 0);
pmatxdeemph : out std_logic_vector(0 downto 0);
pmatxswing : out std_logic_vector(0 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmatxelecidle : out std_logic_vector(0 downto 0);
pmatxdetectrx : out std_logic_vector(0 downto 0);
ppmeidleexit : out std_logic_vector(0 downto 0);
pmaltr : out std_logic_vector(0 downto 0);
pmaearlyeios : out std_logic_vector(0 downto 0);
pmarxdetpd : out std_logic_vector(0 downto 0);
bundlingindown : in std_logic_vector(9 downto 0);
bundlingoutdown : out std_logic_vector(9 downto 0);
rxpolarity8gpcsout : out std_logic_vector(0 downto 0);
speedchangeg2 : in std_logic_vector(0 downto 0);
bundlingoutup : out std_logic_vector(9 downto 0);
bundlinginup : in std_logic_vector(9 downto 0);
masktxpll : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_pipe_gen3_encrypted
generic map (
mode => mode,
ctrl_plane_bonding => ctrl_plane_bonding,
pipe_clk_sel => pipe_clk_sel,
rate_match_pad_insertion => rate_match_pad_insertion,
ind_error_reporting => ind_error_reporting,
phystatus_rst_toggle_g3 => phystatus_rst_toggle_g3,
phystatus_rst_toggle_g12 => phystatus_rst_toggle_g12,
cdr_control => cdr_control,
cid_enable => cid_enable,
parity_chk_ts1 => parity_chk_ts1,
rxvalid_mask => rxvalid_mask,
ph_fifo_reg_mode => ph_fifo_reg_mode,
test_mode_timers => test_mode_timers,
inf_ei_enable => inf_ei_enable,
spd_chnge_g2_sel => spd_chnge_g2_sel,
cp_up_mstr => cp_up_mstr,
cp_dwn_mstr => cp_dwn_mstr,
cp_cons_sel => cp_cons_sel,
elecidle_delay_g12_data => elecidle_delay_g12_data,
elecidle_delay_g12 => elecidle_delay_g12,
elecidle_delay_g3_data => elecidle_delay_g3_data,
elecidle_delay_g3 => elecidle_delay_g3,
phy_status_delay_g12_data => phy_status_delay_g12_data,
phy_status_delay_g12 => phy_status_delay_g12,
phy_status_delay_g3_data => phy_status_delay_g3_data,
phy_status_delay_g3 => phy_status_delay_g3,
sigdet_wait_counter_data => sigdet_wait_counter_data,
sigdet_wait_counter => sigdet_wait_counter,
data_mask_count_val => data_mask_count_val,
data_mask_count => data_mask_count,
pma_done_counter_data => pma_done_counter_data,
pma_done_counter => pma_done_counter,
pc_en_counter_data => pc_en_counter_data,
pc_en_counter => pc_en_counter,
pc_rst_counter_data => pc_rst_counter_data,
pc_rst_counter => pc_rst_counter,
phfifo_flush_wait_data => phfifo_flush_wait_data,
phfifo_flush_wait => phfifo_flush_wait,
asn_clk_enable => asn_clk_enable,
free_run_clk_enable => free_run_clk_enable,
asn_enable => asn_enable
)
port map (
rcvdclk => rcvdclk,
txpmaclk => txpmaclk,
pcsdigclk => pcsdigclk,
pllfixedclk => pllfixedclk,
rtxgen3capen => rtxgen3capen,
rrxgen3capen => rrxgen3capen,
rtxdigclksel => rtxdigclksel,
rrxdigclksel => rrxdigclksel,
rxrstn => rxrstn,
txrstn => txrstn,
scanmoden => scanmoden,
pldasyncstatus => pldasyncstatus,
testout => testout,
gen3datasel => gen3datasel,
gen3clksel => gen3clksel,
pcsrst => pcsrst,
dispcbyte => dispcbyte,
resetpcprts => resetpcprts,
shutdownclk => shutdownclk,
txdata => txdata,
txdatak => txdatak,
txdataskip => txdataskip,
txsynchdr => txsynchdr,
txblkstart => txblkstart,
txelecidle => txelecidle,
txdetectrxloopback => txdetectrxloopback,
txcompliance => txcompliance,
rxpolarity => rxpolarity,
powerdown => powerdown,
rate => rate,
txmargin => txmargin,
txdeemph => txdeemph,
txswing => txswing,
eidleinfersel => eidleinfersel,
currentcoeff => currentcoeff,
currentrxpreset => currentrxpreset,
rxupdatefc => rxupdatefc,
rxdataskip => rxdataskip,
rxsynchdr => rxsynchdr,
rxblkstart => rxblkstart,
rxvalid => rxvalid,
phystatus => phystatus,
rxelecidle => rxelecidle,
rxstatus => rxstatus,
rxdataint => rxdataint,
rxdatakint => rxdatakint,
rxdataskipint => rxdataskipint,
rxsynchdrint => rxsynchdrint,
rxblkstartint => rxblkstartint,
txdataint => txdataint,
txdatakint => txdatakint,
txdataskipint => txdataskipint,
txsynchdrint => txsynchdrint,
txblkstartint => txblkstartint,
testinfei => testinfei,
eidetint => eidetint,
eipartialdetint => eipartialdetint,
idetint => idetint,
blkalgndint => blkalgndint,
clkcompinsertint => clkcompinsertint,
clkcompdeleteint => clkcompdeleteint,
clkcompoverflint => clkcompoverflint,
clkcompundflint => clkcompundflint,
errdecodeint => errdecodeint,
rcvlfsrchkint => rcvlfsrchkint,
errencodeint => errencodeint,
rxpolarityint => rxpolarityint,
revlpbkint => revlpbkint,
inferredrxvalidint => inferredrxvalidint,
rxd8gpcsin => rxd8gpcsin,
rxelecidle8gpcsin => rxelecidle8gpcsin,
pldltr => pldltr,
rxd8gpcsout => rxd8gpcsout,
revlpbk8gpcsout => revlpbk8gpcsout,
pmarxdetectvalid => pmarxdetectvalid,
pmarxfound => pmarxfound,
pmasignaldet => pmasignaldet,
pmapcieswdone => pmapcieswdone,
pmapcieswitch => pmapcieswitch,
pmatxmargin => pmatxmargin,
pmatxdeemph => pmatxdeemph,
pmatxswing => pmatxswing,
pmacurrentcoeff => pmacurrentcoeff,
pmacurrentrxpreset => pmacurrentrxpreset,
pmatxelecidle => pmatxelecidle,
pmatxdetectrx => pmatxdetectrx,
ppmeidleexit => ppmeidleexit,
pmaltr => pmaltr,
pmaearlyeios => pmaearlyeios,
pmarxdetpd => pmarxdetpd,
bundlingindown => bundlingindown,
bundlingoutdown => bundlingoutdown,
rxpolarity8gpcsout => rxpolarity8gpcsout,
speedchangeg2 => speedchangeg2,
bundlingoutup => bundlingoutup,
bundlinginup => bundlinginup,
masktxpll => masktxpll
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_cdr_refclk_select_mux is
generic (
lpm_type : string := "stratixv_hssi_pma_cdr_refclk_select_mux";
channel_number : integer := 0;
refclk_select : string := "ref_iqclk0";
mux_type : string := "cdr_refclk_select_mux";
reference_clock_frequency : string := "0 ps"
);
port (
calclk : in std_logic;
ffplloutbot : in std_logic;
ffpllouttop : in std_logic;
pldclk : in std_logic;
refiqclk0 : in std_logic;
refiqclk1 : in std_logic;
refiqclk10 : in std_logic;
refiqclk2 : in std_logic;
refiqclk3 : in std_logic;
refiqclk4 : in std_logic;
refiqclk5 : in std_logic;
refiqclk6 : in std_logic;
refiqclk7 : in std_logic;
refiqclk8 : in std_logic;
refiqclk9 : in std_logic;
rxiqclk0 : in std_logic;
rxiqclk1 : in std_logic;
rxiqclk10 : in std_logic;
rxiqclk2 : in std_logic;
rxiqclk3 : in std_logic;
rxiqclk4 : in std_logic;
rxiqclk5 : in std_logic;
rxiqclk6 : in std_logic;
rxiqclk7 : in std_logic;
rxiqclk8 : in std_logic;
rxiqclk9 : in std_logic;
clkout : out std_logic
);
end stratixv_hssi_pma_cdr_refclk_select_mux;
architecture behavior of stratixv_hssi_pma_cdr_refclk_select_mux is
component stratixv_hssi_pma_cdr_refclk_select_mux_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_cdr_refclk_select_mux";
channel_number : integer := 0;
refclk_select : string := "ref_iqclk0";
reference_clock_frequency : string := "0 ps"
);
port (
calclk : in std_logic;
ffplloutbot : in std_logic;
ffpllouttop : in std_logic;
pldclk : in std_logic;
refiqclk0 : in std_logic;
refiqclk1 : in std_logic;
refiqclk10 : in std_logic;
refiqclk2 : in std_logic;
refiqclk3 : in std_logic;
refiqclk4 : in std_logic;
refiqclk5 : in std_logic;
refiqclk6 : in std_logic;
refiqclk7 : in std_logic;
refiqclk8 : in std_logic;
refiqclk9 : in std_logic;
rxiqclk0 : in std_logic;
rxiqclk1 : in std_logic;
rxiqclk10 : in std_logic;
rxiqclk2 : in std_logic;
rxiqclk3 : in std_logic;
rxiqclk4 : in std_logic;
rxiqclk5 : in std_logic;
rxiqclk6 : in std_logic;
rxiqclk7 : in std_logic;
rxiqclk8 : in std_logic;
rxiqclk9 : in std_logic;
clkout : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_cdr_refclk_select_mux_encrypted
generic map (
lpm_type => lpm_type,
channel_number => channel_number,
refclk_select => refclk_select,
reference_clock_frequency => reference_clock_frequency
)
port map (
calclk => calclk,
ffplloutbot => ffplloutbot,
ffpllouttop => ffpllouttop,
pldclk => pldclk,
refiqclk0 => refiqclk0,
refiqclk1 => refiqclk1,
refiqclk10 => refiqclk10,
refiqclk2 => refiqclk2,
refiqclk3 => refiqclk3,
refiqclk4 => refiqclk4,
refiqclk5 => refiqclk5,
refiqclk6 => refiqclk6,
refiqclk7 => refiqclk7,
refiqclk8 => refiqclk8,
refiqclk9 => refiqclk9,
rxiqclk0 => rxiqclk0,
rxiqclk1 => rxiqclk1,
rxiqclk10 => rxiqclk10,
rxiqclk2 => rxiqclk2,
rxiqclk3 => rxiqclk3,
rxiqclk4 => rxiqclk4,
rxiqclk5 => rxiqclk5,
rxiqclk6 => rxiqclk6,
rxiqclk7 => rxiqclk7,
rxiqclk8 => rxiqclk8,
rxiqclk9 => rxiqclk9,
clkout => clkout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_rx_buf is
generic (
lpm_type : string := "stratixv_hssi_pma_rx_buf";
adce_pd : string := "false";
bypass_eqz_stages_123 : string := "all_stages_enabled";
eq_bw_sel : string := "bw_full_12p5";
input_vcm_sel : string := "high_vcm";
pdb_dfe : string := "false";
pdb_sd : string := "false";
qpi_enable : string := "false";
rx_dc_gain : string := "dc_gain_0db";
rx_sel_bias_source : string := "bias_vcmdrv";
sd_off : string := "clk_divrx_2";
sd_on : string := "data_pulse_6";
sd_threshold : string := "sdlv_30mv";
serial_loopback : string := "lpbkp_dis";
term_sel : string := "r_100ohm";
vccela_supply_voltage : string := "vccela_1p0v";
vcm_sel : string := "vtt_0p7v";
channel_number : integer := 0
);
port (
adaptcapture : in std_logic;
adaptdone : out std_logic;
adcestandby : in std_logic;
hardoccaldone : out std_logic;
hardoccalen : in std_logic;
eyemonitor : in std_logic_vector(4 downto 0);
ck0sigdet : in std_logic;
datain : in std_logic;
fined2aout : in std_logic;
lpbkp : in std_logic;
refclklpbk : in std_logic;
rstn : in std_logic;
rxqpipulldn : in std_logic;
slpbk : in std_logic;
dataout : out std_logic;
nonuserfrompmaux : out std_logic;
rdlpbkp : out std_logic;
rxpadce : out std_logic;
sd : out std_logic
);
end stratixv_hssi_pma_rx_buf;
architecture behavior of stratixv_hssi_pma_rx_buf is
component stratixv_hssi_pma_rx_buf_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_rx_buf";
adce_pd : string := "false";
bypass_eqz_stages_123 : string := "all_stages_enabled";
eq_bw_sel : string := "bw_full_12p5";
input_vcm_sel : string := "high_vcm";
pdb_dfe : string := "false";
pdb_sd : string := "false";
qpi_enable : string := "false";
rx_dc_gain : string := "dc_gain_0db";
rx_sel_bias_source : string := "bias_vcmdrv";
sd_off : string := "clk_divrx_2";
sd_on : string := "data_pulse_6";
sd_threshold : string := "sdlv_30mv";
serial_loopback : string := "lpbkp_dis";
term_sel : string := "r_100ohm";
vccela_supply_voltage : string := "vccela_1p0v";
vcm_sel : string := "vtt_0p7v";
channel_number : integer := 0
);
port (
ck0sigdet : in std_logic;
datain : in std_logic;
fined2aout : in std_logic;
lpbkp : in std_logic;
adaptcapture : in std_logic;
adaptdone : out std_logic;
adcestandby : in std_logic;
hardoccaldone : out std_logic;
hardoccalen : in std_logic;
eyemonitor : in std_logic_vector(4 downto 0);
refclklpbk : in std_logic;
rstn : in std_logic;
rxqpipulldn : in std_logic;
slpbk : in std_logic;
dataout : out std_logic;
nonuserfrompmaux : out std_logic;
rdlpbkp : out std_logic;
rxpadce : out std_logic;
sd : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_rx_buf_encrypted
generic map (
lpm_type => lpm_type,
adce_pd => adce_pd,
bypass_eqz_stages_123 => bypass_eqz_stages_123,
eq_bw_sel => eq_bw_sel,
input_vcm_sel => input_vcm_sel,
pdb_dfe => pdb_dfe,
pdb_sd => pdb_sd,
qpi_enable => qpi_enable,
rx_dc_gain => rx_dc_gain,
rx_sel_bias_source => rx_sel_bias_source,
sd_off => sd_off,
sd_on => sd_on,
sd_threshold => sd_threshold,
serial_loopback => serial_loopback,
term_sel => term_sel,
vccela_supply_voltage => vccela_supply_voltage,
vcm_sel => vcm_sel,
channel_number => channel_number
)
port map (
ck0sigdet => ck0sigdet,
datain => datain,
fined2aout => fined2aout,
lpbkp => lpbkp,
hardoccalen => hardoccalen,
refclklpbk => refclklpbk,
rstn => rstn,
rxqpipulldn => rxqpipulldn,
slpbk => slpbk,
dataout => dataout,
nonuserfrompmaux => nonuserfrompmaux,
rdlpbkp => rdlpbkp,
rxpadce => rxpadce,
sd => sd,
adaptcapture => adaptcapture,
adaptdone => adaptdone,
adcestandby => adcestandby,
hardoccaldone => hardoccaldone,
eyemonitor => eyemonitor
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_rx_deser is
generic (
lpm_type : string := "stratixv_hssi_pma_rx_deser";
auto_negotiation : string := "false";
bit_slip_bypass : string := "false";
mode : integer := 8;
sdclk_enable : string := "false";
vco_bypass : string := "vco_bypass_normal";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
bslip : in std_logic;
clk90b : in std_logic;
clk270b : in std_logic;
deven : in std_logic;
dodd : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pfdmodelock : in std_logic;
rstn : in std_logic;
clk33pcs : out std_logic;
clkdivrx : out std_logic;
clkdivrxrx : out std_logic;
dout : out std_logic_vector(39 downto 0);
pciel : out std_logic;
pciem : out std_logic
);
end stratixv_hssi_pma_rx_deser;
architecture behavior of stratixv_hssi_pma_rx_deser is
component stratixv_hssi_pma_rx_deser_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_rx_deser";
auto_negotiation : string := "false";
bit_slip_bypass : string := "false";
mode : integer := 8;
sdclk_enable : string := "false";
vco_bypass : string := "vco_bypass_normal";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
bslip : in std_logic;
clk90b : in std_logic;
clk270b : in std_logic;
deven : in std_logic;
dodd : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pfdmodelock : in std_logic;
rstn : in std_logic;
clk33pcs : out std_logic;
clkdivrx : out std_logic;
clkdivrxrx : out std_logic;
dout : out std_logic_vector(39 downto 0);
pciel : out std_logic;
pciem : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_rx_deser_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
bit_slip_bypass => bit_slip_bypass,
mode => mode,
sdclk_enable => sdclk_enable,
vco_bypass => vco_bypass,
channel_number => channel_number,
clk_forward_only_mode => clk_forward_only_mode
)
port map (
bslip => bslip,
clk90b => clk90b,
clk270b => clk270b,
deven => deven,
dodd => dodd,
pciesw => pciesw,
pfdmodelock => pfdmodelock,
rstn => rstn,
clk33pcs => clk33pcs,
clkdivrx => clkdivrx,
clkdivrxrx => clkdivrxrx,
dout => dout,
pciel => pciel,
pciem => pciem
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_buf is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_buf";
elec_idl_gate_ctrl : string := "true";
pre_emp_switching_ctrl_1st_post_tap : string := "fir_1pt_disabled";
pre_emp_switching_ctrl_2nd_post_tap : string := "fir_2pt_disabled";
pre_emp_switching_ctrl_pre_tap : string := "fir_pre_disabled";
qpi_en : string := "false";
rx_det : string := "mode_0";
rx_det_output_sel : string := "rx_det_pcie_out";
rx_det_pdb : string := "true";
sig_inv_2nd_tap : string := "false";
sig_inv_pre_tap : string := "false";
slew_rate_ctrl : string := "slew_30ps";
term_sel : string := "r_100ohm";
vod_switching_ctrl_main_tap : string := "fir_main_2p0ma";
channel_number : integer := 0
);
port (
datain : in std_logic;
rxdetclk : in std_logic;
txdetrx : in std_logic;
txelecidl : in std_logic;
txqpipulldn : in std_logic;
txqpipullup : in std_logic;
compass : out std_logic;
dataout : out std_logic;
detecton : out std_logic_vector(1 downto 0);
fixedclkout : out std_logic;
nonuserfrompmaux : out std_logic;
probepass : out std_logic;
rxdetectvalid : out std_logic;
rxfound : out std_logic
);
end stratixv_hssi_pma_tx_buf;
architecture behavior of stratixv_hssi_pma_tx_buf is
component stratixv_hssi_pma_tx_buf_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_buf";
elec_idl_gate_ctrl : string := "true";
pre_emp_switching_ctrl_1st_post_tap : string := "fir_1pt_disabled";
pre_emp_switching_ctrl_2nd_post_tap : string := "fir_2pt_disabled";
pre_emp_switching_ctrl_pre_tap : string := "fir_pre_disabled";
qpi_en : string := "false";
rx_det : string := "mode_0";
rx_det_output_sel : string := "rx_det_pcie_out";
rx_det_pdb : string := "true";
sig_inv_2nd_tap : string := "false";
sig_inv_pre_tap : string := "false";
slew_rate_ctrl : string := "slew_30ps";
term_sel : string := "r_100ohm";
vod_switching_ctrl_main_tap : string := "fir_main_2p0ma";
channel_number : integer := 0
);
port (
datain : in std_logic;
rxdetclk : in std_logic;
txdetrx : in std_logic;
txelecidl : in std_logic;
txqpipulldn : in std_logic;
txqpipullup : in std_logic;
compass : out std_logic;
dataout : out std_logic;
detecton : out std_logic_vector(1 downto 0);
fixedclkout : out std_logic;
nonuserfrompmaux : out std_logic;
probepass : out std_logic;
rxdetectvalid : out std_logic;
rxfound : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_buf_encrypted
generic map (
lpm_type => lpm_type,
elec_idl_gate_ctrl => elec_idl_gate_ctrl,
pre_emp_switching_ctrl_1st_post_tap => pre_emp_switching_ctrl_1st_post_tap,
pre_emp_switching_ctrl_2nd_post_tap => pre_emp_switching_ctrl_2nd_post_tap,
pre_emp_switching_ctrl_pre_tap => pre_emp_switching_ctrl_pre_tap,
qpi_en => qpi_en,
rx_det => rx_det,
rx_det_output_sel => rx_det_output_sel,
rx_det_pdb => rx_det_pdb,
sig_inv_2nd_tap => sig_inv_2nd_tap,
sig_inv_pre_tap => sig_inv_pre_tap,
slew_rate_ctrl => slew_rate_ctrl,
term_sel => term_sel,
vod_switching_ctrl_main_tap => vod_switching_ctrl_main_tap,
channel_number => channel_number
)
port map (
datain => datain,
rxdetclk => rxdetclk,
txdetrx => txdetrx,
txelecidl => txelecidl,
txqpipulldn => txqpipulldn,
txqpipullup => txqpipullup,
compass => compass,
dataout => dataout,
detecton => detecton,
fixedclkout => fixedclkout,
nonuserfrompmaux => nonuserfrompmaux,
probepass => probepass,
rxdetectvalid => rxdetectvalid,
rxfound => rxfound
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_cgb is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_cgb";
auto_negotiation : string := "false";
x1_div_m_sel : integer := 1;
channel_number : integer := 0;
data_rate : string := "";
mode : integer := 8;
rx_iqclk_sel : string := "cgb_x1_n_div";
tx_mux_power_down : string := "normal";
x1_clock_source_sel : string := "x1_clk_unused";
xn_clock_source_sel : string := "cgb_xn_unused";
xn_network_driver : string := "enable_clock_entwork_driver";
cgb_iqclk_sel : string := "cgb_x1_n_div";
ht_delay_enable : string := "false"
);
port (
clkbcdr1adj : in std_logic;
clkbcdr1loc : in std_logic;
clkbcdrloc : in std_logic;
clkbdnseg : in std_logic;
clkbffpll : in std_logic;
clkblcb : in std_logic;
clkblct : in std_logic;
clkbupseg : in std_logic;
clkcdr1adj : in std_logic;
clkcdr1loc : in std_logic;
clkcdrloc : in std_logic;
clkdnseg : in std_logic;
clkffpll : in std_logic;
clklcb : in std_logic;
clklct : in std_logic;
clkupseg : in std_logic;
cpulsex6adj : in std_logic;
cpulsex6loc : in std_logic;
cpulsexndn : in std_logic;
cpulsexnup : in std_logic;
hfclknx6adj : in std_logic;
hfclknx6loc : in std_logic;
hfclknxndn : in std_logic;
hfclknxnup : in std_logic;
hfclkpx6adj : in std_logic;
hfclkpx6loc : in std_logic;
hfclkpxndn : in std_logic;
hfclkpxnup : in std_logic;
lfclknx6adj : in std_logic;
lfclknx6loc : in std_logic;
lfclknxndn : in std_logic;
lfclknxnup : in std_logic;
lfclkpx6adj : in std_logic;
lfclkpx6loc : in std_logic;
lfclkpxndn : in std_logic;
lfclkpxnup : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0x6adj : in std_logic;
pclk0x6loc : in std_logic;
pclk0xndn : in std_logic;
pclk0xnup : in std_logic;
pclk1x6adj : in std_logic;
pclk1x6loc : in std_logic;
pclk1xndn : in std_logic;
pclk1xnup : in std_logic;
pclkx6adj : in std_logic_vector(2 downto 0);
pclkx6loc : in std_logic_vector(2 downto 0);
pclkxndn : in std_logic_vector(2 downto 0);
pclkxnup : in std_logic_vector(2 downto 0);
rxclk : in std_logic;
txpmarstb : in std_logic;
txpmasyncp : in std_logic;
xnresetin : in std_logic;
cpulse : out std_logic;
cpulseout : out std_logic;
hfclkn : out std_logic;
hfclknout : out std_logic;
hfclkp : out std_logic;
hfclkpout : out std_logic;
lfclkn : out std_logic;
lfclknout : out std_logic;
lfclkp : out std_logic;
lfclkpout : out std_logic;
pcieswdone : out std_logic_vector(1 downto 0);
pclk0 : out std_logic;
pclk0out : out std_logic;
pclk1 : out std_logic;
pclk1out : out std_logic;
pclk : out std_logic_vector(2 downto 0);
pclkout : out std_logic_vector(2 downto 0);
rxiqclk : out std_logic;
xnresetout : out std_logic
);
end stratixv_hssi_pma_tx_cgb;
architecture behavior of stratixv_hssi_pma_tx_cgb is
component stratixv_hssi_pma_tx_cgb_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_cgb";
auto_negotiation : string := "false";
x1_div_m_sel : integer := 1;
channel_number : integer := 0;
data_rate : string := "";
mode : integer := 8;
rx_iqclk_sel : string := "cgb_x1_n_div";
tx_mux_power_down : string := "normal";
x1_clock_source_sel : string := "x1_clk_unused";
xn_clock_source_sel : string := "cgb_xn_unused";
xn_network_driver : string := "enable_clock_entwork_driver";
cgb_iqclk_sel : string := "cgb_x1_n_div";
ht_delay_enable : string := "false"
);
port (
clkbcdr1adj : in std_logic;
clkbcdr1loc : in std_logic;
clkbcdrloc : in std_logic;
clkbdnseg : in std_logic;
clkbffpll : in std_logic;
clkblcb : in std_logic;
clkblct : in std_logic;
clkbupseg : in std_logic;
clkcdr1adj : in std_logic;
clkcdr1loc : in std_logic;
clkcdrloc : in std_logic;
clkdnseg : in std_logic;
clkffpll : in std_logic;
clklcb : in std_logic;
clklct : in std_logic;
clkupseg : in std_logic;
cpulsex6adj : in std_logic;
cpulsex6loc : in std_logic;
cpulsexndn : in std_logic;
cpulsexnup : in std_logic;
hfclknx6adj : in std_logic;
hfclknx6loc : in std_logic;
hfclknxndn : in std_logic;
hfclknxnup : in std_logic;
hfclkpx6adj : in std_logic;
hfclkpx6loc : in std_logic;
hfclkpxndn : in std_logic;
hfclkpxnup : in std_logic;
lfclknx6adj : in std_logic;
lfclknx6loc : in std_logic;
lfclknxndn : in std_logic;
lfclknxnup : in std_logic;
lfclkpx6adj : in std_logic;
lfclkpx6loc : in std_logic;
lfclkpxndn : in std_logic;
lfclkpxnup : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0x6adj : in std_logic;
pclk0x6loc : in std_logic;
pclk0xndn : in std_logic;
pclk0xnup : in std_logic;
pclk1x6adj : in std_logic;
pclk1x6loc : in std_logic;
pclk1xndn : in std_logic;
pclk1xnup : in std_logic;
pclkx6adj : in std_logic_vector(2 downto 0);
pclkx6loc : in std_logic_vector(2 downto 0);
pclkxndn : in std_logic_vector(2 downto 0);
pclkxnup : in std_logic_vector(2 downto 0);
rxclk : in std_logic;
txpmarstb : in std_logic;
txpmasyncp : in std_logic;
xnresetin : in std_logic;
cpulse : out std_logic;
cpulseout : out std_logic;
hfclkn : out std_logic;
hfclknout : out std_logic;
hfclkp : out std_logic;
hfclkpout : out std_logic;
lfclkn : out std_logic;
lfclknout : out std_logic;
lfclkp : out std_logic;
lfclkpout : out std_logic;
pcieswdone : out std_logic_vector(1 downto 0);
pclk0 : out std_logic;
pclk0out : out std_logic;
pclk1 : out std_logic;
pclk1out : out std_logic;
pclk : out std_logic_vector(2 downto 0);
pclkout : out std_logic_vector(2 downto 0);
rxiqclk : out std_logic;
xnresetout : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_cgb_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
x1_div_m_sel => x1_div_m_sel,
channel_number => channel_number,
data_rate => data_rate,
mode => mode,
rx_iqclk_sel => rx_iqclk_sel,
tx_mux_power_down => tx_mux_power_down,
x1_clock_source_sel => x1_clock_source_sel,
xn_clock_source_sel => xn_clock_source_sel,
xn_network_driver => xn_network_driver,
cgb_iqclk_sel => cgb_iqclk_sel,
ht_delay_enable => ht_delay_enable
)
port map (
clkbcdr1adj => clkbcdr1adj,
clkbcdr1loc => clkbcdr1loc,
clkbcdrloc => clkbcdrloc,
clkbdnseg => clkbdnseg,
clkbffpll => clkbffpll,
clkblcb => clkblcb,
clkblct => clkblct,
clkbupseg => clkbupseg,
clkcdr1adj => clkcdr1adj,
clkcdr1loc => clkcdr1loc,
clkcdrloc => clkcdrloc,
clkdnseg => clkdnseg,
clkffpll => clkffpll,
clklcb => clklcb,
clklct => clklct,
clkupseg => clkupseg,
cpulsex6adj => cpulsex6adj,
cpulsex6loc => cpulsex6loc,
cpulsexndn => cpulsexndn,
cpulsexnup => cpulsexnup,
hfclknx6adj => hfclknx6adj,
hfclknx6loc => hfclknx6loc,
hfclknxndn => hfclknxndn,
hfclknxnup => hfclknxnup,
hfclkpx6adj => hfclkpx6adj,
hfclkpx6loc => hfclkpx6loc,
hfclkpxndn => hfclkpxndn,
hfclkpxnup => hfclkpxnup,
lfclknx6adj => lfclknx6adj,
lfclknx6loc => lfclknx6loc,
lfclknxndn => lfclknxndn,
lfclknxnup => lfclknxnup,
lfclkpx6adj => lfclkpx6adj,
lfclkpx6loc => lfclkpx6loc,
lfclkpxndn => lfclkpxndn,
lfclkpxnup => lfclkpxnup,
pciesw => pciesw,
pclk0x6adj => pclk0x6adj,
pclk0x6loc => pclk0x6loc,
pclk0xndn => pclk0xndn,
pclk0xnup => pclk0xnup,
pclk1x6adj => pclk1x6adj,
pclk1x6loc => pclk1x6loc,
pclk1xndn => pclk1xndn,
pclk1xnup => pclk1xnup,
pclkx6adj => pclkx6adj,
pclkx6loc => pclkx6loc,
pclkxndn => pclkxndn,
pclkxnup => pclkxnup,
rxclk => rxclk,
txpmarstb => txpmarstb,
txpmasyncp => txpmasyncp,
xnresetin => xnresetin,
cpulse => cpulse,
cpulseout => cpulseout,
hfclkn => hfclkn,
hfclknout => hfclknout,
hfclkp => hfclkp,
hfclkpout => hfclkpout,
lfclkn => lfclkn,
lfclknout => lfclknout,
lfclkp => lfclkp,
lfclkpout => lfclkpout,
pcieswdone => pcieswdone,
pclk0 => pclk0,
pclk0out => pclk0out,
pclk1 => pclk1,
pclk1out => pclk1out,
pclk => pclk,
pclkout => pclkout,
rxiqclk => rxiqclk,
xnresetout => xnresetout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_ser is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_ser";
auto_negotiation : string := "false";
clk_divtx_deskew : string := "deskew_delay1";
mode : integer := 8;
post_tap_1_en : string := "false";
post_tap_2_en : string := "false";
pre_tap_en : string := "false";
ser_loopback : string := "false";
pclksel : string := "local_pclk";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
cpulse : in std_logic;
datain : in std_logic_vector(39 downto 0);
hfclk : in std_logic;
hfclkn : in std_logic;
lfclk : in std_logic;
lfclkn : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0 : in std_logic;
pclk1 : in std_logic;
pclk2 : in std_logic;
pclk : in std_logic_vector(2 downto 0);
rstn : in std_logic;
clkdivtx : out std_logic;
dataout : out std_logic;
div5 : out std_logic;
lbvop : out std_logic
);
end stratixv_hssi_pma_tx_ser;
architecture behavior of stratixv_hssi_pma_tx_ser is
component stratixv_hssi_pma_tx_ser_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_ser";
auto_negotiation : string := "false";
clk_divtx_deskew : string := "deskew_delay1";
mode : integer := 8;
post_tap_1_en : string := "false";
post_tap_2_en : string := "false";
pre_tap_en : string := "false";
ser_loopback : string := "false";
pclksel : string := "local_pclk";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
cpulse : in std_logic;
datain : in std_logic_vector(39 downto 0);
hfclk : in std_logic;
hfclkn : in std_logic;
lfclk : in std_logic;
lfclkn : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0 : in std_logic;
pclk1 : in std_logic;
pclk2 : in std_logic;
pclk : in std_logic_vector(2 downto 0);
rstn : in std_logic;
clkdivtx : out std_logic;
dataout : out std_logic;
div5 : out std_logic;
lbvop : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_ser_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
clk_divtx_deskew => clk_divtx_deskew,
mode => mode,
post_tap_1_en => post_tap_1_en,
post_tap_2_en => post_tap_2_en,
pre_tap_en => pre_tap_en,
ser_loopback => ser_loopback,
pclksel => pclksel,
channel_number => channel_number,
clk_forward_only_mode => clk_forward_only_mode
)
port map (
cpulse => cpulse,
datain => datain,
hfclk => hfclk,
hfclkn => hfclkn,
lfclk => lfclk,
lfclkn => lfclkn,
pciesw => pciesw,
pclk0 => pclk0,
pclk1 => pclk1,
pclk2 => pclk2,
pclk => pclk,
rstn => rstn,
clkdivtx => clkdivtx,
dataout => dataout,
div5 => div5,
lbvop => lbvop
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_common_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_common_pcs_pma_interface";
auto_speed_ena : string := "dis_auto_speed_ena";
force_freqdet : string := "force_freqdet_dis";
func_mode : string := "disable";
pcie_gen3_cap : string := "non_pcie_gen3_cap";
pipe_if_g3pcs : string := "pipe_if_8gpcs";
pma_if_dft_en : string := "dft_dis";
pma_if_dft_val : string := "dft_0";
ppm_cnt_rst : string := "ppm_cnt_rst_dis";
ppm_deassert_early : string := "deassert_early_dis";
ppm_gen1_2_cnt : string := "cnt_32k";
ppm_post_eidle_delay : string := "cnt_200_cycles";
ppmsel : string := "ppmsel_default";
prot_mode : string := "disabled_prot_mode";
refclk_dig_sel : string := "refclk_dig_dis";
selectpcs : string := "eight_g_pcs";
sup_mode : string := "full_mode"
);
port (
fref : in std_logic;
clklow : in std_logic;
pmapcieswdone : in std_logic_vector(1 downto 0);
pmarxfound : in std_logic;
pmarxdetectvalid : in std_logic;
pmahclk : in std_logic;
pldoffcalen : in std_logic;
aggrcvdclkagg : in std_logic;
aggtxdatats : in std_logic_vector(7 downto 0);
aggtxctlts : in std_logic;
aggfiforstrdqd : in std_logic;
aggendskwqd : in std_logic;
aggendskwrdptrs : in std_logic;
aggalignstatus : in std_logic;
aggalignstatussync0 : in std_logic;
aggcgcomprddall : in std_logic;
aggcgcompwrall : in std_logic;
aggfifordincomp0 : in std_logic;
aggdelcondmet0 : in std_logic;
agginsertincomplete0 : in std_logic;
aggfifoovr0 : in std_logic;
agglatencycomp0 : in std_logic;
aggrxdatars : in std_logic_vector(7 downto 0);
aggrxcontrolrs : in std_logic;
aggrcvdclkaggtoporbot : in std_logic;
aggtxdatatstoporbot : in std_logic_vector(7 downto 0);
aggtxctltstoporbot : in std_logic;
aggfiforstrdqdtoporbot : in std_logic;
aggendskwqdtoporbot : in std_logic;
aggendskwrdptrstoporbot : in std_logic;
aggalignstatustoporbot : in std_logic;
aggalignstatussync0toporbot : in std_logic;
aggcgcomprddalltoporbot : in std_logic;
aggcgcompwralltoporbot : in std_logic;
aggfifordincomp0toporbot : in std_logic;
aggdelcondmet0toporbot : in std_logic;
agginsertincomplete0toporbot : in std_logic;
aggfifoovr0toporbot : in std_logic;
agglatencycomp0toporbot : in std_logic;
aggrxdatarstoporbot : in std_logic_vector(7 downto 0);
aggrxcontrolrstoporbot : in std_logic;
pcsgen3pmapcieswitch : in std_logic_vector(1 downto 0);
pcsgen3pmatxmargin : in std_logic_vector(2 downto 0);
pcsgen3pmatxdeemph : in std_logic;
pcsgen3pmatxswing : in std_logic;
pcsgen3pmacurrentcoeff : in std_logic_vector(17 downto 0);
pcsgen3pmacurrentrxpreset : in std_logic_vector(2 downto 0);
pcsgen3pmatxelecidle : in std_logic;
pcsgen3pmatxdetectrx : in std_logic;
pcsgen3ppmeidleexit : in std_logic;
pcsgen3pmaltr : in std_logic;
pcsgen3pmaearlyeios : in std_logic;
pcs8gpcieswitch : in std_logic;
pcs8gtxelecidle : in std_logic;
pcs8gtxdetectrx : in std_logic;
pcs8gearlyeios : in std_logic;
pcs8gtxdeemphpma : in std_logic;
pcs8gtxmarginpma : in std_logic_vector(2 downto 0);
pcs8gtxswingpma : in std_logic;
pcs8gltrpma : in std_logic;
pcs8geidleexit : in std_logic;
pcsaggtxpcsrst : in std_logic;
pcsaggrxpcsrst : in std_logic;
pcsaggtxdatatc : in std_logic_vector(7 downto 0);
pcsaggtxctltc : in std_logic;
pcsaggrdenablesync : in std_logic;
pcsaggsyncstatus : in std_logic;
pcsaggaligndetsync : in std_logic_vector(1 downto 0);
pcsaggrdalign : in std_logic_vector(1 downto 0);
pcsaggalignstatussync : in std_logic;
pcsaggfifordoutcomp : in std_logic;
pcsaggcgcomprddout : in std_logic_vector(1 downto 0);
pcsaggcgcompwrout : in std_logic_vector(1 downto 0);
pcsaggdelcondmetout : in std_logic;
pcsaggfifoovrout : in std_logic;
pcsagglatencycompout : in std_logic;
pcsagginsertincompleteout : in std_logic;
pcsaggdecdatavalid : in std_logic;
pcsaggdecdata : in std_logic_vector(7 downto 0);
pcsaggdecctl : in std_logic;
pcsaggrunningdisp : in std_logic_vector(1 downto 0);
pldrxclkslip : in std_logic;
pldhardreset : in std_logic;
pcsscanmoden : in std_logic;
pcsscanshiftn : in std_logic;
pcsrefclkdig : in std_logic;
pcsaggscanmoden : in std_logic;
pcsaggscanshiftn : in std_logic;
pcsaggrefclkdig : in std_logic;
pcsgen3gen3datasel : in std_logic;
pldlccmurstb : in std_logic;
pmaoffcaldonein : in std_logic;
pmarxpmarstb : in std_logic;
pmahardreset : out std_logic;
freqlock : out std_logic;
pmapcieswitch : out std_logic_vector(1 downto 0);
pmaearlyeios : out std_logic;
pmatxdetectrx : out std_logic;
pmatxelecidle : out std_logic;
pmatxdeemph : out std_logic;
pmatxswing : out std_logic;
pmatxmargin : out std_logic_vector(2 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmaoffcaldoneout : out std_logic;
pmalccmurstb : out std_logic;
pmaltr : out std_logic;
aggtxpcsrst : out std_logic;
aggrxpcsrst : out std_logic;
aggtxdatatc : out std_logic_vector(7 downto 0);
aggtxctltc : out std_logic;
aggrdenablesync : out std_logic;
aggsyncstatus : out std_logic;
aggaligndetsync : out std_logic_vector(1 downto 0);
aggrdalign : out std_logic_vector(1 downto 0);
aggalignstatussync : out std_logic;
aggfifordoutcomp : out std_logic;
aggcgcomprddout : out std_logic_vector(1 downto 0);
aggcgcompwrout : out std_logic_vector(1 downto 0);
aggdelcondmetout : out std_logic;
aggfifoovrout : out std_logic;
agglatencycompout : out std_logic;
agginsertincompleteout : out std_logic;
aggdecdatavalid : out std_logic;
aggdecdata : out std_logic_vector(7 downto 0);
aggdecctl : out std_logic;
aggrunningdisp : out std_logic_vector(1 downto 0);
pcsgen3pmarxdetectvalid : out std_logic;
pcsgen3pmarxfound : out std_logic;
pcsgen3pmapcieswdone : out std_logic_vector(1 downto 0);
pcsgen3pllfixedclk : out std_logic;
pcsaggrcvdclkagg : out std_logic;
pcsaggtxdatats : out std_logic_vector(7 downto 0);
pcsaggtxctlts : out std_logic;
pcsaggfiforstrdqd : out std_logic;
pcsaggendskwqd : out std_logic;
pcsaggendskwrdptrs : out std_logic;
pcsaggalignstatus : out std_logic;
pcsaggalignstatussync0 : out std_logic;
pcsaggcgcomprddall : out std_logic;
pcsaggcgcompwrall : out std_logic;
pcsaggfifordincomp0 : out std_logic;
pcsaggdelcondmet0 : out std_logic;
pcsagginsertincomplete0 : out std_logic;
pcsaggfifoovr0 : out std_logic;
pcsagglatencycomp0 : out std_logic;
pcsaggrxdatars : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrs : out std_logic;
pcsaggrcvdclkaggtoporbot : out std_logic;
pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0);
pcsaggtxctltstoporbot : out std_logic;
pcsaggfiforstrdqdtoporbot : out std_logic;
pcsaggendskwqdtoporbot : out std_logic;
pcsaggendskwrdptrstoporbot : out std_logic;
pcsaggalignstatustoporbot : out std_logic;
pcsaggalignstatussync0toporbot : out std_logic;
pcsaggcgcomprddalltoporbot : out std_logic;
pcsaggcgcompwralltoporbot : out std_logic;
pcsaggfifordincomp0toporbot : out std_logic;
pcsaggdelcondmet0toporbot : out std_logic;
pcsagginsertincomplete0toporbot : out std_logic;
pcsaggfifoovr0toporbot : out std_logic;
pcsagglatencycomp0toporbot : out std_logic;
pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrstoporbot : out std_logic;
pcs8grxdetectvalid : out std_logic;
pcs8gpmarxfound : out std_logic;
pcs8ggen2ngen1 : out std_logic;
pcs8gpowerstatetransitiondone : out std_logic;
ppmcntlatch : out std_logic_vector(7 downto 0);
pldhclkout : out std_logic;
aggscanmoden : out std_logic;
aggscanshiftn : out std_logic;
aggrefclkdig : out std_logic;
pmaoffcalen : out std_logic;
pmafrefout : out std_logic;
pmaclklowout : out std_logic
);
end stratixv_hssi_common_pcs_pma_interface;
architecture behavior of stratixv_hssi_common_pcs_pma_interface is
component stratixv_hssi_common_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_common_pcs_pma_interface";
auto_speed_ena : string := "dis_auto_speed_ena";
force_freqdet : string := "force_freqdet_dis";
func_mode : string := "disable";
pcie_gen3_cap : string := "non_pcie_gen3_cap";
pipe_if_g3pcs : string := "pipe_if_8gpcs";
pma_if_dft_en : string := "dft_dis";
pma_if_dft_val : string := "dft_0";
ppm_cnt_rst : string := "ppm_cnt_rst_dis";
ppm_deassert_early : string := "deassert_early_dis";
ppm_gen1_2_cnt : string := "cnt_32k";
ppm_post_eidle_delay : string := "cnt_200_cycles";
ppmsel : string := "ppmsel_default";
prot_mode : string := "disabled_prot_mode";
refclk_dig_sel : string := "refclk_dig_dis";
selectpcs : string := "eight_g_pcs";
sup_mode : string := "full_mode"
);
port (
fref : in std_logic;
clklow : in std_logic;
pmapcieswdone : in std_logic_vector(1 downto 0);
pmarxfound : in std_logic;
pmarxdetectvalid : in std_logic;
pmahclk : in std_logic;
pldoffcalen : in std_logic;
aggrcvdclkagg : in std_logic;
aggtxdatats : in std_logic_vector(7 downto 0);
aggtxctlts : in std_logic;
aggfiforstrdqd : in std_logic;
aggendskwqd : in std_logic;
aggendskwrdptrs : in std_logic;
aggalignstatus : in std_logic;
aggalignstatussync0 : in std_logic;
aggcgcomprddall : in std_logic;
aggcgcompwrall : in std_logic;
aggfifordincomp0 : in std_logic;
aggdelcondmet0 : in std_logic;
agginsertincomplete0 : in std_logic;
aggfifoovr0 : in std_logic;
agglatencycomp0 : in std_logic;
aggrxdatars : in std_logic_vector(7 downto 0);
aggrxcontrolrs : in std_logic;
aggrcvdclkaggtoporbot : in std_logic;
aggtxdatatstoporbot : in std_logic_vector(7 downto 0);
aggtxctltstoporbot : in std_logic;
aggfiforstrdqdtoporbot : in std_logic;
aggendskwqdtoporbot : in std_logic;
aggendskwrdptrstoporbot : in std_logic;
aggalignstatustoporbot : in std_logic;
aggalignstatussync0toporbot : in std_logic;
aggcgcomprddalltoporbot : in std_logic;
aggcgcompwralltoporbot : in std_logic;
aggfifordincomp0toporbot : in std_logic;
aggdelcondmet0toporbot : in std_logic;
agginsertincomplete0toporbot : in std_logic;
aggfifoovr0toporbot : in std_logic;
agglatencycomp0toporbot : in std_logic;
aggrxdatarstoporbot : in std_logic_vector(7 downto 0);
aggrxcontrolrstoporbot : in std_logic;
pcsgen3pmapcieswitch : in std_logic_vector(1 downto 0);
pcsgen3pmatxmargin : in std_logic_vector(2 downto 0);
pcsgen3pmatxdeemph : in std_logic;
pcsgen3pmatxswing : in std_logic;
pcsgen3pmacurrentcoeff : in std_logic_vector(17 downto 0);
pcsgen3pmacurrentrxpreset : in std_logic_vector(2 downto 0);
pcsgen3pmatxelecidle : in std_logic;
pcsgen3pmatxdetectrx : in std_logic;
pcsgen3ppmeidleexit : in std_logic;
pcsgen3pmaltr : in std_logic;
pcsgen3pmaearlyeios : in std_logic;
pcs8gpcieswitch : in std_logic;
pcs8gtxelecidle : in std_logic;
pcs8gtxdetectrx : in std_logic;
pcs8gearlyeios : in std_logic;
pcs8gtxdeemphpma : in std_logic;
pcs8gtxmarginpma : in std_logic_vector(2 downto 0);
pcs8gtxswingpma : in std_logic;
pcs8gltrpma : in std_logic;
pcs8geidleexit : in std_logic;
pcsaggtxpcsrst : in std_logic;
pcsaggrxpcsrst : in std_logic;
pcsaggtxdatatc : in std_logic_vector(7 downto 0);
pcsaggtxctltc : in std_logic;
pcsaggrdenablesync : in std_logic;
pcsaggsyncstatus : in std_logic;
pcsaggaligndetsync : in std_logic_vector(1 downto 0);
pcsaggrdalign : in std_logic_vector(1 downto 0);
pcsaggalignstatussync : in std_logic;
pcsaggfifordoutcomp : in std_logic;
pcsaggcgcomprddout : in std_logic_vector(1 downto 0);
pcsaggcgcompwrout : in std_logic_vector(1 downto 0);
pcsaggdelcondmetout : in std_logic;
pcsaggfifoovrout : in std_logic;
pcsagglatencycompout : in std_logic;
pcsagginsertincompleteout : in std_logic;
pcsaggdecdatavalid : in std_logic;
pcsaggdecdata : in std_logic_vector(7 downto 0);
pcsaggdecctl : in std_logic;
pcsaggrunningdisp : in std_logic_vector(1 downto 0);
pldrxclkslip : in std_logic;
pldhardreset : in std_logic;
pcsscanmoden : in std_logic;
pcsscanshiftn : in std_logic;
pcsrefclkdig : in std_logic;
pcsaggscanmoden : in std_logic;
pcsaggscanshiftn : in std_logic;
pcsaggrefclkdig : in std_logic;
pcsgen3gen3datasel : in std_logic;
pldlccmurstb : in std_logic;
pmaoffcaldonein : in std_logic;
pmarxpmarstb : in std_logic;
pmahardreset : out std_logic;
freqlock : out std_logic;
pmapcieswitch : out std_logic_vector(1 downto 0);
pmaearlyeios : out std_logic;
pmatxdetectrx : out std_logic;
pmatxelecidle : out std_logic;
pmatxdeemph : out std_logic;
pmatxswing : out std_logic;
pmatxmargin : out std_logic_vector(2 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmaoffcaldoneout : out std_logic;
pmalccmurstb : out std_logic;
pmaltr : out std_logic;
aggtxpcsrst : out std_logic;
aggrxpcsrst : out std_logic;
aggtxdatatc : out std_logic_vector(7 downto 0);
aggtxctltc : out std_logic;
aggrdenablesync : out std_logic;
aggsyncstatus : out std_logic;
aggaligndetsync : out std_logic_vector(1 downto 0);
aggrdalign : out std_logic_vector(1 downto 0);
aggalignstatussync : out std_logic;
aggfifordoutcomp : out std_logic;
aggcgcomprddout : out std_logic_vector(1 downto 0);
aggcgcompwrout : out std_logic_vector(1 downto 0);
aggdelcondmetout : out std_logic;
aggfifoovrout : out std_logic;
agglatencycompout : out std_logic;
agginsertincompleteout : out std_logic;
aggdecdatavalid : out std_logic;
aggdecdata : out std_logic_vector(7 downto 0);
aggdecctl : out std_logic;
aggrunningdisp : out std_logic_vector(1 downto 0);
pcsgen3pmarxdetectvalid : out std_logic;
pcsgen3pmarxfound : out std_logic;
pcsgen3pmapcieswdone : out std_logic_vector(1 downto 0);
pcsgen3pllfixedclk : out std_logic;
pcsaggrcvdclkagg : out std_logic;
pcsaggtxdatats : out std_logic_vector(7 downto 0);
pcsaggtxctlts : out std_logic;
pcsaggfiforstrdqd : out std_logic;
pcsaggendskwqd : out std_logic;
pcsaggendskwrdptrs : out std_logic;
pcsaggalignstatus : out std_logic;
pcsaggalignstatussync0 : out std_logic;
pcsaggcgcomprddall : out std_logic;
pcsaggcgcompwrall : out std_logic;
pcsaggfifordincomp0 : out std_logic;
pcsaggdelcondmet0 : out std_logic;
pcsagginsertincomplete0 : out std_logic;
pcsaggfifoovr0 : out std_logic;
pcsagglatencycomp0 : out std_logic;
pcsaggrxdatars : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrs : out std_logic;
pcsaggrcvdclkaggtoporbot : out std_logic;
pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0);
pcsaggtxctltstoporbot : out std_logic;
pcsaggfiforstrdqdtoporbot : out std_logic;
pcsaggendskwqdtoporbot : out std_logic;
pcsaggendskwrdptrstoporbot : out std_logic;
pcsaggalignstatustoporbot : out std_logic;
pcsaggalignstatussync0toporbot : out std_logic;
pcsaggcgcomprddalltoporbot : out std_logic;
pcsaggcgcompwralltoporbot : out std_logic;
pcsaggfifordincomp0toporbot : out std_logic;
pcsaggdelcondmet0toporbot : out std_logic;
pcsagginsertincomplete0toporbot : out std_logic;
pcsaggfifoovr0toporbot : out std_logic;
pcsagglatencycomp0toporbot : out std_logic;
pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrstoporbot : out std_logic;
pcs8grxdetectvalid : out std_logic;
pcs8gpmarxfound : out std_logic;
pcs8ggen2ngen1 : out std_logic;
pcs8gpowerstatetransitiondone : out std_logic;
ppmcntlatch : out std_logic_vector(7 downto 0);
pldhclkout : out std_logic;
aggscanmoden : out std_logic;
aggscanshiftn : out std_logic;
aggrefclkdig : out std_logic;
pmaoffcalen : out std_logic;
pmafrefout : out std_logic;
pmaclklowout : out std_logic
);
end component;
begin
inst : stratixv_hssi_common_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
auto_speed_ena => auto_speed_ena,
force_freqdet => force_freqdet,
func_mode => func_mode,
pcie_gen3_cap => pcie_gen3_cap,
pipe_if_g3pcs => pipe_if_g3pcs,
pma_if_dft_en => pma_if_dft_en,
pma_if_dft_val => pma_if_dft_val,
ppm_cnt_rst => ppm_cnt_rst,
ppm_deassert_early => ppm_deassert_early,
ppm_gen1_2_cnt => ppm_gen1_2_cnt,
ppm_post_eidle_delay => ppm_post_eidle_delay,
ppmsel => ppmsel,
prot_mode => prot_mode,
refclk_dig_sel => refclk_dig_sel,
selectpcs => selectpcs,
sup_mode => sup_mode
)
port map (
fref => fref,
clklow => clklow,
pmapcieswdone => pmapcieswdone,
pmarxfound => pmarxfound,
pmarxdetectvalid => pmarxdetectvalid,
pmahclk => pmahclk,
pldoffcalen => pldoffcalen,
aggrcvdclkagg => aggrcvdclkagg,
aggtxdatats => aggtxdatats,
aggtxctlts => aggtxctlts,
aggfiforstrdqd => aggfiforstrdqd,
aggendskwqd => aggendskwqd,
aggendskwrdptrs => aggendskwrdptrs,
aggalignstatus => aggalignstatus,
aggalignstatussync0 => aggalignstatussync0,
aggcgcomprddall => aggcgcomprddall,
aggcgcompwrall => aggcgcompwrall,
aggfifordincomp0 => aggfifordincomp0,
aggdelcondmet0 => aggdelcondmet0,
agginsertincomplete0 => agginsertincomplete0,
aggfifoovr0 => aggfifoovr0,
agglatencycomp0 => agglatencycomp0,
aggrxdatars => aggrxdatars,
aggrxcontrolrs => aggrxcontrolrs,
aggrcvdclkaggtoporbot => aggrcvdclkaggtoporbot,
aggtxdatatstoporbot => aggtxdatatstoporbot,
aggtxctltstoporbot => aggtxctltstoporbot,
aggfiforstrdqdtoporbot => aggfiforstrdqdtoporbot,
aggendskwqdtoporbot => aggendskwqdtoporbot,
aggendskwrdptrstoporbot => aggendskwrdptrstoporbot,
aggalignstatustoporbot => aggalignstatustoporbot,
aggalignstatussync0toporbot => aggalignstatussync0toporbot,
aggcgcomprddalltoporbot => aggcgcomprddalltoporbot,
aggcgcompwralltoporbot => aggcgcompwralltoporbot,
aggfifordincomp0toporbot => aggfifordincomp0toporbot,
aggdelcondmet0toporbot => aggdelcondmet0toporbot,
agginsertincomplete0toporbot => agginsertincomplete0toporbot,
aggfifoovr0toporbot => aggfifoovr0toporbot,
agglatencycomp0toporbot => agglatencycomp0toporbot,
aggrxdatarstoporbot => aggrxdatarstoporbot,
aggrxcontrolrstoporbot => aggrxcontrolrstoporbot,
pcsgen3pmapcieswitch => pcsgen3pmapcieswitch,
pcsgen3pmatxmargin => pcsgen3pmatxmargin,
pcsgen3pmatxdeemph => pcsgen3pmatxdeemph,
pcsgen3pmatxswing => pcsgen3pmatxswing,
pcsgen3pmacurrentcoeff => pcsgen3pmacurrentcoeff,
pcsgen3pmacurrentrxpreset => pcsgen3pmacurrentrxpreset,
pcsgen3pmatxelecidle => pcsgen3pmatxelecidle,
pcsgen3pmatxdetectrx => pcsgen3pmatxdetectrx,
pcsgen3ppmeidleexit => pcsgen3ppmeidleexit,
pcsgen3pmaltr => pcsgen3pmaltr,
pcsgen3pmaearlyeios => pcsgen3pmaearlyeios,
pcs8gpcieswitch => pcs8gpcieswitch,
pcs8gtxelecidle => pcs8gtxelecidle,
pcs8gtxdetectrx => pcs8gtxdetectrx,
pcs8gearlyeios => pcs8gearlyeios,
pcs8gtxdeemphpma => pcs8gtxdeemphpma,
pcs8gtxmarginpma => pcs8gtxmarginpma,
pcs8gtxswingpma => pcs8gtxswingpma,
pcs8gltrpma => pcs8gltrpma,
pcs8geidleexit => pcs8geidleexit,
pcsaggtxpcsrst => pcsaggtxpcsrst,
pcsaggrxpcsrst => pcsaggrxpcsrst,
pcsaggtxdatatc => pcsaggtxdatatc,
pcsaggtxctltc => pcsaggtxctltc,
pcsaggrdenablesync => pcsaggrdenablesync,
pcsaggsyncstatus => pcsaggsyncstatus,
pcsaggaligndetsync => pcsaggaligndetsync,
pcsaggrdalign => pcsaggrdalign,
pcsaggalignstatussync => pcsaggalignstatussync,
pcsaggfifordoutcomp => pcsaggfifordoutcomp,
pcsaggcgcomprddout => pcsaggcgcomprddout,
pcsaggcgcompwrout => pcsaggcgcompwrout,
pcsaggdelcondmetout => pcsaggdelcondmetout,
pcsaggfifoovrout => pcsaggfifoovrout,
pcsagglatencycompout => pcsagglatencycompout,
pcsagginsertincompleteout => pcsagginsertincompleteout,
pcsaggdecdatavalid => pcsaggdecdatavalid,
pcsaggdecdata => pcsaggdecdata,
pcsaggdecctl => pcsaggdecctl,
pcsaggrunningdisp => pcsaggrunningdisp,
pldrxclkslip => pldrxclkslip,
pldhardreset => pldhardreset,
pcsscanmoden => pcsscanmoden,
pcsscanshiftn => pcsscanshiftn,
pcsrefclkdig => pcsrefclkdig,
pcsaggscanmoden => pcsaggscanmoden,
pcsaggscanshiftn => pcsaggscanshiftn,
pcsaggrefclkdig => pcsaggrefclkdig,
pcsgen3gen3datasel => pcsgen3gen3datasel,
pldlccmurstb => pldlccmurstb,
pmaoffcaldonein => pmaoffcaldonein,
pmarxpmarstb => pmarxpmarstb,
pmahardreset => pmahardreset,
freqlock => freqlock,
pmapcieswitch => pmapcieswitch,
pmaearlyeios => pmaearlyeios,
pmatxdetectrx => pmatxdetectrx,
pmatxelecidle => pmatxelecidle,
pmatxdeemph => pmatxdeemph,
pmatxswing => pmatxswing,
pmatxmargin => pmatxmargin,
pmacurrentcoeff => pmacurrentcoeff,
pmacurrentrxpreset => pmacurrentrxpreset,
pmaoffcaldoneout => pmaoffcaldoneout,
pmalccmurstb => pmalccmurstb,
pmaltr => pmaltr,
aggtxpcsrst => aggtxpcsrst,
aggrxpcsrst => aggrxpcsrst,
aggtxdatatc => aggtxdatatc,
aggtxctltc => aggtxctltc,
aggrdenablesync => aggrdenablesync,
aggsyncstatus => aggsyncstatus,
aggaligndetsync => aggaligndetsync,
aggrdalign => aggrdalign,
aggalignstatussync => aggalignstatussync,
aggfifordoutcomp => aggfifordoutcomp,
aggcgcomprddout => aggcgcomprddout,
aggcgcompwrout => aggcgcompwrout,
aggdelcondmetout => aggdelcondmetout,
aggfifoovrout => aggfifoovrout,
agglatencycompout => agglatencycompout,
agginsertincompleteout => agginsertincompleteout,
aggdecdatavalid => aggdecdatavalid,
aggdecdata => aggdecdata,
aggdecctl => aggdecctl,
aggrunningdisp => aggrunningdisp,
pcsgen3pmarxdetectvalid => pcsgen3pmarxdetectvalid,
pcsgen3pmarxfound => pcsgen3pmarxfound,
pcsgen3pmapcieswdone => pcsgen3pmapcieswdone,
pcsgen3pllfixedclk => pcsgen3pllfixedclk,
pcsaggrcvdclkagg => pcsaggrcvdclkagg,
pcsaggtxdatats => pcsaggtxdatats,
pcsaggtxctlts => pcsaggtxctlts,
pcsaggfiforstrdqd => pcsaggfiforstrdqd,
pcsaggendskwqd => pcsaggendskwqd,
pcsaggendskwrdptrs => pcsaggendskwrdptrs,
pcsaggalignstatus => pcsaggalignstatus,
pcsaggalignstatussync0 => pcsaggalignstatussync0,
pcsaggcgcomprddall => pcsaggcgcomprddall,
pcsaggcgcompwrall => pcsaggcgcompwrall,
pcsaggfifordincomp0 => pcsaggfifordincomp0,
pcsaggdelcondmet0 => pcsaggdelcondmet0,
pcsagginsertincomplete0 => pcsagginsertincomplete0,
pcsaggfifoovr0 => pcsaggfifoovr0,
pcsagglatencycomp0 => pcsagglatencycomp0,
pcsaggrxdatars => pcsaggrxdatars,
pcsaggrxcontrolrs => pcsaggrxcontrolrs,
pcsaggrcvdclkaggtoporbot => pcsaggrcvdclkaggtoporbot,
pcsaggtxdatatstoporbot => pcsaggtxdatatstoporbot,
pcsaggtxctltstoporbot => pcsaggtxctltstoporbot,
pcsaggfiforstrdqdtoporbot => pcsaggfiforstrdqdtoporbot,
pcsaggendskwqdtoporbot => pcsaggendskwqdtoporbot,
pcsaggendskwrdptrstoporbot => pcsaggendskwrdptrstoporbot,
pcsaggalignstatustoporbot => pcsaggalignstatustoporbot,
pcsaggalignstatussync0toporbot => pcsaggalignstatussync0toporbot,
pcsaggcgcomprddalltoporbot => pcsaggcgcomprddalltoporbot,
pcsaggcgcompwralltoporbot => pcsaggcgcompwralltoporbot,
pcsaggfifordincomp0toporbot => pcsaggfifordincomp0toporbot,
pcsaggdelcondmet0toporbot => pcsaggdelcondmet0toporbot,
pcsagginsertincomplete0toporbot => pcsagginsertincomplete0toporbot,
pcsaggfifoovr0toporbot => pcsaggfifoovr0toporbot,
pcsagglatencycomp0toporbot => pcsagglatencycomp0toporbot,
pcsaggrxdatarstoporbot => pcsaggrxdatarstoporbot,
pcsaggrxcontrolrstoporbot => pcsaggrxcontrolrstoporbot,
pcs8grxdetectvalid => pcs8grxdetectvalid,
pcs8gpmarxfound => pcs8gpmarxfound,
pcs8ggen2ngen1 => pcs8ggen2ngen1,
pcs8gpowerstatetransitiondone => pcs8gpowerstatetransitiondone,
ppmcntlatch => ppmcntlatch,
pldhclkout => pldhclkout,
aggscanmoden => aggscanmoden,
aggscanshiftn => aggscanshiftn,
aggrefclkdig => aggrefclkdig,
pmaoffcalen => pmaoffcalen,
pmafrefout => pmafrefout,
pmaclklowout => pmaclklowout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_common_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_common_pld_pcs_interface";
data_source : string := "pld";
emsip_enable : string := "emsip_disable";
selectpcs : string := "eight_g_pcs"
);
port (
pldhardresetin : in std_logic;
pldscanmoden : in std_logic;
pldscanshiftn : in std_logic;
pldgen3refclkdig : in std_logic;
pld10grefclkdig : in std_logic;
pld8grefclkdig : in std_logic;
pldaggrefclkdig : in std_logic;
pldpcspmaifrefclkdig : in std_logic;
pldrate : in std_logic_vector(1 downto 0);
pldeidleinfersel : in std_logic_vector(2 downto 0);
pld8gsoftresetallhssi : in std_logic;
pld8gplniotri : in std_logic;
pld8gprbsciden : in std_logic;
pld8gltr : in std_logic;
pld8gtxelecidle : in std_logic;
pld8gtxdetectrxloopback : in std_logic;
pld8gtxdeemph : in std_logic;
pld8gtxmargin : in std_logic_vector(2 downto 0);
pld8gtxswing : in std_logic;
pld8grxpolarity : in std_logic;
pld8gpowerdown : in std_logic_vector(1 downto 0);
pldgen3currentcoeff : in std_logic_vector(17 downto 0);
pldgen3currentrxpreset : in std_logic_vector(2 downto 0);
pcs10gtestdata : in std_logic_vector(19 downto 0);
pcs8gchnltestbusout : in std_logic_vector(9 downto 0);
pcs8grxvalid : in std_logic;
pcs8grxelecidle : in std_logic;
pcs8grxstatus : in std_logic_vector(2 downto 0);
pcs8gphystatus : in std_logic;
pldhclkin : in std_logic;
pcsgen3pldasyncstatus : in std_logic_vector(5 downto 0);
pcsgen3testout : in std_logic_vector(19 downto 0);
emsippcsreset : in std_logic_vector(2 downto 0);
emsippcsctrl : in std_logic_vector(38 downto 0);
pmafref : in std_logic;
pmaclklow : in std_logic;
pmaoffcaldone : in std_logic;
pldoffcalenin : in std_logic;
pcsgen3masktxpll : in std_logic;
rcomemsip : in std_logic;
rcomhipena : in std_logic;
rcomblocksel : in std_logic_vector(1 downto 0);
pldtestdata : out std_logic_vector(19 downto 0);
pld8grxvalid : out std_logic;
pld8grxelecidle : out std_logic;
pld8grxstatus : out std_logic_vector(2 downto 0);
pld8gphystatus : out std_logic;
pldgen3pldasyncstatus : out std_logic_vector(5 downto 0);
pcs10ghardresetn : out std_logic;
pcs10gscanmoden : out std_logic;
pcs10gscanshiftn : out std_logic;
pcs10grefclkdig : out std_logic;
pcs8ghardreset : out std_logic;
pcs8gsoftresetallhssi : out std_logic;
pcs8gplniotri : out std_logic;
pcs8gscanmoden : out std_logic;
pcs8gscanshiftn : out std_logic;
pcs8grefclkdig : out std_logic;
pcs8gprbsciden : out std_logic;
pcs8gltr : out std_logic;
pcs8gtxelecidle : out std_logic;
pcs8gtxdetectrxloopback : out std_logic;
pcs8gtxdeemph : out std_logic;
pcs8gtxmargin : out std_logic_vector(2 downto 0);
pcs8gtxswing : out std_logic;
pcs8grxpolarity : out std_logic;
pcs8grate : out std_logic;
pcs8gpowerdown : out std_logic_vector(1 downto 0);
pcs8geidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3pcsdigclk : out std_logic;
pcsgen3rate : out std_logic_vector(1 downto 0);
pcsgen3eidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3scanmoden : out std_logic;
pcsgen3scanshiftn : out std_logic;
pcsgen3pldltr : out std_logic;
pldhardresetout : out std_logic;
pcsgen3currentcoeff : out std_logic_vector(17 downto 0);
pcsgen3currentrxpreset : out std_logic_vector(2 downto 0);
pcsaggrefclkdig : out std_logic;
pcspcspmaifrefclkdig : out std_logic;
pcsaggscanmoden : out std_logic;
pcsaggscanshiftn : out std_logic;
pcspcspmaifscanmoden : out std_logic;
pcspcspmaifscanshiftn : out std_logic;
emsippcsclkout : out std_logic_vector(2 downto 0);
emsippcsstatus : out std_logic_vector(13 downto 0);
pldfref : out std_logic;
pldclklow : out std_logic;
emsipenabledusermode : out std_logic;
pldoffcalenout : out std_logic;
pldoffcaldone : out std_logic;
pldgen3masktxpll : out std_logic
);
end stratixv_hssi_common_pld_pcs_interface;
architecture behavior of stratixv_hssi_common_pld_pcs_interface is
component stratixv_hssi_common_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_common_pld_pcs_interface";
data_source : string := "pld";
emsip_enable : string := "emsip_disable";
selectpcs : string := "eight_g_pcs"
);
port (
pldhardresetin : in std_logic;
pldscanmoden : in std_logic;
pldscanshiftn : in std_logic;
pldgen3refclkdig : in std_logic;
pld10grefclkdig : in std_logic;
pld8grefclkdig : in std_logic;
pldaggrefclkdig : in std_logic;
pldpcspmaifrefclkdig : in std_logic;
pldrate : in std_logic_vector(1 downto 0);
pldeidleinfersel : in std_logic_vector(2 downto 0);
pld8gsoftresetallhssi : in std_logic;
pld8gplniotri : in std_logic;
pld8gprbsciden : in std_logic;
pld8gltr : in std_logic;
pld8gtxelecidle : in std_logic;
pld8gtxdetectrxloopback : in std_logic;
pld8gtxdeemph : in std_logic;
pld8gtxmargin : in std_logic_vector(2 downto 0);
pld8gtxswing : in std_logic;
pld8grxpolarity : in std_logic;
pld8gpowerdown : in std_logic_vector(1 downto 0);
pldgen3currentcoeff : in std_logic_vector(17 downto 0);
pldgen3currentrxpreset : in std_logic_vector(2 downto 0);
pcs10gtestdata : in std_logic_vector(19 downto 0);
pcs8gchnltestbusout : in std_logic_vector(9 downto 0);
pcs8grxvalid : in std_logic;
pcs8grxelecidle : in std_logic;
pcs8grxstatus : in std_logic_vector(2 downto 0);
pcs8gphystatus : in std_logic;
pldhclkin : in std_logic;
pcsgen3pldasyncstatus : in std_logic_vector(5 downto 0);
pcsgen3testout : in std_logic_vector(19 downto 0);
emsippcsreset : in std_logic_vector(2 downto 0);
emsippcsctrl : in std_logic_vector(38 downto 0);
pmafref : in std_logic;
pmaclklow : in std_logic;
pmaoffcaldone : in std_logic;
pldoffcalenin : in std_logic;
pcsgen3masktxpll : in std_logic;
rcomemsip : in std_logic;
rcomhipena : in std_logic;
rcomblocksel : in std_logic_vector(1 downto 0);
pldtestdata : out std_logic_vector(19 downto 0);
pld8grxvalid : out std_logic;
pld8grxelecidle : out std_logic;
pld8grxstatus : out std_logic_vector(2 downto 0);
pld8gphystatus : out std_logic;
pldgen3pldasyncstatus : out std_logic_vector(5 downto 0);
pcs10ghardresetn : out std_logic;
pcs10gscanmoden : out std_logic;
pcs10gscanshiftn : out std_logic;
pcs10grefclkdig : out std_logic;
pcs8ghardreset : out std_logic;
pcs8gsoftresetallhssi : out std_logic;
pcs8gplniotri : out std_logic;
pcs8gscanmoden : out std_logic;
pcs8gscanshiftn : out std_logic;
pcs8grefclkdig : out std_logic;
pcs8gprbsciden : out std_logic;
pcs8gltr : out std_logic;
pcs8gtxelecidle : out std_logic;
pcs8gtxdetectrxloopback : out std_logic;
pcs8gtxdeemph : out std_logic;
pcs8gtxmargin : out std_logic_vector(2 downto 0);
pcs8gtxswing : out std_logic;
pcs8grxpolarity : out std_logic;
pcs8grate : out std_logic;
pcs8gpowerdown : out std_logic_vector(1 downto 0);
pcs8geidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3pcsdigclk : out std_logic;
pcsgen3rate : out std_logic_vector(1 downto 0);
pcsgen3eidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3scanmoden : out std_logic;
pcsgen3scanshiftn : out std_logic;
pcsgen3pldltr : out std_logic;
pldhardresetout : out std_logic;
pcsgen3currentcoeff : out std_logic_vector(17 downto 0);
pcsgen3currentrxpreset : out std_logic_vector(2 downto 0);
pcsaggrefclkdig : out std_logic;
pcspcspmaifrefclkdig : out std_logic;
pcsaggscanmoden : out std_logic;
pcsaggscanshiftn : out std_logic;
pcspcspmaifscanmoden : out std_logic;
pcspcspmaifscanshiftn : out std_logic;
emsippcsclkout : out std_logic_vector(2 downto 0);
emsippcsstatus : out std_logic_vector(13 downto 0);
pldfref : out std_logic;
pldclklow : out std_logic;
emsipenabledusermode : out std_logic;
pldoffcalenout : out std_logic;
pldoffcaldone : out std_logic;
pldgen3masktxpll : out std_logic
);
end component;
begin
inst : stratixv_hssi_common_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
emsip_enable => emsip_enable,
selectpcs => selectpcs
)
port map (
pldhardresetin => pldhardresetin,
pldscanmoden => pldscanmoden,
pldscanshiftn => pldscanshiftn,
pldgen3refclkdig => pldgen3refclkdig,
pld10grefclkdig => pld10grefclkdig,
pld8grefclkdig => pld8grefclkdig,
pldaggrefclkdig => pldaggrefclkdig,
pldpcspmaifrefclkdig => pldpcspmaifrefclkdig,
pldrate => pldrate,
pldeidleinfersel => pldeidleinfersel,
pld8gsoftresetallhssi => pld8gsoftresetallhssi,
pld8gplniotri => pld8gplniotri,
pld8gprbsciden => pld8gprbsciden,
pld8gltr => pld8gltr,
pld8gtxelecidle => pld8gtxelecidle,
pld8gtxdetectrxloopback => pld8gtxdetectrxloopback,
pld8gtxdeemph => pld8gtxdeemph,
pld8gtxmargin => pld8gtxmargin,
pld8gtxswing => pld8gtxswing,
pld8grxpolarity => pld8grxpolarity,
pld8gpowerdown => pld8gpowerdown,
pldgen3currentcoeff => pldgen3currentcoeff,
pldgen3currentrxpreset => pldgen3currentrxpreset,
pcs10gtestdata => pcs10gtestdata,
pcs8gchnltestbusout => pcs8gchnltestbusout,
pcs8grxvalid => pcs8grxvalid,
pcs8grxelecidle => pcs8grxelecidle,
pcs8grxstatus => pcs8grxstatus,
pcs8gphystatus => pcs8gphystatus,
pldhclkin => pldhclkin,
pcsgen3pldasyncstatus => pcsgen3pldasyncstatus,
pcsgen3testout => pcsgen3testout,
emsippcsreset => emsippcsreset,
emsippcsctrl => emsippcsctrl,
pmafref => pmafref,
pmaclklow => pmaclklow,
pmaoffcaldone => pmaoffcaldone,
pldoffcalenin => pldoffcalenin,
pcsgen3masktxpll => pcsgen3masktxpll,
rcomemsip => rcomemsip,
rcomhipena => rcomhipena,
rcomblocksel => rcomblocksel,
pldtestdata => pldtestdata,
pld8grxvalid => pld8grxvalid,
pld8grxelecidle => pld8grxelecidle,
pld8grxstatus => pld8grxstatus,
pld8gphystatus => pld8gphystatus,
pldgen3pldasyncstatus => pldgen3pldasyncstatus,
pcs10ghardresetn => pcs10ghardresetn,
pcs10gscanmoden => pcs10gscanmoden,
pcs10gscanshiftn => pcs10gscanshiftn,
pcs10grefclkdig => pcs10grefclkdig,
pcs8ghardreset => pcs8ghardreset,
pcs8gsoftresetallhssi => pcs8gsoftresetallhssi,
pcs8gplniotri => pcs8gplniotri,
pcs8gscanmoden => pcs8gscanmoden,
pcs8gscanshiftn => pcs8gscanshiftn,
pcs8grefclkdig => pcs8grefclkdig,
pcs8gprbsciden => pcs8gprbsciden,
pcs8gltr => pcs8gltr,
pcs8gtxelecidle => pcs8gtxelecidle,
pcs8gtxdetectrxloopback => pcs8gtxdetectrxloopback,
pcs8gtxdeemph => pcs8gtxdeemph,
pcs8gtxmargin => pcs8gtxmargin,
pcs8gtxswing => pcs8gtxswing,
pcs8grxpolarity => pcs8grxpolarity,
pcs8grate => pcs8grate,
pcs8gpowerdown => pcs8gpowerdown,
pcs8geidleinfersel => pcs8geidleinfersel,
pcsgen3pcsdigclk => pcsgen3pcsdigclk,
pcsgen3rate => pcsgen3rate,
pcsgen3eidleinfersel => pcsgen3eidleinfersel,
pcsgen3scanmoden => pcsgen3scanmoden,
pcsgen3scanshiftn => pcsgen3scanshiftn,
pcsgen3pldltr => pcsgen3pldltr,
pldhardresetout => pldhardresetout,
pcsgen3currentcoeff => pcsgen3currentcoeff,
pcsgen3currentrxpreset => pcsgen3currentrxpreset,
pcsaggrefclkdig => pcsaggrefclkdig,
pcspcspmaifrefclkdig => pcspcspmaifrefclkdig,
pcsaggscanmoden => pcsaggscanmoden,
pcsaggscanshiftn => pcsaggscanshiftn,
pcspcspmaifscanmoden => pcspcspmaifscanmoden,
pcspcspmaifscanshiftn => pcspcspmaifscanshiftn,
emsippcsclkout => emsippcsclkout,
emsippcsstatus => emsippcsstatus,
pldfref => pldfref,
pldclklow => pldclklow,
emsipenabledusermode => emsipenabledusermode,
pldoffcalenout => pldoffcalenout,
pldoffcaldone => pldoffcaldone,
pldgen3masktxpll => pldgen3masktxpll
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_rx_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_rx_pcs_pma_interface";
clkslip_sel : string := "pld";
prot_mode : string := "other_protocols";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrompma : in std_logic_vector(39 downto 0);
pmasigdet : in std_logic;
pmasignalok : in std_logic;
pcs10grxclkiqout : in std_logic;
pcsgen3rxclkiqout : in std_logic;
pcs8grxclkiqout : in std_logic;
pcs8grxclkslip : in std_logic;
pmaclkdiv33txorrxin : in std_logic;
pmarxplllockin : in std_logic;
pldrxpmarstb : in std_logic;
pldrxclkslip : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxclkslipsel : in std_logic;
pmarxclkslip : out std_logic;
pmarxclkout : out std_logic;
clkoutto10gpcs : out std_logic;
dataoutto10gpcs : out std_logic_vector(39 downto 0);
pcs10gsignalok : out std_logic;
clockouttogen3pcs : out std_logic;
dataouttogen3pcs : out std_logic_vector(31 downto 0);
pcsgen3pmasignaldet : out std_logic;
clockoutto8gpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(19 downto 0);
pcs8gsigdetni : out std_logic;
pmaclkdiv33txorrxout : out std_logic;
pcs10gclkdiv33txorrx : out std_logic;
pmarxpmarstb : out std_logic;
pmarxplllockout : out std_logic
);
end stratixv_hssi_rx_pcs_pma_interface;
architecture behavior of stratixv_hssi_rx_pcs_pma_interface is
component stratixv_hssi_rx_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_rx_pcs_pma_interface";
clkslip_sel : string := "pld";
prot_mode : string := "other_protocols";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrompma : in std_logic_vector(39 downto 0);
pmasigdet : in std_logic;
pmasignalok : in std_logic;
pcs10grxclkiqout : in std_logic;
pcsgen3rxclkiqout : in std_logic;
pcs8grxclkiqout : in std_logic;
pcs8grxclkslip : in std_logic;
pmaclkdiv33txorrxin : in std_logic;
pmarxplllockin : in std_logic;
pldrxpmarstb : in std_logic;
pldrxclkslip : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxclkslipsel : in std_logic;
pmarxclkslip : out std_logic;
pmarxclkout : out std_logic;
clkoutto10gpcs : out std_logic;
dataoutto10gpcs : out std_logic_vector(39 downto 0);
pcs10gsignalok : out std_logic;
clockouttogen3pcs : out std_logic;
dataouttogen3pcs : out std_logic_vector(31 downto 0);
pcsgen3pmasignaldet : out std_logic;
clockoutto8gpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(19 downto 0);
pcs8gsigdetni : out std_logic;
pmaclkdiv33txorrxout : out std_logic;
pcs10gclkdiv33txorrx : out std_logic;
pmarxpmarstb : out std_logic;
pmarxplllockout : out std_logic
);
end component;
begin
inst : stratixv_hssi_rx_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
clkslip_sel => clkslip_sel,
prot_mode => prot_mode,
selectpcs => selectpcs
)
port map (
clockinfrompma => clockinfrompma,
datainfrompma => datainfrompma,
pmasigdet => pmasigdet,
pmasignalok => pmasignalok,
pcs10grxclkiqout => pcs10grxclkiqout,
pcsgen3rxclkiqout => pcsgen3rxclkiqout,
pcs8grxclkiqout => pcs8grxclkiqout,
pcs8grxclkslip => pcs8grxclkslip,
pmaclkdiv33txorrxin => pmaclkdiv33txorrxin,
pmarxplllockin => pmarxplllockin,
pldrxpmarstb => pldrxpmarstb,
pldrxclkslip => pldrxclkslip,
rrxblocksel => rrxblocksel,
rrxclkslipsel => rrxclkslipsel,
pmarxclkslip => pmarxclkslip,
pmarxclkout => pmarxclkout,
clkoutto10gpcs => clkoutto10gpcs,
dataoutto10gpcs => dataoutto10gpcs,
pcs10gsignalok => pcs10gsignalok,
clockouttogen3pcs => clockouttogen3pcs,
dataouttogen3pcs => dataouttogen3pcs,
pcsgen3pmasignaldet => pcsgen3pmasignaldet,
clockoutto8gpcs => clockoutto8gpcs,
dataoutto8gpcs => dataoutto8gpcs,
pcs8gsigdetni => pcs8gsigdetni,
pmaclkdiv33txorrxout => pmaclkdiv33txorrxout,
pcs10gclkdiv33txorrx => pcs10gclkdiv33txorrx,
pmarxpmarstb => pmarxpmarstb,
pmarxplllockout => pmarxplllockout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_rx_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_rx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false";
selectpcs : string := "eight_g_pcs"
);
port (
pld10grxpldclk : in std_logic;
pld10grxpldrstn : in std_logic;
pld10grxalignen : in std_logic;
pld10grxalignclr : in std_logic;
pld10grxrden : in std_logic;
pld10grxdispclr : in std_logic;
pld10grxclrerrblkcnt : in std_logic;
pld10grxclrbercount : in std_logic;
pld10grxprbserrclr : in std_logic;
pld10grxbitslip : in std_logic;
pld8grxurstpma : in std_logic;
pld8grxurstpcs : in std_logic;
pld8gcmpfifourst : in std_logic;
pld8gphfifourstrx : in std_logic;
pld8gencdt : in std_logic;
pld8ga1a2size : in std_logic;
pld8gbitslip : in std_logic;
pld8grdenablermf : in std_logic;
pld8gwrenablermf : in std_logic;
pld8gpldrxclk : in std_logic;
pld8gpolinvrx : in std_logic;
pld8gbitlocreven : in std_logic;
pld8gbytereven : in std_logic;
pld8gbytordpld : in std_logic;
pld8gwrdisablerx : in std_logic;
pld8grdenablerx : in std_logic;
pldgen3rxrstn : in std_logic;
pldrxclkslipin : in std_logic;
pld8gpldextrain : in std_logic_vector(3 downto 0);
clockinfrom10gpcs : in std_logic;
pcs10grxdatavalid : in std_logic;
datainfrom10gpcs : in std_logic_vector(63 downto 0);
pcs10grxcontrol : in std_logic_vector(9 downto 0);
pcs10grxempty : in std_logic;
pcs10grxpempty : in std_logic;
pcs10grxpfull : in std_logic;
pcs10grxoflwerr : in std_logic;
pcs10grxalignval : in std_logic;
pcs10grxblklock : in std_logic;
pcs10grxhiber : in std_logic;
pcs10grxframelock : in std_logic;
pcs10grxrdpossts : in std_logic;
pcs10grxrdnegsts : in std_logic;
pcs10grxskipins : in std_logic;
pcs10grxrxframe : in std_logic;
pcs10grxpyldins : in std_logic;
pcs10grxsyncerr : in std_logic;
pcs10grxscrmerr : in std_logic;
pcs10grxskiperr : in std_logic;
pcs10grxdiagerr : in std_logic;
pcs10grxsherr : in std_logic;
pcs10grxmfrmerr : in std_logic;
pcs10grxcrc32err : in std_logic;
pcs10grxdiagstatus : in std_logic_vector(1 downto 0);
datainfrom8gpcs : in std_logic_vector(63 downto 0);
clockinfrom8gpcs : in std_logic;
pcs8gbisterr : in std_logic;
pcs8grcvdclkpmab : in std_logic;
pcs8gsignaldetectout : in std_logic;
pcs8gbistdone : in std_logic;
pcs8grlvlt : in std_logic;
pcs8gfullrmf : in std_logic;
pcs8gemptyrmf : in std_logic;
pcs8gfullrx : in std_logic;
pcs8gemptyrx : in std_logic;
pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0);
pcs8gbyteordflag : in std_logic;
pcs8gwaboundary : in std_logic_vector(4 downto 0);
pcs8grxdatavalid : in std_logic_vector(3 downto 0);
pcs8grxsynchdr : in std_logic_vector(1 downto 0);
pcs8grxblkstart : in std_logic_vector(3 downto 0);
pmaclkdiv33txorrx : in std_logic;
emsippcsrxclkin : in std_logic_vector(2 downto 0);
emsippcsrxreset : in std_logic_vector(6 downto 0);
emsippcsrxctrl : in std_logic_vector(24 downto 0);
pmarxplllock : in std_logic;
pldrxpmarstbin : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10grxfifoinsert : in std_logic;
pld8gsyncsmeninput : in std_logic;
pcs10grxfifodel : in std_logic;
dataouttopld : out std_logic_vector(63 downto 0);
pld10grxclkout : out std_logic;
pld10grxdatavalid : out std_logic;
pld10grxcontrol : out std_logic_vector(9 downto 0);
pld10grxempty : out std_logic;
pld10grxpempty : out std_logic;
pld10grxpfull : out std_logic;
pld10grxoflwerr : out std_logic;
pld10grxalignval : out std_logic;
pld10grxblklock : out std_logic;
pld10grxhiber : out std_logic;
pld10grxframelock : out std_logic;
pld10grxrdpossts : out std_logic;
pld10grxrdnegsts : out std_logic;
pld10grxskipins : out std_logic;
pld10grxrxframe : out std_logic;
pld10grxpyldins : out std_logic;
pld10grxsyncerr : out std_logic;
pld10grxscrmerr : out std_logic;
pld10grxskiperr : out std_logic;
pld10grxdiagerr : out std_logic;
pld10grxsherr : out std_logic;
pld10grxmfrmerr : out std_logic;
pld10grxcrc32err : out std_logic;
pld10grxdiagstatus : out std_logic_vector(1 downto 0);
pld8grxclkout : out std_logic;
pld8gbisterr : out std_logic;
pld8grcvdclkpmab : out std_logic;
pld8gsignaldetectout : out std_logic;
pld8gbistdone : out std_logic;
pld8grlvlt : out std_logic;
pld8gfullrmf : out std_logic;
pld8gemptyrmf : out std_logic;
pld8gfullrx : out std_logic;
pld8gemptyrx : out std_logic;
pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0);
pld8gbyteordflag : out std_logic;
pld8gwaboundary : out std_logic_vector(4 downto 0);
pld8grxdatavalid : out std_logic_vector(3 downto 0);
pld8grxsynchdr : out std_logic_vector(1 downto 0);
pld8grxblkstart : out std_logic_vector(3 downto 0);
pcs10grxpldclk : out std_logic;
pcs10grxpldrstn : out std_logic;
pcs10grxalignen : out std_logic;
pcs10grxalignclr : out std_logic;
pcs10grxrden : out std_logic;
pcs10grxdispclr : out std_logic;
pcs10grxclrerrblkcnt : out std_logic;
pcs10grxclrbercount : out std_logic;
pcs10grxprbserrclr : out std_logic;
pcs10grxbitslip : out std_logic;
pcs8grxurstpma : out std_logic;
pcs8grxurstpcs : out std_logic;
pcs8gcmpfifourst : out std_logic;
pcs8gphfifourstrx : out std_logic;
pcs8gencdt : out std_logic;
pcs8ga1a2size : out std_logic;
pcs8gbitslip : out std_logic;
pcs8grdenablermf : out std_logic;
pcs8gwrenablermf : out std_logic;
pcs8gpldrxclk : out std_logic;
pcs8gpolinvrx : out std_logic;
pcs8gbitlocreven : out std_logic;
pcs8gbytereven : out std_logic;
pcs8gbytordpld : out std_logic;
pcs8gwrdisablerx : out std_logic;
pcs8grdenablerx : out std_logic;
pcs8gpldextrain : out std_logic_vector(3 downto 0);
pcsgen3rxrstn : out std_logic;
pldrxclkslipout : out std_logic;
pldclkdiv33txorrx : out std_logic;
emsiprxdata : out std_logic_vector(63 downto 0);
emsippcsrxclkout : out std_logic_vector(3 downto 0);
emsippcsrxstatus : out std_logic_vector(63 downto 0);
pldrxpmarstbout : out std_logic;
pldrxplllock : out std_logic;
pld10grxfifodel : out std_logic;
pldrxiqclkout : out std_logic;
pld10grxfifoinsert : out std_logic;
pcs8gsyncsmenoutput : out std_logic
);
end stratixv_hssi_rx_pld_pcs_interface;
architecture behavior of stratixv_hssi_rx_pld_pcs_interface is
component stratixv_hssi_rx_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_rx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false";
selectpcs : string := "eight_g_pcs"
);
port (
pld10grxpldclk : in std_logic;
pld10grxpldrstn : in std_logic;
pld10grxalignen : in std_logic;
pld10grxalignclr : in std_logic;
pld10grxrden : in std_logic;
pld10grxdispclr : in std_logic;
pld10grxclrerrblkcnt : in std_logic;
pld10grxclrbercount : in std_logic;
pld10grxprbserrclr : in std_logic;
pld10grxbitslip : in std_logic;
pld8grxurstpma : in std_logic;
pld8grxurstpcs : in std_logic;
pld8gcmpfifourst : in std_logic;
pld8gphfifourstrx : in std_logic;
pld8gencdt : in std_logic;
pld8ga1a2size : in std_logic;
pld8gbitslip : in std_logic;
pld8grdenablermf : in std_logic;
pld8gwrenablermf : in std_logic;
pld8gpldrxclk : in std_logic;
pld8gpolinvrx : in std_logic;
pld8gbitlocreven : in std_logic;
pld8gbytereven : in std_logic;
pld8gbytordpld : in std_logic;
pld8gwrdisablerx : in std_logic;
pld8grdenablerx : in std_logic;
pldgen3rxrstn : in std_logic;
pldrxclkslipin : in std_logic;
pld8gpldextrain : in std_logic_vector(3 downto 0);
clockinfrom10gpcs : in std_logic;
pcs10grxdatavalid : in std_logic;
datainfrom10gpcs : in std_logic_vector(63 downto 0);
pcs10grxcontrol : in std_logic_vector(9 downto 0);
pcs10grxempty : in std_logic;
pcs10grxpempty : in std_logic;
pcs10grxpfull : in std_logic;
pcs10grxoflwerr : in std_logic;
pcs10grxalignval : in std_logic;
pcs10grxblklock : in std_logic;
pcs10grxhiber : in std_logic;
pcs10grxframelock : in std_logic;
pcs10grxrdpossts : in std_logic;
pcs10grxrdnegsts : in std_logic;
pcs10grxskipins : in std_logic;
pcs10grxrxframe : in std_logic;
pcs10grxpyldins : in std_logic;
pcs10grxsyncerr : in std_logic;
pcs10grxscrmerr : in std_logic;
pcs10grxskiperr : in std_logic;
pcs10grxdiagerr : in std_logic;
pcs10grxsherr : in std_logic;
pcs10grxmfrmerr : in std_logic;
pcs10grxcrc32err : in std_logic;
pcs10grxdiagstatus : in std_logic_vector(1 downto 0);
datainfrom8gpcs : in std_logic_vector(63 downto 0);
clockinfrom8gpcs : in std_logic;
pcs8gbisterr : in std_logic;
pcs8grcvdclkpmab : in std_logic;
pcs8gsignaldetectout : in std_logic;
pcs8gbistdone : in std_logic;
pcs8grlvlt : in std_logic;
pcs8gfullrmf : in std_logic;
pcs8gemptyrmf : in std_logic;
pcs8gfullrx : in std_logic;
pcs8gemptyrx : in std_logic;
pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0);
pcs8gbyteordflag : in std_logic;
pcs8gwaboundary : in std_logic_vector(4 downto 0);
pcs8grxdatavalid : in std_logic_vector(3 downto 0);
pcs8grxsynchdr : in std_logic_vector(1 downto 0);
pcs8grxblkstart : in std_logic_vector(3 downto 0);
pmaclkdiv33txorrx : in std_logic;
emsippcsrxclkin : in std_logic_vector(2 downto 0);
emsippcsrxreset : in std_logic_vector(6 downto 0);
emsippcsrxctrl : in std_logic_vector(24 downto 0);
pmarxplllock : in std_logic;
pldrxpmarstbin : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10grxfifoinsert : in std_logic;
pld8gsyncsmeninput : in std_logic;
pcs10grxfifodel : in std_logic;
dataouttopld : out std_logic_vector(63 downto 0);
pld10grxclkout : out std_logic;
pld10grxdatavalid : out std_logic;
pld10grxcontrol : out std_logic_vector(9 downto 0);
pld10grxempty : out std_logic;
pld10grxpempty : out std_logic;
pld10grxpfull : out std_logic;
pld10grxoflwerr : out std_logic;
pld10grxalignval : out std_logic;
pld10grxblklock : out std_logic;
pld10grxhiber : out std_logic;
pld10grxframelock : out std_logic;
pld10grxrdpossts : out std_logic;
pld10grxrdnegsts : out std_logic;
pld10grxskipins : out std_logic;
pld10grxrxframe : out std_logic;
pld10grxpyldins : out std_logic;
pld10grxsyncerr : out std_logic;
pld10grxscrmerr : out std_logic;
pld10grxskiperr : out std_logic;
pld10grxdiagerr : out std_logic;
pld10grxsherr : out std_logic;
pld10grxmfrmerr : out std_logic;
pld10grxcrc32err : out std_logic;
pld10grxdiagstatus : out std_logic_vector(1 downto 0);
pld8grxclkout : out std_logic;
pld8gbisterr : out std_logic;
pld8grcvdclkpmab : out std_logic;
pld8gsignaldetectout : out std_logic;
pld8gbistdone : out std_logic;
pld8grlvlt : out std_logic;
pld8gfullrmf : out std_logic;
pld8gemptyrmf : out std_logic;
pld8gfullrx : out std_logic;
pld8gemptyrx : out std_logic;
pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0);
pld8gbyteordflag : out std_logic;
pld8gwaboundary : out std_logic_vector(4 downto 0);
pld8grxdatavalid : out std_logic_vector(3 downto 0);
pld8grxsynchdr : out std_logic_vector(1 downto 0);
pld8grxblkstart : out std_logic_vector(3 downto 0);
pcs10grxpldclk : out std_logic;
pcs10grxpldrstn : out std_logic;
pcs10grxalignen : out std_logic;
pcs10grxalignclr : out std_logic;
pcs10grxrden : out std_logic;
pcs10grxdispclr : out std_logic;
pcs10grxclrerrblkcnt : out std_logic;
pcs10grxclrbercount : out std_logic;
pcs10grxprbserrclr : out std_logic;
pcs10grxbitslip : out std_logic;
pcs8grxurstpma : out std_logic;
pcs8grxurstpcs : out std_logic;
pcs8gcmpfifourst : out std_logic;
pcs8gphfifourstrx : out std_logic;
pcs8gencdt : out std_logic;
pcs8ga1a2size : out std_logic;
pcs8gbitslip : out std_logic;
pcs8grdenablermf : out std_logic;
pcs8gwrenablermf : out std_logic;
pcs8gpldrxclk : out std_logic;
pcs8gpolinvrx : out std_logic;
pcs8gbitlocreven : out std_logic;
pcs8gbytereven : out std_logic;
pcs8gbytordpld : out std_logic;
pcs8gwrdisablerx : out std_logic;
pcs8grdenablerx : out std_logic;
pcs8gpldextrain : out std_logic_vector(3 downto 0);
pcsgen3rxrstn : out std_logic;
pldrxclkslipout : out std_logic;
pldclkdiv33txorrx : out std_logic;
emsiprxdata : out std_logic_vector(63 downto 0);
emsippcsrxclkout : out std_logic_vector(3 downto 0);
emsippcsrxstatus : out std_logic_vector(63 downto 0);
pldrxpmarstbout : out std_logic;
pldrxplllock : out std_logic;
pld10grxfifodel : out std_logic;
pldrxiqclkout : out std_logic;
pld10grxfifoinsert : out std_logic;
pcs8gsyncsmenoutput : out std_logic
);
end component;
begin
inst : stratixv_hssi_rx_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
is_10g_0ppm => is_10g_0ppm,
is_8g_0ppm => is_8g_0ppm,
selectpcs => selectpcs
)
port map (
pld10grxpldclk => pld10grxpldclk,
pld10grxpldrstn => pld10grxpldrstn,
pld10grxalignen => pld10grxalignen,
pld10grxalignclr => pld10grxalignclr,
pld10grxrden => pld10grxrden,
pld10grxdispclr => pld10grxdispclr,
pld10grxclrerrblkcnt => pld10grxclrerrblkcnt,
pld10grxclrbercount => pld10grxclrbercount,
pld10grxprbserrclr => pld10grxprbserrclr,
pld10grxbitslip => pld10grxbitslip,
pld8grxurstpma => pld8grxurstpma,
pld8grxurstpcs => pld8grxurstpcs,
pld8gcmpfifourst => pld8gcmpfifourst,
pld8gphfifourstrx => pld8gphfifourstrx,
pld8gencdt => pld8gencdt,
pld8ga1a2size => pld8ga1a2size,
pld8gbitslip => pld8gbitslip,
pld8grdenablermf => pld8grdenablermf,
pld8gwrenablermf => pld8gwrenablermf,
pld8gpldrxclk => pld8gpldrxclk,
pld8gpolinvrx => pld8gpolinvrx,
pld8gbitlocreven => pld8gbitlocreven,
pld8gbytereven => pld8gbytereven,
pld8gbytordpld => pld8gbytordpld,
pld8gwrdisablerx => pld8gwrdisablerx,
pld8grdenablerx => pld8grdenablerx,
pldgen3rxrstn => pldgen3rxrstn,
pldrxclkslipin => pldrxclkslipin,
pld8gpldextrain => pld8gpldextrain,
clockinfrom10gpcs => clockinfrom10gpcs,
pcs10grxdatavalid => pcs10grxdatavalid,
datainfrom10gpcs => datainfrom10gpcs,
pcs10grxcontrol => pcs10grxcontrol,
pcs10grxempty => pcs10grxempty,
pcs10grxpempty => pcs10grxpempty,
pcs10grxpfull => pcs10grxpfull,
pcs10grxoflwerr => pcs10grxoflwerr,
pcs10grxalignval => pcs10grxalignval,
pcs10grxblklock => pcs10grxblklock,
pcs10grxhiber => pcs10grxhiber,
pcs10grxframelock => pcs10grxframelock,
pcs10grxrdpossts => pcs10grxrdpossts,
pcs10grxrdnegsts => pcs10grxrdnegsts,
pcs10grxskipins => pcs10grxskipins,
pcs10grxrxframe => pcs10grxrxframe,
pcs10grxpyldins => pcs10grxpyldins,
pcs10grxsyncerr => pcs10grxsyncerr,
pcs10grxscrmerr => pcs10grxscrmerr,
pcs10grxskiperr => pcs10grxskiperr,
pcs10grxdiagerr => pcs10grxdiagerr,
pcs10grxsherr => pcs10grxsherr,
pcs10grxmfrmerr => pcs10grxmfrmerr,
pcs10grxcrc32err => pcs10grxcrc32err,
pcs10grxdiagstatus => pcs10grxdiagstatus,
datainfrom8gpcs => datainfrom8gpcs,
clockinfrom8gpcs => clockinfrom8gpcs,
pcs8gbisterr => pcs8gbisterr,
pcs8grcvdclkpmab => pcs8grcvdclkpmab,
pcs8gsignaldetectout => pcs8gsignaldetectout,
pcs8gbistdone => pcs8gbistdone,
pcs8grlvlt => pcs8grlvlt,
pcs8gfullrmf => pcs8gfullrmf,
pcs8gemptyrmf => pcs8gemptyrmf,
pcs8gfullrx => pcs8gfullrx,
pcs8gemptyrx => pcs8gemptyrx,
pcs8ga1a2k1k2flag => pcs8ga1a2k1k2flag,
pcs8gbyteordflag => pcs8gbyteordflag,
pcs8gwaboundary => pcs8gwaboundary,
pcs8grxdatavalid => pcs8grxdatavalid,
pcs8grxsynchdr => pcs8grxsynchdr,
pcs8grxblkstart => pcs8grxblkstart,
pmaclkdiv33txorrx => pmaclkdiv33txorrx,
emsippcsrxclkin => emsippcsrxclkin,
emsippcsrxreset => emsippcsrxreset,
emsippcsrxctrl => emsippcsrxctrl,
pmarxplllock => pmarxplllock,
pldrxpmarstbin => pldrxpmarstbin,
rrxblocksel => rrxblocksel,
rrxemsip => rrxemsip,
emsipenabledusermode => emsipenabledusermode,
pcs10grxfifoinsert => pcs10grxfifoinsert,
pld8gsyncsmeninput => pld8gsyncsmeninput,
pcs10grxfifodel => pcs10grxfifodel,
dataouttopld => dataouttopld,
pld10grxclkout => pld10grxclkout,
pld10grxdatavalid => pld10grxdatavalid,
pld10grxcontrol => pld10grxcontrol,
pld10grxempty => pld10grxempty,
pld10grxpempty => pld10grxpempty,
pld10grxpfull => pld10grxpfull,
pld10grxoflwerr => pld10grxoflwerr,
pld10grxalignval => pld10grxalignval,
pld10grxblklock => pld10grxblklock,
pld10grxhiber => pld10grxhiber,
pld10grxframelock => pld10grxframelock,
pld10grxrdpossts => pld10grxrdpossts,
pld10grxrdnegsts => pld10grxrdnegsts,
pld10grxskipins => pld10grxskipins,
pld10grxrxframe => pld10grxrxframe,
pld10grxpyldins => pld10grxpyldins,
pld10grxsyncerr => pld10grxsyncerr,
pld10grxscrmerr => pld10grxscrmerr,
pld10grxskiperr => pld10grxskiperr,
pld10grxdiagerr => pld10grxdiagerr,
pld10grxsherr => pld10grxsherr,
pld10grxmfrmerr => pld10grxmfrmerr,
pld10grxcrc32err => pld10grxcrc32err,
pld10grxdiagstatus => pld10grxdiagstatus,
pld8grxclkout => pld8grxclkout,
pld8gbisterr => pld8gbisterr,
pld8grcvdclkpmab => pld8grcvdclkpmab,
pld8gsignaldetectout => pld8gsignaldetectout,
pld8gbistdone => pld8gbistdone,
pld8grlvlt => pld8grlvlt,
pld8gfullrmf => pld8gfullrmf,
pld8gemptyrmf => pld8gemptyrmf,
pld8gfullrx => pld8gfullrx,
pld8gemptyrx => pld8gemptyrx,
pld8ga1a2k1k2flag => pld8ga1a2k1k2flag,
pld8gbyteordflag => pld8gbyteordflag,
pld8gwaboundary => pld8gwaboundary,
pld8grxdatavalid => pld8grxdatavalid,
pld8grxsynchdr => pld8grxsynchdr,
pld8grxblkstart => pld8grxblkstart,
pcs10grxpldclk => pcs10grxpldclk,
pcs10grxpldrstn => pcs10grxpldrstn,
pcs10grxalignen => pcs10grxalignen,
pcs10grxalignclr => pcs10grxalignclr,
pcs10grxrden => pcs10grxrden,
pcs10grxdispclr => pcs10grxdispclr,
pcs10grxclrerrblkcnt => pcs10grxclrerrblkcnt,
pcs10grxclrbercount => pcs10grxclrbercount,
pcs10grxprbserrclr => pcs10grxprbserrclr,
pcs10grxbitslip => pcs10grxbitslip,
pcs8grxurstpma => pcs8grxurstpma,
pcs8grxurstpcs => pcs8grxurstpcs,
pcs8gcmpfifourst => pcs8gcmpfifourst,
pcs8gphfifourstrx => pcs8gphfifourstrx,
pcs8gencdt => pcs8gencdt,
pcs8ga1a2size => pcs8ga1a2size,
pcs8gbitslip => pcs8gbitslip,
pcs8grdenablermf => pcs8grdenablermf,
pcs8gwrenablermf => pcs8gwrenablermf,
pcs8gpldrxclk => pcs8gpldrxclk,
pcs8gpolinvrx => pcs8gpolinvrx,
pcs8gbitlocreven => pcs8gbitlocreven,
pcs8gbytereven => pcs8gbytereven,
pcs8gbytordpld => pcs8gbytordpld,
pcs8gwrdisablerx => pcs8gwrdisablerx,
pcs8grdenablerx => pcs8grdenablerx,
pcs8gpldextrain => pcs8gpldextrain,
pcsgen3rxrstn => pcsgen3rxrstn,
pldrxclkslipout => pldrxclkslipout,
pldclkdiv33txorrx => pldclkdiv33txorrx,
emsiprxdata => emsiprxdata,
emsippcsrxclkout => emsippcsrxclkout,
emsippcsrxstatus => emsippcsrxstatus,
pldrxpmarstbout => pldrxpmarstbout,
pldrxplllock => pldrxplllock,
pld10grxfifodel => pld10grxfifodel,
pldrxiqclkout => pldrxiqclkout,
pld10grxfifoinsert => pld10grxfifoinsert,
pcs8gsyncsmenoutput => pcs8gsyncsmenoutput
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_tx_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_tx_pcs_pma_interface";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrom10gpcs : in std_logic_vector(39 downto 0);
pcs10gtxclkiqout : in std_logic;
pcsgen3txclkiqout : in std_logic;
datainfromgen3pcs : in std_logic_vector(31 downto 0);
pcs8gtxclkiqout : in std_logic;
datainfrom8gpcs : in std_logic_vector(19 downto 0);
pmaclkdiv33lcin : in std_logic;
pmatxlcplllockin : in std_logic;
pmatxcmuplllockin : in std_logic;
rtxblocksel : in std_logic_vector(1 downto 0);
pcsgen3gen3datasel : in std_logic;
pldtxpmasyncp : in std_logic;
dataouttopma : out std_logic_vector(39 downto 0);
pmatxclkout : out std_logic;
clockoutto10gpcs : out std_logic;
clockoutto8gpcs : out std_logic;
pmaclkdiv33lcout : out std_logic;
pcs10gclkdiv33lc : out std_logic;
pmatxlcplllockout : out std_logic;
pmatxcmuplllockout : out std_logic;
pmatxpmasyncp : out std_logic
);
end stratixv_hssi_tx_pcs_pma_interface;
architecture behavior of stratixv_hssi_tx_pcs_pma_interface is
component stratixv_hssi_tx_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_tx_pcs_pma_interface";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrom10gpcs : in std_logic_vector(39 downto 0);
pcs10gtxclkiqout : in std_logic;
pcsgen3txclkiqout : in std_logic;
datainfromgen3pcs : in std_logic_vector(31 downto 0);
pcs8gtxclkiqout : in std_logic;
datainfrom8gpcs : in std_logic_vector(19 downto 0);
pmaclkdiv33lcin : in std_logic;
pmatxlcplllockin : in std_logic;
pmatxcmuplllockin : in std_logic;
rtxblocksel : in std_logic_vector(1 downto 0);
pcsgen3gen3datasel : in std_logic;
pldtxpmasyncp : in std_logic;
dataouttopma : out std_logic_vector(39 downto 0);
pmatxclkout : out std_logic;
clockoutto10gpcs : out std_logic;
clockoutto8gpcs : out std_logic;
pmaclkdiv33lcout : out std_logic;
pcs10gclkdiv33lc : out std_logic;
pmatxlcplllockout : out std_logic;
pmatxcmuplllockout : out std_logic;
pmatxpmasyncp : out std_logic
);
end component;
begin
inst : stratixv_hssi_tx_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
selectpcs => selectpcs
)
port map (
clockinfrompma => clockinfrompma,
datainfrom10gpcs => datainfrom10gpcs,
pcs10gtxclkiqout => pcs10gtxclkiqout,
pcsgen3txclkiqout => pcsgen3txclkiqout,
datainfromgen3pcs => datainfromgen3pcs,
pcs8gtxclkiqout => pcs8gtxclkiqout,
datainfrom8gpcs => datainfrom8gpcs,
pmaclkdiv33lcin => pmaclkdiv33lcin,
pmatxlcplllockin => pmatxlcplllockin,
pmatxcmuplllockin => pmatxcmuplllockin,
rtxblocksel => rtxblocksel,
pcsgen3gen3datasel => pcsgen3gen3datasel,
pldtxpmasyncp => pldtxpmasyncp,
dataouttopma => dataouttopma,
pmatxclkout => pmatxclkout,
clockoutto10gpcs => clockoutto10gpcs,
clockoutto8gpcs => clockoutto8gpcs,
pmaclkdiv33lcout => pmaclkdiv33lcout,
pcs10gclkdiv33lc => pcs10gclkdiv33lc,
pmatxlcplllockout => pmatxlcplllockout,
pmatxcmuplllockout => pmatxcmuplllockout,
pmatxpmasyncp => pmatxpmasyncp
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_tx_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_tx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false"
);
port (
datainfrompld : in std_logic_vector(63 downto 0);
pld10gtxpldclk : in std_logic;
pld10gtxpldrstn : in std_logic;
pld10gtxdatavalid : in std_logic;
pld10gtxcontrol : in std_logic_vector(8 downto 0);
pld10gtxbitslip : in std_logic_vector(6 downto 0);
pld10gtxdiagstatus : in std_logic_vector(1 downto 0);
pld10gtxwordslip : in std_logic;
pld10gtxbursten : in std_logic;
pld8gpldtxclk : in std_logic;
pld8gpolinvtx : in std_logic;
pld8grevloopbk : in std_logic;
pld8gwrenabletx : in std_logic;
pld8grddisabletx : in std_logic;
pld8gphfifoursttx : in std_logic;
pld8gtxboundarysel : in std_logic_vector(4 downto 0);
pld8gtxdatavalid : in std_logic_vector(3 downto 0);
pld8gtxsynchdr : in std_logic_vector(1 downto 0);
pld8gtxblkstart : in std_logic_vector(3 downto 0);
pldgen3txrstn : in std_logic;
pld8gtxurstpcs : in std_logic;
clockinfrom10gpcs : in std_logic;
pcs10gtxempty : in std_logic;
pcs10gtxpempty : in std_logic;
pcs10gtxpfull : in std_logic;
pcs10gtxfull : in std_logic;
pcs10gtxframe : in std_logic;
pcs10gtxburstenexe : in std_logic;
pcs10gtxwordslipexe : in std_logic;
pcs8gfulltx : in std_logic;
pcs8gemptytx : in std_logic;
clockinfrom8gpcs : in std_logic;
pmaclkdiv33lc : in std_logic;
emsiptxdata : in std_logic_vector(63 downto 0);
emsippcstxclkin : in std_logic_vector(2 downto 0);
emsippcstxreset : in std_logic_vector(5 downto 0);
emsippcstxctrl : in std_logic_vector(43 downto 0);
pmatxlcplllock : in std_logic;
pmatxcmuplllock : in std_logic;
pldtxpmarstbin : in std_logic;
pldlccmurstbin : in std_logic;
rtxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10gextraout : in std_logic_vector(3 downto 0);
pldtxpmasyncpin : in std_logic;
pcs10gtxfifoinsert : in std_logic;
pcs10gtxfifodel : in std_logic;
pld10gextrain : in std_logic_vector(3 downto 0);
pld10gtxclkout : out std_logic;
pld10gtxempty : out std_logic;
pld10gtxpempty : out std_logic;
pld10gtxpfull : out std_logic;
pld10gtxfull : out std_logic;
pld10gtxframe : out std_logic;
pld10gtxburstenexe : out std_logic;
pld10gtxwordslipexe : out std_logic;
pld8gfulltx : out std_logic;
pld8gemptytx : out std_logic;
pld8gtxclkout : out std_logic;
pcs10gtxpldclk : out std_logic;
pcs10gtxpldrstn : out std_logic;
pcs10gtxdatavalid : out std_logic;
dataoutto10gpcs : out std_logic_vector(63 downto 0);
pcs10gtxcontrol : out std_logic_vector(8 downto 0);
pcs10gtxbitslip : out std_logic_vector(6 downto 0);
pcs10gtxdiagstatus : out std_logic_vector(1 downto 0);
pcs10gtxwordslip : out std_logic;
pcs10gtxbursten : out std_logic;
pcs8gtxurstpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(43 downto 0);
pcs8gpldtxclk : out std_logic;
pcs8gpolinvtx : out std_logic;
pcs8grevloopbk : out std_logic;
pcs8gwrenabletx : out std_logic;
pcs8grddisabletx : out std_logic;
pcs8gphfifoursttx : out std_logic;
pcs8gtxboundarysel : out std_logic_vector(4 downto 0);
pcs8gtxdatavalid : out std_logic_vector(3 downto 0);
pcs8gtxsynchdr : out std_logic_vector(1 downto 0);
pcs8gtxblkstart : out std_logic_vector(3 downto 0);
pcsgen3txrstn : out std_logic;
pldclkdiv33lc : out std_logic;
emsippcstxclkout : out std_logic_vector(2 downto 0);
emsippcstxstatus : out std_logic_vector(16 downto 0);
pldtxpmarstbout : out std_logic;
pldlccmurstbout : out std_logic;
pldtxlcplllock : out std_logic;
pldtxcmuplllock : out std_logic;
pldtxiqclkout : out std_logic;
pcs10gextrain : out std_logic_vector(3 downto 0);
pld10gtxfifodel : out std_logic;
pldtxpmasyncpout : out std_logic;
pld10gtxfifoinsert : out std_logic;
pld10gextraout : out std_logic_vector(3 downto 0)
);
end stratixv_hssi_tx_pld_pcs_interface;
architecture behavior of stratixv_hssi_tx_pld_pcs_interface is
component stratixv_hssi_tx_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_tx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false"
);
port (
datainfrompld : in std_logic_vector(63 downto 0);
pld10gtxpldclk : in std_logic;
pld10gtxpldrstn : in std_logic;
pld10gtxdatavalid : in std_logic;
pld10gtxcontrol : in std_logic_vector(8 downto 0);
pld10gtxbitslip : in std_logic_vector(6 downto 0);
pld10gtxdiagstatus : in std_logic_vector(1 downto 0);
pld10gtxwordslip : in std_logic;
pld10gtxbursten : in std_logic;
pld8gpldtxclk : in std_logic;
pld8gpolinvtx : in std_logic;
pld8grevloopbk : in std_logic;
pld8gwrenabletx : in std_logic;
pld8grddisabletx : in std_logic;
pld8gphfifoursttx : in std_logic;
pld8gtxboundarysel : in std_logic_vector(4 downto 0);
pld8gtxdatavalid : in std_logic_vector(3 downto 0);
pld8gtxsynchdr : in std_logic_vector(1 downto 0);
pld8gtxblkstart : in std_logic_vector(3 downto 0);
pldgen3txrstn : in std_logic;
pld8gtxurstpcs : in std_logic;
clockinfrom10gpcs : in std_logic;
pcs10gtxempty : in std_logic;
pcs10gtxpempty : in std_logic;
pcs10gtxpfull : in std_logic;
pcs10gtxfull : in std_logic;
pcs10gtxframe : in std_logic;
pcs10gtxburstenexe : in std_logic;
pcs10gtxwordslipexe : in std_logic;
pcs8gfulltx : in std_logic;
pcs8gemptytx : in std_logic;
clockinfrom8gpcs : in std_logic;
pmaclkdiv33lc : in std_logic;
emsiptxdata : in std_logic_vector(63 downto 0);
emsippcstxclkin : in std_logic_vector(2 downto 0);
emsippcstxreset : in std_logic_vector(5 downto 0);
emsippcstxctrl : in std_logic_vector(43 downto 0);
pmatxlcplllock : in std_logic;
pmatxcmuplllock : in std_logic;
pldtxpmarstbin : in std_logic;
pldlccmurstbin : in std_logic;
rtxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10gextraout : in std_logic_vector(3 downto 0);
pldtxpmasyncpin : in std_logic;
pcs10gtxfifoinsert : in std_logic;
pcs10gtxfifodel : in std_logic;
pld10gextrain : in std_logic_vector(3 downto 0);
pld10gtxclkout : out std_logic;
pld10gtxempty : out std_logic;
pld10gtxpempty : out std_logic;
pld10gtxpfull : out std_logic;
pld10gtxfull : out std_logic;
pld10gtxframe : out std_logic;
pld10gtxburstenexe : out std_logic;
pld10gtxwordslipexe : out std_logic;
pld8gfulltx : out std_logic;
pld8gemptytx : out std_logic;
pld8gtxclkout : out std_logic;
pcs10gtxpldclk : out std_logic;
pcs10gtxpldrstn : out std_logic;
pcs10gtxdatavalid : out std_logic;
dataoutto10gpcs : out std_logic_vector(63 downto 0);
pcs10gtxcontrol : out std_logic_vector(8 downto 0);
pcs10gtxbitslip : out std_logic_vector(6 downto 0);
pcs10gtxdiagstatus : out std_logic_vector(1 downto 0);
pcs10gtxwordslip : out std_logic;
pcs10gtxbursten : out std_logic;
pcs8gtxurstpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(43 downto 0);
pcs8gpldtxclk : out std_logic;
pcs8gpolinvtx : out std_logic;
pcs8grevloopbk : out std_logic;
pcs8gwrenabletx : out std_logic;
pcs8grddisabletx : out std_logic;
pcs8gphfifoursttx : out std_logic;
pcs8gtxboundarysel : out std_logic_vector(4 downto 0);
pcs8gtxdatavalid : out std_logic_vector(3 downto 0);
pcs8gtxsynchdr : out std_logic_vector(1 downto 0);
pcs8gtxblkstart : out std_logic_vector(3 downto 0);
pcsgen3txrstn : out std_logic;
pldclkdiv33lc : out std_logic;
emsippcstxclkout : out std_logic_vector(2 downto 0);
emsippcstxstatus : out std_logic_vector(16 downto 0);
pldtxpmarstbout : out std_logic;
pldlccmurstbout : out std_logic;
pldtxlcplllock : out std_logic;
pldtxcmuplllock : out std_logic;
pldtxiqclkout : out std_logic;
pcs10gextrain : out std_logic_vector(3 downto 0);
pld10gtxfifodel : out std_logic;
pldtxpmasyncpout : out std_logic;
pld10gtxfifoinsert : out std_logic;
pld10gextraout : out std_logic_vector(3 downto 0)
);
end component;
begin
inst : stratixv_hssi_tx_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
is_10g_0ppm => is_10g_0ppm,
is_8g_0ppm => is_8g_0ppm
)
port map (
datainfrompld => datainfrompld,
pld10gtxpldclk => pld10gtxpldclk,
pld10gtxpldrstn => pld10gtxpldrstn,
pld10gtxdatavalid => pld10gtxdatavalid,
pld10gtxcontrol => pld10gtxcontrol,
pld10gtxbitslip => pld10gtxbitslip,
pld10gtxdiagstatus => pld10gtxdiagstatus,
pld10gtxwordslip => pld10gtxwordslip,
pld10gtxbursten => pld10gtxbursten,
pld8gpldtxclk => pld8gpldtxclk,
pld8gpolinvtx => pld8gpolinvtx,
pld8grevloopbk => pld8grevloopbk,
pld8gwrenabletx => pld8gwrenabletx,
pld8grddisabletx => pld8grddisabletx,
pld8gphfifoursttx => pld8gphfifoursttx,
pld8gtxboundarysel => pld8gtxboundarysel,
pld8gtxdatavalid => pld8gtxdatavalid,
pld8gtxsynchdr => pld8gtxsynchdr,
pld8gtxblkstart => pld8gtxblkstart,
pldgen3txrstn => pldgen3txrstn,
pld8gtxurstpcs => pld8gtxurstpcs,
clockinfrom10gpcs => clockinfrom10gpcs,
pcs10gtxempty => pcs10gtxempty,
pcs10gtxpempty => pcs10gtxpempty,
pcs10gtxpfull => pcs10gtxpfull,
pcs10gtxfull => pcs10gtxfull,
pcs10gtxframe => pcs10gtxframe,
pcs10gtxburstenexe => pcs10gtxburstenexe,
pcs10gtxwordslipexe => pcs10gtxwordslipexe,
pcs8gfulltx => pcs8gfulltx,
pcs8gemptytx => pcs8gemptytx,
clockinfrom8gpcs => clockinfrom8gpcs,
pmaclkdiv33lc => pmaclkdiv33lc,
emsiptxdata => emsiptxdata,
emsippcstxclkin => emsippcstxclkin,
emsippcstxreset => emsippcstxreset,
emsippcstxctrl => emsippcstxctrl,
pmatxlcplllock => pmatxlcplllock,
pmatxcmuplllock => pmatxcmuplllock,
pldtxpmarstbin => pldtxpmarstbin,
pldlccmurstbin => pldlccmurstbin,
rtxemsip => rtxemsip,
emsipenabledusermode => emsipenabledusermode,
pcs10gextraout => pcs10gextraout,
pldtxpmasyncpin => pldtxpmasyncpin,
pcs10gtxfifoinsert => pcs10gtxfifoinsert,
pcs10gtxfifodel => pcs10gtxfifodel,
pld10gextrain => pld10gextrain,
pld10gtxclkout => pld10gtxclkout,
pld10gtxempty => pld10gtxempty,
pld10gtxpempty => pld10gtxpempty,
pld10gtxpfull => pld10gtxpfull,
pld10gtxfull => pld10gtxfull,
pld10gtxframe => pld10gtxframe,
pld10gtxburstenexe => pld10gtxburstenexe,
pld10gtxwordslipexe => pld10gtxwordslipexe,
pld8gfulltx => pld8gfulltx,
pld8gemptytx => pld8gemptytx,
pld8gtxclkout => pld8gtxclkout,
pcs10gtxpldclk => pcs10gtxpldclk,
pcs10gtxpldrstn => pcs10gtxpldrstn,
pcs10gtxdatavalid => pcs10gtxdatavalid,
dataoutto10gpcs => dataoutto10gpcs,
pcs10gtxcontrol => pcs10gtxcontrol,
pcs10gtxbitslip => pcs10gtxbitslip,
pcs10gtxdiagstatus => pcs10gtxdiagstatus,
pcs10gtxwordslip => pcs10gtxwordslip,
pcs10gtxbursten => pcs10gtxbursten,
pcs8gtxurstpcs => pcs8gtxurstpcs,
dataoutto8gpcs => dataoutto8gpcs,
pcs8gpldtxclk => pcs8gpldtxclk,
pcs8gpolinvtx => pcs8gpolinvtx,
pcs8grevloopbk => pcs8grevloopbk,
pcs8gwrenabletx => pcs8gwrenabletx,
pcs8grddisabletx => pcs8grddisabletx,
pcs8gphfifoursttx => pcs8gphfifoursttx,
pcs8gtxboundarysel => pcs8gtxboundarysel,
pcs8gtxdatavalid => pcs8gtxdatavalid,
pcs8gtxsynchdr => pcs8gtxsynchdr,
pcs8gtxblkstart => pcs8gtxblkstart,
pcsgen3txrstn => pcsgen3txrstn,
pldclkdiv33lc => pldclkdiv33lc,
emsippcstxclkout => emsippcstxclkout,
emsippcstxstatus => emsippcstxstatus,
pldtxpmarstbout => pldtxpmarstbout,
pldlccmurstbout => pldlccmurstbout,
pldtxlcplllock => pldtxlcplllock,
pldtxcmuplllock => pldtxcmuplllock,
pldtxiqclkout => pldtxiqclkout,
pcs10gextrain => pcs10gextrain,
pld10gtxfifodel => pld10gtxfifodel,
pldtxpmasyncpout => pldtxpmasyncpout,
pld10gtxfifoinsert => pld10gtxfifoinsert,
pld10gextraout => pld10gextraout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_10g_rx_pcs is
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
dis_signal_ok : string := "dis_signal_ok_dis";
gb_rx_idwidth : string := "idwidth_32";
gb_rx_odwidth : string := "odwidth_66";
bit_reverse : string := "bit_reverse_dis";
gb_sel_mode : string := "internal";
lpbk_mode : string := "lpbk_dis";
test_mode : string := "test_off";
blksync_bypass : string := "blksync_bypass_dis";
blksync_pipeln : string := "blksync_pipeln_dis";
blksync_knum_sh_cnt_prelock : string := "int";
blksync_knum_sh_cnt_postlock : string := "int";
blksync_enum_invalid_sh_cnt : string := "int";
blksync_bitslip_wait_cnt : string := "int";
bitslip_wait_cnt_user : string := "int";
blksync_bitslip_type : string := "bitslip_comb";
blksync_bitslip_wait_type : string := "bitslip_match";
dispchk_bypass : string := "dispchk_bypass_dis";
dispchk_rd_level : string := "dispchk_rd_level_min";
dispchk_rd_level_user : string := "int";
dispchk_pipeln : string := "dispchk_pipeln_dis";
descrm_bypass : string := "descrm_bypass_en";
descrm_mode : string := "async";
frmsync_bypass : string := "frmsync_bypass_dis";
frmsync_pipeln : string := "frmsync_pipeln_dis";
frmsync_mfrm_length : string := "int";
frmsync_mfrm_length_user : string := "int";
frmsync_knum_sync : string := "int";
frmsync_enum_sync : string := "int";
frmsync_enum_scrm : string := "int";
frmsync_flag_type : string := "all_framing_words";
dec_64b66b_10g_mode : string := "dec_64b66b_10g_mode_en";
dec_64b66b_rxsm_bypass : string := "dec_64b66b_rxsm_bypass_dis";
rx_sm_bypass : string := "rx_sm_bypass_dis";
rx_sm_pipeln : string := "rx_sm_pipeln_dis";
rx_sm_hiber : string := "rx_sm_hiber_en";
ber_xus_timer_window : string := "int";
ber_bit_err_total_cnt : string := "int";
crcchk_bypass : string := "crcchk_bypass_dis";
crcchk_pipeln : string := "crcchk_pipeln_dis";
crcflag_pipeln : string := "crcflag_pipeln_dis";
crcchk_init : string := "crcchk_init_user_setting";
crcchk_init_user : bit_vector := B"11111111111111111111111111111111";
crcchk_inv : string := "crcchk_inv_dis";
force_align : string := "force_align_dis";
align_del : string := "align_del_en";
control_del : bit_vector := B"11110000";
rxfifo_mode : string := "phase_comp";
master_clk_sel : string := "master_rx_pma_clk";
rd_clk_sel : string := "rd_rx_pma_clk";
gbexp_clken : string := "gbexp_clk_dis";
prbs_clken : string := "prbs_clk_dis";
blksync_clken : string := "blksync_clk_dis";
dispchk_clken : string := "dispchk_clk_dis";
descrm_clken : string := "descrm_clk_dis";
frmsync_clken : string := "frmsync_clk_dis";
dec64b66b_clken : string := "dec64b66b_clk_dis";
ber_clken : string := "ber_clk_dis";
rand_clken : string := "rand_clk_dis";
crcchk_clken : string := "crcchk_clk_dis";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
rxfifo_pempty : string := "pempty_default";
rxfifo_pfull : string := "pfull_default";
rxfifo_full : string := "full_default";
rxfifo_empty : string := "pempty_default";
bitslip_mode : string := "bitslip_dis";
fast_path : string := "fast_path_dis";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_rx_clk_out";
channel_number : integer := 0;
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
test_bus_mode : string := "tx"
);
port (
bercount : out std_logic_vector(5 downto 0);
errorblockcount : out std_logic_vector(7 downto 0);
pcsstatus : out std_logic_vector(0 downto 0);
randomerrorcount : out std_logic_vector(15 downto 0);
prbserrorlatch : out std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rxpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33txorrx : in std_logic_vector(0 downto 0);
rxpmadatavalid : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
rxpldclk : in std_logic_vector(0 downto 0);
rxpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
rxalignen : in std_logic_vector(0 downto 0);
rxalignclr : in std_logic_vector(0 downto 0);
rxrden : in std_logic_vector(0 downto 0);
rxdisparityclr : in std_logic_vector(0 downto 0);
rxclrerrorblockcount : in std_logic_vector(0 downto 0);
rxclrbercount : in std_logic_vector(0 downto 0);
rxbitslip : in std_logic_vector(0 downto 0);
rxprbserrorclr : in std_logic_vector(0 downto 0);
rxclkout : out std_logic_vector(0 downto 0);
rxclkiqout : out std_logic_vector(0 downto 0);
rxdatavalid : out std_logic_vector(0 downto 0);
rxfifoempty : out std_logic_vector(0 downto 0);
rxfifopartialempty : out std_logic_vector(0 downto 0);
rxfifopartialfull : out std_logic_vector(0 downto 0);
rxfifofull : out std_logic_vector(0 downto 0);
rxalignval : out std_logic_vector(0 downto 0);
rxblocklock : out std_logic_vector(0 downto 0);
rxsyncheadererror : out std_logic_vector(0 downto 0);
rxhighber : out std_logic_vector(0 downto 0);
rxframelock : out std_logic_vector(0 downto 0);
rxrdpossts : out std_logic_vector(0 downto 0);
rxrdnegsts : out std_logic_vector(0 downto 0);
rxskipinserted : out std_logic_vector(0 downto 0);
rxrxframe : out std_logic_vector(0 downto 0);
rxpayloadinserted : out std_logic_vector(0 downto 0);
rxsyncworderror : out std_logic_vector(0 downto 0);
rxscramblererror : out std_logic_vector(0 downto 0);
rxskipworderror : out std_logic_vector(0 downto 0);
rxdiagnosticerror : out std_logic_vector(0 downto 0);
rxmetaframeerror : out std_logic_vector(0 downto 0);
rxcrc32error : out std_logic_vector(0 downto 0);
rxdiagnosticstatus : out std_logic_vector(1 downto 0);
rxdata : out std_logic_vector(63 downto 0);
rxcontrol : out std_logic_vector(9 downto 0);
accumdisparity : out std_logic_vector(8 downto 0);
loopbackdatain : in std_logic_vector(39 downto 0);
rxpmadata : in std_logic_vector(39 downto 0);
rxtestdata : out std_logic_vector(19 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_10g_rx_pcs;
architecture behavior of stratixv_hssi_10g_rx_pcs is
component stratixv_hssi_10g_rx_pcs_encrypted
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
dis_signal_ok : string := "dis_signal_ok_dis";
gb_rx_idwidth : string := "idwidth_32";
gb_rx_odwidth : string := "odwidth_66";
bit_reverse : string := "bit_reverse_dis";
gb_sel_mode : string := "internal";
lpbk_mode : string := "lpbk_dis";
test_mode : string := "test_off";
blksync_bypass : string := "blksync_bypass_dis";
blksync_pipeln : string := "blksync_pipeln_dis";
blksync_knum_sh_cnt_prelock : string := "int";
blksync_knum_sh_cnt_postlock : string := "int";
blksync_enum_invalid_sh_cnt : string := "int";
blksync_bitslip_wait_cnt : string := "int";
bitslip_wait_cnt_user : string := "int";
blksync_bitslip_type : string := "bitslip_comb";
blksync_bitslip_wait_type : string := "bitslip_match";
dispchk_bypass : string := "dispchk_bypass_dis";
dispchk_rd_level : string := "dispchk_rd_level_min";
dispchk_rd_level_user : string := "int";
dispchk_pipeln : string := "dispchk_pipeln_dis";
descrm_bypass : string := "descrm_bypass_en";
descrm_mode : string := "async";
frmsync_bypass : string := "frmsync_bypass_dis";
frmsync_pipeln : string := "frmsync_pipeln_dis";
frmsync_mfrm_length : string := "int";
frmsync_mfrm_length_user : string := "int";
frmsync_knum_sync : string := "int";
frmsync_enum_sync : string := "int";
frmsync_enum_scrm : string := "int";
frmsync_flag_type : string := "all_framing_words";
dec_64b66b_10g_mode : string := "dec_64b66b_10g_mode_en";
dec_64b66b_rxsm_bypass : string := "dec_64b66b_rxsm_bypass_dis";
rx_sm_bypass : string := "rx_sm_bypass_dis";
rx_sm_pipeln : string := "rx_sm_pipeln_dis";
rx_sm_hiber : string := "rx_sm_hiber_en";
ber_xus_timer_window : string := "int";
ber_bit_err_total_cnt : string := "int";
crcchk_bypass : string := "crcchk_bypass_dis";
crcchk_pipeln : string := "crcchk_pipeln_dis";
crcflag_pipeln : string := "crcflag_pipeln_dis";
crcchk_init : string := "crcchk_init_user_setting";
crcchk_init_user : bit_vector := B"11111111111111111111111111111111";
crcchk_inv : string := "crcchk_inv_dis";
force_align : string := "force_align_dis";
align_del : string := "align_del_en";
control_del : bit_vector := B"11110000";
rxfifo_mode : string := "phase_comp";
master_clk_sel : string := "master_rx_pma_clk";
rd_clk_sel : string := "rd_rx_pma_clk";
gbexp_clken : string := "gbexp_clk_dis";
prbs_clken : string := "prbs_clk_dis";
blksync_clken : string := "blksync_clk_dis";
dispchk_clken : string := "dispchk_clk_dis";
descrm_clken : string := "descrm_clk_dis";
frmsync_clken : string := "frmsync_clk_dis";
dec64b66b_clken : string := "dec64b66b_clk_dis";
ber_clken : string := "ber_clk_dis";
rand_clken : string := "rand_clk_dis";
crcchk_clken : string := "crcchk_clk_dis";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
rxfifo_pempty : string := "pempty_default";
rxfifo_pfull : string := "pfull_default";
rxfifo_full : string := "full_default";
rxfifo_empty : string := "pempty_default";
bitslip_mode : string := "bitslip_dis";
fast_path : string := "fast_path_dis";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_rx_clk_out";
channel_number : integer := 0;
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
test_bus_mode : string := "tx"
);
port (
bercount : out std_logic_vector(5 downto 0);
errorblockcount : out std_logic_vector(7 downto 0);
pcsstatus : out std_logic_vector(0 downto 0);
randomerrorcount : out std_logic_vector(15 downto 0);
prbserrorlatch : out std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rxpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33txorrx : in std_logic_vector(0 downto 0);
rxpmadatavalid : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
rxpldclk : in std_logic_vector(0 downto 0);
rxpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
rxalignen : in std_logic_vector(0 downto 0);
rxalignclr : in std_logic_vector(0 downto 0);
rxrden : in std_logic_vector(0 downto 0);
rxdisparityclr : in std_logic_vector(0 downto 0);
rxclrerrorblockcount : in std_logic_vector(0 downto 0);
rxclrbercount : in std_logic_vector(0 downto 0);
rxbitslip : in std_logic_vector(0 downto 0);
rxprbserrorclr : in std_logic_vector(0 downto 0);
rxclkout : out std_logic_vector(0 downto 0);
rxclkiqout : out std_logic_vector(0 downto 0);
rxdatavalid : out std_logic_vector(0 downto 0);
rxfifoempty : out std_logic_vector(0 downto 0);
rxfifopartialempty : out std_logic_vector(0 downto 0);
rxfifopartialfull : out std_logic_vector(0 downto 0);
rxfifofull : out std_logic_vector(0 downto 0);
rxalignval : out std_logic_vector(0 downto 0);
rxblocklock : out std_logic_vector(0 downto 0);
rxsyncheadererror : out std_logic_vector(0 downto 0);
rxhighber : out std_logic_vector(0 downto 0);
rxframelock : out std_logic_vector(0 downto 0);
rxrdpossts : out std_logic_vector(0 downto 0);
rxrdnegsts : out std_logic_vector(0 downto 0);
rxskipinserted : out std_logic_vector(0 downto 0);
rxrxframe : out std_logic_vector(0 downto 0);
rxpayloadinserted : out std_logic_vector(0 downto 0);
rxsyncworderror : out std_logic_vector(0 downto 0);
rxscramblererror : out std_logic_vector(0 downto 0);
rxskipworderror : out std_logic_vector(0 downto 0);
rxdiagnosticerror : out std_logic_vector(0 downto 0);
rxmetaframeerror : out std_logic_vector(0 downto 0);
rxcrc32error : out std_logic_vector(0 downto 0);
rxdiagnosticstatus : out std_logic_vector(1 downto 0);
rxdata : out std_logic_vector(63 downto 0);
rxcontrol : out std_logic_vector(9 downto 0);
accumdisparity : out std_logic_vector(8 downto 0);
loopbackdatain : in std_logic_vector(39 downto 0);
rxpmadata : in std_logic_vector(39 downto 0);
rxtestdata : out std_logic_vector(19 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_10g_rx_pcs_encrypted
generic map (
prot_mode => prot_mode,
sup_mode => sup_mode,
dis_signal_ok => dis_signal_ok,
gb_rx_idwidth => gb_rx_idwidth,
gb_rx_odwidth => gb_rx_odwidth,
bit_reverse => bit_reverse,
gb_sel_mode => gb_sel_mode,
lpbk_mode => lpbk_mode,
test_mode => test_mode,
blksync_bypass => blksync_bypass,
blksync_pipeln => blksync_pipeln,
blksync_knum_sh_cnt_prelock => blksync_knum_sh_cnt_prelock,
blksync_knum_sh_cnt_postlock => blksync_knum_sh_cnt_postlock,
blksync_enum_invalid_sh_cnt => blksync_enum_invalid_sh_cnt,
blksync_bitslip_wait_cnt => blksync_bitslip_wait_cnt,
bitslip_wait_cnt_user => bitslip_wait_cnt_user,
blksync_bitslip_type => blksync_bitslip_type,
blksync_bitslip_wait_type => blksync_bitslip_wait_type,
dispchk_bypass => dispchk_bypass,
dispchk_rd_level => dispchk_rd_level,
dispchk_rd_level_user => dispchk_rd_level_user,
dispchk_pipeln => dispchk_pipeln,
descrm_bypass => descrm_bypass,
descrm_mode => descrm_mode,
frmsync_bypass => frmsync_bypass,
frmsync_pipeln => frmsync_pipeln,
frmsync_mfrm_length => frmsync_mfrm_length,
frmsync_mfrm_length_user => frmsync_mfrm_length_user,
frmsync_knum_sync => frmsync_knum_sync,
frmsync_enum_sync => frmsync_enum_sync,
frmsync_enum_scrm => frmsync_enum_scrm,
frmsync_flag_type => frmsync_flag_type,
dec_64b66b_10g_mode => dec_64b66b_10g_mode,
dec_64b66b_rxsm_bypass => dec_64b66b_rxsm_bypass,
rx_sm_bypass => rx_sm_bypass,
rx_sm_pipeln => rx_sm_pipeln,
rx_sm_hiber => rx_sm_hiber,
ber_xus_timer_window => ber_xus_timer_window,
ber_bit_err_total_cnt => ber_bit_err_total_cnt,
crcchk_bypass => crcchk_bypass,
crcchk_pipeln => crcchk_pipeln,
crcflag_pipeln => crcflag_pipeln,
crcchk_init => crcchk_init,
crcchk_init_user => crcchk_init_user,
crcchk_inv => crcchk_inv,
force_align => force_align,
align_del => align_del,
control_del => control_del,
rxfifo_mode => rxfifo_mode,
master_clk_sel => master_clk_sel,
rd_clk_sel => rd_clk_sel,
gbexp_clken => gbexp_clken,
prbs_clken => prbs_clken,
blksync_clken => blksync_clken,
dispchk_clken => dispchk_clken,
descrm_clken => descrm_clken,
frmsync_clken => frmsync_clken,
dec64b66b_clken => dec64b66b_clken,
ber_clken => ber_clken,
rand_clken => rand_clken,
crcchk_clken => crcchk_clken,
wrfifo_clken => wrfifo_clken,
rdfifo_clken => rdfifo_clken,
rxfifo_pempty => rxfifo_pempty,
rxfifo_pfull => rxfifo_pfull,
rxfifo_full => rxfifo_full,
rxfifo_empty => rxfifo_empty,
bitslip_mode => bitslip_mode,
fast_path => fast_path,
stretch_num_stages => stretch_num_stages,
stretch_en => stretch_en,
iqtxrx_clkout_sel => iqtxrx_clkout_sel,
channel_number => channel_number,
frmgen_diag_word => frmgen_diag_word,
frmgen_scrm_word => frmgen_scrm_word,
frmgen_skip_word => frmgen_skip_word,
frmgen_sync_word => frmgen_sync_word,
test_bus_mode => test_bus_mode
)
port map (
bercount => bercount,
errorblockcount => errorblockcount,
pcsstatus => pcsstatus,
randomerrorcount => randomerrorcount,
prbserrorlatch => prbserrorlatch,
txpmaclk => txpmaclk,
rxpmaclk => rxpmaclk,
pmaclkdiv33txorrx => pmaclkdiv33txorrx,
rxpmadatavalid => rxpmadatavalid,
hardresetn => hardresetn,
rxpldclk => rxpldclk,
rxpldrstn => rxpldrstn,
refclkdig => refclkdig,
rxalignen => rxalignen,
rxalignclr => rxalignclr,
rxrden => rxrden,
rxdisparityclr => rxdisparityclr,
rxclrerrorblockcount => rxclrerrorblockcount,
rxclrbercount => rxclrbercount,
rxbitslip => rxbitslip,
rxprbserrorclr => rxprbserrorclr,
rxclkout => rxclkout,
rxclkiqout => rxclkiqout,
rxdatavalid => rxdatavalid,
rxfifoempty => rxfifoempty,
rxfifopartialempty => rxfifopartialempty,
rxfifopartialfull => rxfifopartialfull,
rxfifofull => rxfifofull,
rxalignval => rxalignval,
rxblocklock => rxblocklock,
rxsyncheadererror => rxsyncheadererror,
rxhighber => rxhighber,
rxframelock => rxframelock,
rxrdpossts => rxrdpossts,
rxrdnegsts => rxrdnegsts,
rxskipinserted => rxskipinserted,
rxrxframe => rxrxframe,
rxpayloadinserted => rxpayloadinserted,
rxsyncworderror => rxsyncworderror,
rxscramblererror => rxscramblererror,
rxskipworderror => rxskipworderror,
rxdiagnosticerror => rxdiagnosticerror,
rxmetaframeerror => rxmetaframeerror,
rxcrc32error => rxcrc32error,
rxdiagnosticstatus => rxdiagnosticstatus,
rxdata => rxdata,
rxcontrol => rxcontrol,
accumdisparity => accumdisparity,
loopbackdatain => loopbackdatain,
rxpmadata => rxpmadata,
rxtestdata => rxtestdata,
syncdatain => syncdatain
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_10g_tx_pcs is
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
ctrl_plane_bonding : string := "individual";
master_clk_sel : string := "master_tx_pma_clk";
wr_clk_sel : string := "wr_tx_pma_clk";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
frmgen_clken : string := "frmgen_clk_dis";
crcgen_clken : string := "crcgen_clk_dis";
enc64b66b_txsm_clken : string := "enc64b66b_txsm_clk_dis";
scrm_clken : string := "scrm_clk_dis";
dispgen_clken : string := "dispgen_clk_dis";
prbs_clken : string := "prbs_clk_dis";
sqwgen_clken : string := "sqwgen_clk_dis";
gbred_clken : string := "gbred_clk_dis";
gb_tx_idwidth : string := "idwidth_50";
gb_tx_odwidth : string := "odwidth_32";
txfifo_mode : string := "phase_comp";
txfifo_pempty : string := "pempty_default";
txfifo_pfull : string := "pfull_default";
txfifo_empty : string := "empty_default";
txfifo_full : string := "full_default";
frmgen_bypass : string := "frmgen_bypass_dis";
frmgen_pipeln : string := "frmgen_pipeln_dis";
frmgen_mfrm_length : string := "frmgen_mfrm_length_min";
frmgen_mfrm_length_user : string := "int";
frmgen_pyld_ins : string := "frmgen_pyld_ins_dis";
sh_err : string := "sh_err_dis";
frmgen_burst : string := "frmgen_burst_dis";
frmgen_wordslip : string := "frmgen_wordslip_dis";
crcgen_bypass : string := "crcgen_bypass_dis";
crcgen_init : string := "crcgen_init_user_setting";
crcgen_init_user : bit_vector := B"11111111111111111111111111111111";
crcgen_inv : string := "crcgen_inv_dis";
crcgen_err : string := "crcgen_err_dis";
enc_64b66b_10g_mode : string := "enc_64b66b_10g_mode_en";
enc_64b66b_txsm_bypass : string := "enc_64b66b_txsm_bypass_dis";
tx_sm_bypass : string := "tx_sm_bypass_dis";
tx_sm_pipeln : string := "tx_sm_pipeln_dis";
scrm_bypass : string := "scrm_bypass_dis";
test_mode : string := "test_off";
pseudo_random : string := "all_0";
pseudo_seed_a : string := "pseudo_seed_a_user_setting";
pseudo_seed_a_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
pseudo_seed_b : string := "pseudo_seed_b_user_setting";
pseudo_seed_b_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
bit_reverse : string := "bit_reverse_dis";
scrm_seed : string := "scram_seed_user_setting";
scrm_seed_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
scrm_mode : string := "async";
dispgen_bypass : string := "dispgen_bypass_dis";
dispgen_err : string := "dispgen_err_dis";
dispgen_pipeln : string := "dispgen_pipeln_dis";
gb_sel_mode : string := "internal";
sq_wave : string := "sq_wave_4";
bitslip_en : string := "bitslip_dis";
fastpath : string := "fastpath_dis";
distup_bypass_pipeln : string := "distup_bypass_pipeln_dis";
distup_master : string := "distup_master_en";
distdwn_bypass_pipeln : string := "distdwn_bypass_pipeln_dis";
distdwn_master : string := "distdwn_master_en";
compin_sel : string := "compin_master";
comp_cnt : string := "comp_cnt_00";
indv : string := "indv_en";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_tx_pma_clk";
channel_number : integer := 0;
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
test_bus_mode : string := "tx";
lpm_type : string := "stratixv_hssi_10g_tx_pcs"
);
port (
txpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33lc : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
txpldclk : in std_logic_vector(0 downto 0);
txpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txdatavalid : in std_logic_vector(0 downto 0);
txbitslip : in std_logic_vector(6 downto 0);
txdiagnosticstatus : in std_logic_vector(1 downto 0);
txwordslip : in std_logic_vector(0 downto 0);
txbursten : in std_logic_vector(0 downto 0);
txdisparityclr : in std_logic_vector(0 downto 0);
txclkout : out std_logic_vector(0 downto 0);
txclkiqout : out std_logic_vector(0 downto 0);
txfifoempty : out std_logic_vector(0 downto 0);
txfifopartialempty : out std_logic_vector(0 downto 0);
txfifopartialfull : out std_logic_vector(0 downto 0);
txfifofull : out std_logic_vector(0 downto 0);
txframe : out std_logic_vector(0 downto 0);
txburstenexe : out std_logic_vector(0 downto 0);
txwordslipexe : out std_logic_vector(0 downto 0);
distupindv : in std_logic_vector(0 downto 0);
distdwnindv : in std_logic_vector(0 downto 0);
distupinwren : in std_logic_vector(0 downto 0);
distdwninwren : in std_logic_vector(0 downto 0);
distupinrden : in std_logic_vector(0 downto 0);
distdwninrden : in std_logic_vector(0 downto 0);
distupoutdv : out std_logic_vector(0 downto 0);
distdwnoutdv : out std_logic_vector(0 downto 0);
distupoutwren : out std_logic_vector(0 downto 0);
distdwnoutwren : out std_logic_vector(0 downto 0);
distupoutrden : out std_logic_vector(0 downto 0);
distdwnoutrden : out std_logic_vector(0 downto 0);
txtestdata : out std_logic_vector(19 downto 0);
txdata : in std_logic_vector(63 downto 0);
txcontrol : in std_logic_vector(8 downto 0);
loopbackdataout : out std_logic_vector(39 downto 0);
txpmadata : out std_logic_vector(39 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_10g_tx_pcs;
architecture behavior of stratixv_hssi_10g_tx_pcs is
component stratixv_hssi_10g_tx_pcs_encrypted
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
ctrl_plane_bonding : string := "individual";
master_clk_sel : string := "master_tx_pma_clk";
wr_clk_sel : string := "wr_tx_pma_clk";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
frmgen_clken : string := "frmgen_clk_dis";
crcgen_clken : string := "crcgen_clk_dis";
enc64b66b_txsm_clken : string := "enc64b66b_txsm_clk_dis";
scrm_clken : string := "scrm_clk_dis";
dispgen_clken : string := "dispgen_clk_dis";
prbs_clken : string := "prbs_clk_dis";
sqwgen_clken : string := "sqwgen_clk_dis";
gbred_clken : string := "gbred_clk_dis";
gb_tx_idwidth : string := "idwidth_50";
gb_tx_odwidth : string := "odwidth_32";
txfifo_mode : string := "phase_comp";
txfifo_pempty : string := "pempty_default";
txfifo_pfull : string := "pfull_default";
txfifo_empty : string := "empty_default";
txfifo_full : string := "full_default";
frmgen_bypass : string := "frmgen_bypass_dis";
frmgen_pipeln : string := "frmgen_pipeln_dis";
frmgen_mfrm_length : string := "frmgen_mfrm_length_min";
frmgen_mfrm_length_user : string := "int";
frmgen_pyld_ins : string := "frmgen_pyld_ins_dis";
sh_err : string := "sh_err_dis";
frmgen_burst : string := "frmgen_burst_dis";
frmgen_wordslip : string := "frmgen_wordslip_dis";
crcgen_bypass : string := "crcgen_bypass_dis";
crcgen_init : string := "crcgen_init_user_setting";
crcgen_init_user : bit_vector := B"11111111111111111111111111111111";
crcgen_inv : string := "crcgen_inv_dis";
crcgen_err : string := "crcgen_err_dis";
enc_64b66b_10g_mode : string := "enc_64b66b_10g_mode_en";
enc_64b66b_txsm_bypass : string := "enc_64b66b_txsm_bypass_dis";
tx_sm_bypass : string := "tx_sm_bypass_dis";
tx_sm_pipeln : string := "tx_sm_pipeln_dis";
scrm_bypass : string := "scrm_bypass_dis";
test_mode : string := "test_off";
pseudo_random : string := "all_0";
pseudo_seed_a : string := "pseudo_seed_a_user_setting";
pseudo_seed_a_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
pseudo_seed_b : string := "pseudo_seed_b_user_setting";
pseudo_seed_b_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
bit_reverse : string := "bit_reverse_dis";
scrm_seed : string := "scram_seed_user_setting";
scrm_seed_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
scrm_mode : string := "async";
dispgen_bypass : string := "dispgen_bypass_dis";
dispgen_err : string := "dispgen_err_dis";
dispgen_pipeln : string := "dispgen_pipeln_dis";
gb_sel_mode : string := "internal";
sq_wave : string := "sq_wave_4";
bitslip_en : string := "bitslip_dis";
fastpath : string := "fastpath_dis";
distup_bypass_pipeln : string := "distup_bypass_pipeln_dis";
distup_master : string := "distup_master_en";
distdwn_bypass_pipeln : string := "distdwn_bypass_pipeln_dis";
distdwn_master : string := "distdwn_master_en";
compin_sel : string := "compin_master";
comp_cnt : string := "comp_cnt_00";
indv : string := "indv_en";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_tx_pma_clk";
channel_number : integer := 0;
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
test_bus_mode : string := "tx";
lpm_type : string := "stratixv_hssi_10g_tx_pcs"
);
port (
txpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33lc : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
txpldclk : in std_logic_vector(0 downto 0);
txpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txdatavalid : in std_logic_vector(0 downto 0);
txbitslip : in std_logic_vector(6 downto 0);
txdiagnosticstatus : in std_logic_vector(1 downto 0);
txwordslip : in std_logic_vector(0 downto 0);
txbursten : in std_logic_vector(0 downto 0);
txdisparityclr : in std_logic_vector(0 downto 0);
txclkout : out std_logic_vector(0 downto 0);
txclkiqout : out std_logic_vector(0 downto 0);
txfifoempty : out std_logic_vector(0 downto 0);
txfifopartialempty : out std_logic_vector(0 downto 0);
txfifopartialfull : out std_logic_vector(0 downto 0);
txfifofull : out std_logic_vector(0 downto 0);
txframe : out std_logic_vector(0 downto 0);
txburstenexe : out std_logic_vector(0 downto 0);
txwordslipexe : out std_logic_vector(0 downto 0);
distupindv : in std_logic_vector(0 downto 0);
distdwnindv : in std_logic_vector(0 downto 0);
distupinwren : in std_logic_vector(0 downto 0);
distdwninwren : in std_logic_vector(0 downto 0);
distupinrden : in std_logic_vector(0 downto 0);
distdwninrden : in std_logic_vector(0 downto 0);
distupoutdv : out std_logic_vector(0 downto 0);
distdwnoutdv : out std_logic_vector(0 downto 0);
distupoutwren : out std_logic_vector(0 downto 0);
distdwnoutwren : out std_logic_vector(0 downto 0);
distupoutrden : out std_logic_vector(0 downto 0);
distdwnoutrden : out std_logic_vector(0 downto 0);
txtestdata : out std_logic_vector(19 downto 0);
txdata : in std_logic_vector(63 downto 0);
txcontrol : in std_logic_vector(8 downto 0);
loopbackdataout : out std_logic_vector(39 downto 0);
txpmadata : out std_logic_vector(39 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_10g_tx_pcs_encrypted
generic map (
prot_mode => prot_mode,
sup_mode => sup_mode,
ctrl_plane_bonding => ctrl_plane_bonding,
master_clk_sel => master_clk_sel,
wr_clk_sel => wr_clk_sel,
wrfifo_clken => wrfifo_clken,
rdfifo_clken => rdfifo_clken,
frmgen_clken => frmgen_clken,
crcgen_clken => crcgen_clken,
enc64b66b_txsm_clken => enc64b66b_txsm_clken,
scrm_clken => scrm_clken,
dispgen_clken => dispgen_clken,
prbs_clken => prbs_clken,
sqwgen_clken => sqwgen_clken,
gbred_clken => gbred_clken,
gb_tx_idwidth => gb_tx_idwidth,
gb_tx_odwidth => gb_tx_odwidth,
txfifo_mode => txfifo_mode,
txfifo_pempty => txfifo_pempty,
txfifo_pfull => txfifo_pfull,
txfifo_empty => txfifo_empty,
txfifo_full => txfifo_full,
frmgen_bypass => frmgen_bypass,
frmgen_pipeln => frmgen_pipeln,
frmgen_mfrm_length => frmgen_mfrm_length,
frmgen_mfrm_length_user => frmgen_mfrm_length_user,
frmgen_pyld_ins => frmgen_pyld_ins,
sh_err => sh_err,
frmgen_burst => frmgen_burst,
frmgen_wordslip => frmgen_wordslip,
crcgen_bypass => crcgen_bypass,
crcgen_init => crcgen_init,
crcgen_init_user => crcgen_init_user,
crcgen_inv => crcgen_inv,
crcgen_err => crcgen_err,
enc_64b66b_10g_mode => enc_64b66b_10g_mode,
enc_64b66b_txsm_bypass => enc_64b66b_txsm_bypass,
tx_sm_bypass => tx_sm_bypass,
tx_sm_pipeln => tx_sm_pipeln,
scrm_bypass => scrm_bypass,
test_mode => test_mode,
pseudo_random => pseudo_random,
pseudo_seed_a => pseudo_seed_a,
pseudo_seed_a_user => pseudo_seed_a_user,
pseudo_seed_b => pseudo_seed_b,
pseudo_seed_b_user => pseudo_seed_b_user,
bit_reverse => bit_reverse,
scrm_seed => scrm_seed,
scrm_seed_user => scrm_seed_user,
scrm_mode => scrm_mode,
dispgen_bypass => dispgen_bypass,
dispgen_err => dispgen_err,
dispgen_pipeln => dispgen_pipeln,
gb_sel_mode => gb_sel_mode,
sq_wave => sq_wave,
bitslip_en => bitslip_en,
fastpath => fastpath,
distup_bypass_pipeln => distup_bypass_pipeln,
distup_master => distup_master,
distdwn_bypass_pipeln => distdwn_bypass_pipeln,
distdwn_master => distdwn_master,
compin_sel => compin_sel,
comp_cnt => comp_cnt,
indv => indv,
stretch_num_stages => stretch_num_stages,
stretch_en => stretch_en,
iqtxrx_clkout_sel => iqtxrx_clkout_sel,
channel_number => channel_number,
frmgen_sync_word => frmgen_sync_word,
frmgen_scrm_word => frmgen_scrm_word,
frmgen_skip_word => frmgen_skip_word,
frmgen_diag_word => frmgen_diag_word,
test_bus_mode => test_bus_mode,
lpm_type => lpm_type
)
port map (
txpmaclk => txpmaclk,
pmaclkdiv33lc => pmaclkdiv33lc,
hardresetn => hardresetn,
txpldclk => txpldclk,
txpldrstn => txpldrstn,
refclkdig => refclkdig,
txdatavalid => txdatavalid,
txbitslip => txbitslip,
txdiagnosticstatus => txdiagnosticstatus,
txwordslip => txwordslip,
txbursten => txbursten,
txdisparityclr => txdisparityclr,
txclkout => txclkout,
txclkiqout => txclkiqout,
txfifoempty => txfifoempty,
txfifopartialempty => txfifopartialempty,
txfifopartialfull => txfifopartialfull,
txfifofull => txfifofull,
txframe => txframe,
txburstenexe => txburstenexe,
txwordslipexe => txwordslipexe,
distupindv => distupindv,
distdwnindv => distdwnindv,
distupinwren => distupinwren,
distdwninwren => distdwninwren,
distupinrden => distupinrden,
distdwninrden => distdwninrden,
distupoutdv => distupoutdv,
distdwnoutdv => distdwnoutdv,
distupoutwren => distupoutwren,
distdwnoutwren => distdwnoutwren,
distupoutrden => distupoutrden,
distdwnoutrden => distdwnoutrden,
txtestdata => txtestdata,
txdata => txdata,
txcontrol => txcontrol,
loopbackdataout => loopbackdataout,
txpmadata => txpmadata,
syncdatain => syncdatain
);
end behavior;
------------------------------------------------------------------------------------
-- This is the HSSI Simulation Atom Model Encryption wrapper for the AVMM Interface
-- Entity Name : stratixv_hssi_avmm_interface
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_avmm_interface is
generic (
num_ch0_atoms : integer := 0;
num_ch1_atoms : integer := 0;
num_ch2_atoms : integer := 0
);
port (
avmmrstn : in std_logic_vector(0 downto 0);
avmmclk : in std_logic_vector(0 downto 0);
avmmwrite : in std_logic_vector(0 downto 0);
avmmread : in std_logic_vector(0 downto 0);
avmmbyteen : in std_logic_vector(1 downto 0);
avmmaddress : in std_logic_vector(10 downto 0);
avmmwritedata : in std_logic_vector(15 downto 0);
blockselect : in std_logic_vector(90-1 downto 0);
readdatachnl : in std_logic_vector(90*16-1 downto 0);
avmmreaddata : out std_logic_vector(15 downto 0);
clkchnl : out std_logic_vector(0 downto 0);
rstnchnl : out std_logic_vector(0 downto 0);
writedatachnl : out std_logic_vector(15 downto 0);
regaddrchnl : out std_logic_vector(10 downto 0);
writechnl : out std_logic_vector(0 downto 0);
readchnl : out std_logic_vector(0 downto 0);
byteenchnl : out std_logic_vector(1 downto 0);
-- The following ports are not modelled. They exist to match the avmm interface atom interface
refclkdig : in std_logic_vector(0 downto 0);
avmmreservedin : in std_logic_vector(0 downto 0);
avmmreservedout : out std_logic_vector(0 downto 0);
dpriorstntop : out std_logic_vector(0 downto 0);
dprioclktop : out std_logic_vector(0 downto 0);
mdiodistopchnl : out std_logic_vector(0 downto 0);
dpriorstnmid : out std_logic_vector(0 downto 0);
dprioclkmid : out std_logic_vector(0 downto 0);
mdiodismidchnl : out std_logic_vector(0 downto 0);
dpriorstnbot : out std_logic_vector(0 downto 0);
dprioclkbot : out std_logic_vector(0 downto 0);
mdiodisbotchnl : out std_logic_vector(0 downto 0);
dpriotestsitopchnl : out std_logic_vector(3 downto 0);
dpriotestsimidchnl : out std_logic_vector(3 downto 0);
dpriotestsibotchnl : out std_logic_vector(3 downto 0);
-- The following ports belong to pm_adce and pm_tst_mux blocks in the PMA
pmatestbus : out std_logic_vector(23 downto 0);
pmatestbussel : in std_logic_vector(11 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
interfacesel : in std_logic_vector(0 downto 0);
sershiftload : in std_logic_vector(0 downto 0)
);
end stratixv_hssi_avmm_interface;
architecture behavior of stratixv_hssi_avmm_interface is
component stratixv_hssi_avmm_interface_encrypted
generic (
num_ch0_atoms : integer := 0;
num_ch1_atoms : integer := 0;
num_ch2_atoms : integer := 0
);
port (
avmmrstn : in std_logic_vector(0 downto 0);
avmmclk : in std_logic_vector(0 downto 0);
avmmwrite : in std_logic_vector(0 downto 0);
avmmread : in std_logic_vector(0 downto 0);
avmmbyteen : in std_logic_vector(1 downto 0);
avmmaddress : in std_logic_vector(10 downto 0);
avmmwritedata : in std_logic_vector(15 downto 0);
blockselect : in std_logic_vector(90-1 downto 0);
readdatachnl : in std_logic_vector(90*16-1 downto 0);
avmmreaddata : out std_logic_vector(15 downto 0);
clkchnl : out std_logic_vector(0 downto 0);
rstnchnl : out std_logic_vector(0 downto 0);
writedatachnl : out std_logic_vector(15 downto 0);
regaddrchnl : out std_logic_vector(10 downto 0);
writechnl : out std_logic_vector(0 downto 0);
readchnl : out std_logic_vector(0 downto 0);
byteenchnl : out std_logic_vector(1 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
avmmreservedin : in std_logic_vector(0 downto 0);
avmmreservedout : out std_logic_vector(0 downto 0);
dpriorstntop : out std_logic_vector(0 downto 0);
dprioclktop : out std_logic_vector(0 downto 0);
mdiodistopchnl : out std_logic_vector(0 downto 0);
dpriorstnmid : out std_logic_vector(0 downto 0);
dprioclkmid : out std_logic_vector(0 downto 0);
mdiodismidchnl : out std_logic_vector(0 downto 0);
dpriorstnbot : out std_logic_vector(0 downto 0);
dprioclkbot : out std_logic_vector(0 downto 0);
mdiodisbotchnl : out std_logic_vector(0 downto 0);
dpriotestsitopchnl : out std_logic_vector(3 downto 0);
dpriotestsimidchnl : out std_logic_vector(3 downto 0);
dpriotestsibotchnl : out std_logic_vector(3 downto 0);
pmatestbus : out std_logic_vector(23 downto 0);
pmatestbussel : in std_logic_vector(11 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
interfacesel : in std_logic_vector(0 downto 0);
sershiftload : in std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_avmm_interface_encrypted
generic map (
num_ch0_atoms => num_ch0_atoms,
num_ch1_atoms => num_ch1_atoms,
num_ch2_atoms => num_ch2_atoms
)
port map (
avmmrstn => avmmrstn ,
avmmclk => avmmclk ,
avmmwrite => avmmwrite ,
avmmread => avmmread ,
avmmbyteen => avmmbyteen ,
avmmaddress => avmmaddress ,
avmmwritedata => avmmwritedata ,
blockselect => blockselect ,
readdatachnl => readdatachnl ,
avmmreaddata => avmmreaddata ,
clkchnl => clkchnl ,
rstnchnl => rstnchnl ,
writedatachnl => writedatachnl ,
regaddrchnl => regaddrchnl ,
writechnl => writechnl ,
readchnl => readchnl ,
byteenchnl => byteenchnl ,
refclkdig => refclkdig ,
avmmreservedin => avmmreservedin ,
avmmreservedout => avmmreservedout ,
dpriorstntop => dpriorstntop ,
dprioclktop => dprioclktop ,
mdiodistopchnl => mdiodistopchnl ,
dpriorstnmid => dpriorstnmid ,
dprioclkmid => dprioclkmid ,
mdiodismidchnl => mdiodismidchnl ,
dpriorstnbot => dpriorstnbot ,
dprioclkbot => dprioclkbot ,
mdiodisbotchnl => mdiodisbotchnl ,
dpriotestsitopchnl => dpriotestsitopchnl ,
dpriotestsimidchnl => dpriotestsimidchnl ,
dpriotestsibotchnl => dpriotestsibotchnl ,
pmatestbus => pmatestbus ,
pmatestbussel => pmatestbussel ,
scanmoden => scanmoden ,
scanshiftn => scanshiftn ,
interfacesel => interfacesel ,
sershiftload => sershiftload
);
end behavior;
|
----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.std_Pkg.ALL;
ENTITY dsram IS GENERIC
(
WIDTH : positive := 32;
SIZE : positive := 8
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END dsram;
ARCHITECTURE arch OF dsram IS
TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type;
BEGIN
PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF ena_i = '1' THEN
IF wre_i = '1' THEN
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
END IF;
dat_o <= ram(my_conv_integer(adr_i));
END IF;
END IF;
END PROCESS;
END arch;
|
----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.std_Pkg.ALL;
ENTITY dsram IS GENERIC
(
WIDTH : positive := 32;
SIZE : positive := 8
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END dsram;
ARCHITECTURE arch OF dsram IS
TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type;
BEGIN
PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF ena_i = '1' THEN
IF wre_i = '1' THEN
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
END IF;
dat_o <= ram(my_conv_integer(adr_i));
END IF;
END IF;
END PROCESS;
END arch;
|
----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.std_Pkg.ALL;
ENTITY dsram IS GENERIC
(
WIDTH : positive := 32;
SIZE : positive := 8
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END dsram;
ARCHITECTURE arch OF dsram IS
TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type;
BEGIN
PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF ena_i = '1' THEN
IF wre_i = '1' THEN
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
END IF;
dat_o <= ram(my_conv_integer(adr_i));
END IF;
END IF;
END PROCESS;
END arch;
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO; |
n = 256
bitrev:
0: "126"
1: "0"
2: "62"
3: "64"
4: "94"
5: "32"
6: "30"
7: "96"
8: "110"
9: "16"
10: "46"
11: "80"
12: "78"
13: "48"
14: "14"
15: "112"
16: "118"
17: "8"
18: "54"
19: "72"
20: "86"
21: "40"
22: "22"
23: "104"
24: "102"
25: "24"
26: "38"
27: "88"
28: "70"
29: "56"
30: "6"
31: "120"
32: "122"
33: "4"
34: "58"
35: "68"
36: "90"
37: "36"
38: "26"
39: "100"
40: "106"
41: "20"
42: "42"
43: "84"
44: "74"
45: "52"
46: "10"
47: "116"
48: "114"
49: "12"
50: "50"
51: "76"
52: "82"
53: "44"
54: "18"
55: "108"
56: "98"
57: "28"
58: "34"
59: "92"
60: "66"
61: "60"
62: "2"
63: "124"
T:
X"4000",
X"0",
X"3fec",
X"fffffcdc",
X"3fb1",
X"fffff9ba",
X"3f4f",
X"fffff69c",
X"3ec5",
X"fffff384",
X"3e15",
X"fffff073",
X"3d3f",
X"ffffed6c",
X"3c42",
X"ffffea70",
X"3b21",
X"ffffe782",
X"39db",
X"ffffe4a3",
X"3871",
X"ffffe1d5",
X"36e5",
X"ffffdf19",
X"3537",
X"ffffdc72",
X"3368",
X"ffffd9e0",
X"3179",
X"ffffd766",
X"2f6c",
X"ffffd505",
X"2d41",
X"ffffd2bf",
X"2afb",
X"ffffd094",
X"289a",
X"ffffce87",
X"2620",
X"ffffcc98",
X"238e",
X"ffffcac9",
X"20e7",
X"ffffc91b",
X"1e2b",
X"ffffc78f",
X"1b5d",
X"ffffc625",
X"187e",
X"ffffc4df",
X"1590",
X"ffffc3be",
X"1294",
X"ffffc2c1",
X"f8d",
X"ffffc1eb",
X"c7c",
X"ffffc13b",
X"964",
X"ffffc0b1",
X"646",
X"ffffc04f",
X"324",
X"ffffc014",
X"0",
X"ffffc000",
X"fffffcdd",
X"ffffc014",
X"fffff9bb",
X"ffffc04f",
X"fffff69d",
X"ffffc0b1",
X"fffff385",
X"ffffc13b",
X"fffff074",
X"ffffc1eb",
X"ffffed6d",
X"ffffc2c1",
X"ffffea71",
X"ffffc3be",
X"ffffe783",
X"ffffc4df",
X"ffffe4a4",
X"ffffc625",
X"ffffe1d6",
X"ffffc78f",
X"ffffdf1a",
X"ffffc91b",
X"ffffdc73",
X"ffffcac9",
X"ffffd9e1",
X"ffffcc98",
X"ffffd767",
X"ffffce87",
X"ffffd506",
X"ffffd094",
X"ffffd2c0",
X"ffffd2bf",
X"ffffd095",
X"ffffd505",
X"ffffce88",
X"ffffd766",
X"ffffcc99",
X"ffffd9e0",
X"ffffcaca",
X"ffffdc72",
X"ffffc91c",
X"ffffdf19",
X"ffffc790",
X"ffffe1d5",
X"ffffc626",
X"ffffe4a3",
X"ffffc4e0",
X"ffffe782",
X"ffffc3bf",
X"ffffea70",
X"ffffc2c2",
X"ffffed6c",
X"ffffc1ec",
X"fffff073",
X"ffffc13c",
X"fffff384",
X"ffffc0b2",
X"fffff69c",
X"ffffc050",
X"fffff9ba",
X"ffffc015",
X"fffffcdc",
X"3ffe",
X"64",
X"3ffc",
X"12d",
X"3ff7",
X"1f6",
X"3fef",
X"2bf",
X"3fe6",
X"388",
X"3fda",
X"450",
X"3fcb",
X"519",
X"3fb9",
X"5e1",
X"3fa6",
X"6aa",
X"3f90",
X"772",
X"3f77",
X"839",
X"3f5c",
X"900",
X"3f3f",
X"9c7",
X"3f1f",
X"a8d",
X"3efc",
X"b53",
X"3ed7",
X"c19",
X"3eb0",
X"cde",
X"3e86",
X"da3",
X"3e5a",
X"e67",
X"3e2c",
X"f2b",
X"3dfb",
X"fee",
X"3dc8",
X"10b0",
X"3d93",
X"1172",
X"3d5b",
X"1233",
X"3d20",
X"12f3",
X"3ce3",
X"13b3",
X"3ca4",
X"1472",
X"3c62",
X"1530",
X"3c1f",
X"15ee",
X"3bd9",
X"16aa",
X"3b90",
X"1766",
X"3b46",
X"1820",
X"3af9",
X"18da",
X"3aa9",
X"1992",
X"3a58",
X"1a4a",
X"3a04",
X"1b01",
X"39af",
X"1bb7",
X"3957",
X"1c6b",
X"38fc",
X"1d1f",
X"389f",
X"1dd1",
X"3840",
X"1e83",
X"37e0",
X"1f33",
X"377d",
X"1fe2",
X"3717",
X"2090",
X"36b0",
X"213c",
X"3646",
X"21e7",
X"35db",
X"2291",
X"356d",
X"2339",
X"34fe",
X"23e1",
X"348c",
X"2487",
X"3418",
X"252b",
X"33a2",
X"25ce",
X"332b",
X"2670",
X"32b1",
X"2710",
X"3235",
X"27ae",
X"31b7",
X"284b",
X"3138",
X"28e7",
X"30b6",
X"2981",
X"3033",
X"2a19",
X"2fae",
X"2aaf",
X"2f27",
X"2b44",
X"2e9e",
X"2bd7",
X"2e13",
X"2c69",
X"2d87",
X"2cf9",
X"1ffd",
X"ffffff37",
X"1fea",
X"fffffda6",
X"1fc2",
X"fffffc15",
X"1f87",
X"fffffa88",
X"1f39",
X"fffff8fd",
X"1ed7",
X"fffff777",
X"1e62",
X"fffff5f7",
X"1ddb",
X"fffff47c",
X"1d41",
X"fffff309",
X"1c95",
X"fffff19d",
X"1bd8",
X"fffff03a",
X"1b09",
X"ffffeee2",
X"1a29",
X"ffffed93",
X"193a",
X"ffffec50",
X"183b",
X"ffffeb19",
X"172d",
X"ffffe9f0",
X"1610",
X"ffffe8d3",
X"14e7",
X"ffffe7c5",
X"13b0",
X"ffffe6c6",
X"126d",
X"ffffe5d7",
X"111e",
X"ffffe4f7",
X"fc6",
X"ffffe428",
X"e63",
X"ffffe36b",
X"cf7",
X"ffffe2bf",
X"b84",
X"ffffe225",
X"a09",
X"ffffe19e",
X"889",
X"ffffe129",
X"703",
X"ffffe0c7",
X"578",
X"ffffe079",
X"3eb",
X"ffffe03e",
X"25a",
X"ffffe016",
X"c9",
X"ffffe003",
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_divider_GNKAPZN5MO is
generic ( Signed : natural := 0;
width : natural := 24;
pipeline : natural := 0);
port(
aclr : in std_logic;
clock : in std_logic;
denom : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
numer : in std_logic_vector((width)-1 downto 0);
quotient : out std_logic_vector((width)-1 downto 0);
remain : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_divider_GNKAPZN5MO is
Begin
-- Divide Operator - Simulink Block "alt_dspbuilder_divider"
Divideri : alt_dspbuilder_dividerAltr generic map (
widthin => 24,
isunsigned => 1,
pipeline => 0)
port map (
numer => numer,
denom => denom,
quotient => quotient,
remain => remain,
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_divider_GNKAPZN5MO is
generic ( Signed : natural := 0;
width : natural := 24;
pipeline : natural := 0);
port(
aclr : in std_logic;
clock : in std_logic;
denom : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
numer : in std_logic_vector((width)-1 downto 0);
quotient : out std_logic_vector((width)-1 downto 0);
remain : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_divider_GNKAPZN5MO is
Begin
-- Divide Operator - Simulink Block "alt_dspbuilder_divider"
Divideri : alt_dspbuilder_dividerAltr generic map (
widthin => 24,
isunsigned => 1,
pipeline => 0)
port map (
numer => numer,
denom => denom,
quotient => quotient,
remain => remain,
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_divider_GNKAPZN5MO is
generic ( Signed : natural := 0;
width : natural := 24;
pipeline : natural := 0);
port(
aclr : in std_logic;
clock : in std_logic;
denom : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
numer : in std_logic_vector((width)-1 downto 0);
quotient : out std_logic_vector((width)-1 downto 0);
remain : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_divider_GNKAPZN5MO is
Begin
-- Divide Operator - Simulink Block "alt_dspbuilder_divider"
Divideri : alt_dspbuilder_dividerAltr generic map (
widthin => 24,
isunsigned => 1,
pipeline => 0)
port map (
numer => numer,
denom => denom,
quotient => quotient,
remain => remain,
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_divider_GNKAPZN5MO is
generic ( Signed : natural := 0;
width : natural := 24;
pipeline : natural := 0);
port(
aclr : in std_logic;
clock : in std_logic;
denom : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
numer : in std_logic_vector((width)-1 downto 0);
quotient : out std_logic_vector((width)-1 downto 0);
remain : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_divider_GNKAPZN5MO is
Begin
-- Divide Operator - Simulink Block "alt_dspbuilder_divider"
Divideri : alt_dspbuilder_dividerAltr generic map (
widthin => 24,
isunsigned => 1,
pipeline => 0)
port map (
numer => numer,
denom => denom,
quotient => quotient,
remain => remain,
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
entity Q16_8_ABS is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q16_8_ABS is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_ABS : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1)
VARIABLE temp : SIGNED(15 downto 0);
begin
temp := abs( SIGNED( INPUT_1(15 downto 0) ) );
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(temp, 32) );
END PROCESS;
-------------------------------------------------------------------------
end;
|
-- #############################################################################
-- DE1_SoC_top_level.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.4
-- Creation date : 04/02/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_top_level is
port(
-- ADC
-- ADC_CS_n : out std_logic;
-- ADC_DIN : out std_logic;
-- ADC_DOUT : in std_logic;
-- ADC_SCLK : out std_logic;
-- Audio
-- AUD_ADCDAT : in std_logic;
-- AUD_ADCLRCK : inout std_logic;
-- AUD_BCLK : inout std_logic;
-- AUD_DACDAT : out std_logic;
-- AUD_DACLRCK : inout std_logic;
-- AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
-- CLOCK2_50 : in std_logic;
-- CLOCK3_50 : in std_logic;
-- CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
-- FPGA_I2C_SCLK : out std_logic;
-- FPGA_I2C_SDAT : inout std_logic;
-- SEG7
-- HEX0_N : out std_logic_vector(6 downto 0);
-- HEX1_N : out std_logic_vector(6 downto 0);
-- HEX2_N : out std_logic_vector(6 downto 0);
-- HEX3_N : out std_logic_vector(6 downto 0);
-- HEX4_N : out std_logic_vector(6 downto 0);
-- HEX5_N : out std_logic_vector(6 downto 0);
-- IR
-- IRDA_RXD : in std_logic;
-- IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
-- PS2_CLK : inout std_logic;
-- PS2_CLK2 : inout std_logic;
-- PS2_DAT : inout std_logic;
-- PS2_DAT2 : inout std_logic;
-- SW
-- SW : in std_logic_vector(9 downto 0);
-- Video-In
-- TD_CLK27 : inout std_logic;
-- TD_DATA : out std_logic_vector(7 downto 0);
-- TD_HS : out std_logic;
-- TD_RESET_N : out std_logic;
-- TD_VS : out std_logic;
-- VGA
-- VGA_B : out std_logic_vector(7 downto 0);
-- VGA_BLANK_N : out std_logic;
-- VGA_CLK : out std_logic;
-- VGA_G : out std_logic_vector(7 downto 0);
-- VGA_HS : out std_logic;
-- VGA_R : out std_logic_vector(7 downto 0);
-- VGA_SYNC_N : out std_logic;
-- VGA_VS : out std_logic;
-- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_top_level;
architecture rtl of DE1_SoC_top_level is
component soc_system is
port(
clk_clk : in std_logic := 'X';
hps_0_ddr_mem_a : out std_logic_vector(14 downto 0);
hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0);
hps_0_ddr_mem_ck : out std_logic;
hps_0_ddr_mem_ck_n : out std_logic;
hps_0_ddr_mem_cke : out std_logic;
hps_0_ddr_mem_cs_n : out std_logic;
hps_0_ddr_mem_ras_n : out std_logic;
hps_0_ddr_mem_cas_n : out std_logic;
hps_0_ddr_mem_we_n : out std_logic;
hps_0_ddr_mem_reset_n : out std_logic;
hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_odt : out std_logic;
hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0);
hps_0_ddr_oct_rzqin : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDC : out std_logic;
hps_0_io_hps_io_qspi_inst_CLK : out std_logic;
hps_0_io_hps_io_qspi_inst_SS0 : out std_logic;
hps_0_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_CLK : out std_logic;
hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_STP : out std_logic;
hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_0_io_hps_io_spim1_inst_CLK : out std_logic;
hps_0_io_hps_io_spim1_inst_MOSI : out std_logic;
hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X';
hps_0_io_hps_io_spim1_inst_SS0 : out std_logic;
hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_0_io_hps_io_uart0_inst_TX : out std_logic;
hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X';
pll_0_sdram_clk : out std_logic;
reset_reset_n : in std_logic := 'X';
sdram_controller_0_wire_addr : out std_logic_vector(12 downto 0);
sdram_controller_0_wire_ba : out std_logic_vector(1 downto 0);
sdram_controller_0_wire_cas_n : out std_logic;
sdram_controller_0_wire_cke : out std_logic;
sdram_controller_0_wire_cs_n : out std_logic;
sdram_controller_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
sdram_controller_0_wire_dqm : out std_logic_vector(1 downto 0);
sdram_controller_0_wire_ras_n : out std_logic;
sdram_controller_0_wire_we_n : out std_logic;
nios_leds_external_connection_export : out std_logic_vector(4 downto 0);
hps_fpga_leds_external_connection_export : out std_logic_vector(4 downto 0)
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map(
clk_clk => CLOCK_50,
hps_0_ddr_mem_a => HPS_DDR3_ADDR,
hps_0_ddr_mem_ba => HPS_DDR3_BA,
hps_0_ddr_mem_ck => HPS_DDR3_CK_P,
hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N,
hps_0_ddr_mem_cke => HPS_DDR3_CKE,
hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N,
hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N,
hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N,
hps_0_ddr_mem_we_n => HPS_DDR3_WE_N,
hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N,
hps_0_ddr_mem_dq => HPS_DDR3_DQ,
hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P,
hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N,
hps_0_ddr_mem_odt => HPS_DDR3_ODT,
hps_0_ddr_mem_dm => HPS_DDR3_DM,
hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ,
hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_0_io_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_0_io_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_0_io_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_0_io_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_0_io_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_0_io_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT,
hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK,
hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT,
hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK,
hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO,
hps_0_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL,
hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N,
hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
pll_0_sdram_clk => DRAM_CLK,
reset_reset_n => KEY_N(0),
sdram_controller_0_wire_addr => DRAM_ADDR,
sdram_controller_0_wire_ba => DRAM_BA,
sdram_controller_0_wire_cas_n => DRAM_CAS_N,
sdram_controller_0_wire_cke => DRAM_CKE,
sdram_controller_0_wire_cs_n => DRAM_CS_N,
sdram_controller_0_wire_dq => DRAM_DQ,
sdram_controller_0_wire_dqm(1) => DRAM_UDQM,
sdram_controller_0_wire_dqm(0) => DRAM_LDQM,
sdram_controller_0_wire_ras_n => DRAM_RAS_N,
sdram_controller_0_wire_we_n => DRAM_WE_N,
nios_leds_external_connection_export => LEDR(4 downto 0),
hps_fpga_leds_external_connection_export => LEDR(9 downto 5)
);
end;
|
-- #############################################################################
-- DE1_SoC_top_level.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.4
-- Creation date : 04/02/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_top_level is
port(
-- ADC
-- ADC_CS_n : out std_logic;
-- ADC_DIN : out std_logic;
-- ADC_DOUT : in std_logic;
-- ADC_SCLK : out std_logic;
-- Audio
-- AUD_ADCDAT : in std_logic;
-- AUD_ADCLRCK : inout std_logic;
-- AUD_BCLK : inout std_logic;
-- AUD_DACDAT : out std_logic;
-- AUD_DACLRCK : inout std_logic;
-- AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
-- CLOCK2_50 : in std_logic;
-- CLOCK3_50 : in std_logic;
-- CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
-- FPGA_I2C_SCLK : out std_logic;
-- FPGA_I2C_SDAT : inout std_logic;
-- SEG7
-- HEX0_N : out std_logic_vector(6 downto 0);
-- HEX1_N : out std_logic_vector(6 downto 0);
-- HEX2_N : out std_logic_vector(6 downto 0);
-- HEX3_N : out std_logic_vector(6 downto 0);
-- HEX4_N : out std_logic_vector(6 downto 0);
-- HEX5_N : out std_logic_vector(6 downto 0);
-- IR
-- IRDA_RXD : in std_logic;
-- IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
-- PS2_CLK : inout std_logic;
-- PS2_CLK2 : inout std_logic;
-- PS2_DAT : inout std_logic;
-- PS2_DAT2 : inout std_logic;
-- SW
-- SW : in std_logic_vector(9 downto 0);
-- Video-In
-- TD_CLK27 : inout std_logic;
-- TD_DATA : out std_logic_vector(7 downto 0);
-- TD_HS : out std_logic;
-- TD_RESET_N : out std_logic;
-- TD_VS : out std_logic;
-- VGA
-- VGA_B : out std_logic_vector(7 downto 0);
-- VGA_BLANK_N : out std_logic;
-- VGA_CLK : out std_logic;
-- VGA_G : out std_logic_vector(7 downto 0);
-- VGA_HS : out std_logic;
-- VGA_R : out std_logic_vector(7 downto 0);
-- VGA_SYNC_N : out std_logic;
-- VGA_VS : out std_logic;
-- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_top_level;
architecture rtl of DE1_SoC_top_level is
component soc_system is
port(
clk_clk : in std_logic := 'X';
hps_0_ddr_mem_a : out std_logic_vector(14 downto 0);
hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0);
hps_0_ddr_mem_ck : out std_logic;
hps_0_ddr_mem_ck_n : out std_logic;
hps_0_ddr_mem_cke : out std_logic;
hps_0_ddr_mem_cs_n : out std_logic;
hps_0_ddr_mem_ras_n : out std_logic;
hps_0_ddr_mem_cas_n : out std_logic;
hps_0_ddr_mem_we_n : out std_logic;
hps_0_ddr_mem_reset_n : out std_logic;
hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X');
hps_0_ddr_mem_odt : out std_logic;
hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0);
hps_0_ddr_oct_rzqin : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDC : out std_logic;
hps_0_io_hps_io_qspi_inst_CLK : out std_logic;
hps_0_io_hps_io_qspi_inst_SS0 : out std_logic;
hps_0_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_CLK : out std_logic;
hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_STP : out std_logic;
hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_0_io_hps_io_spim1_inst_CLK : out std_logic;
hps_0_io_hps_io_spim1_inst_MOSI : out std_logic;
hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X';
hps_0_io_hps_io_spim1_inst_SS0 : out std_logic;
hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_0_io_hps_io_uart0_inst_TX : out std_logic;
hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X';
pll_0_sdram_clk : out std_logic;
reset_reset_n : in std_logic := 'X';
sdram_controller_0_wire_addr : out std_logic_vector(12 downto 0);
sdram_controller_0_wire_ba : out std_logic_vector(1 downto 0);
sdram_controller_0_wire_cas_n : out std_logic;
sdram_controller_0_wire_cke : out std_logic;
sdram_controller_0_wire_cs_n : out std_logic;
sdram_controller_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
sdram_controller_0_wire_dqm : out std_logic_vector(1 downto 0);
sdram_controller_0_wire_ras_n : out std_logic;
sdram_controller_0_wire_we_n : out std_logic;
nios_leds_external_connection_export : out std_logic_vector(4 downto 0);
hps_fpga_leds_external_connection_export : out std_logic_vector(4 downto 0)
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map(
clk_clk => CLOCK_50,
hps_0_ddr_mem_a => HPS_DDR3_ADDR,
hps_0_ddr_mem_ba => HPS_DDR3_BA,
hps_0_ddr_mem_ck => HPS_DDR3_CK_P,
hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N,
hps_0_ddr_mem_cke => HPS_DDR3_CKE,
hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N,
hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N,
hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N,
hps_0_ddr_mem_we_n => HPS_DDR3_WE_N,
hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N,
hps_0_ddr_mem_dq => HPS_DDR3_DQ,
hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P,
hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N,
hps_0_ddr_mem_odt => HPS_DDR3_ODT,
hps_0_ddr_mem_dm => HPS_DDR3_DM,
hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ,
hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_0_io_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_0_io_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_0_io_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_0_io_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_0_io_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_0_io_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT,
hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK,
hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT,
hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK,
hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO,
hps_0_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL,
hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N,
hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
pll_0_sdram_clk => DRAM_CLK,
reset_reset_n => KEY_N(0),
sdram_controller_0_wire_addr => DRAM_ADDR,
sdram_controller_0_wire_ba => DRAM_BA,
sdram_controller_0_wire_cas_n => DRAM_CAS_N,
sdram_controller_0_wire_cke => DRAM_CKE,
sdram_controller_0_wire_cs_n => DRAM_CS_N,
sdram_controller_0_wire_dq => DRAM_DQ,
sdram_controller_0_wire_dqm(1) => DRAM_UDQM,
sdram_controller_0_wire_dqm(0) => DRAM_LDQM,
sdram_controller_0_wire_ras_n => DRAM_RAS_N,
sdram_controller_0_wire_we_n => DRAM_WE_N,
nios_leds_external_connection_export => LEDR(4 downto 0),
hps_fpga_leds_external_connection_export => LEDR(9 downto 5)
);
end;
|
-----------------------------------------------------------------------------
-- LEON Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
-- scb : inout std_logic_vector(7 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
rts1 : out std_ulogic;
cts1 : in std_ulogic;
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
rts2 : out std_ulogic;
cts2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emdintn : in std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_logic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRPCI2_MASTER + CFG_SDCTRL;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN + CFG_SDCTRL;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
----------------------------------------------------------------------
--- FIR component declaration --------------------------------------
----------------------------------------------------------------------
component fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_logic;
rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset: in std_logic
);
end component;
signal rm_reset : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI+CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM+2*CFG_PRC, -- CFG_PRC if FIR core not included,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => CFG_NCPU, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => CFG_NCPU-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#900#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 12, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc(0),
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(12), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
perf <= l3stat_in_none;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, syso.proc_error);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, sysi.dsu_enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, sysi.dsu_break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, syso.dsu_active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
ftmctrl0 : if CFG_MCTRLFT = 1 generate -- LEON2 memory controller
sr1 : ftmctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 4, sden => CFG_MCTRLFT_SDEN, ram8 => CFG_MCTRLFT_RAM8BIT,
ram16 => CFG_MCTRLFT_RAM16BIT, invclk => CFG_MCTRLFT_INVCLK,
sepbus => CFG_MCTRLFT_SEPBUS, oepol => OEPOL, edac => CFG_MCTRLFT_EDAC)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
cb_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (cb, memo.cb(7 downto 0), memo.vcdrive(7 downto 0), memi.cb(7 downto 0));
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRLFT_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRLFT_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
scb_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
-- port map (scb, memo.scb(7 downto 0), memo.svcdrive(7 downto 0), memi.scb(7 downto 0));
port map (sd(39 downto 32), memo.scb(7 downto 0), memo.svcdrive(7 downto 0), memi.scb(7 downto 0));
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 + CFG_MCTRLFT = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
-- sdc : if CFG_SDCTRL = 1 generate
-- sdc : sdctrl64 generic map (hindex => 3, haddr => 16#400#, hmask => 16#C00#,
-- ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK
---- , sdbits => 32 + 32*CFG_SDCTRL_SD64
-- )
-- port map (rstn, clkm, ahbsi2, ahbso2(3), sdi, sdo2);
-- sa_pad : outpadv generic map (width => 15, tech => padtech)
-- port map (sa, sdo2.address);
-- sd_pad : iopadv generic map (width => 32, tech => padtech)
-- port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
-- sd2 : if CFG_SDCTRL_SD64 = 1 generate
-- sd_pad2 : iopadv generic map (width => 32)
-- port map (sd(63 downto 32), sdo2.data(63 downto 32), sdo2.bdrive, sdi.data(63 downto 32));
-- end generate;
-- sdcke_pad : outpadv generic map (width =>2, tech => padtech)
-- port map (sdcke, sdo2.sdcke);
-- sdwen_pad : outpad generic map (tech => padtech)
-- port map (sdwen, sdo2.sdwen);
-- sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
-- port map (sdcsn, sdo2.sdcsn);
-- sdras_pad : outpad generic map (tech => padtech)
-- port map (sdrasn, sdo2.rasn);
-- sdcas_pad : outpad generic map (tech => padtech)
-- port map (sdcasn, sdo2.casn);
-- sddqm_pad : outpadv generic map (width =>8, tech => padtech)
-- port map (sddqm, sdo2.dqm(7 downto 0));
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
cts1_pad : inpad generic map (tech => padtech) port map (cts1, u1i.ctsn);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
rts1_pad : outpad generic map (tech => padtech) port map (rts1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
cts2_pad : inpad generic map (tech => padtech) port map (cts2, u2i.ctsn);
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
rts2_pad : outpad generic map (tech => padtech) port map (rts2, u2o.rtsn);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(6), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pci : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 or CFG_PCI /= 0 generate
grpci2x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and (CFG_PCI+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4,
haddr => 16#C00#,
hmask => 16#E00#,
ioaddr => 16#000#,
pindex => 4,
paddr => 4,
irq => 4,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_PCI = 0 and
CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4,
haddr => 16#C00#,
hmask => 16#E00#,
ioaddr => 16#000#,
pindex => 4,
paddr => 4,
irq => 4,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
grpci1x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) = 0 and CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 13, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(13));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(8)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 1, oepol => OEPOL,
noreset => 0, drivereset => 0, int => 10) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio, pci_int);
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => fabtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i, paddr => 10+i, pirq => 5+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1, memtech => memtech,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN, netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
-----------------------------------------------------------------------
prc : if CFG_PRC = 1 generate
p1 : dprc generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM, pindex => 10+CFG_SPW_NUM, paddr => 10+CFG_SPW_NUM, edac_en => CFG_EDAC_EN,
pirq => 10+CFG_SPW_NUM, technology => CFG_FABTECH, crc_en => CFG_CRC_EN, words_block => CFG_WORDS_BLOCK, fifo_dcm_inst => CFG_DCM_FIFO, fifo_depth => CFG_DPR_FIFO)
port map(rstn => rstn, clkm => clkm, clkraw => lclk, clk100 => '0', ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH
+CFG_SPW_NUM), apbi => apbi, apbo => apbo(10+CFG_SPW_NUM), rm_reset => rm_reset);
--------------------------------------------------------------------
-- FIR component instantiation (for dprc demo) -------------------
--------------------------------------------------------------------
fir_ex : FIR_AHB_DMA_APB
generic map (hindex=>CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM+CFG_PRC, pindex=>10+CFG_SPW_NUM+1, paddr=>10+CFG_SPW_NUM+1,
pmask=>16#fff#, technology =>CFG_FABTECH)
port map (rstn=>rstn, clk=>clkm, apbi=>apbi, apbo=>apbo(10+CFG_SPW_NUM+1), ahbin=>ahbmi, ahbout=>ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH
+CFG_SPW_NUM+CFG_PRC), rm_reset => rm_reset(0));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-CPCI-XC4V Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; |
-- libraries -------------------------------------------------------------------------------------------{{{
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
---------------------------------------------------------------------------------------------------------}}}
entity mult_add_sub is -- {{{
generic (DATA_W : natural := 32);
port (
sub : in std_logic; -- level 10.
a, c : in unsigned (DATA_W-1 downto 0); -- level 10.
b : in unsigned (DATA_W downto 0); -- level 10.
sra_sign_v : in std_logic := '0'; -- level 10.
sra_sign : in unsigned (DATA_W downto 0); -- level 10.
sltu_true_p0 : out std_logic := '0'; -- level 15.
res_low_p0 : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 15.
res_high : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 16.
clk, ce : in std_logic
);
end entity; --}}}
architecture Behavioral of mult_add_sub is
-- signals definitions ----------------------------------------------------------------------------------{{{
signal c_sub, res_low_low_d0 : unsigned(DATA_W downto 0) := (others=>'0');
signal res_low_low : unsigned(DATA_W downto 0) := (others=>'0');
signal res_low_high, res_high_low : unsigned(DATA_W downto 0) := (others=>'0');
signal res_high_high : unsigned(DATA_W downto 0) := (others=>'0');
signal res_middle : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal res_middle_high : unsigned(DATA_W downto 0) := (others=>'0');
signal zeros : unsigned(DATA_W downto 0) := (others=>'0');
signal res_middle_low : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal res_low_i : std_logic_vector(DATA_W downto 0) := (others=>'0');
signal a_high_d0, a_high_d1, a_high_d2 : unsigned(DATA_W/2-1 downto 0) := (others=>'0');
signal b_high_d0, b_high_d1, b_high_d2 : unsigned(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_low : unsigned(DATA_W downto 0) := (others=>'0');
signal sra_sign_high_d0 : signed(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_set_to_ones : std_logic := '0';
signal sra_sign_high_d1 : signed(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_high_d2 : signed(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_v_d0, sra_sign_v_d1 : std_logic := '0';
signal a_low_extended : unsigned(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_d0 : unsigned(DATA_W downto 0) := (others=>'0');
attribute use_dsp48 :string;
attribute use_dsp48 of res_middle : signal is "no";
---------------------------------------------------------------------------------------------------------}}}
begin
-- DSPs -------------------------------------------------------------------------------------------------{{{
mul_add_low_low: entity DSP48E1 generic map(
SIZE_A => DATA_W/2+1,
SIZE_B => DATA_W/2,
SUB => false
) port map(
clk => clk,
ce => ce,
ain => a_low_extended, -- level 10.
bin => b(DATA_W/2-1 downto 0), -- level 10.
cin => c_sub, -- level 11.
res => res_low_low -- level 13.
);
mul_add_low_high: entity DSP48E1 generic map(
SIZE_A => DATA_W/2,
SIZE_B => DATA_W/2+1,
SUB => true
) port map(
clk => clk,
ce => ce,
ain => a(DATA_W/2-1 downto 0), -- level 10.
bin => b(DATA_W downto DATA_W/2), -- level 10.
cin => sra_sign_low, -- level 11.
res => res_low_high -- level 13.
);
mul_add_high_low: entity DSP48E1 generic map(
SIZE_A => DATA_W/2,
SIZE_B => DATA_W/2,
SUB => false
) port map(
clk => clk,
ce => ce,
ain => a(DATA_W-1 downto DATA_W/2), -- level 10.
bin => b(DATA_W/2-1 downto 0), -- level 10.
cin => zeros(DATA_W-1 downto 0),
res => res_high_low(DATA_W-1 downto 0) -- level 13.
);
mul_add_high_high: entity DSP48E1 generic map(
SIZE_A => DATA_W/2,
SIZE_B => DATA_W/2+1,
SUB => false
) port map(
clk => clk,
ce => ce,
ain => a_high_d2, -- level 13.
bin => b_high_d2, -- level 13.
cin => res_middle_high, -- level 14.
res => res_high_high -- level 16.
);
---------------------------------------------------------------------------------------------------------}}}
-- other logic ------------------------------------------------------------------------------------------{{{
res_middle_low(DATA_W-1 downto DATA_W/2) <= res_middle(DATA_W/2-1 downto 0); -- level 14.
res_middle_high(DATA_W/2-1 downto 0) <= res_middle(DATA_W-1 downto DATA_W/2); -- level 14.
res_high <= std_logic_vector(res_high_high(DATA_W-1 downto 0)); -- level 16.
res_middle_high(DATA_W downto DATA_W/2) <= unsigned(sra_sign_high_d2); -- level 14.
a_low_extended <= '0' & a(DATA_W/2-1 downto 0);
process(clk)
begin
if rising_edge(clk) then
sra_sign_low(DATA_W downto DATA_W/2) <= sra_sign(DATA_W/2 downto 0); -- @ 11.
sra_sign_d0 <= sra_sign; -- @ 11.
sra_sign_v_d0 <= sra_sign_v; -- @ 11.
sra_sign_high_d0 <= -signed(sra_sign_d0(DATA_W downto DATA_W/2)); ---@ 12.
sra_sign_v_d1 <= sra_sign_v_d0; -- @ 12.
if sra_sign_high_d0 = (sra_sign_high_d0'range => '0') and sra_sign_v_d1 = '1' then -- level 12.
sra_sign_set_to_ones <= '1'; -- @ 13.
else
sra_sign_set_to_ones <= '0'; -- @ 13.
end if;
sra_sign_high_d1 <= sra_sign_high_d0; -- @ 13.
if sra_sign_set_to_ones = '1' then -- level 13.
sra_sign_high_d2 <= (others=>'1');
else
sra_sign_high_d2 <= sra_sign_high_d1; -- @ 14.
end if;
if sub = '1' then -- level 10.
c_sub <= unsigned(-signed('0' & c)); -- @ 11.
else
c_sub <= '0' & c; -- @ 11.
end if;
a_high_d0 <= a(DATA_W-1 downto DATA_W/2); -- @ 11.
b_high_d0 <= b(DATA_W downto DATA_W/2); -- @ 11.
a_high_d1 <= a_high_d0; -- @ 12.
b_high_d1 <= b_high_d0; -- @ 12.
a_high_d2 <= a_high_d1; -- @ 13.
b_high_d2 <= b_high_d1; -- @ 13.
-- stage 0 after DSPs
res_low_low_d0 <= res_low_low; -- @ 14.
res_middle <= res_high_low(DATA_W-1 downto 0) + res_low_high(DATA_W-1 downto 0); -- @ 14.
-- stage 1 after DSP
res_low_i <= std_logic_vector(res_low_low_d0 + unsigned('0'&res_middle_low)); -- @ 15.
end if;
end process;
res_low_p0 <= res_low_i(DATA_W-1 downto 0); -- @ 15.
sltu_true_p0 <= res_low_i(DATA_W); -- @ 15.
---------------------------------------------------------------------------------------------------------}}}
end architecture;
|
----- Libraries -----
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BaudRateGenerator is
port ( clk, reset : in std_logic;
clk_baud : out std_logic
);
end BaudRateGenerator;
architecture Gen115200 of BaudRateGenerator is
begin
process(clk, reset)
variable clk_count : integer;
begin
--clk_baud <= '0';
if reset = '0' then
clk_count := 0;
elsif rising_edge(clk) then
clk_count := clk_count + 1;
else
null;
end if;
-- if clk_count rem 434 = 0 then -- Possible horrible way to implement this. What happens when the clk_count register is full?
case clk_count is
--when 433 => -- FOR 115200 Hz
when 200 => -- FOR SIMULATION
clk_baud <= '1';
--when 434 => -- FOR 115200 Hz
when 201 => -- FOR SIMULATION
clk_count := 0;
when others =>
clk_baud <= '0';
end case;
end process;
end Gen115200; |
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 15:45:01 02/10/2014
-- Design Name:
-- Module Name: AudioDemo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Description:
-- This module represents the Audio Demo for the Nexys4 DDR onboard ADMP421 Omnidirectional Microphone
-- The module consists of several components:
-- - Deserializer, module name PdmDes, that generates the pdm_clk signal for the microphone,
-- receives the microphone data and deserializes it in 16-bit samples. No PDM decoding is done
--
-- - RAM controller, module name RamCntrl, that emulates a RAM Memory Controller and writes the samples to,
-- or reads from a RAM Memory.
--
-- - RAM to DDR interface and DDR controller, module name Ram2Ddr, that creates a RAM-style interface
-- for the Nexys4 onboard Micron MT47H64M16HR-25 1Gb (64M X 16) DDR2 memory. The DDR interface was generated
-- using Memory Interface Generator (MIG) v 1.9. The Ram2Ddr component is controlled by the RamCntrl controller
-- described above and can be also used separately as a memory solution for ISE designs
--
-- - Serializer, module name PdmSer, that receives the samples read from the memory, deserializes and
-- sends the PDM modulated data to the Sallen-Key Butterworth Low Pass 4th Order Filter, from where
-- audio can be listened on the Mono Audio Out connector (J8)
--
-- - Led-Bar, module name LedBar, that generates the progressbar on LD15..LD0 which moves to left
-- when recording ands to right when playing back
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity AudioDemo is
port (
-- Common
clk_i : in std_logic;
clk_200_i : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
rst_i : in std_logic;
-- Peripherals
btn_u : in std_logic;
leds_o : out std_logic_vector(15 downto 0);
-- Microphone PDM signals
pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone
pdm_m_data_i : in std_logic; -- Input PDM data from the microphone
pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge
-- Audio output signals
pwm_audio_o : inout std_logic; -- Output Audio data to the lowpass filters
pwm_sdaudio_o : out std_logic; -- Output Audio enable
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay
-- component in the VGA controller
);
end AudioDemo;
architecture Behavioral of AudioDemo is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component Dbncr is
generic(
NR_OF_CLKS : integer := 4095);
port(
clk_i : in std_logic;
sig_i : in std_logic;
pls_o : out std_logic);
end component;
-- deserializer
component PdmDes is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_HZ : integer := 2000000
);
port(
clk_i : in std_logic;
en_i : in std_logic; -- Enable deserializing (during record)
done_o : out std_logic; -- Signaling that 16 bits are deserialized
data_o : out std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- output deserialized data
-- PDM
pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone
pdm_m_data_i : in std_logic; -- Input PDM data from the microphone
pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge
pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay
-- component in the VGA controller
);
end component;
-- RAM Controller
component RamCntrl is
generic (
-- read/write cycle (ns)
C_RW_CYCLE_NS : integer := 100
);
port (
-- Control interface
clk_i : in std_logic; -- 100 MHz system clock
rst_i : in std_logic; -- active high system reset
rnw_i : in std_logic; -- read/write
be_i : in std_logic_vector(3 downto 0); -- byte enable
addr_i : in std_logic_vector(31 downto 0); -- address input
data_i : in std_logic_vector(31 downto 0); -- data input
cs_i : in std_logic; -- active high chip select
data_o : out std_logic_vector(31 downto 0); -- data output
rd_ack_o : out std_logic; -- read acknowledge flag
wr_ack_o : out std_logic; -- write acknowledge flag
-- RAM Memory signals
Mem_A : out std_logic_vector(26 downto 0); -- Address
Mem_DQ_O : out std_logic_vector(15 downto 0); -- Data Out
Mem_DQ_I : in std_logic_vector(15 downto 0); -- Data In
Mem_DQ_T : out std_logic_vector(15 downto 0); -- Data Tristate Enable, used for a bidirectional data bus only
Mem_CEN : out std_logic; -- Chip Enable
Mem_OEN : out std_logic; -- Output Enable
Mem_WEN : out std_logic; -- Write Enable
Mem_UB : out std_logic; -- Upper Byte
Mem_LB : out std_logic -- Lower Byte
);
end component;
-- RAM to DDR interface and DDR Controller
component Ram2Ddr is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0));
end component;
-- pdm serializer
component PdmSer is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_HZ : integer := 2000000
);
port(
clk_i : in std_logic;
en_i : in std_logic; -- Enable serializing (during playback)
done_o : out std_logic; -- Signaling that data_i is sent
data_i : in std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- input data
-- PWM
pwm_audio_o : inout std_logic -- Output audio data
);
end component;
-- led-bar
component LedBar is
generic(
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_SECONDS_TO_RECORD : integer := 3);
port(
clk_i : in std_logic; -- system clock
en_i : in std_logic; -- active-high enable
rnl_i : in std_logic; -- Right/Left shift select
leds_o : out std_logic_vector(15 downto 0)); -- output LED bus
end component;
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
constant SECONDS_TO_RECORD : integer := 5;
constant PDM_FREQ_HZ : integer := 2000000;
constant SYS_CLK_FREQ_MHZ : integer := 100;
constant NR_OF_BITS : integer := 16;
constant NR_SAMPLES_TO_REC : integer := (((SECONDS_TO_RECORD*PDM_FREQ_HZ)/NR_OF_BITS) - 1);
constant RW_CYCLE_NS : integer := 1200;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
type state_type is (stIdle, stRecord, stInter, stPlayback);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal state, next_state : state_type;
-- common
signal btnu_int : std_logic;
signal rnw_int : std_logic;
signal addr_int : std_logic_vector(31 downto 0);
signal done_int : std_logic;
signal pwm_audio_o_int : std_logic;
-- record
signal en_des : std_logic;
signal done_des : std_logic;
signal done_async_des : std_logic;
signal data_des : std_logic_vector(15 downto 0) := (others => '0');
signal data_dess : std_logic_vector(31 downto 0) := (others => '0');
signal addr_rec : std_logic_vector(31 downto 0) := (others => '0');
signal cntRecSamples : integer := 0;
signal done_des_dly : std_logic;
-- playback
signal en_ser : std_logic;
signal done_ser : std_logic;
signal rd_ack_int : std_logic;
signal data_ser : std_logic_vector(31 downto 0);
signal data_serr : std_logic_vector(15 downto 0);
signal done_async_ser : std_logic;
signal addr_play : std_logic_vector(31 downto 0) := (others => '0');
signal cntPlaySamples : integer := 0;
signal done_ser_dly : std_logic;
-- led-bar
signal en_leds : std_logic;
signal rnl_int : std_logic;
-- memory interconnection signals
signal mem_a : std_logic_vector(26 downto 0);
signal mem_a_int : std_logic_vector(26 downto 0);
signal mem_dq_i : std_logic_vector(15 downto 0);
signal mem_dq_o : std_logic_vector(15 downto 0);
signal mem_cen : std_logic;
signal mem_oen : std_logic;
signal mem_wen : std_logic;
signal mem_ub : std_logic;
signal mem_lb : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
Btnu: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btn_u,
pls_o => btnu_int);
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
Deserializer: PdmDes
generic map(
C_NR_OF_BITS => NR_OF_BITS,
C_SYS_CLK_FREQ_MHZ => SYS_CLK_FREQ_MHZ,
C_PDM_FREQ_HZ => PDM_FREQ_HZ)
port map(
clk_i => clk_i,
en_i => en_des,
done_o => done_async_des,
data_o => data_des,
pdm_m_clk_o => pdm_m_clk_o,
pdm_m_data_i => pdm_m_data_i,
pdm_lrsel_o => pdm_lrsel_o,
pdm_clk_rising_o => pdm_clk_rising_o
);
------------------------------------------------------------------------
-- Memory
------------------------------------------------------------------------
RAM: RamCntrl
generic map (
C_RW_CYCLE_NS => RW_CYCLE_NS)
port map (
clk_i => clk_i,
rst_i => rst_i,
rnw_i => rnw_int,
be_i => "0011", -- 16-bit access
addr_i => addr_int,
data_i => data_dess,
cs_i => done_int,
data_o => data_ser,
rd_ack_o => rd_ack_int,
wr_ack_o => open,
-- RAM Memory signals
Mem_A => mem_a,
Mem_DQ_O => mem_dq_i,
Mem_DQ_I => mem_dq_o,
Mem_DQ_T => open,
Mem_CEN => mem_cen,
Mem_OEN => mem_oen,
Mem_WEN => mem_wen,
Mem_UB => mem_ub,
Mem_LB => mem_lb
);
DDR: Ram2Ddr
port map (
clk_200MHz_i => clk_200_i,
rst_i => rst_i,
device_temp_i => device_temp_i,
-- RAM interface
ram_a => mem_a,
ram_dq_i => mem_dq_i,
ram_dq_o => mem_dq_o,
ram_cen => mem_cen,
ram_oen => mem_oen,
ram_wen => mem_wen,
ram_ub => mem_ub,
ram_lb => mem_lb,
-- DDR2 interface
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n
);
done_int <= done_des when state = stRecord else
done_ser when state = stPlayback else '0';
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
process(clk_i)
begin
if rising_edge(clk_i) then
if rd_ack_int = '1' then
data_serr <= data_ser(15 downto 0);
end if;
-- done deserializer
done_des <= done_async_des;
-- deserialized data
data_dess <= x"0000" & data_des;
-- done serializer
done_ser <= done_async_ser;
end if;
end process;
Serializer: PdmSer
generic map(
C_NR_OF_BITS => NR_OF_BITS,
C_SYS_CLK_FREQ_MHZ => SYS_CLK_FREQ_MHZ,
C_PDM_FREQ_HZ => PDM_FREQ_HZ)
port map(
clk_i => clk_i,
en_i => en_ser,
done_o => done_async_ser,
data_i => data_serr,
pwm_audio_o => pwm_audio_o
);
-- count the recorded samples
process(clk_i)
begin
if rising_edge(clk_i) then
if state = stRecord then
if done_des = '1' then
cntRecSamples <= cntRecSamples + 1;
end if;
if done_des_dly = '1' then
addr_rec <= addr_rec + "10";
end if;
else
cntRecSamples <= 0;
addr_rec <= (others => '0');
end if;
done_des_dly <= done_des;
end if;
end process;
-- count the played samples
process(clk_i)
begin
if rising_edge(clk_i) then
if state = stPlayback then
if done_ser = '1' then
cntPlaySamples <= cntPlaySamples + 1;
end if;
if done_ser_dly = '1' then
addr_play <= addr_play + "10";
end if;
else
cntPlaySamples <= 0;
addr_play <= (others => '0');
end if;
done_ser_dly <= done_ser;
end if;
end process;
------------------------------------------------------------------------
-- FSM
------------------------------------------------------------------------
SYNC_PROC: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
state <= stIdle;
else
state <= next_state;
end if;
end if;
end process;
--Decode Outputs from the State Machine
OUTPUT_DECODE: process(clk_i)
begin
if rising_edge(clk_i) then
case (state) is
when stIdle =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '0';
addr_int <= (others => '0');
en_leds <= '0';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
when stRecord =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '1';
addr_int <= addr_rec;
en_leds <= '1';
rnl_int <= '1';
pwm_sdaudio_o <= '1';
when stInter =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '0';
addr_int <= (others => '0');
en_leds <= '0';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
when stPlayback =>
rnw_int <= '1';
en_ser <= '1';
en_des <= '0';
addr_int <= addr_play;
en_leds <= '1';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
when others =>
rnw_int <= '0';
en_ser <= '0';
en_des <= '0';
addr_int <= (others => '0');
en_leds <= '0';
rnl_int <= '0';
pwm_sdaudio_o <= '1';
end case;
end if;
end process;
NEXT_STATE_DECODE: process(state, btnu_int, cntRecSamples, cntPlaySamples)
begin
next_state <= state;
case (state) is
when stIdle =>
if btnu_int = '1' then
next_state <= stRecord;
end if;
when stRecord =>
if cntRecSamples = NR_SAMPLES_TO_REC then
next_state <= stInter;
end if;
when stInter =>
next_state <= stPlayback;
when stPlayback =>
if btnu_int = '1' then
next_state <= stIdle;
elsif cntPlaySamples = NR_SAMPLES_TO_REC then
next_state <= stIdle;
end if;
when others =>
next_state <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- LED-bar display
------------------------------------------------------------------------
Leds: LedBar
generic map(
C_SYS_CLK_FREQ_MHZ => SYS_CLK_FREQ_MHZ,
C_SECONDS_TO_RECORD => SECONDS_TO_RECORD)
port map(
clk_i => clk_i,
en_i => en_leds,
rnl_i => rnl_int,
leds_o => leds_o);
end Behavioral;
|
-- This -*- vhdl -*- file was generated from std_logic_1164-body.proto
-- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
-- This is a template file. To avoid errors and duplication, the python
-- script build.py generate most of the bodies.
package body std_logic_1164 is
type table_1d is array (std_ulogic) of std_ulogic;
type table_2d is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX0X0000X", -- 0
"UXX11111X", -- 1
"UX01ZWLHX", -- Z
"UX01WWWWX", -- W
"UX01LWLWX", -- L
"UX01HWWHX", -- H
"UXXXXXXXX" -- -
);
function resolved (s : std_ulogic_vector) return std_ulogic
is
variable res : std_ulogic := 'Z';
begin
for I in s'range loop
res := resolution (res, s (I));
end loop;
return res;
end resolved;
constant and_table : table_2d :=
-- UX01ZWLH-
("UU0UUU0UU", -- U
"UX0XXX0XX", -- X
"000000000", -- 0
"UX01XX01X", -- 1
"UX0XXX0XX", -- Z
"UX0XXX0XX", -- W
"000000000", -- L
"UX01XX01X", -- H
"UX0XXX0XX" -- -
);
constant nand_table : table_2d :=
-- UX01ZWLH-
("UU1UUU1UU", -- U
"UX1XXX1XX", -- X
"111111111", -- 0
"UX10XX10X", -- 1
"UX1XXX1XX", -- Z
"UX1XXX1XX", -- W
"111111111", -- L
"UX10XX10X", -- H
"UX1XXX1XX" -- -
);
constant or_table : table_2d :=
-- UX01ZWLH-
("UUU1UUU1U", -- U
"UXX1XXX1X", -- X
"UX01XX01X", -- 0
"111111111", -- 1
"UXX1XXX1X", -- Z
"UXX1XXX1X", -- W
"UX01XX01X", -- L
"111111111", -- H
"UXX1XXX1X" -- -
);
constant nor_table : table_2d :=
-- UX01ZWLH-
("UUU0UUU0U", -- U
"UXX0XXX0X", -- X
"UX10XX10X", -- 0
"000000000", -- 1
"UXX0XXX0X", -- Z
"UXX0XXX0X", -- W
"UX10XX10X", -- L
"000000000", -- H
"UXX0XXX0X" -- -
);
constant xor_table : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX01XX01X", -- 0
"UX10XX10X", -- 1
"UXXXXXXXX", -- Z
"UXXXXXXXX", -- W
"UX01XX01X", -- L
"UX10XX10X", -- H
"UXXXXXXXX" -- -
);
constant xnor_table : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX10XX10X", -- 0
"UX01XX01X", -- 1
"UXXXXXXXX", -- Z
"UXXXXXXXX", -- W
"UX10XX10X", -- L
"UX01XX01X", -- H
"UXXXXXXXX" -- -
);
constant not_table : table_1d :=
-- UX01ZWLH-
"UX10XX10X";
function "and" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return and_table (l, r);
end "and";
function "nand" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return nand_table (l, r);
end "nand";
function "or" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return or_table (l, r);
end "or";
function "nor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return nor_table (l, r);
end "nor";
function "xor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return xor_table (l, r);
end "xor";
function "xnor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return xnor_table (l, r);
end "xnor";
function "not" (l : std_ulogic) return UX01 is
begin
return not_table (l);
end "not";
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := and_table (la (I), ra (I));
end loop;
end if;
return res;
end "and";
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nand_table (la (I), ra (I));
end loop;
end if;
return res;
end "nand";
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := or_table (la (I), ra (I));
end loop;
end if;
return res;
end "or";
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nor_table (la (I), ra (I));
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xor";
function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xnor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xnor";
function "not" (l : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not_table (la (I));
end loop;
return res;
end "not";
function "and" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := and_table (la (I), ra (I));
end loop;
end if;
return res;
end "and";
function "nand" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nand_table (la (I), ra (I));
end loop;
end if;
return res;
end "nand";
function "or" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := or_table (la (I), ra (I));
end loop;
end if;
return res;
end "or";
function "nor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nor_table (la (I), ra (I));
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xor";
function "xnor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xnor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xnor";
function "not" (l : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not_table (la (I));
end loop;
return res;
end "not";
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit is
begin
case s is
when '0' | 'L' =>
return '0';
when '1' | 'H' =>
return '1';
when others =>
return xmap;
end case;
end to_bit;
type bit_to_std_table is array (bit) of std_ulogic;
constant bit_to_std : bit_to_std_table := "01";
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector
is
subtype res_range is natural range s'length - 1 downto 0;
alias as : std_ulogic_vector (res_range) is s;
variable res : bit_vector (res_range);
variable b : bit;
begin
for I in res_range loop
-- Inline for efficiency.
case as (I) is
when '0' | 'L' =>
b := '0';
when '1' | 'H' =>
b := '1';
when others =>
b := xmap;
end case;
res (I) := b;
end loop;
return res;
end to_bitvector;
function to_bitvector (s : std_logic_vector; xmap : bit := '0')
return bit_vector
is
subtype res_range is natural range s'length - 1 downto 0;
alias as : std_logic_vector (res_range) is s;
variable res : bit_vector (res_range);
variable b : bit;
begin
for I in res_range loop
-- Inline for efficiency.
case as (I) is
when '0' | 'L' =>
b := '0';
when '1' | 'H' =>
b := '1';
when others =>
b := xmap;
end case;
res (I) := b;
end loop;
return res;
end to_bitvector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector is
subtype res_range is natural range b'length - 1 downto 0;
alias ab : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for I in res_range loop
res (I) := bit_to_std (ab (I));
end loop;
return res;
end to_stdulogicvector;
function to_stdlogicvector (b : bit_vector) return std_logic_vector is
subtype res_range is natural range b'length - 1 downto 0;
alias ab : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for I in res_range loop
res (I) := bit_to_std (ab (I));
end loop;
return res;
end to_stdlogicvector;
function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (s'length - 1 downto 0);
begin
return res_type (s);
end to_stdulogicvector;
function to_stdlogicvector (s : std_ulogic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (s'length - 1 downto 0);
begin
return res_type (s);
end to_stdlogicvector;
function to_stdulogic (b : bit) return std_ulogic is
begin
return bit_to_std (b);
end to_stdulogic;
-- Normalization.
type table_std_x01 is array (std_ulogic) of X01;
constant std_to_x01 : table_std_x01 := ('U' | 'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
type table_bit_x01 is array (bit) of X01;
constant bit_to_x01 : table_bit_x01 := ('0' => '0',
'1' => '1');
type table_std_x01z is array (std_ulogic) of X01Z;
constant std_to_x01z : table_std_x01z := ('U' | 'X' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1',
'Z' => 'Z');
type table_std_ux01 is array (std_ulogic) of UX01;
constant std_to_ux01 : table_std_ux01 := ('U' => 'U',
'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01 (sa (i));
end loop;
return res;
end to_X01;
function to_X01 (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01 (sa (i));
end loop;
return res;
end to_X01;
function to_X01 (s : std_ulogic) return X01 is
begin
return std_to_x01 (s);
end to_X01;
function to_X01 (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01;
function to_X01 (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01;
function to_X01 (b : bit) return X01 is
begin
return bit_to_x01 (b);
end to_X01;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01z (sa (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01z (sa (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (s : std_ulogic) return X01Z is
begin
return std_to_x01z (s);
end to_X01Z;
function to_X01Z (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (b : bit) return X01Z is
begin
return bit_to_x01 (b);
end to_X01Z;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_ux01 (sa (i));
end loop;
return res;
end to_UX01;
function to_UX01 (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_ux01 (sa (i));
end loop;
return res;
end to_UX01;
function to_UX01 (s : std_ulogic) return UX01 is
begin
return std_to_ux01 (s);
end to_UX01;
function to_UX01 (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_UX01;
function to_UX01 (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_UX01;
function to_UX01 (b : bit) return UX01 is
begin
return bit_to_x01 (b);
end to_UX01;
function rising_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '0'
and to_x01 (s) = '1';
end rising_edge;
function falling_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '1'
and to_x01 (s) = '0';
end falling_edge;
type std_x_array is array (std_ulogic) of boolean;
constant std_x : std_x_array := ('U' | 'X' | 'Z' | 'W' | '-' => true,
'0' | '1' | 'L' | 'H' => false);
function is_X (s : std_ulogic_vector) return boolean is
begin
for i in s'range loop
if std_x (s (i)) then
return true;
end if;
end loop;
return false;
end is_X;
function is_X (s : std_logic_vector) return boolean is
begin
for i in s'range loop
if std_x (s (i)) then
return true;
end if;
end loop;
return false;
end is_X;
function is_X (s : std_ulogic) return boolean is
begin
return std_x (s);
end is_X;
end std_logic_1164;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1190.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p03n01i01190ent IS
END c08s01b00x00p03n01i01190ent;
ARCHITECTURE c08s01b00x00p03n01i01190arch OF c08s01b00x00p03n01i01190ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
variable ii : integer;
BEGIN
k <= 5 after 5 ns;
wait on ii;
assert FALSE
report "***FAILED TEST: c08s01b00x00p03n01i01190 - Variable in sensitivity list."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p03n01i01190arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1190.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p03n01i01190ent IS
END c08s01b00x00p03n01i01190ent;
ARCHITECTURE c08s01b00x00p03n01i01190arch OF c08s01b00x00p03n01i01190ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
variable ii : integer;
BEGIN
k <= 5 after 5 ns;
wait on ii;
assert FALSE
report "***FAILED TEST: c08s01b00x00p03n01i01190 - Variable in sensitivity list."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p03n01i01190arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1190.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p03n01i01190ent IS
END c08s01b00x00p03n01i01190ent;
ARCHITECTURE c08s01b00x00p03n01i01190arch OF c08s01b00x00p03n01i01190ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
variable ii : integer;
BEGIN
k <= 5 after 5 ns;
wait on ii;
assert FALSE
report "***FAILED TEST: c08s01b00x00p03n01i01190 - Variable in sensitivity list."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p03n01i01190arch;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_FAST_t_opr is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_mask_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_mask_data_stream_V_full_n : IN STD_LOGIC;
p_mask_data_stream_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_FAST_t_opr is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st39_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101";
constant ap_const_lv11_6 : STD_LOGIC_VECTOR (10 downto 0) := "00000000110";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv9_14 : STD_LOGIC_VECTOR (8 downto 0) := "000010100";
constant ap_const_lv9_1EC : STD_LOGIC_VECTOR (8 downto 0) := "111101100";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_const_lv4_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv8_14 : STD_LOGIC_VECTOR (7 downto 0) := "00010100";
constant ap_const_lv32_FFFFFFEC : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111101100";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_true : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal p_2_reg_515 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it1 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_48 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal exitcond_reg_5147 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_5156 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_61 : BOOLEAN;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it27 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it28 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it29 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it30 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it31 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it32 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it33 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it34 : STD_LOGIC := '0';
signal or_cond4_reg_5201 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_136 : BOOLEAN;
signal ap_reg_ppiten_pp0_it35 : STD_LOGIC := '0';
signal ap_reg_ppstg_p_2_reg_515_pp0_it2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it3 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it4 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it5 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it6 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it7 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it8 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it9 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it10 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it11 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it12 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it13 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it14 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it15 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it16 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it17 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it18 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it19 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it20 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it21 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it22 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it23 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it24 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it25 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it26 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it27 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it28 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it29 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it30 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it31 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_fu_782_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_reg_5098 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_bdd_180 : BOOLEAN;
signal tmp_15_fu_786_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_15_reg_5103 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_s_fu_790_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_s_reg_5108 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_5_fu_796_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_5_reg_5113 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond1_fu_802_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_196 : BOOLEAN;
signal i_V_fu_807_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_5122 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_7_fu_813_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_5127 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_818_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_5132 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_824_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_5137 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_fu_840_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_reg_5142 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_851_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal j_V_reg_5151 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal k_buf_val_0_V_addr_reg_5161 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_addr_reg_5167 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_addr_reg_5173 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_addr_reg_5179 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_addr_reg_5185 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_addr_reg_5191 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond1_fu_883_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond1_reg_5197 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond4_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal win_val_0_V_2_1_reg_5205 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_4_3_reg_5210 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_5_3_reg_5215 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_2_3_reg_5220 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_5_3_reg_5225 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_4_3_reg_5230 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_2_reg_5235 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_fu_1252_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal lhs_V_reg_5240 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_fu_1260_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_reg_5252 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp1_fu_1278_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp1_reg_5261 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_20_fu_1286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_reg_5266 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_s_fu_1296_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_s_reg_5271 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_1_fu_1314_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_1_reg_5280 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_24_fu_1322_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_5285 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_2_fu_1332_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_2_reg_5290 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_2_fu_1350_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_2_reg_5299 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_27_fu_1358_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_reg_5304 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_3_fu_1368_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_3_reg_5309 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_3_fu_1386_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_3_reg_5318 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_fu_1394_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_5323 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_4_fu_1404_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_4_reg_5328 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_4_fu_1410_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_4_reg_5337 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_4_fu_1416_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_4_reg_5343 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_5_fu_1426_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_5_reg_5348 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_5_fu_1432_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_5_reg_5357 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_5_fu_1438_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_5_reg_5363 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_6_fu_1448_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_6_reg_5368 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_6_fu_1454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_6_reg_5377 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_6_fu_1460_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_6_reg_5383 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_7_fu_1470_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_7_reg_5388 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_7_fu_1476_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_7_reg_5397 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_7_fu_1482_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_7_reg_5403 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_fu_1516_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_reg_5408 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_val_V_assign_load_1_s_fu_1521_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_s_reg_5417 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp3_fu_1539_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp3_reg_5422 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_23_fu_1547_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_5427 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_1_fu_1557_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_1_reg_5432 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_182_1_fu_1568_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_1_reg_5441 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_1_fu_1574_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_1_reg_5447 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_2_fu_1584_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_2_reg_5452 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_182_2_fu_1595_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_2_reg_5461 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_2_fu_1601_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_2_reg_5467 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_3_fu_1611_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_3_reg_5472 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_4_fu_1626_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_4_reg_5483 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_5_fu_1654_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_5_reg_5494 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_6_fu_1682_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_6_reg_5505 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_7_fu_1710_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_7_reg_5516 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_val_V_assign_load_1_13_fu_1726_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_13_reg_5527 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_39_fu_1740_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_39_reg_5532 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_fu_1746_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_reg_5537 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_fu_1764_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_reg_5543 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond7_fu_1782_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond7_reg_5548 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond8_fu_1800_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond8_reg_5553 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond9_fu_1818_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond9_reg_5559 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_not_fu_1824_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_not_reg_5566 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_5_fu_1830_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_5_reg_5572 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_6_not_fu_1836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_6_not_reg_5578 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_6_fu_1842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_6_reg_5584 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_0_op_op87_op_fu_1848_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_0_op_op87_op_reg_5590 : STD_LOGIC_VECTOR (3 downto 0);
signal phitmp43_op_op_cast_cast_cast_fu_1856_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal phitmp43_op_op_cast_cast_cast_reg_5595 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_40_fu_1864_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_40_reg_5600 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_demorgan_fu_1870_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_demorgan_reg_5605 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_demorgan_fu_1876_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_demorgan_reg_5610 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_demorgan_fu_1882_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_demorgan_reg_5615 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_demorgan_fu_1888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_demorgan_reg_5620 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_3_fu_1930_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_3_reg_5625 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_5_fu_1962_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_5_reg_5631 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_4_fu_1970_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_4_reg_5638 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_4_fu_1975_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_4_reg_5644 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_5_fu_1980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_5_reg_5649 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_5_fu_1985_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_5_reg_5655 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_1990_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_5660 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_6_fu_2036_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_6_reg_5665 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond10_fu_2055_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond10_reg_5670 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_7_fu_2061_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_7_reg_5675 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond11_fu_2075_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond11_reg_5681 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_9_fu_2081_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_9_reg_5687 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_9_fu_2087_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_9_reg_5693 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_demorgan_fu_2093_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_demorgan_reg_5699 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_demorgan_fu_2097_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_demorgan_reg_5704 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_10_fu_2131_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_10_reg_5709 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_12_fu_2163_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_12_reg_5715 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_7_fu_2171_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_7_reg_5722 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_7_fu_2176_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_7_reg_5728 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond_fu_2186_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond_reg_5733 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_9_fu_2251_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_9_reg_5738 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_9_fu_2257_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_9_reg_5743 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond3_demorgan_fu_2286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond3_demorgan_reg_5748 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_s_fu_2292_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_s_reg_5753 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond14_fu_2310_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond14_reg_5759 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_demorgan_fu_2316_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_demorgan_reg_5764 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_fu_2322_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_reg_5769 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_10_fu_2328_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_10_reg_5775 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_2334_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_reg_5781 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp5_reg_5781_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_1_fu_2391_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_1_reg_5786 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_2_fu_2435_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_2_reg_5791 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_3_fu_2464_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_3_reg_5796 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_demorgan_fu_2470_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_demorgan_reg_5801 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_3_fu_2476_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_3_reg_5806 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond17_fu_2494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond17_reg_5811 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_demorgan_fu_2500_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_demorgan_reg_5816 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond18_fu_2511_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond18_reg_5821 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp6_fu_2516_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp6_reg_5827 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_5_fu_2581_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_5_reg_5832 : STD_LOGIC_VECTOR (0 downto 0);
signal count_3_fu_2594_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_3_reg_5837 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp8_fu_2600_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp8_reg_5842 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp4_fu_2606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_reg_5847 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_fu_2610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_reg_5852 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_fu_2614_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_reg_5857 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_7_fu_2653_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_7_reg_5862 : STD_LOGIC_VECTOR (0 downto 0);
signal count_4_fu_2666_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_4_reg_5867 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_12_fu_2678_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_12_reg_5872 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp3_fu_2689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_reg_5878 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_fu_2694_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_reg_5883 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp12_reg_5883_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_11_fu_2725_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_11_reg_5888 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_13_fu_2743_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_13_reg_5893 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_14_fu_2755_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_14_reg_5898 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp13_fu_2762_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp13_reg_5904 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_13_fu_2787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_13_reg_5909 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_15_fu_2805_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_15_reg_5914 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_fu_2817_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_reg_5919 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_16_fu_2822_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_16_reg_5924 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_2828_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_reg_5929 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_fu_2833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_reg_5934 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp11_reg_5934_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_fu_2837_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_reg_5939 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_fu_2861_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_reg_5944 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_s_fu_2870_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_s_reg_5949 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_image_filter_reg_int_s_fu_542_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_1_reg_5953 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_547_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_1_reg_5959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_572_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_7_reg_5965 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_577_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_7_reg_5971 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_3_fu_3031_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_3_reg_5977 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_3_fu_3045_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_3_reg_5982 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_582_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_1_reg_5987 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_587_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_1_reg_5993 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_592_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_5_reg_5999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_597_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_5_reg_6005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_fu_3143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_reg_6011 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_602_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_9_reg_6017 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_607_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_9_reg_6023 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_612_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_1_reg_6029 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_617_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_1_reg_6036 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_fu_3262_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_43_reg_6043 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_67_fu_3268_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_67_reg_6048 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_image_filter_reg_int_s_fu_652_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_3_reg_6053 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_657_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_3_reg_6059 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_662_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_7_reg_6065 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_667_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_7_reg_6071 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_fu_3434_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_a_0_flag_d_assign_load_5_reg_6077 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_fu_3447_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_reg_6083 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_48_fu_3454_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_48_reg_6088 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_fu_3473_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_reg_6093 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_71_fu_3486_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_71_reg_6099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_3493_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_reg_6104 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_2_fu_3497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_2_reg_6109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_712_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_3_reg_6115 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_717_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_3_reg_6122 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_5_fu_3505_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_5_reg_6129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_5_fu_3517_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_5_reg_6134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_7_fu_3529_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_7_reg_6139 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_7_fu_3541_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_7_reg_6144 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_9_fu_3554_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_9_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_9_fu_3568_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_9_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_s_fu_3582_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_s_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_s_fu_3596_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_s_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_2_fu_3609_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_2_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_2_fu_3621_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_2_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_4_fu_3633_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_4_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_4_fu_3645_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_4_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_1_fu_3666_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_1_reg_6195 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_tmp_s_fu_3680_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_tmp_s_reg_6200 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_1_fu_3686_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_1_reg_6206 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_s_fu_3713_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_s_reg_6211 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_1_fu_3725_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_1_reg_6217 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_3732_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_57_reg_6222 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_s_fu_3754_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_s_reg_6227 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_1_fu_3766_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_1_reg_6233 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_fu_3773_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_83_reg_6238 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_4_fu_3777_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_4_reg_6243 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_722_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_5_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_727_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_5_reg_6256 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_tmp_232_1_fu_3788_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_tmp_232_1_reg_6263 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_2_fu_3794_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_2_reg_6269 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_tmp_239_1_fu_3808_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_tmp_239_1_reg_6274 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_2_fu_3814_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_2_reg_6280 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_2_fu_3841_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_2_reg_6285 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_2_fu_3853_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_2_reg_6291 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_fu_3860_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_59_reg_6296 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_2_fu_3882_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_2_reg_6301 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_2_fu_3894_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_2_reg_6307 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_3901_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_85_reg_6312 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_6_fu_3905_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_6_reg_6317 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_732_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_7_reg_6323 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_737_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_7_reg_6330 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_2_tmp_232_2_fu_3916_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_2_tmp_232_2_reg_6337 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_3_fu_3922_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_3_reg_6343 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_2_tmp_239_2_fu_3936_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_2_tmp_239_2_reg_6348 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_3_fu_3942_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_3_reg_6354 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_3_fu_3969_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_3_reg_6359 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_3_fu_3981_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_3_reg_6365 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_fu_3988_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_61_reg_6370 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_3_fu_4010_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_3_reg_6375 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_3_fu_4022_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_3_reg_6381 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_87_fu_4029_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_reg_6386 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_8_fu_4033_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_8_reg_6391 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_742_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_9_reg_6397 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_747_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_9_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_3_tmp_232_3_fu_4044_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_3_tmp_232_3_reg_6411 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_4_fu_4050_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_4_reg_6417 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_3_tmp_239_3_fu_4064_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_3_tmp_239_3_reg_6422 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_4_fu_4070_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_4_reg_6428 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_4_fu_4097_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_4_reg_6433 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_4_fu_4109_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_4_reg_6439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_4116_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_63_reg_6444 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_4_fu_4138_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_4_reg_6449 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_4_fu_4150_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_4_reg_6455 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_89_fu_4157_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_89_reg_6460 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_s_fu_4161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_s_reg_6465 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_752_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_s_reg_6471 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_757_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_s_reg_6478 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_4_tmp_232_4_fu_4172_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_4_tmp_232_4_reg_6485 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_5_fu_4178_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_5_reg_6491 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_4_tmp_239_4_fu_4192_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_4_tmp_239_4_reg_6496 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_5_fu_4198_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_5_reg_6502 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_5_fu_4225_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_5_reg_6507 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_5_fu_4237_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_5_reg_6513 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_fu_4244_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_reg_6518 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_5_fu_4266_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_5_reg_6523 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_5_fu_4278_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_5_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_91_fu_4285_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_91_reg_6534 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_11_fu_4289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_11_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_762_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_1_reg_6545 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_767_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_1_reg_6552 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_5_tmp_232_5_fu_4300_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_5_tmp_232_5_reg_6559 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_6_fu_4306_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_6_reg_6565 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_5_tmp_239_5_fu_4320_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_5_tmp_239_5_reg_6570 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_6_fu_4326_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_6_reg_6576 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_6_fu_4353_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_6_reg_6581 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_6_fu_4365_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_6_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_75_fu_4372_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_reg_6592 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_6_fu_4394_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_6_reg_6597 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_6_fu_4406_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_6_reg_6603 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_93_fu_4413_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_93_reg_6608 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_13_fu_4417_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_13_reg_6613 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_772_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_2_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_777_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_2_reg_6626 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_6_tmp_232_6_fu_4428_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_6_tmp_232_6_reg_6633 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_7_fu_4434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_7_reg_6639 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_6_tmp_239_6_fu_4448_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_6_tmp_239_6_reg_6644 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_7_fu_4454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_7_reg_6650 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_7_fu_4481_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_reg_6655 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_7_fu_4493_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_7_reg_6661 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_4500_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_reg_6666 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_7_fu_4522_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_7_reg_6671 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_7_fu_4534_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_7_reg_6676 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_95_fu_4541_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_95_reg_6681 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_fu_4545_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_reg_6686 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_tmp_232_7_fu_4557_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_tmp_232_7_reg_6691 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_4571_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_reg_6697 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_addr_reg_6702 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_addr_reg_6708 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_100_v_fu_4593_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_100_v_reg_6714 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_53_fu_4600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_53_reg_6719 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal core_buf_val_0_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_load_reg_6724 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_load_reg_6729 : STD_LOGIC_VECTOR (7 downto 0);
signal phitmp2_fu_4606_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp19_fu_4701_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_reg_6739 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_fu_4712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_reg_6744 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_fu_4723_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_reg_6749 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_fu_4735_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_reg_6754 : STD_LOGIC_VECTOR (0 downto 0);
signal k_buf_val_0_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_0_V_ce0 : STD_LOGIC;
signal k_buf_val_0_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_0_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_0_V_ce1 : STD_LOGIC;
signal k_buf_val_0_V_we1 : STD_LOGIC;
signal k_buf_val_0_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_1_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_ce0 : STD_LOGIC;
signal k_buf_val_1_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_1_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_ce1 : STD_LOGIC;
signal k_buf_val_1_V_we1 : STD_LOGIC;
signal k_buf_val_1_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_2_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_ce0 : STD_LOGIC;
signal k_buf_val_2_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_2_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_ce1 : STD_LOGIC;
signal k_buf_val_2_V_we1 : STD_LOGIC;
signal k_buf_val_2_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_3_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_ce0 : STD_LOGIC;
signal k_buf_val_3_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_3_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_ce1 : STD_LOGIC;
signal k_buf_val_3_V_we1 : STD_LOGIC;
signal k_buf_val_3_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_4_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_ce0 : STD_LOGIC;
signal k_buf_val_4_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_4_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_ce1 : STD_LOGIC;
signal k_buf_val_4_V_we1 : STD_LOGIC;
signal k_buf_val_4_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_5_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_ce0 : STD_LOGIC;
signal k_buf_val_5_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_5_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_ce1 : STD_LOGIC;
signal k_buf_val_5_V_we1 : STD_LOGIC;
signal k_buf_val_5_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_0_V_ce0 : STD_LOGIC;
signal core_buf_val_0_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_0_V_ce1 : STD_LOGIC;
signal core_buf_val_0_V_we1 : STD_LOGIC;
signal core_buf_val_0_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_ce0 : STD_LOGIC;
signal core_buf_val_1_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_ce1 : STD_LOGIC;
signal core_buf_val_1_V_we1 : STD_LOGIC;
signal core_buf_val_1_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_reg_int_s_fu_542_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_542_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_547_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_547_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_552_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_552_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_552_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_557_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_557_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_557_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_562_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_562_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_562_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_567_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_567_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_567_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_572_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_572_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_577_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_577_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_582_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_582_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_587_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_587_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_592_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_592_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_597_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_597_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_602_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_602_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_607_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_607_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_612_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_612_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_617_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_617_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_622_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_622_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_622_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_627_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_627_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_627_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_632_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_632_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_632_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_637_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_637_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_637_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_642_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_642_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_642_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_647_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_647_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_647_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_652_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_652_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_657_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_657_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_662_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_662_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_667_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_667_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_672_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_672_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_672_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_677_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_677_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_677_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_682_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_682_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_682_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_687_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_687_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_687_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_692_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_692_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_692_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_697_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_697_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_697_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_702_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_702_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_702_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_707_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_707_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_707_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_712_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_712_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_717_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_717_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_722_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_722_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_727_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_727_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_732_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_732_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_737_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_737_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_742_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_742_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_747_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_747_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_752_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_752_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_757_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_757_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_762_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_762_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_767_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_767_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_772_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_772_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_777_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_777_ap_ce : STD_LOGIC;
signal p_s_reg_504 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st39_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_2075 : BOOLEAN;
signal p_2_phi_fu_519_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it0 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it6 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it7 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it8 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it9 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it10 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it11 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it12 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it13 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it14 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it15 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it16 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it17 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it18 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it19 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it20 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it21 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it22 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it23 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it24 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it25 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it26 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it27 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it28 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it29 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it30 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it31 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it32 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it33 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it34 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_12_fu_867_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_fu_4577_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal win_val_6_V_5_fu_132 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_0_V_0_fu_136 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_0_V_1_fu_140 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_0_V_2_fu_4620_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_6_V_4_fu_144 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_1_V_0_fu_148 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_1_V_1_fu_152 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_1_V_2_fu_4623_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_6_V_3_fu_156 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_2_V_0_fu_160 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_2_V_1_fu_164 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_2_V_1_2_fu_4643_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_0_V_2_3_fu_168 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_2_fu_172 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_3_fu_176 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_4_fu_180 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_5_fu_184 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_1_3_fu_188 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_1_fu_192 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_2_fu_196 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_3_fu_200 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_4_fu_204 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_5_fu_208 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_0_3_fu_212 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_0_fu_216 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_1_fu_220 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_2_fu_224 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_3_fu_228 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_4_fu_232 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_5_fu_236 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_0_3_fu_240 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_0_fu_244 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_1_fu_248 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_2_fu_252 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_3_fu_256 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_4_fu_260 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_5_fu_264 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_0_3_fu_268 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_0_fu_272 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_1_fu_276 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_2_fu_280 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_3_fu_284 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_4_fu_288 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_5_fu_292 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_1_3_fu_296 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_1_fu_300 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_2_fu_304 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_3_fu_308 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_4_fu_312 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_5_fu_316 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_3_fu_320 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_fu_324 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_2_V_2_fu_4635_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_830_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_877_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_97_fu_888_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal icmp1_fu_898_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_fu_1256_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_18_fu_1266_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_1272_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_s_fu_1292_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_1_fu_1302_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_1_fu_1308_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_2_fu_1328_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_2_fu_1338_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_2_fu_1344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_3_fu_1364_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_3_fu_1374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_3_fu_1380_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_4_fu_1400_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_5_fu_1422_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_6_fu_1444_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_7_fu_1466_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_fu_1512_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_fu_1527_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_1533_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_1_1_fu_1553_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_2_fu_1580_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_3_fu_1607_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_4_fu_1622_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_1638_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_4_fu_1631_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_5_fu_1650_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_fu_1666_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_5_fu_1659_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_6_fu_1678_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_fu_1694_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_6_fu_1687_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_7_fu_1706_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_37_fu_1722_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_7_fu_1715_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_1_fu_1562_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_0_not_fu_1734_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_2_fu_1589_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_1_fu_1758_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_1_not_fu_1752_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_4_fu_1616_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_2_fu_1776_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_not_fu_1770_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_6_fu_1642_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_3_fu_1794_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_3_not_fu_1788_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_8_fu_1670_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_4_fu_1812_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_4_not_fu_1806_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_11_fu_1698_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_25_fu_1907_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_1_fu_1900_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_28_fu_1926_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_2_fu_1919_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_3_fu_1938_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_3_fu_1943_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_1956_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_3_fu_1948_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_41_fu_2010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp42_op_cast_cast_cast_fu_2003_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_2_op_op_fu_1998_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond3_fu_1994_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_42_fu_2030_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp3_cast_cast_cast_fu_2022_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_4_op_fu_2014_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal flag_val_V_assign_load_2_s_fu_1894_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_7_fu_2049_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_7_not_fu_2044_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_9_fu_1911_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_8_fu_2069_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_2108_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_4_fu_2101_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_34_fu_2127_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_5_fu_2120_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_6_fu_2139_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_6_fu_2144_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_2157_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_6_fu_2149_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_185_7_fu_2181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_8_fu_2197_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_185_8_fu_2202_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond1_fu_2213_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp4_fu_2208_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_8_fu_2224_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond2_demorgan_fu_2241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_9_fu_2235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond2_fu_2245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond12_fu_2231_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_s_fu_2265_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_s_fu_2269_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond13_fu_2274_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp5_fu_2280_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal flag_val_V_assign_load_1_7_fu_2112_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_1_fu_2300_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_8_fu_2305_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_7_fu_2191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_8_fu_2218_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_38_fu_2347_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_7_fu_2340_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal count_s_fu_2359_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_185_s_fu_2364_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond3_fu_2370_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_1_fu_2381_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_fu_2386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_1_fu_2397_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_fu_2407_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond12_demorgan_fu_2425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_2_fu_2413_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond12_fu_2429_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond15_fu_2403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp6_fu_2419_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_181_3_fu_2449_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_11_fu_2453_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_2_fu_2441_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond16_fu_2458_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_14_fu_2351_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_4_fu_2484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_12_fu_2489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_fu_2506_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_s_fu_2375_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_fu_2521_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_3_cast_fu_2531_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal count_2_fu_2534_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_4_fu_2540_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_fu_2552_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp7_fu_2546_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_4_fu_2563_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_5_fu_2570_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond15_fu_2576_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_5_fu_2587_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_3_fu_2526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_4_fu_2557_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_6_fu_2620_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond5_fu_2625_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_10_fu_2636_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_10_fu_2642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_fu_2648_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_11_fu_2659_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp9_fu_2672_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp7_fu_2685_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_6_fu_2630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_11_fu_2699_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_fu_2704_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_12_fu_2715_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_fu_2720_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_13_fu_2731_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_5_fu_2737_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp10_fu_2749_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_10_fu_2709_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_fu_2767_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_14_fu_2777_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_fu_2782_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_15_fu_2793_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_6_fu_2799_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp_fu_2811_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_12_fu_2772_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_14_fu_2842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_15_fu_2846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_fu_2850_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp16_fu_2856_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp10_fu_2866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_1_fu_2875_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_1_fu_2879_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_1_fu_2890_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_1_fu_2894_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_3_fu_2905_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_3_fu_2909_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_3_fu_2920_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_3_fu_2924_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_5_fu_2935_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_5_fu_2939_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_5_fu_2950_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_5_fu_2954_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_7_fu_2965_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_7_fu_2969_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_7_fu_2980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_7_fu_2984_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_192_1_fu_2995_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_1_fu_3010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_3_fu_3025_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_3_fu_3039_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_5_fu_3053_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_5_fu_3068_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_9_fu_3083_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_9_fu_3087_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_9_fu_3098_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_9_fu_3102_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_199_1_fu_3113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_1_fu_3128_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_s_fu_3146_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_s_fu_3150_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_s_fu_3161_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_s_fu_3165_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_2_fu_3176_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_2_fu_3180_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_2_fu_3191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_2_fu_3195_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_4_fu_3206_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_4_fu_3210_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_4_fu_3221_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_4_fu_3225_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_192_7_fu_3236_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_7_fu_3249_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_9_fu_3277_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_9_fu_3290_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_s_fu_3303_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_s_fu_3318_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_2_fu_3333_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_2_fu_3348_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_4_fu_3363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_4_fu_3376_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_3_fu_3389_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_3_fu_3404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_0_flag_d_assign_load_5_fu_3419_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_fu_3428_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_44_fu_3424_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_9_fu_3274_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_fu_3442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_68_fu_3458_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_fu_3467_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_80_fu_3463_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_3481_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_5_fu_3500_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_5_fu_3512_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_7_fu_3524_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_7_fu_3536_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_9_fu_3548_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_9_fu_3562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_s_fu_3576_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_s_fu_3590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_2_fu_3604_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_2_fu_3616_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_4_fu_3628_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_4_fu_3640_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_3655_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_cast_fu_3672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_72_fu_3675_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_1_fu_3698_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_1_fu_3707_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_fu_3703_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_10_fu_3692_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_1_fu_3720_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_1_fu_3739_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_tmp_239_cast_fu_3736_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_1_fu_3748_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_82_fu_3744_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_1_fu_3761_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_cast_fu_3780_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_1_fu_3783_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_cast_50_fu_3800_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_1_fu_3803_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_2_fu_3826_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_tmp_232_1_cast_fu_3823_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_2_fu_3835_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_58_fu_3831_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_12_fu_3820_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_2_fu_3848_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_2_fu_3867_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_tmp_239_1_cast_fu_3864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_2_fu_3876_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_84_fu_3872_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_2_fu_3889_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_2_cast_fu_3908_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_2_fu_3911_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_2_cast_fu_3928_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_2_fu_3931_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_3_fu_3954_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_2_tmp_232_2_cast_fu_3951_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_3_fu_3963_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_3959_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_14_fu_3948_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_3_fu_3976_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_3_fu_3995_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_2_tmp_239_2_cast_fu_3992_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_3_fu_4004_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_86_fu_4000_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_3_fu_4017_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_3_cast_fu_4036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_3_fu_4039_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_3_cast_fu_4056_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_3_fu_4059_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_4_fu_4082_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_3_tmp_232_3_cast_fu_4079_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_4_fu_4091_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_4087_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_1_fu_4076_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_4_fu_4104_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_4_fu_4123_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_3_tmp_239_3_cast_fu_4120_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_4_fu_4132_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_88_fu_4128_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_4_fu_4145_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_4_cast_fu_4164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_4_fu_4167_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_4_cast_fu_4184_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_4_fu_4187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_5_fu_4210_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_4_tmp_232_4_cast_fu_4207_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_5_fu_4219_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_4215_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_3_fu_4204_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_5_fu_4232_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_5_fu_4251_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_4_tmp_239_4_cast_fu_4248_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_5_fu_4260_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_90_fu_4256_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_5_fu_4273_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_5_cast_fu_4292_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_5_fu_4295_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_5_cast_fu_4312_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_5_fu_4315_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_6_fu_4338_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_5_tmp_232_5_cast_fu_4335_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_6_fu_4347_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_fu_4343_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_5_fu_4332_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_6_fu_4360_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_6_fu_4379_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_5_tmp_239_5_cast_fu_4376_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_6_fu_4388_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_92_fu_4384_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_6_fu_4401_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_6_cast_fu_4420_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_6_fu_4423_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_6_cast_fu_4440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_6_fu_4443_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_7_fu_4466_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_6_tmp_232_6_cast_fu_4463_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_7_fu_4475_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_77_fu_4471_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_7_fu_4460_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_7_fu_4488_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_7_fu_4507_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_6_tmp_239_6_cast_fu_4504_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_7_fu_4516_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_94_fu_4512_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_7_fu_4529_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_7_cast_fu_4549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_7_fu_4552_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_7_cast_fu_4563_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_7_fu_4566_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_fu_4583_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_51_fu_4588_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_4647_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_73_fu_4653_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_242_1_fu_4659_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp21_fu_4706_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_74_fu_4671_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_245_1_fu_4677_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp24_fu_4717_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_242_2_fu_4665_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_fu_4695_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_54_fu_4689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_fu_4729_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_245_2_fu_4683_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp22_fu_4775_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_fu_4771_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_4779_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_bdd_2152 : BOOLEAN;
signal ap_sig_bdd_250 : BOOLEAN;
signal ap_sig_bdd_2159 : BOOLEAN;
signal ap_sig_bdd_2108 : BOOLEAN;
signal ap_sig_bdd_2156 : BOOLEAN;
signal ap_sig_bdd_1776 : BOOLEAN;
component image_filter_reg_int_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component image_filter_FAST_t_opr_k_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
component image_filter_FAST_t_opr_core_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
k_buf_val_0_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_0_V_address0,
ce0 => k_buf_val_0_V_ce0,
q0 => k_buf_val_0_V_q0,
address1 => k_buf_val_0_V_address1,
ce1 => k_buf_val_0_V_ce1,
we1 => k_buf_val_0_V_we1,
d1 => k_buf_val_0_V_d1);
k_buf_val_1_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_1_V_address0,
ce0 => k_buf_val_1_V_ce0,
q0 => k_buf_val_1_V_q0,
address1 => k_buf_val_1_V_address1,
ce1 => k_buf_val_1_V_ce1,
we1 => k_buf_val_1_V_we1,
d1 => k_buf_val_1_V_d1);
k_buf_val_2_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_2_V_address0,
ce0 => k_buf_val_2_V_ce0,
q0 => k_buf_val_2_V_q0,
address1 => k_buf_val_2_V_address1,
ce1 => k_buf_val_2_V_ce1,
we1 => k_buf_val_2_V_we1,
d1 => k_buf_val_2_V_d1);
k_buf_val_3_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_3_V_address0,
ce0 => k_buf_val_3_V_ce0,
q0 => k_buf_val_3_V_q0,
address1 => k_buf_val_3_V_address1,
ce1 => k_buf_val_3_V_ce1,
we1 => k_buf_val_3_V_we1,
d1 => k_buf_val_3_V_d1);
k_buf_val_4_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_4_V_address0,
ce0 => k_buf_val_4_V_ce0,
q0 => k_buf_val_4_V_q0,
address1 => k_buf_val_4_V_address1,
ce1 => k_buf_val_4_V_ce1,
we1 => k_buf_val_4_V_we1,
d1 => k_buf_val_4_V_d1);
k_buf_val_5_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_5_V_address0,
ce0 => k_buf_val_5_V_ce0,
q0 => k_buf_val_5_V_q0,
address1 => k_buf_val_5_V_address1,
ce1 => k_buf_val_5_V_ce1,
we1 => k_buf_val_5_V_we1,
d1 => k_buf_val_5_V_d1);
core_buf_val_0_V_U : component image_filter_FAST_t_opr_core_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1927,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => core_buf_val_0_V_address0,
ce0 => core_buf_val_0_V_ce0,
q0 => core_buf_val_0_V_q0,
address1 => core_buf_val_0_V_address1,
ce1 => core_buf_val_0_V_ce1,
we1 => core_buf_val_0_V_we1,
d1 => core_buf_val_0_V_d1);
core_buf_val_1_V_U : component image_filter_FAST_t_opr_core_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1927,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => core_buf_val_1_V_address0,
ce0 => core_buf_val_1_V_ce0,
q0 => core_buf_val_1_V_q0,
address1 => core_buf_val_1_V_address1,
ce1 => core_buf_val_1_V_ce1,
we1 => core_buf_val_1_V_we1,
d1 => core_buf_val_1_V_d1);
grp_image_filter_reg_int_s_fu_542 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_542_in_r,
ap_return => grp_image_filter_reg_int_s_fu_542_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_542_ap_ce);
grp_image_filter_reg_int_s_fu_547 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_547_in_r,
ap_return => grp_image_filter_reg_int_s_fu_547_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_547_ap_ce);
grp_image_filter_reg_int_s_fu_552 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_552_in_r,
ap_return => grp_image_filter_reg_int_s_fu_552_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_552_ap_ce);
grp_image_filter_reg_int_s_fu_557 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_557_in_r,
ap_return => grp_image_filter_reg_int_s_fu_557_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_557_ap_ce);
grp_image_filter_reg_int_s_fu_562 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_562_in_r,
ap_return => grp_image_filter_reg_int_s_fu_562_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_562_ap_ce);
grp_image_filter_reg_int_s_fu_567 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_567_in_r,
ap_return => grp_image_filter_reg_int_s_fu_567_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_567_ap_ce);
grp_image_filter_reg_int_s_fu_572 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_572_in_r,
ap_return => grp_image_filter_reg_int_s_fu_572_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_572_ap_ce);
grp_image_filter_reg_int_s_fu_577 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_577_in_r,
ap_return => grp_image_filter_reg_int_s_fu_577_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_577_ap_ce);
grp_image_filter_reg_int_s_fu_582 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_582_in_r,
ap_return => grp_image_filter_reg_int_s_fu_582_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_582_ap_ce);
grp_image_filter_reg_int_s_fu_587 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_587_in_r,
ap_return => grp_image_filter_reg_int_s_fu_587_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_587_ap_ce);
grp_image_filter_reg_int_s_fu_592 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_592_in_r,
ap_return => grp_image_filter_reg_int_s_fu_592_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_592_ap_ce);
grp_image_filter_reg_int_s_fu_597 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_597_in_r,
ap_return => grp_image_filter_reg_int_s_fu_597_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_597_ap_ce);
grp_image_filter_reg_int_s_fu_602 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_602_in_r,
ap_return => grp_image_filter_reg_int_s_fu_602_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_602_ap_ce);
grp_image_filter_reg_int_s_fu_607 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_607_in_r,
ap_return => grp_image_filter_reg_int_s_fu_607_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_607_ap_ce);
grp_image_filter_reg_int_s_fu_612 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_612_in_r,
ap_return => grp_image_filter_reg_int_s_fu_612_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_612_ap_ce);
grp_image_filter_reg_int_s_fu_617 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_617_in_r,
ap_return => grp_image_filter_reg_int_s_fu_617_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_617_ap_ce);
grp_image_filter_reg_int_s_fu_622 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_622_in_r,
ap_return => grp_image_filter_reg_int_s_fu_622_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_622_ap_ce);
grp_image_filter_reg_int_s_fu_627 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_627_in_r,
ap_return => grp_image_filter_reg_int_s_fu_627_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_627_ap_ce);
grp_image_filter_reg_int_s_fu_632 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_632_in_r,
ap_return => grp_image_filter_reg_int_s_fu_632_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_632_ap_ce);
grp_image_filter_reg_int_s_fu_637 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_637_in_r,
ap_return => grp_image_filter_reg_int_s_fu_637_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_637_ap_ce);
grp_image_filter_reg_int_s_fu_642 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_642_in_r,
ap_return => grp_image_filter_reg_int_s_fu_642_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_642_ap_ce);
grp_image_filter_reg_int_s_fu_647 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_647_in_r,
ap_return => grp_image_filter_reg_int_s_fu_647_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_647_ap_ce);
grp_image_filter_reg_int_s_fu_652 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_652_in_r,
ap_return => grp_image_filter_reg_int_s_fu_652_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_652_ap_ce);
grp_image_filter_reg_int_s_fu_657 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_657_in_r,
ap_return => grp_image_filter_reg_int_s_fu_657_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_657_ap_ce);
grp_image_filter_reg_int_s_fu_662 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_662_in_r,
ap_return => grp_image_filter_reg_int_s_fu_662_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_662_ap_ce);
grp_image_filter_reg_int_s_fu_667 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_667_in_r,
ap_return => grp_image_filter_reg_int_s_fu_667_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_667_ap_ce);
grp_image_filter_reg_int_s_fu_672 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_672_in_r,
ap_return => grp_image_filter_reg_int_s_fu_672_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_672_ap_ce);
grp_image_filter_reg_int_s_fu_677 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_677_in_r,
ap_return => grp_image_filter_reg_int_s_fu_677_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_677_ap_ce);
grp_image_filter_reg_int_s_fu_682 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_682_in_r,
ap_return => grp_image_filter_reg_int_s_fu_682_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_682_ap_ce);
grp_image_filter_reg_int_s_fu_687 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_687_in_r,
ap_return => grp_image_filter_reg_int_s_fu_687_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_687_ap_ce);
grp_image_filter_reg_int_s_fu_692 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_692_in_r,
ap_return => grp_image_filter_reg_int_s_fu_692_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_692_ap_ce);
grp_image_filter_reg_int_s_fu_697 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_697_in_r,
ap_return => grp_image_filter_reg_int_s_fu_697_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_697_ap_ce);
grp_image_filter_reg_int_s_fu_702 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_702_in_r,
ap_return => grp_image_filter_reg_int_s_fu_702_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_702_ap_ce);
grp_image_filter_reg_int_s_fu_707 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_707_in_r,
ap_return => grp_image_filter_reg_int_s_fu_707_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_707_ap_ce);
grp_image_filter_reg_int_s_fu_712 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_712_in_r,
ap_return => grp_image_filter_reg_int_s_fu_712_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_712_ap_ce);
grp_image_filter_reg_int_s_fu_717 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_717_in_r,
ap_return => grp_image_filter_reg_int_s_fu_717_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_717_ap_ce);
grp_image_filter_reg_int_s_fu_722 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_722_in_r,
ap_return => grp_image_filter_reg_int_s_fu_722_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_722_ap_ce);
grp_image_filter_reg_int_s_fu_727 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_727_in_r,
ap_return => grp_image_filter_reg_int_s_fu_727_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_727_ap_ce);
grp_image_filter_reg_int_s_fu_732 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_732_in_r,
ap_return => grp_image_filter_reg_int_s_fu_732_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_732_ap_ce);
grp_image_filter_reg_int_s_fu_737 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_737_in_r,
ap_return => grp_image_filter_reg_int_s_fu_737_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_737_ap_ce);
grp_image_filter_reg_int_s_fu_742 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_742_in_r,
ap_return => grp_image_filter_reg_int_s_fu_742_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_742_ap_ce);
grp_image_filter_reg_int_s_fu_747 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_747_in_r,
ap_return => grp_image_filter_reg_int_s_fu_747_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_747_ap_ce);
grp_image_filter_reg_int_s_fu_752 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_752_in_r,
ap_return => grp_image_filter_reg_int_s_fu_752_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_752_ap_ce);
grp_image_filter_reg_int_s_fu_757 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_757_in_r,
ap_return => grp_image_filter_reg_int_s_fu_757_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_757_ap_ce);
grp_image_filter_reg_int_s_fu_762 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_762_in_r,
ap_return => grp_image_filter_reg_int_s_fu_762_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_762_ap_ce);
grp_image_filter_reg_int_s_fu_767 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_767_in_r,
ap_return => grp_image_filter_reg_int_s_fu_767_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_767_ap_ce);
grp_image_filter_reg_int_s_fu_772 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_772_in_r,
ap_return => grp_image_filter_reg_int_s_fu_772_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_772_ap_ce);
grp_image_filter_reg_int_s_fu_777 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_777_in_r,
ap_return => grp_image_filter_reg_int_s_fu_777_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_777_ap_ce);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_lv1_0 = exitcond_fu_846_p2)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it23 assign process. --
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it24 assign process. --
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it25 assign process. --
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it26 assign process. --
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it27 assign process. --
ap_reg_ppiten_pp0_it27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it28 assign process. --
ap_reg_ppiten_pp0_it28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it29 assign process. --
ap_reg_ppiten_pp0_it29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it30 assign process. --
ap_reg_ppiten_pp0_it30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it31 assign process. --
ap_reg_ppiten_pp0_it31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it32 assign process. --
ap_reg_ppiten_pp0_it32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it33 assign process. --
ap_reg_ppiten_pp0_it33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it34 assign process. --
ap_reg_ppiten_pp0_it34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it35 assign process. --
ap_reg_ppiten_pp0_it35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2)) or (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33))))) then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it1 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_250) then
if (ap_sig_bdd_2152) then
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_const_lv8_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_reg_phiprechg_core_1_reg_527pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it13 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it13_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_2108) then
if (ap_sig_bdd_2159) then
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_const_lv8_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_reg_phiprechg_core_1_reg_527pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it34 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it34_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_1776) then
if (ap_sig_bdd_2156) then
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= phitmp2_fu_4606_p2;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= ap_reg_phiprechg_core_1_reg_527pp0_it33;
end if;
end if;
end if;
end process;
-- p_2_reg_515 assign process. --
p_2_reg_515_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_2_reg_515 <= j_V_reg_5151;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
p_2_reg_515 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_s_reg_504 assign process. --
p_s_reg_504_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_3)) then
p_s_reg_504 <= i_V_reg_5122;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_180))) then
p_s_reg_504 <= ap_const_lv11_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))) then
a0_2_reg_6285 <= a0_2_fu_3841_p3;
b0_2_reg_6301 <= b0_2_fu_3882_p3;
tmp_232_2_reg_6291 <= tmp_232_2_fu_3853_p3;
tmp_239_2_reg_6307 <= tmp_239_2_fu_3894_p3;
tmp_59_reg_6296 <= tmp_59_fu_3860_p1;
tmp_85_reg_6312 <= tmp_85_fu_3901_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)))) then
a0_2_tmp_232_2_reg_6337 <= a0_2_tmp_232_2_fu_3916_p3;
b0_2_tmp_239_2_reg_6348 <= b0_2_tmp_239_2_fu_3936_p3;
tmp_209_3_reg_6343 <= tmp_209_3_fu_3922_p2;
tmp_221_3_reg_6354 <= tmp_221_3_fu_3942_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))) then
a0_3_reg_6359 <= a0_3_fu_3969_p3;
b0_3_reg_6375 <= b0_3_fu_4010_p3;
tmp_232_3_reg_6365 <= tmp_232_3_fu_3981_p3;
tmp_239_3_reg_6381 <= tmp_239_3_fu_4022_p3;
tmp_61_reg_6370 <= tmp_61_fu_3988_p1;
tmp_87_reg_6386 <= tmp_87_fu_4029_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)))) then
a0_3_tmp_232_3_reg_6411 <= a0_3_tmp_232_3_fu_4044_p3;
b0_3_tmp_239_3_reg_6422 <= b0_3_tmp_239_3_fu_4064_p3;
tmp_209_4_reg_6417 <= tmp_209_4_fu_4050_p2;
tmp_221_4_reg_6428 <= tmp_221_4_fu_4070_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))) then
a0_4_reg_6433 <= a0_4_fu_4097_p3;
b0_4_reg_6449 <= b0_4_fu_4138_p3;
tmp_232_4_reg_6439 <= tmp_232_4_fu_4109_p3;
tmp_239_4_reg_6455 <= tmp_239_4_fu_4150_p3;
tmp_63_reg_6444 <= tmp_63_fu_4116_p1;
tmp_89_reg_6460 <= tmp_89_fu_4157_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)))) then
a0_4_tmp_232_4_reg_6485 <= a0_4_tmp_232_4_fu_4172_p3;
b0_4_tmp_239_4_reg_6496 <= b0_4_tmp_239_4_fu_4192_p3;
tmp_209_5_reg_6491 <= tmp_209_5_fu_4178_p2;
tmp_221_5_reg_6502 <= tmp_221_5_fu_4198_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))) then
a0_5_reg_6507 <= a0_5_fu_4225_p3;
b0_5_reg_6523 <= b0_5_fu_4266_p3;
tmp_232_5_reg_6513 <= tmp_232_5_fu_4237_p3;
tmp_239_5_reg_6529 <= tmp_239_5_fu_4278_p3;
tmp_65_reg_6518 <= tmp_65_fu_4244_p1;
tmp_91_reg_6534 <= tmp_91_fu_4285_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)))) then
a0_5_tmp_232_5_reg_6559 <= a0_5_tmp_232_5_fu_4300_p3;
b0_5_tmp_239_5_reg_6570 <= b0_5_tmp_239_5_fu_4320_p3;
tmp_209_6_reg_6565 <= tmp_209_6_fu_4306_p2;
tmp_221_6_reg_6576 <= tmp_221_6_fu_4326_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))) then
a0_6_reg_6581 <= a0_6_fu_4353_p3;
b0_6_reg_6597 <= b0_6_fu_4394_p3;
tmp_232_6_reg_6587 <= tmp_232_6_fu_4365_p3;
tmp_239_6_reg_6603 <= tmp_239_6_fu_4406_p3;
tmp_75_reg_6592 <= tmp_75_fu_4372_p1;
tmp_93_reg_6608 <= tmp_93_fu_4413_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)))) then
a0_6_tmp_232_6_reg_6633 <= a0_6_tmp_232_6_fu_4428_p3;
b0_6_tmp_239_6_reg_6644 <= b0_6_tmp_239_6_fu_4448_p3;
tmp_209_7_reg_6639 <= tmp_209_7_fu_4434_p2;
tmp_221_7_reg_6650 <= tmp_221_7_fu_4454_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it29) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it29)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it29)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29)))) then
a0_7_reg_6655 <= a0_7_fu_4481_p3;
b0_7_reg_6671 <= b0_7_fu_4522_p3;
tmp_232_7_reg_6661 <= tmp_232_7_fu_4493_p3;
tmp_239_7_reg_6676 <= tmp_239_7_fu_4534_p3;
tmp_78_reg_6666 <= tmp_78_fu_4500_p1;
tmp_95_reg_6681 <= tmp_95_fu_4541_p1;
tmp_96_reg_6686 <= tmp_96_fu_4545_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it30) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it30)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it30)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30)))) then
a0_7_tmp_232_7_reg_6691 <= a0_7_tmp_232_7_fu_4557_p3;
tmp_79_reg_6697 <= tmp_79_fu_4571_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))) then
a0_s_reg_6211 <= a0_s_fu_3713_p3;
b0_s_reg_6227 <= b0_s_fu_3754_p3;
tmp_232_1_reg_6217 <= tmp_232_1_fu_3725_p3;
tmp_239_1_reg_6233 <= tmp_239_1_fu_3766_p3;
tmp_57_reg_6222 <= tmp_57_fu_3732_p1;
tmp_83_reg_6238 <= tmp_83_fu_3773_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)))) then
a0_tmp_232_1_reg_6263 <= a0_tmp_232_1_fu_3788_p3;
b0_tmp_239_1_reg_6274 <= b0_tmp_239_1_fu_3808_p3;
tmp_209_2_reg_6269 <= tmp_209_2_fu_3794_p2;
tmp_221_2_reg_6280 <= tmp_221_2_fu_3814_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it10 <= ap_reg_phiprechg_core_1_reg_527pp0_it9;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it11 <= ap_reg_phiprechg_core_1_reg_527pp0_it10;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it12 <= ap_reg_phiprechg_core_1_reg_527pp0_it11;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it13) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it14 <= ap_reg_phiprechg_core_1_reg_527pp0_it13;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it15 <= ap_reg_phiprechg_core_1_reg_527pp0_it14;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it15) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it16 <= ap_reg_phiprechg_core_1_reg_527pp0_it15;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it16) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it17 <= ap_reg_phiprechg_core_1_reg_527pp0_it16;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it17) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it18 <= ap_reg_phiprechg_core_1_reg_527pp0_it17;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it18) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it19 <= ap_reg_phiprechg_core_1_reg_527pp0_it18;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it2 <= ap_reg_phiprechg_core_1_reg_527pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it19) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it20 <= ap_reg_phiprechg_core_1_reg_527pp0_it19;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it20) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it21 <= ap_reg_phiprechg_core_1_reg_527pp0_it20;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it21) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it22 <= ap_reg_phiprechg_core_1_reg_527pp0_it21;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it22) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it23 <= ap_reg_phiprechg_core_1_reg_527pp0_it22;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it23) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it24 <= ap_reg_phiprechg_core_1_reg_527pp0_it23;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it24) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it25 <= ap_reg_phiprechg_core_1_reg_527pp0_it24;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it25) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it26 <= ap_reg_phiprechg_core_1_reg_527pp0_it25;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it27 <= ap_reg_phiprechg_core_1_reg_527pp0_it26;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it27) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it28 <= ap_reg_phiprechg_core_1_reg_527pp0_it27;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it28) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it29 <= ap_reg_phiprechg_core_1_reg_527pp0_it28;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it3 <= ap_reg_phiprechg_core_1_reg_527pp0_it2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it29) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it30 <= ap_reg_phiprechg_core_1_reg_527pp0_it29;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it30) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it31 <= ap_reg_phiprechg_core_1_reg_527pp0_it30;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it31) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it32 <= ap_reg_phiprechg_core_1_reg_527pp0_it31;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it33 <= ap_reg_phiprechg_core_1_reg_527pp0_it32;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it4 <= ap_reg_phiprechg_core_1_reg_527pp0_it3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it5 <= ap_reg_phiprechg_core_1_reg_527pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it6 <= ap_reg_phiprechg_core_1_reg_527pp0_it5;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it6) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it7 <= ap_reg_phiprechg_core_1_reg_527pp0_it6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it8 <= ap_reg_phiprechg_core_1_reg_527pp0_it7;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it9 <= ap_reg_phiprechg_core_1_reg_527pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 <= core_buf_val_1_V_addr_reg_6708;
ap_reg_ppstg_exitcond_reg_5147_pp0_it10 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it9;
ap_reg_ppstg_exitcond_reg_5147_pp0_it11 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it10;
ap_reg_ppstg_exitcond_reg_5147_pp0_it12 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it11;
ap_reg_ppstg_exitcond_reg_5147_pp0_it13 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it12;
ap_reg_ppstg_exitcond_reg_5147_pp0_it14 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it13;
ap_reg_ppstg_exitcond_reg_5147_pp0_it15 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it14;
ap_reg_ppstg_exitcond_reg_5147_pp0_it16 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it15;
ap_reg_ppstg_exitcond_reg_5147_pp0_it17 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it16;
ap_reg_ppstg_exitcond_reg_5147_pp0_it18 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it17;
ap_reg_ppstg_exitcond_reg_5147_pp0_it19 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it18;
ap_reg_ppstg_exitcond_reg_5147_pp0_it2 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it1;
ap_reg_ppstg_exitcond_reg_5147_pp0_it20 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it19;
ap_reg_ppstg_exitcond_reg_5147_pp0_it21 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it20;
ap_reg_ppstg_exitcond_reg_5147_pp0_it22 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it21;
ap_reg_ppstg_exitcond_reg_5147_pp0_it23 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it22;
ap_reg_ppstg_exitcond_reg_5147_pp0_it24 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it23;
ap_reg_ppstg_exitcond_reg_5147_pp0_it25 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it24;
ap_reg_ppstg_exitcond_reg_5147_pp0_it26 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it25;
ap_reg_ppstg_exitcond_reg_5147_pp0_it27 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it26;
ap_reg_ppstg_exitcond_reg_5147_pp0_it28 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it27;
ap_reg_ppstg_exitcond_reg_5147_pp0_it29 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it28;
ap_reg_ppstg_exitcond_reg_5147_pp0_it3 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it2;
ap_reg_ppstg_exitcond_reg_5147_pp0_it30 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it29;
ap_reg_ppstg_exitcond_reg_5147_pp0_it31 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it30;
ap_reg_ppstg_exitcond_reg_5147_pp0_it32 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it31;
ap_reg_ppstg_exitcond_reg_5147_pp0_it33 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it32;
ap_reg_ppstg_exitcond_reg_5147_pp0_it4 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it3;
ap_reg_ppstg_exitcond_reg_5147_pp0_it5 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it4;
ap_reg_ppstg_exitcond_reg_5147_pp0_it6 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it5;
ap_reg_ppstg_exitcond_reg_5147_pp0_it7 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it6;
ap_reg_ppstg_exitcond_reg_5147_pp0_it8 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it7;
ap_reg_ppstg_exitcond_reg_5147_pp0_it9 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it8;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 <= flag_d_max2_1_reg_5959;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 <= ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14;
ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 <= flag_d_max2_7_reg_5971;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 <= flag_d_max4_1_reg_5993;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 <= ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 <= flag_d_max4_5_reg_6005;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 <= ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 <= flag_d_min2_1_reg_5953;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 <= ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14;
ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 <= flag_d_min2_7_reg_5965;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 <= flag_d_min4_1_reg_5987;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 <= ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 <= flag_d_min4_5_reg_5999;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 <= ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 <= flag_val_V_assign_load_1_s_reg_5417;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 <= ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 <= iscorner_2_i_s_reg_5949;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 <= not_or_cond10_demorgan_reg_5699;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 <= not_or_cond11_demorgan_reg_5704;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 <= not_or_cond6_demorgan_reg_5605;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 <= not_or_cond7_demorgan_reg_5610;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 <= not_or_cond8_demorgan_reg_5615;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 <= not_or_cond9_demorgan_reg_5620;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 <= not_or_cond_reg_5733;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it9;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it10;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it11;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it12;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it13;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it14;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it15;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it16;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it17;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it18;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it1;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it19;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it20;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it21;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it22;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it23;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it24;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it25;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it26;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it27;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it28;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it2;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it29;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it30;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it31;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it3;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it4;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it5;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it6;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it7;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it8;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 <= or_cond2_reg_5660;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it5;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it6;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it7;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it8;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it9;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it10;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it11;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it12;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it13;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it14;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it15;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it16;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it17;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it18;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it1;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it19;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it20;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it21;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it22;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it23;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it24;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it25;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it26;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it27;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it28;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it2;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it29;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it30;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it31;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it32;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it33;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it3;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it4;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it5;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it6;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it7;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it8;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 <= or_cond5_reg_5537;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it4;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it5;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it6;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 <= or_cond6_reg_5543;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it4;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it5;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it6;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 <= or_cond7_reg_5548;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it4;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it5;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 <= or_cond8_reg_5553;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it4;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it5;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it7;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 <= or_cond9_reg_5559;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it4;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it5;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it6;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it10 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it9;
ap_reg_ppstg_or_cond_reg_5156_pp0_it11 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it10;
ap_reg_ppstg_or_cond_reg_5156_pp0_it12 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it11;
ap_reg_ppstg_or_cond_reg_5156_pp0_it13 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it12;
ap_reg_ppstg_or_cond_reg_5156_pp0_it14 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it13;
ap_reg_ppstg_or_cond_reg_5156_pp0_it15 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it14;
ap_reg_ppstg_or_cond_reg_5156_pp0_it16 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it15;
ap_reg_ppstg_or_cond_reg_5156_pp0_it17 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it16;
ap_reg_ppstg_or_cond_reg_5156_pp0_it18 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it17;
ap_reg_ppstg_or_cond_reg_5156_pp0_it19 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it18;
ap_reg_ppstg_or_cond_reg_5156_pp0_it2 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it1;
ap_reg_ppstg_or_cond_reg_5156_pp0_it20 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it19;
ap_reg_ppstg_or_cond_reg_5156_pp0_it21 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it20;
ap_reg_ppstg_or_cond_reg_5156_pp0_it22 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it21;
ap_reg_ppstg_or_cond_reg_5156_pp0_it23 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it22;
ap_reg_ppstg_or_cond_reg_5156_pp0_it24 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it23;
ap_reg_ppstg_or_cond_reg_5156_pp0_it25 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it24;
ap_reg_ppstg_or_cond_reg_5156_pp0_it26 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it25;
ap_reg_ppstg_or_cond_reg_5156_pp0_it27 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it26;
ap_reg_ppstg_or_cond_reg_5156_pp0_it28 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it27;
ap_reg_ppstg_or_cond_reg_5156_pp0_it29 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it28;
ap_reg_ppstg_or_cond_reg_5156_pp0_it3 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it2;
ap_reg_ppstg_or_cond_reg_5156_pp0_it30 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it29;
ap_reg_ppstg_or_cond_reg_5156_pp0_it31 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it30;
ap_reg_ppstg_or_cond_reg_5156_pp0_it32 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it31;
ap_reg_ppstg_or_cond_reg_5156_pp0_it33 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it32;
ap_reg_ppstg_or_cond_reg_5156_pp0_it4 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it3;
ap_reg_ppstg_or_cond_reg_5156_pp0_it5 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it4;
ap_reg_ppstg_or_cond_reg_5156_pp0_it6 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it5;
ap_reg_ppstg_or_cond_reg_5156_pp0_it7 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it6;
ap_reg_ppstg_or_cond_reg_5156_pp0_it8 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it9 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it8;
ap_reg_ppstg_p_2_reg_515_pp0_it10 <= ap_reg_ppstg_p_2_reg_515_pp0_it9;
ap_reg_ppstg_p_2_reg_515_pp0_it11 <= ap_reg_ppstg_p_2_reg_515_pp0_it10;
ap_reg_ppstg_p_2_reg_515_pp0_it12 <= ap_reg_ppstg_p_2_reg_515_pp0_it11;
ap_reg_ppstg_p_2_reg_515_pp0_it13 <= ap_reg_ppstg_p_2_reg_515_pp0_it12;
ap_reg_ppstg_p_2_reg_515_pp0_it14 <= ap_reg_ppstg_p_2_reg_515_pp0_it13;
ap_reg_ppstg_p_2_reg_515_pp0_it15 <= ap_reg_ppstg_p_2_reg_515_pp0_it14;
ap_reg_ppstg_p_2_reg_515_pp0_it16 <= ap_reg_ppstg_p_2_reg_515_pp0_it15;
ap_reg_ppstg_p_2_reg_515_pp0_it17 <= ap_reg_ppstg_p_2_reg_515_pp0_it16;
ap_reg_ppstg_p_2_reg_515_pp0_it18 <= ap_reg_ppstg_p_2_reg_515_pp0_it17;
ap_reg_ppstg_p_2_reg_515_pp0_it19 <= ap_reg_ppstg_p_2_reg_515_pp0_it18;
ap_reg_ppstg_p_2_reg_515_pp0_it2 <= ap_reg_ppstg_p_2_reg_515_pp0_it1;
ap_reg_ppstg_p_2_reg_515_pp0_it20 <= ap_reg_ppstg_p_2_reg_515_pp0_it19;
ap_reg_ppstg_p_2_reg_515_pp0_it21 <= ap_reg_ppstg_p_2_reg_515_pp0_it20;
ap_reg_ppstg_p_2_reg_515_pp0_it22 <= ap_reg_ppstg_p_2_reg_515_pp0_it21;
ap_reg_ppstg_p_2_reg_515_pp0_it23 <= ap_reg_ppstg_p_2_reg_515_pp0_it22;
ap_reg_ppstg_p_2_reg_515_pp0_it24 <= ap_reg_ppstg_p_2_reg_515_pp0_it23;
ap_reg_ppstg_p_2_reg_515_pp0_it25 <= ap_reg_ppstg_p_2_reg_515_pp0_it24;
ap_reg_ppstg_p_2_reg_515_pp0_it26 <= ap_reg_ppstg_p_2_reg_515_pp0_it25;
ap_reg_ppstg_p_2_reg_515_pp0_it27 <= ap_reg_ppstg_p_2_reg_515_pp0_it26;
ap_reg_ppstg_p_2_reg_515_pp0_it28 <= ap_reg_ppstg_p_2_reg_515_pp0_it27;
ap_reg_ppstg_p_2_reg_515_pp0_it29 <= ap_reg_ppstg_p_2_reg_515_pp0_it28;
ap_reg_ppstg_p_2_reg_515_pp0_it3 <= ap_reg_ppstg_p_2_reg_515_pp0_it2;
ap_reg_ppstg_p_2_reg_515_pp0_it30 <= ap_reg_ppstg_p_2_reg_515_pp0_it29;
ap_reg_ppstg_p_2_reg_515_pp0_it31 <= ap_reg_ppstg_p_2_reg_515_pp0_it30;
ap_reg_ppstg_p_2_reg_515_pp0_it4 <= ap_reg_ppstg_p_2_reg_515_pp0_it3;
ap_reg_ppstg_p_2_reg_515_pp0_it5 <= ap_reg_ppstg_p_2_reg_515_pp0_it4;
ap_reg_ppstg_p_2_reg_515_pp0_it6 <= ap_reg_ppstg_p_2_reg_515_pp0_it5;
ap_reg_ppstg_p_2_reg_515_pp0_it7 <= ap_reg_ppstg_p_2_reg_515_pp0_it6;
ap_reg_ppstg_p_2_reg_515_pp0_it8 <= ap_reg_ppstg_p_2_reg_515_pp0_it7;
ap_reg_ppstg_p_2_reg_515_pp0_it9 <= ap_reg_ppstg_p_2_reg_515_pp0_it8;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 <= r_V_1_1_reg_5432;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 <= r_V_1_2_reg_5452;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 <= r_V_1_3_reg_5472;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 <= r_V_1_4_reg_5483;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 <= r_V_1_5_reg_5494;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 <= r_V_1_6_reg_5505;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 <= r_V_1_7_reg_5516;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it9;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it10;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it12;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it13;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it14;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it15;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it16;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it17;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it18;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it19;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it20;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it21;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 <= r_V_1_reg_5408;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it4;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it5;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it6;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it7;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it8;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it9;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it10;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it12;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it13;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it14;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it15;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 <= r_V_2_reg_5290;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it3;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it4;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it5;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it6;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it7;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it8;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it9;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it10;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it11;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it12;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it13;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it14;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it15;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it16;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it17;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it18;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it19;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it20;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it21;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it22;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it23;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it24;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 <= r_V_3_reg_5309;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it3;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it4;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it5;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it6;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it7;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it8;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it9;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it10;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it12;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it13;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it14;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it15;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it16;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it17;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 <= r_V_4_reg_5328;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it3;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it4;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it5;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it6;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it7;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it8;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it9;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it10;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it11;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it12;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it13;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it14;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it15;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it16;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it17;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it18;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it19;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it20;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it21;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it22;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it23;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it24;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it25;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it26;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 <= r_V_5_reg_5348;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it3;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it4;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it5;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it6;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it7;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it8;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it9;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it10;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it12;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it13;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it14;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it15;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it16;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it17;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it18;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it19;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 <= r_V_6_reg_5368;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it3;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it4;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it5;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it6;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it7;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it8;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it9;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it10;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it11;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it12;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it13;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it14;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it15;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it16;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it17;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it18;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it19;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it20;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it21;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it22;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it23;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it24;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it25;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it26;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it27;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it28;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 <= r_V_7_reg_5388;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it3;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it4;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it5;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it6;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it7;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it8;
ap_reg_ppstg_r_V_reg_5252_pp0_it10 <= ap_reg_ppstg_r_V_reg_5252_pp0_it9;
ap_reg_ppstg_r_V_reg_5252_pp0_it11 <= ap_reg_ppstg_r_V_reg_5252_pp0_it10;
ap_reg_ppstg_r_V_reg_5252_pp0_it12 <= ap_reg_ppstg_r_V_reg_5252_pp0_it11;
ap_reg_ppstg_r_V_reg_5252_pp0_it13 <= ap_reg_ppstg_r_V_reg_5252_pp0_it12;
ap_reg_ppstg_r_V_reg_5252_pp0_it14 <= ap_reg_ppstg_r_V_reg_5252_pp0_it13;
ap_reg_ppstg_r_V_reg_5252_pp0_it3 <= r_V_reg_5252;
ap_reg_ppstg_r_V_reg_5252_pp0_it4 <= ap_reg_ppstg_r_V_reg_5252_pp0_it3;
ap_reg_ppstg_r_V_reg_5252_pp0_it5 <= ap_reg_ppstg_r_V_reg_5252_pp0_it4;
ap_reg_ppstg_r_V_reg_5252_pp0_it6 <= ap_reg_ppstg_r_V_reg_5252_pp0_it5;
ap_reg_ppstg_r_V_reg_5252_pp0_it7 <= ap_reg_ppstg_r_V_reg_5252_pp0_it6;
ap_reg_ppstg_r_V_reg_5252_pp0_it8 <= ap_reg_ppstg_r_V_reg_5252_pp0_it7;
ap_reg_ppstg_r_V_reg_5252_pp0_it9 <= ap_reg_ppstg_r_V_reg_5252_pp0_it8;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it9;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it10;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it11;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it12;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it13;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it14;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it15;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it16;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it17;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it18;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it19;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it20;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it21;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it22;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 <= r_V_s_reg_5271;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it3;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it4;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it5;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it6;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it7;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it8;
ap_reg_ppstg_tmp11_reg_5934_pp0_it11 <= tmp11_reg_5934;
ap_reg_ppstg_tmp12_reg_5883_pp0_it9 <= tmp12_reg_5883;
ap_reg_ppstg_tmp3_reg_5878_pp0_it10 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it9;
ap_reg_ppstg_tmp3_reg_5878_pp0_it11 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it10;
ap_reg_ppstg_tmp3_reg_5878_pp0_it9 <= tmp3_reg_5878;
ap_reg_ppstg_tmp5_reg_5781_pp0_it6 <= tmp5_reg_5781;
ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 <= tmp_200_3_reg_5977;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 <= tmp_210_2_reg_6169;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 <= tmp_210_4_reg_6179;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 <= tmp_210_7_reg_6139;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 <= tmp_210_9_reg_6149;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 <= tmp_210_s_reg_6159;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22;
ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 <= tmp_213_3_reg_5982;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 <= tmp_225_2_reg_6174;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 <= tmp_225_4_reg_6184;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 <= tmp_225_7_reg_6144;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 <= tmp_225_9_reg_6154;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 <= tmp_225_s_reg_6164;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 <= tmp_39_reg_5532;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 <= ap_reg_ppstg_tmp_39_reg_5532_pp0_it4;
ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 <= tmp_53_reg_6719;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppstg_exitcond_reg_5147_pp0_it1 <= exitcond_reg_5147;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 <= or_cond1_reg_5197;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 <= or_cond4_reg_5201;
ap_reg_ppstg_or_cond_reg_5156_pp0_it1 <= or_cond_reg_5156;
ap_reg_ppstg_p_2_reg_515_pp0_it1 <= p_2_reg_515;
exitcond_reg_5147 <= exitcond_fu_846_p2;
win_val_0_V_2_1_reg_5205 <= win_val_0_V_2_fu_172;
win_val_1_V_4_3_reg_5210 <= win_val_1_V_4_fu_204;
win_val_2_V_5_3_reg_5215 <= win_val_2_V_5_fu_236;
win_val_3_V_2_3_reg_5220 <= win_val_3_V_2_fu_252;
win_val_4_V_5_3_reg_5225 <= win_val_4_V_5_fu_292;
win_val_5_V_4_3_reg_5230 <= win_val_5_V_4_fu_312;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it15)))) then
b0_reg_6093 <= b0_fu_3473_p3;
p_a_0_flag_d_assign_load_5_reg_6077 <= p_a_0_flag_d_assign_load_5_fu_3434_p3;
tmp_47_reg_6083 <= tmp_47_fu_3447_p3;
tmp_48_reg_6088 <= tmp_48_fu_3454_p1;
tmp_71_reg_6099 <= tmp_71_fu_3486_p3;
tmp_81_reg_6104 <= tmp_81_fu_3493_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))) then
b0_tmp_s_reg_6200 <= b0_tmp_s_fu_3680_p3;
p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 <= p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3;
tmp_209_1_reg_6195 <= tmp_209_1_fu_3666_p2;
tmp_221_1_reg_6206 <= tmp_221_1_fu_3686_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it31))) then
core_buf_val_0_V_addr_reg_6702 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_1_V_addr_reg_6708 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
tmp_53_reg_6719 <= tmp_53_fu_4600_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32))) then
core_buf_val_0_V_load_reg_6724 <= core_buf_val_0_V_q0;
core_buf_val_1_V_load_reg_6729 <= core_buf_val_1_V_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) then
core_win_val_0_V_0_fu_136(0) <= core_win_val_0_V_1_fu_140(0);
core_win_val_0_V_0_fu_136(1) <= core_win_val_0_V_1_fu_140(1);
core_win_val_0_V_0_fu_136(2) <= core_win_val_0_V_1_fu_140(2);
core_win_val_0_V_0_fu_136(3) <= core_win_val_0_V_1_fu_140(3);
core_win_val_0_V_0_fu_136(4) <= core_win_val_0_V_1_fu_140(4);
core_win_val_0_V_0_fu_136(5) <= core_win_val_0_V_1_fu_140(5);
core_win_val_0_V_0_fu_136(6) <= core_win_val_0_V_1_fu_140(6);
core_win_val_0_V_0_fu_136(7) <= core_win_val_0_V_1_fu_140(7);
core_win_val_0_V_1_fu_140(0) <= core_win_val_0_V_2_fu_4620_p1(0);
core_win_val_0_V_1_fu_140(1) <= core_win_val_0_V_2_fu_4620_p1(1);
core_win_val_0_V_1_fu_140(2) <= core_win_val_0_V_2_fu_4620_p1(2);
core_win_val_0_V_1_fu_140(3) <= core_win_val_0_V_2_fu_4620_p1(3);
core_win_val_0_V_1_fu_140(4) <= core_win_val_0_V_2_fu_4620_p1(4);
core_win_val_0_V_1_fu_140(5) <= core_win_val_0_V_2_fu_4620_p1(5);
core_win_val_0_V_1_fu_140(6) <= core_win_val_0_V_2_fu_4620_p1(6);
core_win_val_0_V_1_fu_140(7) <= core_win_val_0_V_2_fu_4620_p1(7);
core_win_val_1_V_0_fu_148(0) <= core_win_val_1_V_1_fu_152(0);
core_win_val_1_V_0_fu_148(1) <= core_win_val_1_V_1_fu_152(1);
core_win_val_1_V_0_fu_148(2) <= core_win_val_1_V_1_fu_152(2);
core_win_val_1_V_0_fu_148(3) <= core_win_val_1_V_1_fu_152(3);
core_win_val_1_V_0_fu_148(4) <= core_win_val_1_V_1_fu_152(4);
core_win_val_1_V_0_fu_148(5) <= core_win_val_1_V_1_fu_152(5);
core_win_val_1_V_0_fu_148(6) <= core_win_val_1_V_1_fu_152(6);
core_win_val_1_V_0_fu_148(7) <= core_win_val_1_V_1_fu_152(7);
core_win_val_1_V_1_fu_152(0) <= core_win_val_1_V_2_fu_4623_p1(0);
core_win_val_1_V_1_fu_152(1) <= core_win_val_1_V_2_fu_4623_p1(1);
core_win_val_1_V_1_fu_152(2) <= core_win_val_1_V_2_fu_4623_p1(2);
core_win_val_1_V_1_fu_152(3) <= core_win_val_1_V_2_fu_4623_p1(3);
core_win_val_1_V_1_fu_152(4) <= core_win_val_1_V_2_fu_4623_p1(4);
core_win_val_1_V_1_fu_152(5) <= core_win_val_1_V_2_fu_4623_p1(5);
core_win_val_1_V_1_fu_152(6) <= core_win_val_1_V_2_fu_4623_p1(6);
core_win_val_1_V_1_fu_152(7) <= core_win_val_1_V_2_fu_4623_p1(7);
core_win_val_2_V_0_fu_160(0) <= core_win_val_2_V_1_fu_164(0);
core_win_val_2_V_0_fu_160(1) <= core_win_val_2_V_1_fu_164(1);
core_win_val_2_V_0_fu_160(2) <= core_win_val_2_V_1_fu_164(2);
core_win_val_2_V_0_fu_160(3) <= core_win_val_2_V_1_fu_164(3);
core_win_val_2_V_0_fu_160(4) <= core_win_val_2_V_1_fu_164(4);
core_win_val_2_V_0_fu_160(5) <= core_win_val_2_V_1_fu_164(5);
core_win_val_2_V_0_fu_160(6) <= core_win_val_2_V_1_fu_164(6);
core_win_val_2_V_0_fu_160(7) <= core_win_val_2_V_1_fu_164(7);
core_win_val_2_V_1_fu_164(0) <= core_win_val_2_V_1_2_fu_4643_p1(0);
core_win_val_2_V_1_fu_164(1) <= core_win_val_2_V_1_2_fu_4643_p1(1);
core_win_val_2_V_1_fu_164(2) <= core_win_val_2_V_1_2_fu_4643_p1(2);
core_win_val_2_V_1_fu_164(3) <= core_win_val_2_V_1_2_fu_4643_p1(3);
core_win_val_2_V_1_fu_164(4) <= core_win_val_2_V_1_2_fu_4643_p1(4);
core_win_val_2_V_1_fu_164(5) <= core_win_val_2_V_1_2_fu_4643_p1(5);
core_win_val_2_V_1_fu_164(6) <= core_win_val_2_V_1_2_fu_4643_p1(6);
core_win_val_2_V_1_fu_164(7) <= core_win_val_2_V_1_2_fu_4643_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it2)))) then
count_1_i_0_op_op87_op_reg_5590(0) <= count_1_i_0_op_op87_op_fu_1848_p3(0);
flag_val_V_assign_load_1_13_reg_5527 <= flag_val_V_assign_load_1_13_fu_1726_p3;
flag_val_V_assign_load_1_s_reg_5417 <= flag_val_V_assign_load_1_s_fu_1521_p3;
not_or_cond6_demorgan_reg_5605 <= not_or_cond6_demorgan_fu_1870_p2;
not_or_cond7_demorgan_reg_5610 <= not_or_cond7_demorgan_fu_1876_p2;
not_or_cond8_demorgan_reg_5615 <= not_or_cond8_demorgan_fu_1882_p2;
not_or_cond9_demorgan_reg_5620 <= not_or_cond9_demorgan_fu_1888_p2;
or_cond5_reg_5537 <= or_cond5_fu_1746_p2;
or_cond6_reg_5543 <= or_cond6_fu_1764_p2;
or_cond7_reg_5548 <= or_cond7_fu_1782_p2;
or_cond8_reg_5553 <= or_cond8_fu_1800_p2;
or_cond9_reg_5559 <= or_cond9_fu_1818_p2;
phitmp3_reg_5422 <= phitmp3_fu_1539_p3;
phitmp43_op_op_cast_cast_cast_reg_5595(0) <= phitmp43_op_op_cast_cast_cast_fu_1856_p3(0);
r_V_1_1_reg_5432 <= r_V_1_1_fu_1557_p2;
r_V_1_2_reg_5452 <= r_V_1_2_fu_1584_p2;
r_V_1_3_reg_5472 <= r_V_1_3_fu_1611_p2;
r_V_1_4_reg_5483 <= r_V_1_4_fu_1626_p2;
r_V_1_5_reg_5494 <= r_V_1_5_fu_1654_p2;
r_V_1_6_reg_5505 <= r_V_1_6_fu_1682_p2;
r_V_1_7_reg_5516 <= r_V_1_7_fu_1710_p2;
r_V_1_reg_5408 <= r_V_1_fu_1516_p2;
tmp_181_5_not_reg_5566 <= tmp_181_5_not_fu_1824_p2;
tmp_181_6_not_reg_5578 <= tmp_181_6_not_fu_1836_p2;
tmp_182_1_reg_5441 <= tmp_182_1_fu_1568_p2;
tmp_182_2_reg_5461 <= tmp_182_2_fu_1595_p2;
tmp_183_5_reg_5572 <= tmp_183_5_fu_1830_p2;
tmp_183_6_reg_5584 <= tmp_183_6_fu_1842_p2;
tmp_184_1_reg_5447 <= tmp_184_1_fu_1574_p2;
tmp_184_2_reg_5467 <= tmp_184_2_fu_1601_p2;
tmp_23_reg_5427 <= tmp_23_fu_1547_p2;
tmp_39_reg_5532 <= tmp_39_fu_1740_p2;
tmp_40_reg_5600 <= tmp_40_fu_1864_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it7) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it7)))) then
count_1_i_12_reg_5872 <= count_1_i_12_fu_2678_p3;
count_4_reg_5867 <= count_4_fu_2666_p2;
p_iscorner_0_i_7_reg_5862 <= p_iscorner_0_i_7_fu_2653_p2;
tmp12_reg_5883 <= tmp12_fu_2694_p2;
tmp3_reg_5878 <= tmp3_fu_2689_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it8) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it8)))) then
count_1_i_14_reg_5898 <= count_1_i_14_fu_2755_p3;
p_iscorner_0_i_11_reg_5888 <= p_iscorner_0_i_11_fu_2725_p2;
tmp13_reg_5904 <= tmp13_fu_2762_p2;
tmp_185_13_reg_5893 <= tmp_185_13_fu_2743_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it5) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it5)))) then
count_1_i_3_reg_5806 <= count_1_i_3_fu_2476_p3;
not_or_cond13_demorgan_reg_5801 <= not_or_cond13_demorgan_fu_2470_p2;
not_or_cond14_demorgan_reg_5816 <= not_or_cond14_demorgan_fu_2500_p2;
or_cond17_reg_5811 <= or_cond17_fu_2494_p2;
or_cond18_reg_5821 <= or_cond18_fu_2511_p2;
p_iscorner_0_i_1_reg_5786 <= p_iscorner_0_i_1_fu_2391_p2;
p_iscorner_0_i_2_reg_5791 <= p_iscorner_0_i_2_fu_2435_p2;
tmp6_reg_5827 <= tmp6_fu_2516_p2;
tmp_185_3_reg_5796 <= tmp_185_3_fu_2464_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it3) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it3)))) then
count_1_i_6_reg_5665 <= count_1_i_6_fu_2036_p3;
count_1_i_7_reg_5675 <= count_1_i_7_fu_2061_p3;
flag_val_V_assign_load_1_3_reg_5625 <= flag_val_V_assign_load_1_3_fu_1930_p3;
flag_val_V_assign_load_1_5_reg_5631 <= flag_val_V_assign_load_1_5_fu_1962_p3;
not_or_cond10_demorgan_reg_5699 <= not_or_cond10_demorgan_fu_2093_p2;
not_or_cond11_demorgan_reg_5704 <= not_or_cond11_demorgan_fu_2097_p2;
or_cond10_reg_5670 <= or_cond10_fu_2055_p2;
or_cond11_reg_5681 <= or_cond11_fu_2075_p2;
or_cond2_reg_5660 <= or_cond2_fu_1990_p2;
tmp_181_9_reg_5687 <= tmp_181_9_fu_2081_p2;
tmp_182_4_reg_5638 <= tmp_182_4_fu_1970_p2;
tmp_182_5_reg_5649 <= tmp_182_5_fu_1980_p2;
tmp_183_9_reg_5693 <= tmp_183_9_fu_2087_p2;
tmp_184_4_reg_5644 <= tmp_184_4_fu_1975_p2;
tmp_184_5_reg_5655 <= tmp_184_5_fu_1985_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it4) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it4)))) then
count_1_i_9_reg_5743 <= count_1_i_9_fu_2257_p3;
count_1_i_s_reg_5753 <= count_1_i_s_fu_2292_p3;
flag_val_V_assign_load_1_10_reg_5709 <= flag_val_V_assign_load_1_10_fu_2131_p3;
flag_val_V_assign_load_1_12_reg_5715 <= flag_val_V_assign_load_1_12_fu_2163_p3;
not_or_cond3_demorgan_reg_5748 <= not_or_cond3_demorgan_fu_2286_p2;
not_or_cond4_demorgan_reg_5764 <= not_or_cond4_demorgan_fu_2316_p2;
not_or_cond_reg_5733 <= not_or_cond_fu_2186_p2;
or_cond14_reg_5759 <= or_cond14_fu_2310_p2;
p_iscorner_0_i_9_reg_5738 <= p_iscorner_0_i_9_fu_2251_p2;
tmp5_reg_5781 <= tmp5_fu_2334_p2;
tmp_181_2_reg_5769 <= tmp_181_2_fu_2322_p2;
tmp_182_7_reg_5722 <= tmp_182_7_fu_2171_p2;
tmp_183_10_reg_5775 <= tmp_183_10_fu_2328_p2;
tmp_184_7_reg_5728 <= tmp_184_7_fu_2176_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it6) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it6)))) then
count_3_reg_5837 <= count_3_fu_2594_p2;
p_iscorner_0_i_5_reg_5832 <= p_iscorner_0_i_5_fu_2581_p2;
tmp4_reg_5847 <= tmp4_fu_2606_p2;
tmp8_reg_5852 <= tmp8_fu_2610_p2;
tmp9_reg_5857 <= tmp9_fu_2614_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)))) then
flag_d_assign_11_reg_6539 <= flag_d_assign_11_fu_4289_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)))) then
flag_d_assign_13_reg_6613 <= flag_d_assign_13_fu_4417_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)))) then
flag_d_assign_2_reg_6109 <= flag_d_assign_2_fu_3497_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)))) then
flag_d_assign_4_reg_6243 <= flag_d_assign_4_fu_3777_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)))) then
flag_d_assign_6_reg_6317 <= flag_d_assign_6_fu_3905_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)))) then
flag_d_assign_8_reg_6391 <= flag_d_assign_8_fu_4033_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)))) then
flag_d_assign_reg_6011 <= flag_d_assign_fu_3143_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)))) then
flag_d_assign_s_reg_6465 <= flag_d_assign_s_fu_4161_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949)))) then
flag_d_max2_1_reg_5959 <= grp_image_filter_reg_int_s_fu_547_ap_return;
flag_d_max2_7_reg_5971 <= grp_image_filter_reg_int_s_fu_577_ap_return;
flag_d_min2_1_reg_5953 <= grp_image_filter_reg_int_s_fu_542_ap_return;
flag_d_min2_7_reg_5965 <= grp_image_filter_reg_int_s_fu_572_ap_return;
tmp_200_3_reg_5977 <= tmp_200_3_fu_3031_p3;
tmp_213_3_reg_5982 <= tmp_213_3_fu_3045_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))) then
flag_d_max2_9_reg_6023 <= grp_image_filter_reg_int_s_fu_607_ap_return;
flag_d_max8_1_reg_6036 <= grp_image_filter_reg_int_s_fu_617_ap_return;
flag_d_min2_9_reg_6017 <= grp_image_filter_reg_int_s_fu_602_ap_return;
flag_d_min8_1_reg_6029 <= grp_image_filter_reg_int_s_fu_612_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))) then
flag_d_max4_1_reg_5993 <= grp_image_filter_reg_int_s_fu_587_ap_return;
flag_d_max4_5_reg_6005 <= grp_image_filter_reg_int_s_fu_597_ap_return;
flag_d_min4_1_reg_5987 <= grp_image_filter_reg_int_s_fu_582_ap_return;
flag_d_min4_5_reg_5999 <= grp_image_filter_reg_int_s_fu_592_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))) then
flag_d_max4_3_reg_6059 <= grp_image_filter_reg_int_s_fu_657_ap_return;
flag_d_max4_7_reg_6071 <= grp_image_filter_reg_int_s_fu_667_ap_return;
flag_d_min4_3_reg_6053 <= grp_image_filter_reg_int_s_fu_652_ap_return;
flag_d_min4_7_reg_6065 <= grp_image_filter_reg_int_s_fu_662_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))) then
flag_d_max8_3_reg_6122 <= grp_image_filter_reg_int_s_fu_717_ap_return;
flag_d_min8_3_reg_6115 <= grp_image_filter_reg_int_s_fu_712_ap_return;
tmp_210_2_reg_6169 <= tmp_210_2_fu_3609_p3;
tmp_210_4_reg_6179 <= tmp_210_4_fu_3633_p3;
tmp_210_5_reg_6129 <= tmp_210_5_fu_3505_p3;
tmp_210_7_reg_6139 <= tmp_210_7_fu_3529_p3;
tmp_210_9_reg_6149 <= tmp_210_9_fu_3554_p3;
tmp_210_s_reg_6159 <= tmp_210_s_fu_3582_p3;
tmp_225_2_reg_6174 <= tmp_225_2_fu_3621_p3;
tmp_225_4_reg_6184 <= tmp_225_4_fu_3645_p3;
tmp_225_5_reg_6134 <= tmp_225_5_fu_3517_p3;
tmp_225_7_reg_6144 <= tmp_225_7_fu_3541_p3;
tmp_225_9_reg_6154 <= tmp_225_9_fu_3568_p3;
tmp_225_s_reg_6164 <= tmp_225_s_fu_3596_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)))) then
flag_d_max8_5_reg_6256 <= grp_image_filter_reg_int_s_fu_727_ap_return;
flag_d_min8_5_reg_6249 <= grp_image_filter_reg_int_s_fu_722_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)))) then
flag_d_max8_7_reg_6330 <= grp_image_filter_reg_int_s_fu_737_ap_return;
flag_d_min8_7_reg_6323 <= grp_image_filter_reg_int_s_fu_732_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)))) then
flag_d_max8_9_reg_6404 <= grp_image_filter_reg_int_s_fu_747_ap_return;
flag_d_min8_9_reg_6397 <= grp_image_filter_reg_int_s_fu_742_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_5122 <= i_V_fu_807_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
icmp_reg_5142 <= icmp_fu_840_p2;
tmp_7_reg_5127 <= tmp_7_fu_813_p2;
tmp_8_reg_5132 <= tmp_8_fu_818_p2;
tmp_9_reg_5137 <= tmp_9_fu_824_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)))) then
iscorner_2_i_s_reg_5949 <= iscorner_2_i_s_fu_2870_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
j_V_reg_5151 <= j_V_fu_851_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = exitcond_fu_846_p2) and not((ap_const_lv1_0 = or_cond_fu_862_p2)))) then
k_buf_val_0_V_addr_reg_5161 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_1_V_addr_reg_5167 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_2_V_addr_reg_5173 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_3_V_addr_reg_5179 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_4_V_addr_reg_5185 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_5_V_addr_reg_5191 <= tmp_12_fu_867_p1(11 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it1)))) then
lhs_V_reg_5240(0) <= lhs_V_fu_1252_p1(0);
lhs_V_reg_5240(1) <= lhs_V_fu_1252_p1(1);
lhs_V_reg_5240(2) <= lhs_V_fu_1252_p1(2);
lhs_V_reg_5240(3) <= lhs_V_fu_1252_p1(3);
lhs_V_reg_5240(4) <= lhs_V_fu_1252_p1(4);
lhs_V_reg_5240(5) <= lhs_V_fu_1252_p1(5);
lhs_V_reg_5240(6) <= lhs_V_fu_1252_p1(6);
lhs_V_reg_5240(7) <= lhs_V_fu_1252_p1(7);
phitmp1_reg_5261 <= phitmp1_fu_1278_p3;
phitmp_1_reg_5280 <= phitmp_1_fu_1314_p3;
phitmp_2_reg_5299 <= phitmp_2_fu_1350_p3;
phitmp_3_reg_5318 <= phitmp_3_fu_1386_p3;
r_V_2_reg_5290 <= r_V_2_fu_1332_p2;
r_V_3_reg_5309 <= r_V_3_fu_1368_p2;
r_V_4_reg_5328 <= r_V_4_fu_1404_p2;
r_V_5_reg_5348 <= r_V_5_fu_1426_p2;
r_V_6_reg_5368 <= r_V_6_fu_1448_p2;
r_V_7_reg_5388 <= r_V_7_fu_1470_p2;
r_V_reg_5252 <= r_V_fu_1260_p2;
r_V_s_reg_5271 <= r_V_s_fu_1296_p2;
tmp_176_4_reg_5337 <= tmp_176_4_fu_1410_p2;
tmp_176_5_reg_5357 <= tmp_176_5_fu_1432_p2;
tmp_176_6_reg_5377 <= tmp_176_6_fu_1454_p2;
tmp_176_7_reg_5397 <= tmp_176_7_fu_1476_p2;
tmp_177_4_reg_5343 <= tmp_177_4_fu_1416_p2;
tmp_177_5_reg_5363 <= tmp_177_5_fu_1438_p2;
tmp_177_6_reg_5383 <= tmp_177_6_fu_1460_p2;
tmp_177_7_reg_5403 <= tmp_177_7_fu_1482_p2;
tmp_20_reg_5266 <= tmp_20_fu_1286_p2;
tmp_24_reg_5285 <= tmp_24_fu_1322_p2;
tmp_27_reg_5304 <= tmp_27_fu_1358_p2;
tmp_29_reg_5323 <= tmp_29_fu_1394_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it9) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it9)))) then
not_or_cond11_reg_5919 <= not_or_cond11_fu_2817_p2;
p_iscorner_0_i_13_reg_5909 <= p_iscorner_0_i_13_fu_2787_p2;
tmp11_reg_5934 <= tmp11_fu_2833_p2;
tmp15_reg_5939 <= tmp15_fu_2837_p2;
tmp2_reg_5929 <= tmp2_fu_2828_p2;
tmp_185_15_reg_5914 <= tmp_185_15_fu_2805_p2;
tmp_185_16_reg_5924 <= tmp_185_16_fu_2822_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = exitcond_fu_846_p2))) then
or_cond1_reg_5197 <= or_cond1_fu_883_p2;
or_cond4_reg_5201 <= or_cond4_fu_904_p2;
or_cond_reg_5156 <= or_cond_fu_862_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it6) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it6)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond5_reg_5537_pp0_it6))) then
phitmp8_reg_5842 <= phitmp8_fu_2600_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it10) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it10)))) then
tmp14_reg_5944 <= tmp14_fu_2861_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) then
tmp19_reg_6739 <= tmp19_fu_4701_p2;
tmp20_reg_6744 <= tmp20_fu_4712_p2;
tmp23_reg_6749 <= tmp23_fu_4723_p2;
tmp25_reg_6754 <= tmp25_fu_4735_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it31) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it31)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it31)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31)))) then
tmp_100_v_reg_6714 <= tmp_100_v_fu_4593_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_180))) then
tmp_15_reg_5103 <= tmp_15_fu_786_p1;
tmp_5_reg_5113 <= tmp_5_fu_796_p2;
tmp_reg_5098 <= tmp_fu_782_p1;
tmp_s_reg_5108 <= tmp_s_fu_790_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)))) then
tmp_211_1_reg_6545 <= grp_image_filter_reg_int_s_fu_762_ap_return;
tmp_226_1_reg_6552 <= grp_image_filter_reg_int_s_fu_767_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)))) then
tmp_211_2_reg_6619 <= grp_image_filter_reg_int_s_fu_772_ap_return;
tmp_226_2_reg_6626 <= grp_image_filter_reg_int_s_fu_777_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)))) then
tmp_211_s_reg_6471 <= grp_image_filter_reg_int_s_fu_752_ap_return;
tmp_226_s_reg_6478 <= grp_image_filter_reg_int_s_fu_757_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))) then
tmp_43_reg_6043 <= tmp_43_fu_3262_p2;
tmp_67_reg_6048 <= tmp_67_fu_3268_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it1)))) then
win_val_0_V_2_3_fu_168 <= win_val_0_V_2_1_reg_5205;
win_val_1_V_1_3_fu_188 <= win_val_1_V_1_fu_192;
win_val_1_V_1_fu_192 <= win_val_1_V_2_fu_196;
win_val_1_V_2_fu_196 <= win_val_1_V_3_fu_200;
win_val_1_V_3_fu_200 <= win_val_1_V_4_3_reg_5210;
win_val_2_V_0_3_fu_212 <= win_val_2_V_0_fu_216;
win_val_2_V_0_fu_216 <= win_val_2_V_1_fu_220;
win_val_2_V_1_fu_220 <= win_val_2_V_2_fu_224;
win_val_2_V_2_fu_224 <= win_val_2_V_3_fu_228;
win_val_2_V_3_fu_228 <= win_val_2_V_4_fu_232;
win_val_2_V_4_fu_232 <= win_val_2_V_5_3_reg_5215;
win_val_3_V_0_3_fu_240 <= win_val_3_V_0_fu_244;
win_val_3_V_0_fu_244 <= win_val_3_V_1_fu_248;
win_val_3_V_1_fu_248 <= win_val_3_V_2_3_reg_5220;
win_val_4_V_0_3_fu_268 <= win_val_4_V_0_fu_272;
win_val_4_V_0_fu_272 <= win_val_4_V_1_fu_276;
win_val_4_V_1_fu_276 <= win_val_4_V_2_fu_280;
win_val_4_V_2_fu_280 <= win_val_4_V_3_fu_284;
win_val_4_V_3_fu_284 <= win_val_4_V_4_fu_288;
win_val_4_V_4_fu_288 <= win_val_4_V_5_3_reg_5225;
win_val_5_V_1_3_fu_296 <= win_val_5_V_1_fu_300;
win_val_5_V_1_fu_300 <= win_val_5_V_2_fu_304;
win_val_5_V_2_fu_304 <= win_val_5_V_3_fu_308;
win_val_5_V_3_fu_308 <= win_val_5_V_4_3_reg_5230;
win_val_6_V_2_3_fu_320 <= win_val_6_V_2_fu_324;
win_val_6_V_2_fu_324 <= win_val_6_V_2_2_reg_5235;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
win_val_0_V_2_fu_172 <= win_val_0_V_3_fu_176;
win_val_0_V_3_fu_176 <= win_val_0_V_4_fu_180;
win_val_0_V_4_fu_180 <= win_val_0_V_5_fu_184;
win_val_0_V_5_fu_184 <= k_buf_val_0_V_q0;
win_val_1_V_4_fu_204 <= win_val_1_V_5_fu_208;
win_val_1_V_5_fu_208 <= k_buf_val_1_V_q0;
win_val_2_V_5_fu_236 <= k_buf_val_2_V_q0;
win_val_3_V_2_fu_252 <= win_val_3_V_3_fu_256;
win_val_3_V_3_fu_256 <= win_val_3_V_4_fu_260;
win_val_3_V_4_fu_260 <= win_val_3_V_5_fu_264;
win_val_3_V_5_fu_264 <= k_buf_val_3_V_q0;
win_val_4_V_5_fu_292 <= k_buf_val_4_V_q0;
win_val_5_V_4_fu_312 <= win_val_5_V_5_fu_316;
win_val_5_V_5_fu_316 <= k_buf_val_5_V_q0;
win_val_6_V_3_fu_156 <= win_val_6_V_4_fu_144;
win_val_6_V_4_fu_144 <= win_val_6_V_5_fu_132;
win_val_6_V_5_fu_132 <= p_src_data_stream_V_dout;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
win_val_6_V_2_2_reg_5235 <= win_val_6_V_3_fu_156;
end if;
end if;
end process;
lhs_V_reg_5240(8) <= '0';
count_1_i_0_op_op87_op_reg_5590(3 downto 1) <= "100";
phitmp43_op_op_cast_cast_cast_reg_5595(3 downto 1) <= "011";
core_win_val_0_V_0_fu_136(15 downto 8) <= "00000000";
core_win_val_0_V_1_fu_140(15 downto 8) <= "00000000";
core_win_val_1_V_0_fu_148(15 downto 8) <= "00000000";
core_win_val_1_V_1_fu_152(15 downto 8) <= "00000000";
core_win_val_2_V_0_fu_160(15 downto 8) <= "00000000";
core_win_val_2_V_1_fu_164(15 downto 8) <= "00000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_sig_bdd_180, exitcond1_fu_802_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_180)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33)))) then
ap_NS_fsm <= ap_ST_st39_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_st39_fsm_3 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
a0_2_cast_fu_3908_p1 <= std_logic_vector(resize(unsigned(a0_2_reg_6285),32));
a0_2_fu_3841_p3 <=
a0_tmp_232_1_reg_6263 when (tmp_217_2_fu_3835_p2(0) = '1') else
tmp_58_fu_3831_p1;
a0_2_tmp_232_2_cast_fu_3951_p1 <= std_logic_vector(resize(unsigned(a0_2_tmp_232_2_reg_6337),32));
a0_2_tmp_232_2_fu_3916_p3 <=
a0_2_reg_6285 when (tmp_233_2_fu_3911_p2(0) = '1') else
tmp_59_reg_6296;
a0_3_cast_fu_4036_p1 <= std_logic_vector(resize(unsigned(a0_3_reg_6359),32));
a0_3_fu_3969_p3 <=
a0_2_tmp_232_2_reg_6337 when (tmp_217_3_fu_3963_p2(0) = '1') else
tmp_60_fu_3959_p1;
a0_3_tmp_232_3_cast_fu_4079_p1 <= std_logic_vector(resize(unsigned(a0_3_tmp_232_3_reg_6411),32));
a0_3_tmp_232_3_fu_4044_p3 <=
a0_3_reg_6359 when (tmp_233_3_fu_4039_p2(0) = '1') else
tmp_61_reg_6370;
a0_4_cast_fu_4164_p1 <= std_logic_vector(resize(unsigned(a0_4_reg_6433),32));
a0_4_fu_4097_p3 <=
a0_3_tmp_232_3_reg_6411 when (tmp_217_4_fu_4091_p2(0) = '1') else
tmp_62_fu_4087_p1;
a0_4_tmp_232_4_cast_fu_4207_p1 <= std_logic_vector(resize(unsigned(a0_4_tmp_232_4_reg_6485),32));
a0_4_tmp_232_4_fu_4172_p3 <=
a0_4_reg_6433 when (tmp_233_4_fu_4167_p2(0) = '1') else
tmp_63_reg_6444;
a0_5_cast_fu_4292_p1 <= std_logic_vector(resize(unsigned(a0_5_reg_6507),32));
a0_5_fu_4225_p3 <=
a0_4_tmp_232_4_reg_6485 when (tmp_217_5_fu_4219_p2(0) = '1') else
tmp_64_fu_4215_p1;
a0_5_tmp_232_5_cast_fu_4335_p1 <= std_logic_vector(resize(unsigned(a0_5_tmp_232_5_reg_6559),32));
a0_5_tmp_232_5_fu_4300_p3 <=
a0_5_reg_6507 when (tmp_233_5_fu_4295_p2(0) = '1') else
tmp_65_reg_6518;
a0_6_cast_fu_4420_p1 <= std_logic_vector(resize(unsigned(a0_6_reg_6581),32));
a0_6_fu_4353_p3 <=
a0_5_tmp_232_5_reg_6559 when (tmp_217_6_fu_4347_p2(0) = '1') else
tmp_66_fu_4343_p1;
a0_6_tmp_232_6_cast_fu_4463_p1 <= std_logic_vector(resize(unsigned(a0_6_tmp_232_6_reg_6633),32));
a0_6_tmp_232_6_fu_4428_p3 <=
a0_6_reg_6581 when (tmp_233_6_fu_4423_p2(0) = '1') else
tmp_75_reg_6592;
a0_7_cast_fu_4549_p1 <= std_logic_vector(resize(unsigned(a0_7_reg_6655),32));
a0_7_fu_4481_p3 <=
a0_6_tmp_232_6_reg_6633 when (tmp_217_7_fu_4475_p2(0) = '1') else
tmp_77_fu_4471_p1;
a0_7_tmp_232_7_fu_4557_p3 <=
a0_7_reg_6655 when (tmp_233_7_fu_4552_p2(0) = '1') else
tmp_78_reg_6666;
a0_cast_fu_3780_p1 <= std_logic_vector(resize(unsigned(a0_s_reg_6211),32));
a0_s_fu_3713_p3 <=
p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 when (tmp_217_1_fu_3707_p2(0) = '1') else
tmp_56_fu_3703_p1;
a0_tmp_232_1_cast_fu_3823_p1 <= std_logic_vector(resize(unsigned(a0_tmp_232_1_reg_6263),32));
a0_tmp_232_1_fu_3788_p3 <=
a0_s_reg_6211 when (tmp_233_1_fu_3783_p2(0) = '1') else
tmp_57_reg_6222;
a_0_flag_d_assign_load_5_fu_3419_p3 <=
flag_d_min8_1_reg_6029 when (tmp_43_reg_6043(0) = '1') else
flag_d_assign_reg_6011;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond1_fu_802_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond1_fu_802_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_core_1_reg_527pp0_it0 <= "XXXXXXXX";
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(p_mask_data_stream_V_full_n, ap_reg_ppstg_or_cond4_reg_5201_pp0_it34)
begin
ap_sig_bdd_136 <= ((p_mask_data_stream_V_full_n = ap_const_logic_0) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond4_reg_5201_pp0_it34));
end process;
-- ap_sig_bdd_1776 assign process. --
ap_sig_bdd_1776_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_1776 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_180 assign process. --
ap_sig_bdd_180_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_180 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_196 assign process. --
ap_sig_bdd_196_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_196 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_2075 assign process. --
ap_sig_bdd_2075_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2075 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_2108 assign process. --
ap_sig_bdd_2108_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it12, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_2108 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it12) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_2152 assign process. --
ap_sig_bdd_2152_assign_proc : process(exitcond_fu_846_p2, or_cond1_fu_883_p2)
begin
ap_sig_bdd_2152 <= ((ap_const_lv1_0 = exitcond_fu_846_p2) and (ap_const_lv1_0 = or_cond1_fu_883_p2));
end process;
-- ap_sig_bdd_2156 assign process. --
ap_sig_bdd_2156_assign_proc : process(ap_reg_ppstg_exitcond_reg_5147_pp0_it32, ap_reg_ppstg_or_cond1_reg_5197_pp0_it32, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)
begin
ap_sig_bdd_2156 <= ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it32)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)));
end process;
-- ap_sig_bdd_2159 assign process. --
ap_sig_bdd_2159_assign_proc : process(ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, iscorner_2_i_s_fu_2870_p2)
begin
ap_sig_bdd_2159 <= ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and (ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2));
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_250 assign process. --
ap_sig_bdd_250_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_250 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_48 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_61 assign process. --
ap_sig_bdd_61_assign_proc : process(p_src_data_stream_V_empty_n, exitcond_reg_5147, or_cond_reg_5156)
begin
ap_sig_bdd_61 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_48)
begin
if (ap_sig_bdd_48) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_196)
begin
if (ap_sig_bdd_196) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_3 assign process. --
ap_sig_cseq_ST_st39_fsm_3_assign_proc : process(ap_sig_bdd_2075)
begin
if (ap_sig_bdd_2075) then
ap_sig_cseq_ST_st39_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_3 <= ap_const_logic_0;
end if;
end process;
b0_2_cast_fu_3928_p1 <= std_logic_vector(resize(signed(b0_2_reg_6301),32));
b0_2_fu_3882_p3 <=
b0_tmp_239_1_reg_6274 when (tmp_228_2_fu_3876_p2(0) = '1') else
tmp_84_fu_3872_p1;
b0_2_tmp_239_2_cast_fu_3992_p1 <= std_logic_vector(resize(signed(b0_2_tmp_239_2_reg_6348),32));
b0_2_tmp_239_2_fu_3936_p3 <=
b0_2_reg_6301 when (tmp_240_2_fu_3931_p2(0) = '1') else
tmp_85_reg_6312;
b0_3_cast_fu_4056_p1 <= std_logic_vector(resize(signed(b0_3_reg_6375),32));
b0_3_fu_4010_p3 <=
b0_2_tmp_239_2_reg_6348 when (tmp_228_3_fu_4004_p2(0) = '1') else
tmp_86_fu_4000_p1;
b0_3_tmp_239_3_cast_fu_4120_p1 <= std_logic_vector(resize(signed(b0_3_tmp_239_3_reg_6422),32));
b0_3_tmp_239_3_fu_4064_p3 <=
b0_3_reg_6375 when (tmp_240_3_fu_4059_p2(0) = '1') else
tmp_87_reg_6386;
b0_4_cast_fu_4184_p1 <= std_logic_vector(resize(signed(b0_4_reg_6449),32));
b0_4_fu_4138_p3 <=
b0_3_tmp_239_3_reg_6422 when (tmp_228_4_fu_4132_p2(0) = '1') else
tmp_88_fu_4128_p1;
b0_4_tmp_239_4_cast_fu_4248_p1 <= std_logic_vector(resize(signed(b0_4_tmp_239_4_reg_6496),32));
b0_4_tmp_239_4_fu_4192_p3 <=
b0_4_reg_6449 when (tmp_240_4_fu_4187_p2(0) = '1') else
tmp_89_reg_6460;
b0_5_cast_fu_4312_p1 <= std_logic_vector(resize(signed(b0_5_reg_6523),32));
b0_5_fu_4266_p3 <=
b0_4_tmp_239_4_reg_6496 when (tmp_228_5_fu_4260_p2(0) = '1') else
tmp_90_fu_4256_p1;
b0_5_tmp_239_5_cast_fu_4376_p1 <= std_logic_vector(resize(signed(b0_5_tmp_239_5_reg_6570),32));
b0_5_tmp_239_5_fu_4320_p3 <=
b0_5_reg_6523 when (tmp_240_5_fu_4315_p2(0) = '1') else
tmp_91_reg_6534;
b0_6_cast_fu_4440_p1 <= std_logic_vector(resize(signed(b0_6_reg_6597),32));
b0_6_fu_4394_p3 <=
b0_5_tmp_239_5_reg_6570 when (tmp_228_6_fu_4388_p2(0) = '1') else
tmp_92_fu_4384_p1;
b0_6_tmp_239_6_cast_fu_4504_p1 <= std_logic_vector(resize(signed(b0_6_tmp_239_6_reg_6644),32));
b0_6_tmp_239_6_fu_4448_p3 <=
b0_6_reg_6597 when (tmp_240_6_fu_4443_p2(0) = '1') else
tmp_93_reg_6608;
b0_7_cast_fu_4563_p1 <= std_logic_vector(resize(signed(b0_7_reg_6671),32));
b0_7_fu_4522_p3 <=
b0_6_tmp_239_6_reg_6644 when (tmp_228_7_fu_4516_p2(0) = '1') else
tmp_94_fu_4512_p1;
b0_cast_50_fu_3800_p1 <= std_logic_vector(resize(signed(b0_s_reg_6227),32));
b0_cast_fu_3672_p1 <= std_logic_vector(resize(signed(b0_reg_6093),32));
b0_fu_3473_p3 <=
ap_const_lv9_1EC when (tmp_69_fu_3467_p2(0) = '1') else
tmp_80_fu_3463_p1;
b0_s_fu_3754_p3 <=
b0_tmp_s_reg_6200 when (tmp_228_1_fu_3748_p2(0) = '1') else
tmp_82_fu_3744_p1;
b0_tmp_239_1_cast_fu_3864_p1 <= std_logic_vector(resize(signed(b0_tmp_239_1_reg_6274),32));
b0_tmp_239_1_fu_3808_p3 <=
b0_s_reg_6227 when (tmp_240_1_fu_3803_p2(0) = '1') else
tmp_83_reg_6238;
b0_tmp_239_cast_fu_3736_p1 <= std_logic_vector(resize(signed(b0_tmp_s_reg_6200),32));
b0_tmp_s_fu_3680_p3 <=
b0_reg_6093 when (tmp_72_fu_3675_p2(0) = '1') else
tmp_81_reg_6104;
core_buf_val_0_V_address0 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_0_V_address1 <= core_buf_val_0_V_addr_reg_6702;
-- core_buf_val_0_V_ce0 assign process. --
core_buf_val_0_V_ce0_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it32, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_0_V_ce0 <= ap_const_logic_1;
else
core_buf_val_0_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- core_buf_val_0_V_ce1 assign process. --
core_buf_val_0_V_ce1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_0_V_ce1 <= ap_const_logic_1;
else
core_buf_val_0_V_ce1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_0_V_d1 <= core_buf_val_1_V_q0;
-- core_buf_val_0_V_we1 assign process. --
core_buf_val_0_V_we1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it32)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32)))) then
core_buf_val_0_V_we1 <= ap_const_logic_1;
else
core_buf_val_0_V_we1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_1_V_address0 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_1_V_address1 <= ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33;
-- core_buf_val_1_V_ce0 assign process. --
core_buf_val_1_V_ce0_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it32, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_1_V_ce0 <= ap_const_logic_1;
else
core_buf_val_1_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- core_buf_val_1_V_ce1 assign process. --
core_buf_val_1_V_ce1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_1_V_ce1 <= ap_const_logic_1;
else
core_buf_val_1_V_ce1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_1_V_d1 <= core_win_val_2_V_2_fu_4635_p3;
-- core_buf_val_1_V_we1 assign process. --
core_buf_val_1_V_we1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it33)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33)))) then
core_buf_val_1_V_we1 <= ap_const_logic_1;
else
core_buf_val_1_V_we1 <= ap_const_logic_0;
end if;
end process;
core_win_val_0_V_2_fu_4620_p1 <= std_logic_vector(resize(unsigned(core_buf_val_0_V_load_reg_6724),16));
core_win_val_1_V_2_fu_4623_p1 <= std_logic_vector(resize(unsigned(core_buf_val_1_V_load_reg_6729),16));
core_win_val_2_V_1_2_fu_4643_p1 <= std_logic_vector(resize(unsigned(core_win_val_2_V_2_fu_4635_p3),16));
core_win_val_2_V_2_fu_4635_p3 <=
ap_reg_phiprechg_core_1_reg_527pp0_it34 when (ap_reg_ppstg_or_cond_reg_5156_pp0_it33(0) = '1') else
ap_const_lv8_0;
count_1_fu_2407_p2 <= std_logic_vector(unsigned(count_1_i_1_fu_2397_p3) + unsigned(ap_const_lv4_1));
count_1_i_0_op_op87_op_fu_1848_p3 <=
ap_const_lv4_8 when (or_cond5_fu_1746_p2(0) = '1') else
ap_const_lv4_9;
count_1_i_10_fu_2636_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7(0) = '1') else
phitmp8_reg_5842;
count_1_i_11_fu_2659_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond6_reg_5543_pp0_it7(0) = '1') else
count_1_i_10_fu_2636_p3;
count_1_i_12_fu_2678_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond7_reg_5548_pp0_it7(0) = '1') else
phitmp9_fu_2672_p2;
count_1_i_13_fu_2731_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond8_reg_5553_pp0_it8(0) = '1') else
count_1_i_12_reg_5872;
count_1_i_14_fu_2755_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond9_reg_5559_pp0_it8(0) = '1') else
phitmp10_fu_2749_p2;
count_1_i_15_fu_2793_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond2_reg_5660_pp0_it9(0) = '1') else
count_1_i_14_reg_5898;
count_1_i_1_fu_2397_p3 <=
ap_const_lv4_1 when (or_cond14_reg_5759(0) = '1') else
count_1_i_s_reg_5753;
count_1_i_2_fu_2441_p3 <=
ap_const_lv4_2 when (or_cond15_fu_2403_p2(0) = '1') else
phitmp6_fu_2419_p2;
count_1_i_2_op_op_fu_1998_p3 <=
phitmp43_op_op_cast_cast_cast_reg_5595 when (tmp_40_reg_5600(0) = '1') else
count_1_i_0_op_op87_op_reg_5590;
count_1_i_3_cast_fu_2531_p1 <= std_logic_vector(resize(unsigned(count_1_i_3_reg_5806),5));
count_1_i_3_fu_2476_p3 <=
ap_const_lv4_1 when (or_cond16_fu_2458_p2(0) = '1') else
count_1_i_2_fu_2441_p3;
count_1_i_4_fu_2563_p3 <=
ap_const_lv5_2 when (or_cond17_reg_5811(0) = '1') else
phitmp7_fu_2546_p2;
count_1_i_4_op_fu_2014_p3 <=
phitmp42_op_cast_cast_cast_fu_2003_p3 when (tmp_41_fu_2010_p2(0) = '1') else
count_1_i_2_op_op_fu_1998_p3;
count_1_i_5_fu_2587_p3 <=
ap_const_lv5_1 when (or_cond18_reg_5821(0) = '1') else
count_1_i_4_fu_2563_p3;
count_1_i_6_fu_2036_p3 <=
phitmp3_cast_cast_cast_fu_2022_p3 when (tmp_42_fu_2030_p2(0) = '1') else
count_1_i_4_op_fu_2014_p3;
count_1_i_7_fu_2061_p3 <=
ap_const_lv4_1 when (or_cond10_fu_2055_p2(0) = '1') else
count_1_i_6_fu_2036_p3;
count_1_i_8_fu_2224_p3 <=
ap_const_lv4_2 when (or_cond11_reg_5681(0) = '1') else
phitmp4_fu_2208_p2;
count_1_i_9_fu_2257_p3 <=
ap_const_lv4_1 when (or_cond12_fu_2231_p2(0) = '1') else
count_1_i_8_fu_2224_p3;
count_1_i_s_fu_2292_p3 <=
ap_const_lv4_2 when (or_cond13_fu_2274_p2(0) = '1') else
phitmp5_fu_2280_p2;
count_2_fu_2534_p2 <= std_logic_vector(unsigned(count_1_i_3_cast_fu_2531_p1) + unsigned(ap_const_lv5_1));
count_3_fu_2594_p2 <= std_logic_vector(unsigned(count_1_i_5_fu_2587_p3) + unsigned(ap_const_lv5_1));
count_4_fu_2666_p2 <= std_logic_vector(unsigned(count_1_i_11_fu_2659_p3) + unsigned(ap_const_lv5_1));
count_5_fu_2737_p2 <= std_logic_vector(unsigned(count_1_i_13_fu_2731_p3) + unsigned(ap_const_lv5_1));
count_6_fu_2799_p2 <= std_logic_vector(unsigned(count_1_i_15_fu_2793_p3) + unsigned(ap_const_lv5_1));
count_8_fu_2197_p2 <= std_logic_vector(unsigned(count_1_i_7_reg_5675) + unsigned(ap_const_lv4_1));
count_s_fu_2359_p2 <= std_logic_vector(unsigned(count_1_i_9_reg_5743) + unsigned(ap_const_lv4_1));
exitcond1_fu_802_p2 <= "1" when (p_s_reg_504 = tmp_5_reg_5113) else "0";
exitcond_fu_846_p2 <= "1" when (p_2_phi_fu_519_p4 = tmp_s_reg_5108) else "0";
flag_d_assign_10_fu_3692_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17),32));
flag_d_assign_11_fu_4289_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26),32));
flag_d_assign_12_fu_3820_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19),32));
flag_d_assign_13_fu_4417_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28),32));
flag_d_assign_14_fu_3948_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21),32));
flag_d_assign_1_fu_4076_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it23),32));
flag_d_assign_2_fu_3497_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it16),32));
flag_d_assign_3_fu_4204_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it25),32));
flag_d_assign_4_fu_3777_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it18),32));
flag_d_assign_5_fu_4332_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it27),32));
flag_d_assign_6_fu_3905_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it20),32));
flag_d_assign_7_fu_4460_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it29),32));
flag_d_assign_8_fu_4033_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it22),32));
flag_d_assign_9_fu_3274_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15),32));
flag_d_assign_fu_3143_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14),32));
flag_d_assign_s_fu_4161_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24),32));
flag_val_V_assign_load_1_10_fu_2131_p3 <=
phitmp1_5_fu_2120_p3 when (tmp_34_fu_2127_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_11_fu_1698_p3 <=
phitmp_6_fu_1687_p3 when (tmp_35_fu_1694_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_12_fu_2163_p3 <=
phitmp1_6_fu_2149_p3 when (tmp_36_fu_2157_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_13_fu_1726_p3 <=
phitmp_7_fu_1715_p3 when (tmp_37_fu_1722_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_14_fu_2351_p3 <=
phitmp1_7_fu_2340_p3 when (tmp_38_fu_2347_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_1_fu_1562_p3 <=
phitmp_1_reg_5280 when (tmp_24_reg_5285(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_2_fu_1589_p3 <=
phitmp_2_reg_5299 when (tmp_27_reg_5304(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_3_fu_1930_p3 <=
phitmp1_2_fu_1919_p3 when (tmp_28_fu_1926_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_4_fu_1616_p3 <=
phitmp_3_reg_5318 when (tmp_29_reg_5323(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_5_fu_1962_p3 <=
phitmp1_3_fu_1948_p3 when (tmp_30_fu_1956_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_6_fu_1642_p3 <=
phitmp_4_fu_1631_p3 when (tmp_31_fu_1638_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_7_fu_2112_p3 <=
phitmp1_4_fu_2101_p3 when (tmp_32_fu_2108_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_8_fu_1670_p3 <=
phitmp_5_fu_1659_p3 when (tmp_33_fu_1666_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_9_fu_1911_p3 <=
phitmp1_1_fu_1900_p3 when (tmp_25_fu_1907_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_s_fu_1521_p3 <=
phitmp1_reg_5261 when (tmp_20_reg_5266(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_2_s_fu_1894_p3 <=
phitmp3_reg_5422 when (tmp_23_reg_5427(0) = '1') else
ap_const_lv2_0;
-- grp_image_filter_reg_int_s_fu_542_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_542_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_542_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_542_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_542_in_r <= std_logic_vector(resize(signed(tmp_193_1_fu_2879_p3),32));
-- grp_image_filter_reg_int_s_fu_547_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_547_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_547_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_547_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_547_in_r <= std_logic_vector(resize(signed(tmp_203_1_fu_2894_p3),32));
-- grp_image_filter_reg_int_s_fu_552_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_552_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_552_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_552_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_552_in_r <= std_logic_vector(resize(signed(tmp_193_3_fu_2909_p3),32));
-- grp_image_filter_reg_int_s_fu_557_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_557_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_557_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_557_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_557_in_r <= std_logic_vector(resize(signed(tmp_203_3_fu_2924_p3),32));
-- grp_image_filter_reg_int_s_fu_562_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_562_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_562_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_562_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_562_in_r <= std_logic_vector(resize(signed(tmp_193_5_fu_2939_p3),32));
-- grp_image_filter_reg_int_s_fu_567_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_567_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_567_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_567_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_567_in_r <= std_logic_vector(resize(signed(tmp_203_5_fu_2954_p3),32));
-- grp_image_filter_reg_int_s_fu_572_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_572_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_572_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_572_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_572_in_r <= std_logic_vector(resize(signed(tmp_193_7_fu_2969_p3),32));
-- grp_image_filter_reg_int_s_fu_577_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_577_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_577_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_577_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_577_in_r <= std_logic_vector(resize(signed(tmp_203_7_fu_2984_p3),32));
-- grp_image_filter_reg_int_s_fu_582_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_582_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_582_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_582_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_582_in_r <=
grp_image_filter_reg_int_s_fu_542_ap_return when (tmp_192_1_fu_2995_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_552_ap_return;
-- grp_image_filter_reg_int_s_fu_587_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_587_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_587_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_587_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_587_in_r <=
grp_image_filter_reg_int_s_fu_547_ap_return when (tmp_202_1_fu_3010_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_557_ap_return;
-- grp_image_filter_reg_int_s_fu_592_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_592_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_592_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_592_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_592_in_r <=
grp_image_filter_reg_int_s_fu_562_ap_return when (tmp_192_5_fu_3053_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_572_ap_return;
-- grp_image_filter_reg_int_s_fu_597_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_597_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_597_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_597_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_597_in_r <=
grp_image_filter_reg_int_s_fu_567_ap_return when (tmp_202_5_fu_3068_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_577_ap_return;
-- grp_image_filter_reg_int_s_fu_602_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_602_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_602_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_602_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_602_in_r <= std_logic_vector(resize(signed(tmp_193_9_fu_3087_p3),32));
-- grp_image_filter_reg_int_s_fu_607_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_607_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_607_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_607_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_607_in_r <= std_logic_vector(resize(signed(tmp_203_9_fu_3102_p3),32));
-- grp_image_filter_reg_int_s_fu_612_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_612_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_612_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_612_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_612_in_r <=
grp_image_filter_reg_int_s_fu_582_ap_return when (tmp_199_1_fu_3113_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_592_ap_return;
-- grp_image_filter_reg_int_s_fu_617_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_617_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_617_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_617_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_617_in_r <=
grp_image_filter_reg_int_s_fu_587_ap_return when (tmp_212_1_fu_3128_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_597_ap_return;
-- grp_image_filter_reg_int_s_fu_622_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_622_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_622_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_622_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_622_in_r <= std_logic_vector(resize(signed(tmp_193_s_fu_3150_p3),32));
-- grp_image_filter_reg_int_s_fu_627_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_627_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_627_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_627_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_627_in_r <= std_logic_vector(resize(signed(tmp_203_s_fu_3165_p3),32));
-- grp_image_filter_reg_int_s_fu_632_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_632_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_632_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_632_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_632_in_r <= std_logic_vector(resize(signed(tmp_193_2_fu_3180_p3),32));
-- grp_image_filter_reg_int_s_fu_637_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_637_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_637_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_637_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_637_in_r <= std_logic_vector(resize(signed(tmp_203_2_fu_3195_p3),32));
-- grp_image_filter_reg_int_s_fu_642_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_642_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_642_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_642_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_642_in_r <= std_logic_vector(resize(signed(tmp_193_4_fu_3210_p3),32));
-- grp_image_filter_reg_int_s_fu_647_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_647_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_647_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_647_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_647_in_r <= std_logic_vector(resize(signed(tmp_203_4_fu_3225_p3),32));
-- grp_image_filter_reg_int_s_fu_652_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_652_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_652_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_652_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_652_in_r <= ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14;
-- grp_image_filter_reg_int_s_fu_657_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_657_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_657_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_657_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_657_in_r <= ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14;
-- grp_image_filter_reg_int_s_fu_662_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_662_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_662_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_662_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_662_in_r <=
ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 when (tmp_192_7_fu_3236_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_602_ap_return;
-- grp_image_filter_reg_int_s_fu_667_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_667_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_667_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_667_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_667_in_r <=
ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 when (tmp_202_7_fu_3249_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_607_ap_return;
-- grp_image_filter_reg_int_s_fu_672_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_672_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_672_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_672_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_672_in_r <=
flag_d_min2_9_reg_6017 when (tmp_192_9_fu_3277_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_622_ap_return;
-- grp_image_filter_reg_int_s_fu_677_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_677_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_677_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_677_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_677_in_r <=
flag_d_max2_9_reg_6023 when (tmp_202_9_fu_3290_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_627_ap_return;
-- grp_image_filter_reg_int_s_fu_682_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_682_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_682_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_682_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_682_in_r <=
grp_image_filter_reg_int_s_fu_622_ap_return when (tmp_192_s_fu_3303_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_632_ap_return;
-- grp_image_filter_reg_int_s_fu_687_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_687_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_687_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_687_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_687_in_r <=
grp_image_filter_reg_int_s_fu_627_ap_return when (tmp_202_s_fu_3318_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_637_ap_return;
-- grp_image_filter_reg_int_s_fu_692_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_692_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_692_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_692_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_692_in_r <=
grp_image_filter_reg_int_s_fu_632_ap_return when (tmp_192_2_fu_3333_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_642_ap_return;
-- grp_image_filter_reg_int_s_fu_697_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_697_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_697_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_697_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_697_in_r <=
grp_image_filter_reg_int_s_fu_637_ap_return when (tmp_202_2_fu_3348_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_647_ap_return;
-- grp_image_filter_reg_int_s_fu_702_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_702_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_702_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_702_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_702_in_r <=
grp_image_filter_reg_int_s_fu_642_ap_return when (tmp_192_4_fu_3363_p2(0) = '1') else
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15;
-- grp_image_filter_reg_int_s_fu_707_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_707_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_707_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_707_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_707_in_r <=
grp_image_filter_reg_int_s_fu_647_ap_return when (tmp_202_4_fu_3376_p2(0) = '1') else
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15;
-- grp_image_filter_reg_int_s_fu_712_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_712_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_712_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_712_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_712_in_r <=
grp_image_filter_reg_int_s_fu_652_ap_return when (tmp_199_3_fu_3389_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_662_ap_return;
-- grp_image_filter_reg_int_s_fu_717_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_717_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_717_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_717_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_717_in_r <=
grp_image_filter_reg_int_s_fu_657_ap_return when (tmp_212_3_fu_3404_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_667_ap_return;
-- grp_image_filter_reg_int_s_fu_722_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_722_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it17, ap_reg_ppstg_exitcond_reg_5147_pp0_it18, ap_reg_ppstg_or_cond1_reg_5197_pp0_it17, ap_reg_ppstg_or_cond1_reg_5197_pp0_it18, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))))) then
grp_image_filter_reg_int_s_fu_722_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_722_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_722_in_r <= tmp_210_5_reg_6129;
-- grp_image_filter_reg_int_s_fu_727_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_727_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it17, ap_reg_ppstg_exitcond_reg_5147_pp0_it18, ap_reg_ppstg_or_cond1_reg_5197_pp0_it17, ap_reg_ppstg_or_cond1_reg_5197_pp0_it18, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))))) then
grp_image_filter_reg_int_s_fu_727_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_727_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_727_in_r <= tmp_225_5_reg_6134;
-- grp_image_filter_reg_int_s_fu_732_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_732_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it19, ap_reg_ppstg_exitcond_reg_5147_pp0_it20, ap_reg_ppstg_or_cond1_reg_5197_pp0_it19, ap_reg_ppstg_or_cond1_reg_5197_pp0_it20, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))))) then
grp_image_filter_reg_int_s_fu_732_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_732_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_732_in_r <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19;
-- grp_image_filter_reg_int_s_fu_737_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_737_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it19, ap_reg_ppstg_exitcond_reg_5147_pp0_it20, ap_reg_ppstg_or_cond1_reg_5197_pp0_it19, ap_reg_ppstg_or_cond1_reg_5197_pp0_it20, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))))) then
grp_image_filter_reg_int_s_fu_737_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_737_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_737_in_r <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19;
-- grp_image_filter_reg_int_s_fu_742_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_742_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it21, ap_reg_ppstg_exitcond_reg_5147_pp0_it22, ap_reg_ppstg_or_cond1_reg_5197_pp0_it21, ap_reg_ppstg_or_cond1_reg_5197_pp0_it22, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))))) then
grp_image_filter_reg_int_s_fu_742_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_742_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_742_in_r <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21;
-- grp_image_filter_reg_int_s_fu_747_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_747_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it21, ap_reg_ppstg_exitcond_reg_5147_pp0_it22, ap_reg_ppstg_or_cond1_reg_5197_pp0_it21, ap_reg_ppstg_or_cond1_reg_5197_pp0_it22, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))))) then
grp_image_filter_reg_int_s_fu_747_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_747_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_747_in_r <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21;
-- grp_image_filter_reg_int_s_fu_752_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_752_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it23, ap_reg_ppstg_exitcond_reg_5147_pp0_it24, ap_reg_ppstg_or_cond1_reg_5197_pp0_it23, ap_reg_ppstg_or_cond1_reg_5197_pp0_it24, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))))) then
grp_image_filter_reg_int_s_fu_752_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_752_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_752_in_r <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23;
-- grp_image_filter_reg_int_s_fu_757_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_757_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it23, ap_reg_ppstg_exitcond_reg_5147_pp0_it24, ap_reg_ppstg_or_cond1_reg_5197_pp0_it23, ap_reg_ppstg_or_cond1_reg_5197_pp0_it24, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))))) then
grp_image_filter_reg_int_s_fu_757_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_757_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_757_in_r <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23;
-- grp_image_filter_reg_int_s_fu_762_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_762_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it25, ap_reg_ppstg_exitcond_reg_5147_pp0_it26, ap_reg_ppstg_or_cond1_reg_5197_pp0_it25, ap_reg_ppstg_or_cond1_reg_5197_pp0_it26, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))))) then
grp_image_filter_reg_int_s_fu_762_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_762_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_762_in_r <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25;
-- grp_image_filter_reg_int_s_fu_767_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_767_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it25, ap_reg_ppstg_exitcond_reg_5147_pp0_it26, ap_reg_ppstg_or_cond1_reg_5197_pp0_it25, ap_reg_ppstg_or_cond1_reg_5197_pp0_it26, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))))) then
grp_image_filter_reg_int_s_fu_767_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_767_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_767_in_r <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25;
-- grp_image_filter_reg_int_s_fu_772_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_772_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it27, ap_reg_ppstg_exitcond_reg_5147_pp0_it28, ap_reg_ppstg_or_cond1_reg_5197_pp0_it27, ap_reg_ppstg_or_cond1_reg_5197_pp0_it28, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))))) then
grp_image_filter_reg_int_s_fu_772_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_772_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_772_in_r <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27;
-- grp_image_filter_reg_int_s_fu_777_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_777_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it27, ap_reg_ppstg_exitcond_reg_5147_pp0_it28, ap_reg_ppstg_or_cond1_reg_5197_pp0_it27, ap_reg_ppstg_or_cond1_reg_5197_pp0_it28, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))))) then
grp_image_filter_reg_int_s_fu_777_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_777_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_777_in_r <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27;
i_V_fu_807_p2 <= std_logic_vector(unsigned(p_s_reg_504) + unsigned(ap_const_lv11_1));
icmp1_fu_898_p2 <= "1" when (tmp_97_fu_888_p4 = ap_const_lv9_0) else "0";
icmp_fu_840_p2 <= "1" when (tmp_16_fu_830_p4 = ap_const_lv9_0) else "0";
iscorner_2_i_7_fu_2191_p2 <= (tmp_185_7_fu_2181_p2 and not_or_cond_fu_2186_p2);
iscorner_2_i_s_fu_2870_p2 <= (tmp10_fu_2866_p2 or ap_reg_ppstg_tmp3_reg_5878_pp0_it11);
j_V_fu_851_p2 <= std_logic_vector(unsigned(p_2_phi_fu_519_p4) + unsigned(ap_const_lv11_1));
k_buf_val_0_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_0_V_address1 <= k_buf_val_0_V_addr_reg_5161;
-- k_buf_val_0_V_ce0 assign process. --
k_buf_val_0_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_0_V_ce0 <= ap_const_logic_1;
else
k_buf_val_0_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_0_V_ce1 assign process. --
k_buf_val_0_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_0_V_ce1 <= ap_const_logic_1;
else
k_buf_val_0_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_0_V_d1 <= k_buf_val_1_V_q0;
-- k_buf_val_0_V_we1 assign process. --
k_buf_val_0_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_0_V_we1 <= ap_const_logic_1;
else
k_buf_val_0_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_1_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_1_V_address1 <= k_buf_val_1_V_addr_reg_5167;
-- k_buf_val_1_V_ce0 assign process. --
k_buf_val_1_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_1_V_ce0 <= ap_const_logic_1;
else
k_buf_val_1_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_1_V_ce1 assign process. --
k_buf_val_1_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_1_V_ce1 <= ap_const_logic_1;
else
k_buf_val_1_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_1_V_d1 <= k_buf_val_2_V_q0;
-- k_buf_val_1_V_we1 assign process. --
k_buf_val_1_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_1_V_we1 <= ap_const_logic_1;
else
k_buf_val_1_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_2_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_2_V_address1 <= k_buf_val_2_V_addr_reg_5173;
-- k_buf_val_2_V_ce0 assign process. --
k_buf_val_2_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_2_V_ce0 <= ap_const_logic_1;
else
k_buf_val_2_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_2_V_ce1 assign process. --
k_buf_val_2_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_2_V_ce1 <= ap_const_logic_1;
else
k_buf_val_2_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_2_V_d1 <= k_buf_val_3_V_q0;
-- k_buf_val_2_V_we1 assign process. --
k_buf_val_2_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_2_V_we1 <= ap_const_logic_1;
else
k_buf_val_2_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_3_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_3_V_address1 <= k_buf_val_3_V_addr_reg_5179;
-- k_buf_val_3_V_ce0 assign process. --
k_buf_val_3_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_3_V_ce0 <= ap_const_logic_1;
else
k_buf_val_3_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_3_V_ce1 assign process. --
k_buf_val_3_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_3_V_ce1 <= ap_const_logic_1;
else
k_buf_val_3_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_3_V_d1 <= k_buf_val_4_V_q0;
-- k_buf_val_3_V_we1 assign process. --
k_buf_val_3_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_3_V_we1 <= ap_const_logic_1;
else
k_buf_val_3_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_4_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_4_V_address1 <= k_buf_val_4_V_addr_reg_5185;
-- k_buf_val_4_V_ce0 assign process. --
k_buf_val_4_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_4_V_ce0 <= ap_const_logic_1;
else
k_buf_val_4_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_4_V_ce1 assign process. --
k_buf_val_4_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_4_V_ce1 <= ap_const_logic_1;
else
k_buf_val_4_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_4_V_d1 <= k_buf_val_5_V_q0;
-- k_buf_val_4_V_we1 assign process. --
k_buf_val_4_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_4_V_we1 <= ap_const_logic_1;
else
k_buf_val_4_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_5_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_5_V_address1 <= k_buf_val_5_V_addr_reg_5191;
-- k_buf_val_5_V_ce0 assign process. --
k_buf_val_5_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_5_V_ce0 <= ap_const_logic_1;
else
k_buf_val_5_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_5_V_ce1 assign process. --
k_buf_val_5_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_5_V_ce1 <= ap_const_logic_1;
else
k_buf_val_5_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_5_V_d1 <= p_src_data_stream_V_dout;
-- k_buf_val_5_V_we1 assign process. --
k_buf_val_5_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_5_V_we1 <= ap_const_logic_1;
else
k_buf_val_5_V_we1 <= ap_const_logic_0;
end if;
end process;
lhs_V_fu_1252_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_2_fu_252),9));
not_or_cond10_demorgan_fu_2093_p2 <= (tmp_183_5_reg_5572 or tmp_181_5_not_reg_5566);
not_or_cond10_fu_2782_p2 <= (ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 xor ap_const_lv1_1);
not_or_cond11_demorgan_fu_2097_p2 <= (tmp_183_6_reg_5584 or tmp_181_6_not_reg_5578);
not_or_cond11_fu_2817_p2 <= (ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 xor ap_const_lv1_1);
not_or_cond12_demorgan_fu_2425_p2 <= (tmp_181_2_reg_5769 or tmp_183_10_reg_5775);
not_or_cond12_fu_2429_p2 <= (not_or_cond12_demorgan_fu_2425_p2 xor ap_const_lv1_1);
not_or_cond13_demorgan_fu_2470_p2 <= (tmp_181_3_fu_2449_p2 or tmp_183_11_fu_2453_p2);
not_or_cond13_fu_2521_p2 <= (not_or_cond13_demorgan_reg_5801 xor ap_const_lv1_1);
not_or_cond14_demorgan_fu_2500_p2 <= (tmp_181_4_fu_2484_p2 or tmp_183_12_fu_2489_p2);
not_or_cond14_fu_2552_p2 <= (not_or_cond14_demorgan_reg_5816 xor ap_const_lv1_1);
not_or_cond15_fu_2576_p2 <= (or_cond18_reg_5821 xor ap_const_lv1_1);
not_or_cond1_fu_2213_p2 <= (or_cond11_reg_5681 xor ap_const_lv1_1);
not_or_cond2_demorgan_fu_2241_p2 <= (tmp_181_9_reg_5687 or tmp_183_9_reg_5693);
not_or_cond2_fu_2245_p2 <= (not_or_cond2_demorgan_fu_2241_p2 xor ap_const_lv1_1);
not_or_cond3_demorgan_fu_2286_p2 <= (tmp_181_s_fu_2265_p2 or tmp_183_s_fu_2269_p2);
not_or_cond3_fu_2370_p2 <= (not_or_cond3_demorgan_reg_5748 xor ap_const_lv1_1);
not_or_cond4_demorgan_fu_2316_p2 <= (tmp_181_1_fu_2300_p2 or tmp_183_8_fu_2305_p2);
not_or_cond4_fu_2386_p2 <= (not_or_cond4_demorgan_reg_5764 xor ap_const_lv1_1);
not_or_cond5_fu_2625_p2 <= (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 xor ap_const_lv1_1);
not_or_cond6_demorgan_fu_1870_p2 <= (tmp_183_1_fu_1758_p2 or tmp_181_1_not_fu_1752_p2);
not_or_cond6_fu_2648_p2 <= (ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 xor ap_const_lv1_1);
not_or_cond7_demorgan_fu_1876_p2 <= (tmp_183_2_fu_1776_p2 or tmp_181_2_not_fu_1770_p2);
not_or_cond7_fu_2704_p2 <= (ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 xor ap_const_lv1_1);
not_or_cond8_demorgan_fu_1882_p2 <= (tmp_183_3_fu_1794_p2 or tmp_181_3_not_fu_1788_p2);
not_or_cond8_fu_2720_p2 <= (ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 xor ap_const_lv1_1);
not_or_cond9_demorgan_fu_1888_p2 <= (tmp_183_4_fu_1812_p2 or tmp_181_4_not_fu_1806_p2);
not_or_cond9_fu_2767_p2 <= (ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 xor ap_const_lv1_1);
not_or_cond_fu_2186_p2 <= (or_cond10_reg_5670 xor ap_const_lv1_1);
or_cond10_fu_2055_p2 <= (tmp_183_7_fu_2049_p2 or tmp_181_7_not_fu_2044_p2);
or_cond11_fu_2075_p2 <= (tmp_181_8_fu_2069_p2 or tmp_183_7_fu_2049_p2);
or_cond12_fu_2231_p2 <= (tmp_181_9_reg_5687 or tmp_183_9_reg_5693);
or_cond13_fu_2274_p2 <= (tmp_181_s_fu_2265_p2 or tmp_183_s_fu_2269_p2);
or_cond14_fu_2310_p2 <= (tmp_181_1_fu_2300_p2 or tmp_183_8_fu_2305_p2);
or_cond15_fu_2403_p2 <= (tmp_181_2_reg_5769 or tmp_183_10_reg_5775);
or_cond16_fu_2458_p2 <= (tmp_181_3_fu_2449_p2 or tmp_183_11_fu_2453_p2);
or_cond17_fu_2494_p2 <= (tmp_181_4_fu_2484_p2 or tmp_183_12_fu_2489_p2);
or_cond18_fu_2511_p2 <= (tmp_181_5_fu_2506_p2 or ap_reg_ppstg_tmp_39_reg_5532_pp0_it5);
or_cond1_fu_883_p2 <= (tmp_8_reg_5132 and tmp_17_fu_877_p2);
or_cond2_fu_1990_p2 <= (tmp_183_5_reg_5572 or tmp_181_5_not_reg_5566);
or_cond3_fu_1994_p2 <= (tmp_183_6_reg_5584 or tmp_181_6_not_reg_5578);
or_cond4_fu_904_p2 <= (icmp_reg_5142 or icmp1_fu_898_p2);
or_cond5_fu_1746_p2 <= (tmp_39_fu_1740_p2 or tmp_181_0_not_fu_1734_p2);
or_cond6_fu_1764_p2 <= (tmp_183_1_fu_1758_p2 or tmp_181_1_not_fu_1752_p2);
or_cond7_fu_1782_p2 <= (tmp_183_2_fu_1776_p2 or tmp_181_2_not_fu_1770_p2);
or_cond8_fu_1800_p2 <= (tmp_183_3_fu_1794_p2 or tmp_181_3_not_fu_1788_p2);
or_cond9_fu_1818_p2 <= (tmp_183_4_fu_1812_p2 or tmp_181_4_not_fu_1806_p2);
or_cond_fu_862_p2 <= (tmp_7_reg_5127 and tmp_11_fu_857_p2);
-- p_2_phi_fu_519_p4 assign process. --
p_2_phi_fu_519_p4_assign_proc : process(p_2_reg_515, ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, ap_reg_ppiten_pp0_it1, j_V_reg_5151)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) then
p_2_phi_fu_519_p4 <= j_V_reg_5151;
else
p_2_phi_fu_519_p4 <= p_2_reg_515;
end if;
end process;
p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 <= std_logic_vector(resize(unsigned(p_a_0_flag_d_assign_load_5_reg_6077),32));
p_a_0_flag_d_assign_load_5_fu_3434_p3 <=
ap_const_lv8_14 when (tmp_45_fu_3428_p2(0) = '1') else
tmp_44_fu_3424_p1;
p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 <= std_logic_vector(resize(unsigned(p_a_0_flag_d_assign_load_5_tmp_s_reg_6189),32));
p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 <=
p_a_0_flag_d_assign_load_5_reg_6077 when (tmp_49_fu_3655_p2(0) = '1') else
tmp_48_reg_6088;
p_iscorner_0_i_10_fu_2709_p2 <= (tmp_185_11_fu_2699_p2 and not_or_cond7_fu_2704_p2);
p_iscorner_0_i_11_fu_2725_p2 <= (tmp_185_12_fu_2715_p2 and not_or_cond8_fu_2720_p2);
p_iscorner_0_i_12_fu_2772_p2 <= (tmp_185_13_reg_5893 and not_or_cond9_fu_2767_p2);
p_iscorner_0_i_13_fu_2787_p2 <= (tmp_185_14_fu_2777_p2 and not_or_cond10_fu_2782_p2);
p_iscorner_0_i_14_fu_2842_p2 <= (tmp_185_15_reg_5914 and not_or_cond11_reg_5919);
p_iscorner_0_i_15_fu_2846_p2 <= (tmp2_reg_5929 and tmp_185_16_reg_5924);
p_iscorner_0_i_1_fu_2391_p2 <= (tmp_185_1_fu_2381_p2 and not_or_cond4_fu_2386_p2);
p_iscorner_0_i_2_fu_2435_p2 <= (tmp_185_2_fu_2413_p2 and not_or_cond12_fu_2429_p2);
p_iscorner_0_i_3_fu_2526_p2 <= (tmp_185_3_reg_5796 and not_or_cond13_fu_2521_p2);
p_iscorner_0_i_4_fu_2557_p2 <= (tmp_185_4_fu_2540_p2 and not_or_cond14_fu_2552_p2);
p_iscorner_0_i_5_fu_2581_p2 <= (tmp_185_5_fu_2570_p2 and not_or_cond15_fu_2576_p2);
p_iscorner_0_i_6_fu_2630_p2 <= (tmp_185_6_fu_2620_p2 and not_or_cond5_fu_2625_p2);
p_iscorner_0_i_7_fu_2653_p2 <= (tmp_185_10_fu_2642_p2 and not_or_cond6_fu_2648_p2);
p_iscorner_0_i_8_fu_2218_p2 <= (tmp_185_8_fu_2202_p2 and not_or_cond1_fu_2213_p2);
p_iscorner_0_i_9_fu_2251_p2 <= (tmp_185_9_fu_2235_p2 and not_or_cond2_fu_2245_p2);
p_iscorner_0_i_s_fu_2375_p2 <= (tmp_185_s_fu_2364_p2 and not_or_cond3_fu_2370_p2);
p_mask_data_stream_V_din <=
ap_const_lv8_FF when (tmp_26_fu_4779_p2(0) = '1') else
ap_const_lv8_0;
-- p_mask_data_stream_V_write assign process. --
p_mask_data_stream_V_write_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_or_cond4_reg_5201_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_lv1_0 = ap_reg_ppstg_or_cond4_reg_5201_pp0_it34) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_mask_data_stream_V_write <= ap_const_logic_1;
else
p_mask_data_stream_V_write <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_V_read assign process. --
p_src_data_stream_V_read_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_src_data_stream_V_read <= ap_const_logic_1;
else
p_src_data_stream_V_read <= ap_const_logic_0;
end if;
end process;
phitmp10_fu_2749_p2 <= std_logic_vector(unsigned(count_1_i_13_fu_2731_p3) + unsigned(ap_const_lv5_2));
phitmp1_1_fu_1900_p3 <=
ap_const_lv2_1 when (tmp_182_1_reg_5441(0) = '1') else
ap_const_lv2_2;
phitmp1_2_fu_1919_p3 <=
ap_const_lv2_1 when (tmp_182_2_reg_5461(0) = '1') else
ap_const_lv2_2;
phitmp1_3_fu_1948_p3 <=
ap_const_lv2_1 when (tmp_182_3_fu_1938_p2(0) = '1') else
ap_const_lv2_2;
phitmp1_4_fu_2101_p3 <=
ap_const_lv2_1 when (tmp_182_4_reg_5638(0) = '1') else
ap_const_lv2_2;
phitmp1_5_fu_2120_p3 <=
ap_const_lv2_1 when (tmp_182_5_reg_5649(0) = '1') else
ap_const_lv2_2;
phitmp1_6_fu_2149_p3 <=
ap_const_lv2_1 when (tmp_182_6_fu_2139_p2(0) = '1') else
ap_const_lv2_2;
phitmp1_7_fu_2340_p3 <=
ap_const_lv2_1 when (tmp_182_7_reg_5722(0) = '1') else
ap_const_lv2_2;
phitmp1_fu_1278_p3 <=
ap_const_lv2_1 when (tmp_18_fu_1266_p2(0) = '1') else
ap_const_lv2_2;
phitmp2_fu_4606_p2 <= std_logic_vector(unsigned(tmp_100_v_reg_6714) + unsigned(ap_const_lv8_FF));
phitmp3_cast_cast_cast_fu_2022_p3 <=
ap_const_lv4_2 when (or_cond3_fu_1994_p2(0) = '1') else
ap_const_lv4_3;
phitmp3_fu_1539_p3 <=
ap_const_lv2_1 when (tmp_21_fu_1527_p2(0) = '1') else
ap_const_lv2_2;
phitmp42_op_cast_cast_cast_fu_2003_p3 <=
ap_const_lv4_4 when (or_cond9_reg_5559(0) = '1') else
ap_const_lv4_5;
phitmp43_op_op_cast_cast_cast_fu_1856_p3 <=
ap_const_lv4_6 when (or_cond7_fu_1782_p2(0) = '1') else
ap_const_lv4_7;
phitmp4_fu_2208_p2 <= std_logic_vector(unsigned(count_1_i_7_reg_5675) + unsigned(ap_const_lv4_2));
phitmp5_fu_2280_p2 <= std_logic_vector(unsigned(count_1_i_9_fu_2257_p3) + unsigned(ap_const_lv4_2));
phitmp6_fu_2419_p2 <= std_logic_vector(unsigned(count_1_i_1_fu_2397_p3) + unsigned(ap_const_lv4_2));
phitmp7_fu_2546_p2 <= std_logic_vector(unsigned(count_1_i_3_cast_fu_2531_p1) + unsigned(ap_const_lv5_2));
phitmp8_fu_2600_p2 <= std_logic_vector(unsigned(count_1_i_5_fu_2587_p3) + unsigned(ap_const_lv5_2));
phitmp9_fu_2672_p2 <= std_logic_vector(unsigned(count_1_i_11_fu_2659_p3) + unsigned(ap_const_lv5_2));
phitmp_1_fu_1314_p3 <=
ap_const_lv2_1 when (tmp_176_1_fu_1302_p2(0) = '1') else
ap_const_lv2_2;
phitmp_2_fu_1350_p3 <=
ap_const_lv2_1 when (tmp_176_2_fu_1338_p2(0) = '1') else
ap_const_lv2_2;
phitmp_3_fu_1386_p3 <=
ap_const_lv2_1 when (tmp_176_3_fu_1374_p2(0) = '1') else
ap_const_lv2_2;
phitmp_4_fu_1631_p3 <=
ap_const_lv2_1 when (tmp_176_4_reg_5337(0) = '1') else
ap_const_lv2_2;
phitmp_5_fu_1659_p3 <=
ap_const_lv2_1 when (tmp_176_5_reg_5357(0) = '1') else
ap_const_lv2_2;
phitmp_6_fu_1687_p3 <=
ap_const_lv2_1 when (tmp_176_6_reg_5377(0) = '1') else
ap_const_lv2_2;
phitmp_7_fu_1715_p3 <=
ap_const_lv2_1 when (tmp_176_7_reg_5397(0) = '1') else
ap_const_lv2_2;
phitmp_fu_2811_p2 <= std_logic_vector(unsigned(count_1_i_15_fu_2793_p3) + unsigned(ap_const_lv5_2));
r_V_1_1_fu_1557_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_1_fu_1553_p1));
r_V_1_2_fu_1584_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_2_fu_1580_p1));
r_V_1_3_fu_1611_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_3_fu_1607_p1));
r_V_1_4_fu_1626_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_4_fu_1622_p1));
r_V_1_5_fu_1654_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_5_fu_1650_p1));
r_V_1_6_fu_1682_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_6_fu_1678_p1));
r_V_1_7_fu_1710_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_7_fu_1706_p1));
r_V_1_fu_1516_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_fu_1512_p1));
r_V_2_fu_1332_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_2_fu_1328_p1));
r_V_3_fu_1368_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_3_fu_1364_p1));
r_V_4_fu_1404_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_4_fu_1400_p1));
r_V_5_fu_1426_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_5_fu_1422_p1));
r_V_6_fu_1448_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_6_fu_1444_p1));
r_V_7_fu_1470_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_7_fu_1466_p1));
r_V_fu_1260_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_fu_1256_p1));
r_V_s_fu_1296_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_s_fu_1292_p1));
rhs_V_1_1_fu_1553_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_2_3_fu_320),9));
rhs_V_1_2_fu_1580_p1 <= std_logic_vector(resize(unsigned(win_val_5_V_1_3_fu_296),9));
rhs_V_1_3_fu_1607_p1 <= std_logic_vector(resize(unsigned(win_val_4_V_0_3_fu_268),9));
rhs_V_1_4_fu_1622_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_0_3_fu_240),9));
rhs_V_1_5_fu_1650_p1 <= std_logic_vector(resize(unsigned(win_val_2_V_0_3_fu_212),9));
rhs_V_1_6_fu_1678_p1 <= std_logic_vector(resize(unsigned(win_val_1_V_1_3_fu_188),9));
rhs_V_1_7_fu_1706_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_2_3_fu_168),9));
rhs_V_1_fu_1512_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_2_fu_324),9));
rhs_V_2_fu_1328_p1 <= std_logic_vector(resize(unsigned(win_val_1_V_4_fu_204),9));
rhs_V_3_fu_1364_p1 <= std_logic_vector(resize(unsigned(win_val_2_V_5_fu_236),9));
rhs_V_4_fu_1400_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_5_fu_264),9));
rhs_V_5_fu_1422_p1 <= std_logic_vector(resize(unsigned(win_val_4_V_5_fu_292),9));
rhs_V_6_fu_1444_p1 <= std_logic_vector(resize(unsigned(win_val_5_V_4_fu_312),9));
rhs_V_7_fu_1466_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_3_fu_156),9));
rhs_V_fu_1256_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_2_fu_172),9));
rhs_V_s_fu_1292_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_3_fu_176),9));
tmp10_fu_2866_p2 <= (tmp14_reg_5944 or ap_reg_ppstg_tmp11_reg_5934_pp0_it11);
tmp11_fu_2833_p2 <= (tmp13_reg_5904 or ap_reg_ppstg_tmp12_reg_5883_pp0_it9);
tmp12_fu_2694_p2 <= (p_iscorner_0_i_5_reg_5832 or p_iscorner_0_i_6_fu_2630_p2);
tmp13_fu_2762_p2 <= (p_iscorner_0_i_7_reg_5862 or p_iscorner_0_i_10_fu_2709_p2);
tmp14_fu_2861_p2 <= (tmp16_fu_2856_p2 or tmp15_reg_5939);
tmp15_fu_2837_p2 <= (p_iscorner_0_i_11_reg_5888 or p_iscorner_0_i_12_fu_2772_p2);
tmp16_fu_2856_p2 <= (tmp17_fu_2850_p2 or p_iscorner_0_i_13_reg_5909);
tmp17_fu_2850_p2 <= (p_iscorner_0_i_14_fu_2842_p2 or p_iscorner_0_i_15_fu_2846_p2);
tmp18_fu_4771_p2 <= (tmp20_reg_6744 and tmp19_reg_6739);
tmp19_fu_4701_p2 <= (tmp_52_fu_4647_p2 and tmp_9_reg_5137);
tmp20_fu_4712_p2 <= (tmp21_fu_4706_p2 and ap_reg_ppstg_tmp_53_reg_6719_pp0_it33);
tmp21_fu_4706_p2 <= (tmp_73_fu_4653_p2 and tmp_242_1_fu_4659_p2);
tmp22_fu_4775_p2 <= (tmp25_reg_6754 and tmp23_reg_6749);
tmp23_fu_4723_p2 <= (tmp24_fu_4717_p2 and tmp_242_2_fu_4665_p2);
tmp24_fu_4717_p2 <= (tmp_74_fu_4671_p2 and tmp_245_1_fu_4677_p2);
tmp25_fu_4735_p2 <= (tmp26_fu_4729_p2 and tmp_245_2_fu_4683_p2);
tmp26_fu_4729_p2 <= (tmp_55_fu_4695_p2 and tmp_54_fu_4689_p2);
tmp2_fu_2828_p2 <= (not_or_cond11_fu_2817_p2 and ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9);
tmp3_fu_2689_p2 <= (tmp7_fu_2685_p2 or tmp4_reg_5847);
tmp4_fu_2606_p2 <= (tmp6_reg_5827 or ap_reg_ppstg_tmp5_reg_5781_pp0_it6);
tmp5_fu_2334_p2 <= (iscorner_2_i_7_fu_2191_p2 or p_iscorner_0_i_8_fu_2218_p2);
tmp6_fu_2516_p2 <= (p_iscorner_0_i_9_reg_5738 or p_iscorner_0_i_s_fu_2375_p2);
tmp7_fu_2685_p2 <= (tmp9_reg_5857 or tmp8_reg_5852);
tmp8_fu_2610_p2 <= (p_iscorner_0_i_1_reg_5786 or p_iscorner_0_i_2_reg_5791);
tmp9_fu_2614_p2 <= (p_iscorner_0_i_3_fu_2526_p2 or p_iscorner_0_i_4_fu_2557_p2);
tmp_100_v_fu_4593_p3 <=
a0_7_tmp_232_7_reg_6691 when (tmp_51_fu_4588_p2(0) = '1') else
tmp_50_fu_4583_p2;
tmp_11_fu_857_p2 <= "1" when (unsigned(p_2_phi_fu_519_p4) < unsigned(tmp_15_reg_5103)) else "0";
tmp_12_fu_867_p1 <= std_logic_vector(resize(unsigned(p_2_phi_fu_519_p4),64));
tmp_14_fu_4577_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_p_2_reg_515_pp0_it31),64));
tmp_15_fu_786_p1 <= p_src_cols_V_read(11 - 1 downto 0);
tmp_16_fu_830_p4 <= p_s_reg_504(10 downto 2);
tmp_176_1_fu_1302_p2 <= "1" when (signed(r_V_s_fu_1296_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_2_fu_1338_p2 <= "1" when (signed(r_V_2_fu_1332_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_3_fu_1374_p2 <= "1" when (signed(r_V_3_fu_1368_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_4_fu_1410_p2 <= "1" when (signed(r_V_4_fu_1404_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_5_fu_1432_p2 <= "1" when (signed(r_V_5_fu_1426_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_6_fu_1454_p2 <= "1" when (signed(r_V_6_fu_1448_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_7_fu_1476_p2 <= "1" when (signed(r_V_7_fu_1470_p2) > signed(ap_const_lv9_14)) else "0";
tmp_177_1_fu_1308_p2 <= "1" when (signed(r_V_s_fu_1296_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_2_fu_1344_p2 <= "1" when (signed(r_V_2_fu_1332_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_3_fu_1380_p2 <= "1" when (signed(r_V_3_fu_1368_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_4_fu_1416_p2 <= "1" when (signed(r_V_4_fu_1404_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_5_fu_1438_p2 <= "1" when (signed(r_V_5_fu_1426_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_6_fu_1460_p2 <= "1" when (signed(r_V_6_fu_1448_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_7_fu_1482_p2 <= "1" when (signed(r_V_7_fu_1470_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_17_fu_877_p2 <= "1" when (unsigned(p_2_phi_fu_519_p4) > unsigned(ap_const_lv11_5)) else "0";
tmp_181_0_not_fu_1734_p2 <= "0" when (flag_val_V_assign_load_1_s_fu_1521_p3 = flag_val_V_assign_load_1_1_fu_1562_p3) else "1";
tmp_181_1_fu_2300_p2 <= "0" when (flag_val_V_assign_load_1_5_reg_5631 = flag_val_V_assign_load_1_7_fu_2112_p3) else "1";
tmp_181_1_not_fu_1752_p2 <= "0" when (flag_val_V_assign_load_1_1_fu_1562_p3 = flag_val_V_assign_load_1_2_fu_1589_p3) else "1";
tmp_181_2_fu_2322_p2 <= "0" when (flag_val_V_assign_load_1_7_fu_2112_p3 = flag_val_V_assign_load_1_10_fu_2131_p3) else "1";
tmp_181_2_not_fu_1770_p2 <= "0" when (flag_val_V_assign_load_1_2_fu_1589_p3 = flag_val_V_assign_load_1_4_fu_1616_p3) else "1";
tmp_181_3_fu_2449_p2 <= "0" when (flag_val_V_assign_load_1_10_reg_5709 = flag_val_V_assign_load_1_12_reg_5715) else "1";
tmp_181_3_not_fu_1788_p2 <= "0" when (flag_val_V_assign_load_1_4_fu_1616_p3 = flag_val_V_assign_load_1_6_fu_1642_p3) else "1";
tmp_181_4_fu_2484_p2 <= "0" when (flag_val_V_assign_load_1_12_reg_5715 = flag_val_V_assign_load_1_14_fu_2351_p3) else "1";
tmp_181_4_not_fu_1806_p2 <= "0" when (flag_val_V_assign_load_1_6_fu_1642_p3 = flag_val_V_assign_load_1_8_fu_1670_p3) else "1";
tmp_181_5_fu_2506_p2 <= "0" when (flag_val_V_assign_load_1_14_fu_2351_p3 = ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5) else "1";
tmp_181_5_not_fu_1824_p2 <= "0" when (flag_val_V_assign_load_1_8_fu_1670_p3 = flag_val_V_assign_load_1_11_fu_1698_p3) else "1";
tmp_181_6_not_fu_1836_p2 <= "0" when (flag_val_V_assign_load_1_11_fu_1698_p3 = flag_val_V_assign_load_1_13_fu_1726_p3) else "1";
tmp_181_7_not_fu_2044_p2 <= "0" when (flag_val_V_assign_load_1_13_reg_5527 = flag_val_V_assign_load_2_s_fu_1894_p3) else "1";
tmp_181_8_fu_2069_p2 <= "0" when (flag_val_V_assign_load_2_s_fu_1894_p3 = flag_val_V_assign_load_1_9_fu_1911_p3) else "1";
tmp_181_9_fu_2081_p2 <= "0" when (flag_val_V_assign_load_1_9_fu_1911_p3 = flag_val_V_assign_load_1_3_fu_1930_p3) else "1";
tmp_181_s_fu_2265_p2 <= "0" when (flag_val_V_assign_load_1_3_reg_5625 = flag_val_V_assign_load_1_5_reg_5631) else "1";
tmp_182_1_fu_1568_p2 <= "1" when (signed(r_V_1_1_fu_1557_p2) > signed(ap_const_lv9_14)) else "0";
tmp_182_2_fu_1595_p2 <= "1" when (signed(r_V_1_2_fu_1584_p2) > signed(ap_const_lv9_14)) else "0";
tmp_182_3_fu_1938_p2 <= "1" when (signed(r_V_1_3_reg_5472) > signed(ap_const_lv9_14)) else "0";
tmp_182_4_fu_1970_p2 <= "1" when (signed(r_V_1_4_reg_5483) > signed(ap_const_lv9_14)) else "0";
tmp_182_5_fu_1980_p2 <= "1" when (signed(r_V_1_5_reg_5494) > signed(ap_const_lv9_14)) else "0";
tmp_182_6_fu_2139_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) > signed(ap_const_lv9_14)) else "0";
tmp_182_7_fu_2171_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) > signed(ap_const_lv9_14)) else "0";
tmp_183_10_fu_2328_p2 <= "1" when (flag_val_V_assign_load_1_7_fu_2112_p3 = ap_const_lv2_0) else "0";
tmp_183_11_fu_2453_p2 <= "1" when (flag_val_V_assign_load_1_10_reg_5709 = ap_const_lv2_0) else "0";
tmp_183_12_fu_2489_p2 <= "1" when (flag_val_V_assign_load_1_12_reg_5715 = ap_const_lv2_0) else "0";
tmp_183_1_fu_1758_p2 <= "1" when (flag_val_V_assign_load_1_1_fu_1562_p3 = ap_const_lv2_0) else "0";
tmp_183_2_fu_1776_p2 <= "1" when (flag_val_V_assign_load_1_2_fu_1589_p3 = ap_const_lv2_0) else "0";
tmp_183_3_fu_1794_p2 <= "1" when (flag_val_V_assign_load_1_4_fu_1616_p3 = ap_const_lv2_0) else "0";
tmp_183_4_fu_1812_p2 <= "1" when (flag_val_V_assign_load_1_6_fu_1642_p3 = ap_const_lv2_0) else "0";
tmp_183_5_fu_1830_p2 <= "1" when (flag_val_V_assign_load_1_8_fu_1670_p3 = ap_const_lv2_0) else "0";
tmp_183_6_fu_1842_p2 <= "1" when (flag_val_V_assign_load_1_11_fu_1698_p3 = ap_const_lv2_0) else "0";
tmp_183_7_fu_2049_p2 <= "1" when (flag_val_V_assign_load_2_s_fu_1894_p3 = ap_const_lv2_0) else "0";
tmp_183_8_fu_2305_p2 <= "1" when (flag_val_V_assign_load_1_5_reg_5631 = ap_const_lv2_0) else "0";
tmp_183_9_fu_2087_p2 <= "1" when (flag_val_V_assign_load_1_9_fu_1911_p3 = ap_const_lv2_0) else "0";
tmp_183_s_fu_2269_p2 <= "1" when (flag_val_V_assign_load_1_3_reg_5625 = ap_const_lv2_0) else "0";
tmp_184_1_fu_1574_p2 <= "1" when (signed(r_V_1_1_fu_1557_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_2_fu_1601_p2 <= "1" when (signed(r_V_1_2_fu_1584_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_3_fu_1943_p2 <= "1" when (signed(r_V_1_3_reg_5472) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_4_fu_1975_p2 <= "1" when (signed(r_V_1_4_reg_5483) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_5_fu_1985_p2 <= "1" when (signed(r_V_1_5_reg_5494) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_6_fu_2144_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_7_fu_2176_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) < signed(ap_const_lv9_1EC)) else "0";
tmp_185_10_fu_2642_p2 <= "1" when (unsigned(count_1_i_10_fu_2636_p3) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_11_fu_2699_p2 <= "1" when (unsigned(count_4_reg_5867) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_12_fu_2715_p2 <= "1" when (unsigned(count_1_i_12_reg_5872) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_13_fu_2743_p2 <= "1" when (unsigned(count_5_fu_2737_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_14_fu_2777_p2 <= "1" when (unsigned(count_1_i_14_reg_5898) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_15_fu_2805_p2 <= "1" when (unsigned(count_6_fu_2799_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_16_fu_2822_p2 <= "1" when (unsigned(phitmp_fu_2811_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_1_fu_2381_p2 <= "1" when (unsigned(count_1_i_s_reg_5753) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_2_fu_2413_p2 <= "1" when (unsigned(count_1_fu_2407_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_3_fu_2464_p2 <= "1" when (unsigned(count_1_i_2_fu_2441_p3) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_4_fu_2540_p2 <= "1" when (unsigned(count_2_fu_2534_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_5_fu_2570_p2 <= "1" when (unsigned(count_1_i_4_fu_2563_p3) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_6_fu_2620_p2 <= "1" when (unsigned(count_3_reg_5837) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_7_fu_2181_p2 <= "1" when (unsigned(count_1_i_6_reg_5665) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_8_fu_2202_p2 <= "1" when (unsigned(count_8_fu_2197_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_9_fu_2235_p2 <= "1" when (unsigned(count_1_i_8_fu_2224_p3) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_s_fu_2364_p2 <= "1" when (unsigned(count_s_fu_2359_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_188_1_fu_2875_p2 <= "1" when (signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) < signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)) else "0";
tmp_188_2_fu_3176_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) < signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)) else "0";
tmp_188_3_fu_2905_p2 <= "1" when (signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) < signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)) else "0";
tmp_188_4_fu_3206_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) < signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)) else "0";
tmp_188_5_fu_2935_p2 <= "1" when (signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) < signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)) else "0";
tmp_188_7_fu_2965_p2 <= "1" when (signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) < signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)) else "0";
tmp_188_9_fu_3083_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) < signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)) else "0";
tmp_188_s_fu_3146_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) < signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)) else "0";
tmp_18_fu_1266_p2 <= "1" when (signed(r_V_fu_1260_p2) > signed(ap_const_lv9_14)) else "0";
tmp_192_1_fu_2995_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_542_ap_return) < signed(grp_image_filter_reg_int_s_fu_552_ap_return)) else "0";
tmp_192_2_fu_3333_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_632_ap_return) < signed(grp_image_filter_reg_int_s_fu_642_ap_return)) else "0";
tmp_192_3_fu_3025_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_552_ap_return) < signed(grp_image_filter_reg_int_s_fu_562_ap_return)) else "0";
tmp_192_4_fu_3363_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_642_ap_return) < signed(ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15)) else "0";
tmp_192_5_fu_3053_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_562_ap_return) < signed(grp_image_filter_reg_int_s_fu_572_ap_return)) else "0";
tmp_192_7_fu_3236_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14) < signed(grp_image_filter_reg_int_s_fu_602_ap_return)) else "0";
tmp_192_9_fu_3277_p2 <= "1" when (signed(flag_d_min2_9_reg_6017) < signed(grp_image_filter_reg_int_s_fu_622_ap_return)) else "0";
tmp_192_s_fu_3303_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_622_ap_return) < signed(grp_image_filter_reg_int_s_fu_632_ap_return)) else "0";
tmp_193_1_fu_2879_p3 <=
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 when (tmp_188_1_fu_2875_p2(0) = '1') else
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
tmp_193_2_fu_3180_p3 <=
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 when (tmp_188_2_fu_3176_p2(0) = '1') else
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
tmp_193_3_fu_2909_p3 <=
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 when (tmp_188_3_fu_2905_p2(0) = '1') else
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
tmp_193_4_fu_3210_p3 <=
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 when (tmp_188_4_fu_3206_p2(0) = '1') else
ap_reg_ppstg_r_V_reg_5252_pp0_it14;
tmp_193_5_fu_2939_p3 <=
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 when (tmp_188_5_fu_2935_p2(0) = '1') else
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
tmp_193_7_fu_2969_p3 <=
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 when (tmp_188_7_fu_2965_p2(0) = '1') else
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
tmp_193_9_fu_3087_p3 <=
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 when (tmp_188_9_fu_3083_p2(0) = '1') else
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
tmp_193_s_fu_3150_p3 <=
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 when (tmp_188_s_fu_3146_p2(0) = '1') else
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
tmp_195_1_fu_2890_p2 <= "1" when (signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) > signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)) else "0";
tmp_195_2_fu_3191_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) > signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)) else "0";
tmp_195_3_fu_2920_p2 <= "1" when (signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) > signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)) else "0";
tmp_195_4_fu_3221_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) > signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)) else "0";
tmp_195_5_fu_2950_p2 <= "1" when (signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) > signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)) else "0";
tmp_195_7_fu_2980_p2 <= "1" when (signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) > signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)) else "0";
tmp_195_9_fu_3098_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) > signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)) else "0";
tmp_195_s_fu_3161_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) > signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)) else "0";
tmp_199_1_fu_3113_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_582_ap_return) < signed(grp_image_filter_reg_int_s_fu_592_ap_return)) else "0";
tmp_199_2_fu_3604_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_692_ap_return) < signed(ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16)) else "0";
tmp_199_3_fu_3389_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_652_ap_return) < signed(grp_image_filter_reg_int_s_fu_662_ap_return)) else "0";
tmp_199_4_fu_3628_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_702_ap_return) < signed(flag_d_min4_3_reg_6053)) else "0";
tmp_199_5_fu_3500_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16) < signed(grp_image_filter_reg_int_s_fu_672_ap_return)) else "0";
tmp_199_7_fu_3524_p2 <= "1" when (signed(flag_d_min4_7_reg_6065) < signed(grp_image_filter_reg_int_s_fu_682_ap_return)) else "0";
tmp_199_9_fu_3548_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_672_ap_return) < signed(grp_image_filter_reg_int_s_fu_692_ap_return)) else "0";
tmp_199_s_fu_3576_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_682_ap_return) < signed(grp_image_filter_reg_int_s_fu_702_ap_return)) else "0";
tmp_19_fu_1272_p2 <= "1" when (signed(r_V_fu_1260_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_200_3_fu_3031_p3 <=
grp_image_filter_reg_int_s_fu_552_ap_return when (tmp_192_3_fu_3025_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_562_ap_return;
tmp_202_1_fu_3010_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_547_ap_return) > signed(grp_image_filter_reg_int_s_fu_557_ap_return)) else "0";
tmp_202_2_fu_3348_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_637_ap_return) > signed(grp_image_filter_reg_int_s_fu_647_ap_return)) else "0";
tmp_202_3_fu_3039_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_557_ap_return) > signed(grp_image_filter_reg_int_s_fu_567_ap_return)) else "0";
tmp_202_4_fu_3376_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_647_ap_return) > signed(ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15)) else "0";
tmp_202_5_fu_3068_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_567_ap_return) > signed(grp_image_filter_reg_int_s_fu_577_ap_return)) else "0";
tmp_202_7_fu_3249_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14) > signed(grp_image_filter_reg_int_s_fu_607_ap_return)) else "0";
tmp_202_9_fu_3290_p2 <= "1" when (signed(flag_d_max2_9_reg_6023) > signed(grp_image_filter_reg_int_s_fu_627_ap_return)) else "0";
tmp_202_s_fu_3318_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_627_ap_return) > signed(grp_image_filter_reg_int_s_fu_637_ap_return)) else "0";
tmp_203_1_fu_2894_p3 <=
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 when (tmp_195_1_fu_2890_p2(0) = '1') else
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
tmp_203_2_fu_3195_p3 <=
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 when (tmp_195_2_fu_3191_p2(0) = '1') else
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
tmp_203_3_fu_2924_p3 <=
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 when (tmp_195_3_fu_2920_p2(0) = '1') else
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
tmp_203_4_fu_3225_p3 <=
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 when (tmp_195_4_fu_3221_p2(0) = '1') else
ap_reg_ppstg_r_V_reg_5252_pp0_it14;
tmp_203_5_fu_2954_p3 <=
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 when (tmp_195_5_fu_2950_p2(0) = '1') else
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
tmp_203_7_fu_2984_p3 <=
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 when (tmp_195_7_fu_2980_p2(0) = '1') else
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
tmp_203_9_fu_3102_p3 <=
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 when (tmp_195_9_fu_3098_p2(0) = '1') else
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
tmp_203_s_fu_3165_p3 <=
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 when (tmp_195_s_fu_3161_p2(0) = '1') else
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
tmp_209_1_fu_3666_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_712_ap_return) < signed(flag_d_assign_2_fu_3497_p1)) else "0";
tmp_209_2_fu_3794_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_722_ap_return) < signed(flag_d_assign_4_fu_3777_p1)) else "0";
tmp_209_3_fu_3922_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_732_ap_return) < signed(flag_d_assign_6_fu_3905_p1)) else "0";
tmp_209_4_fu_4050_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_742_ap_return) < signed(flag_d_assign_8_fu_4033_p1)) else "0";
tmp_209_5_fu_4178_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_752_ap_return) < signed(flag_d_assign_s_fu_4161_p1)) else "0";
tmp_209_6_fu_4306_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_762_ap_return) < signed(flag_d_assign_11_fu_4289_p1)) else "0";
tmp_209_7_fu_4434_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_772_ap_return) < signed(flag_d_assign_13_fu_4417_p1)) else "0";
tmp_20_fu_1286_p2 <= (tmp_18_fu_1266_p2 or tmp_19_fu_1272_p2);
tmp_210_2_fu_3609_p3 <=
grp_image_filter_reg_int_s_fu_692_ap_return when (tmp_199_2_fu_3604_p2(0) = '1') else
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16;
tmp_210_4_fu_3633_p3 <=
grp_image_filter_reg_int_s_fu_702_ap_return when (tmp_199_4_fu_3628_p2(0) = '1') else
flag_d_min4_3_reg_6053;
tmp_210_5_fu_3505_p3 <=
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 when (tmp_199_5_fu_3500_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_672_ap_return;
tmp_210_7_fu_3529_p3 <=
flag_d_min4_7_reg_6065 when (tmp_199_7_fu_3524_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_682_ap_return;
tmp_210_9_fu_3554_p3 <=
grp_image_filter_reg_int_s_fu_672_ap_return when (tmp_199_9_fu_3548_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_692_ap_return;
tmp_210_s_fu_3582_p3 <=
grp_image_filter_reg_int_s_fu_682_ap_return when (tmp_199_s_fu_3576_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_702_ap_return;
tmp_212_1_fu_3128_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_587_ap_return) > signed(grp_image_filter_reg_int_s_fu_597_ap_return)) else "0";
tmp_212_2_fu_3616_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_697_ap_return) > signed(ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16)) else "0";
tmp_212_3_fu_3404_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_657_ap_return) > signed(grp_image_filter_reg_int_s_fu_667_ap_return)) else "0";
tmp_212_4_fu_3640_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_707_ap_return) > signed(flag_d_max4_3_reg_6059)) else "0";
tmp_212_5_fu_3512_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16) > signed(grp_image_filter_reg_int_s_fu_677_ap_return)) else "0";
tmp_212_7_fu_3536_p2 <= "1" when (signed(flag_d_max4_7_reg_6071) > signed(grp_image_filter_reg_int_s_fu_687_ap_return)) else "0";
tmp_212_9_fu_3562_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_677_ap_return) > signed(grp_image_filter_reg_int_s_fu_697_ap_return)) else "0";
tmp_212_s_fu_3590_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_687_ap_return) > signed(grp_image_filter_reg_int_s_fu_707_ap_return)) else "0";
tmp_213_3_fu_3045_p3 <=
grp_image_filter_reg_int_s_fu_557_ap_return when (tmp_202_3_fu_3039_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_567_ap_return;
tmp_216_1_fu_3698_p3 <=
flag_d_min8_3_reg_6115 when (tmp_209_1_reg_6195(0) = '1') else
flag_d_assign_2_reg_6109;
tmp_216_2_fu_3826_p3 <=
flag_d_min8_5_reg_6249 when (tmp_209_2_reg_6269(0) = '1') else
flag_d_assign_4_reg_6243;
tmp_216_3_fu_3954_p3 <=
flag_d_min8_7_reg_6323 when (tmp_209_3_reg_6343(0) = '1') else
flag_d_assign_6_reg_6317;
tmp_216_4_fu_4082_p3 <=
flag_d_min8_9_reg_6397 when (tmp_209_4_reg_6417(0) = '1') else
flag_d_assign_8_reg_6391;
tmp_216_5_fu_4210_p3 <=
tmp_211_s_reg_6471 when (tmp_209_5_reg_6491(0) = '1') else
flag_d_assign_s_reg_6465;
tmp_216_6_fu_4338_p3 <=
tmp_211_1_reg_6545 when (tmp_209_6_reg_6565(0) = '1') else
flag_d_assign_11_reg_6539;
tmp_216_7_fu_4466_p3 <=
tmp_211_2_reg_6619 when (tmp_209_7_reg_6639(0) = '1') else
flag_d_assign_13_reg_6613;
tmp_217_1_fu_3707_p2 <= "1" when (signed(p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1) > signed(tmp_216_1_fu_3698_p3)) else "0";
tmp_217_2_fu_3835_p2 <= "1" when (signed(a0_tmp_232_1_cast_fu_3823_p1) > signed(tmp_216_2_fu_3826_p3)) else "0";
tmp_217_3_fu_3963_p2 <= "1" when (signed(a0_2_tmp_232_2_cast_fu_3951_p1) > signed(tmp_216_3_fu_3954_p3)) else "0";
tmp_217_4_fu_4091_p2 <= "1" when (signed(a0_3_tmp_232_3_cast_fu_4079_p1) > signed(tmp_216_4_fu_4082_p3)) else "0";
tmp_217_5_fu_4219_p2 <= "1" when (signed(a0_4_tmp_232_4_cast_fu_4207_p1) > signed(tmp_216_5_fu_4210_p3)) else "0";
tmp_217_6_fu_4347_p2 <= "1" when (signed(a0_5_tmp_232_5_cast_fu_4335_p1) > signed(tmp_216_6_fu_4338_p3)) else "0";
tmp_217_7_fu_4475_p2 <= "1" when (signed(a0_6_tmp_232_6_cast_fu_4463_p1) > signed(tmp_216_7_fu_4466_p3)) else "0";
tmp_21_fu_1527_p2 <= "1" when (signed(r_V_1_fu_1516_p2) > signed(ap_const_lv9_14)) else "0";
tmp_221_1_fu_3686_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_717_ap_return) > signed(flag_d_assign_2_fu_3497_p1)) else "0";
tmp_221_2_fu_3814_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_727_ap_return) > signed(flag_d_assign_4_fu_3777_p1)) else "0";
tmp_221_3_fu_3942_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_737_ap_return) > signed(flag_d_assign_6_fu_3905_p1)) else "0";
tmp_221_4_fu_4070_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_747_ap_return) > signed(flag_d_assign_8_fu_4033_p1)) else "0";
tmp_221_5_fu_4198_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_757_ap_return) > signed(flag_d_assign_s_fu_4161_p1)) else "0";
tmp_221_6_fu_4326_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_767_ap_return) > signed(flag_d_assign_11_fu_4289_p1)) else "0";
tmp_221_7_fu_4454_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_777_ap_return) > signed(flag_d_assign_13_fu_4417_p1)) else "0";
tmp_225_2_fu_3621_p3 <=
grp_image_filter_reg_int_s_fu_697_ap_return when (tmp_212_2_fu_3616_p2(0) = '1') else
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16;
tmp_225_4_fu_3645_p3 <=
grp_image_filter_reg_int_s_fu_707_ap_return when (tmp_212_4_fu_3640_p2(0) = '1') else
flag_d_max4_3_reg_6059;
tmp_225_5_fu_3517_p3 <=
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 when (tmp_212_5_fu_3512_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_677_ap_return;
tmp_225_7_fu_3541_p3 <=
flag_d_max4_7_reg_6071 when (tmp_212_7_fu_3536_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_687_ap_return;
tmp_225_9_fu_3568_p3 <=
grp_image_filter_reg_int_s_fu_677_ap_return when (tmp_212_9_fu_3562_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_697_ap_return;
tmp_225_s_fu_3596_p3 <=
grp_image_filter_reg_int_s_fu_687_ap_return when (tmp_212_s_fu_3590_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_707_ap_return;
tmp_227_1_fu_3739_p3 <=
flag_d_max8_3_reg_6122 when (tmp_221_1_reg_6206(0) = '1') else
flag_d_assign_2_reg_6109;
tmp_227_2_fu_3867_p3 <=
flag_d_max8_5_reg_6256 when (tmp_221_2_reg_6280(0) = '1') else
flag_d_assign_4_reg_6243;
tmp_227_3_fu_3995_p3 <=
flag_d_max8_7_reg_6330 when (tmp_221_3_reg_6354(0) = '1') else
flag_d_assign_6_reg_6317;
tmp_227_4_fu_4123_p3 <=
flag_d_max8_9_reg_6404 when (tmp_221_4_reg_6428(0) = '1') else
flag_d_assign_8_reg_6391;
tmp_227_5_fu_4251_p3 <=
tmp_226_s_reg_6478 when (tmp_221_5_reg_6502(0) = '1') else
flag_d_assign_s_reg_6465;
tmp_227_6_fu_4379_p3 <=
tmp_226_1_reg_6552 when (tmp_221_6_reg_6576(0) = '1') else
flag_d_assign_11_reg_6539;
tmp_227_7_fu_4507_p3 <=
tmp_226_2_reg_6626 when (tmp_221_7_reg_6650(0) = '1') else
flag_d_assign_13_reg_6613;
tmp_228_1_fu_3748_p2 <= "1" when (signed(b0_tmp_239_cast_fu_3736_p1) < signed(tmp_227_1_fu_3739_p3)) else "0";
tmp_228_2_fu_3876_p2 <= "1" when (signed(b0_tmp_239_1_cast_fu_3864_p1) < signed(tmp_227_2_fu_3867_p3)) else "0";
tmp_228_3_fu_4004_p2 <= "1" when (signed(b0_2_tmp_239_2_cast_fu_3992_p1) < signed(tmp_227_3_fu_3995_p3)) else "0";
tmp_228_4_fu_4132_p2 <= "1" when (signed(b0_3_tmp_239_3_cast_fu_4120_p1) < signed(tmp_227_4_fu_4123_p3)) else "0";
tmp_228_5_fu_4260_p2 <= "1" when (signed(b0_4_tmp_239_4_cast_fu_4248_p1) < signed(tmp_227_5_fu_4251_p3)) else "0";
tmp_228_6_fu_4388_p2 <= "1" when (signed(b0_5_tmp_239_5_cast_fu_4376_p1) < signed(tmp_227_6_fu_4379_p3)) else "0";
tmp_228_7_fu_4516_p2 <= "1" when (signed(b0_6_tmp_239_6_cast_fu_4504_p1) < signed(tmp_227_7_fu_4507_p3)) else "0";
tmp_22_fu_1533_p2 <= "1" when (signed(r_V_1_fu_1516_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_231_1_fu_3720_p2 <= "1" when (signed(flag_d_min8_3_reg_6115) < signed(flag_d_assign_10_fu_3692_p1)) else "0";
tmp_231_2_fu_3848_p2 <= "1" when (signed(flag_d_min8_5_reg_6249) < signed(flag_d_assign_12_fu_3820_p1)) else "0";
tmp_231_3_fu_3976_p2 <= "1" when (signed(flag_d_min8_7_reg_6323) < signed(flag_d_assign_14_fu_3948_p1)) else "0";
tmp_231_4_fu_4104_p2 <= "1" when (signed(flag_d_min8_9_reg_6397) < signed(flag_d_assign_1_fu_4076_p1)) else "0";
tmp_231_5_fu_4232_p2 <= "1" when (signed(tmp_211_s_reg_6471) < signed(flag_d_assign_3_fu_4204_p1)) else "0";
tmp_231_6_fu_4360_p2 <= "1" when (signed(tmp_211_1_reg_6545) < signed(flag_d_assign_5_fu_4332_p1)) else "0";
tmp_231_7_fu_4488_p2 <= "1" when (signed(tmp_211_2_reg_6619) < signed(flag_d_assign_7_fu_4460_p1)) else "0";
tmp_232_1_fu_3725_p3 <=
flag_d_min8_3_reg_6115 when (tmp_231_1_fu_3720_p2(0) = '1') else
flag_d_assign_10_fu_3692_p1;
tmp_232_2_fu_3853_p3 <=
flag_d_min8_5_reg_6249 when (tmp_231_2_fu_3848_p2(0) = '1') else
flag_d_assign_12_fu_3820_p1;
tmp_232_3_fu_3981_p3 <=
flag_d_min8_7_reg_6323 when (tmp_231_3_fu_3976_p2(0) = '1') else
flag_d_assign_14_fu_3948_p1;
tmp_232_4_fu_4109_p3 <=
flag_d_min8_9_reg_6397 when (tmp_231_4_fu_4104_p2(0) = '1') else
flag_d_assign_1_fu_4076_p1;
tmp_232_5_fu_4237_p3 <=
tmp_211_s_reg_6471 when (tmp_231_5_fu_4232_p2(0) = '1') else
flag_d_assign_3_fu_4204_p1;
tmp_232_6_fu_4365_p3 <=
tmp_211_1_reg_6545 when (tmp_231_6_fu_4360_p2(0) = '1') else
flag_d_assign_5_fu_4332_p1;
tmp_232_7_fu_4493_p3 <=
tmp_211_2_reg_6619 when (tmp_231_7_fu_4488_p2(0) = '1') else
flag_d_assign_7_fu_4460_p1;
tmp_233_1_fu_3783_p2 <= "1" when (signed(a0_cast_fu_3780_p1) > signed(tmp_232_1_reg_6217)) else "0";
tmp_233_2_fu_3911_p2 <= "1" when (signed(a0_2_cast_fu_3908_p1) > signed(tmp_232_2_reg_6291)) else "0";
tmp_233_3_fu_4039_p2 <= "1" when (signed(a0_3_cast_fu_4036_p1) > signed(tmp_232_3_reg_6365)) else "0";
tmp_233_4_fu_4167_p2 <= "1" when (signed(a0_4_cast_fu_4164_p1) > signed(tmp_232_4_reg_6439)) else "0";
tmp_233_5_fu_4295_p2 <= "1" when (signed(a0_5_cast_fu_4292_p1) > signed(tmp_232_5_reg_6513)) else "0";
tmp_233_6_fu_4423_p2 <= "1" when (signed(a0_6_cast_fu_4420_p1) > signed(tmp_232_6_reg_6587)) else "0";
tmp_233_7_fu_4552_p2 <= "1" when (signed(a0_7_cast_fu_4549_p1) > signed(tmp_232_7_reg_6661)) else "0";
tmp_236_1_fu_3761_p2 <= "1" when (signed(flag_d_max8_3_reg_6122) > signed(flag_d_assign_10_fu_3692_p1)) else "0";
tmp_236_2_fu_3889_p2 <= "1" when (signed(flag_d_max8_5_reg_6256) > signed(flag_d_assign_12_fu_3820_p1)) else "0";
tmp_236_3_fu_4017_p2 <= "1" when (signed(flag_d_max8_7_reg_6330) > signed(flag_d_assign_14_fu_3948_p1)) else "0";
tmp_236_4_fu_4145_p2 <= "1" when (signed(flag_d_max8_9_reg_6404) > signed(flag_d_assign_1_fu_4076_p1)) else "0";
tmp_236_5_fu_4273_p2 <= "1" when (signed(tmp_226_s_reg_6478) > signed(flag_d_assign_3_fu_4204_p1)) else "0";
tmp_236_6_fu_4401_p2 <= "1" when (signed(tmp_226_1_reg_6552) > signed(flag_d_assign_5_fu_4332_p1)) else "0";
tmp_236_7_fu_4529_p2 <= "1" when (signed(tmp_226_2_reg_6626) > signed(flag_d_assign_7_fu_4460_p1)) else "0";
tmp_239_1_fu_3766_p3 <=
flag_d_max8_3_reg_6122 when (tmp_236_1_fu_3761_p2(0) = '1') else
flag_d_assign_10_fu_3692_p1;
tmp_239_2_fu_3894_p3 <=
flag_d_max8_5_reg_6256 when (tmp_236_2_fu_3889_p2(0) = '1') else
flag_d_assign_12_fu_3820_p1;
tmp_239_3_fu_4022_p3 <=
flag_d_max8_7_reg_6330 when (tmp_236_3_fu_4017_p2(0) = '1') else
flag_d_assign_14_fu_3948_p1;
tmp_239_4_fu_4150_p3 <=
flag_d_max8_9_reg_6404 when (tmp_236_4_fu_4145_p2(0) = '1') else
flag_d_assign_1_fu_4076_p1;
tmp_239_5_fu_4278_p3 <=
tmp_226_s_reg_6478 when (tmp_236_5_fu_4273_p2(0) = '1') else
flag_d_assign_3_fu_4204_p1;
tmp_239_6_fu_4406_p3 <=
tmp_226_1_reg_6552 when (tmp_236_6_fu_4401_p2(0) = '1') else
flag_d_assign_5_fu_4332_p1;
tmp_239_7_fu_4534_p3 <=
tmp_226_2_reg_6626 when (tmp_236_7_fu_4529_p2(0) = '1') else
flag_d_assign_7_fu_4460_p1;
tmp_23_fu_1547_p2 <= (tmp_21_fu_1527_p2 or tmp_22_fu_1533_p2);
tmp_240_1_fu_3803_p2 <= "1" when (signed(b0_cast_50_fu_3800_p1) < signed(tmp_239_1_reg_6233)) else "0";
tmp_240_2_fu_3931_p2 <= "1" when (signed(b0_2_cast_fu_3928_p1) < signed(tmp_239_2_reg_6307)) else "0";
tmp_240_3_fu_4059_p2 <= "1" when (signed(b0_3_cast_fu_4056_p1) < signed(tmp_239_3_reg_6381)) else "0";
tmp_240_4_fu_4187_p2 <= "1" when (signed(b0_4_cast_fu_4184_p1) < signed(tmp_239_4_reg_6455)) else "0";
tmp_240_5_fu_4315_p2 <= "1" when (signed(b0_5_cast_fu_4312_p1) < signed(tmp_239_5_reg_6529)) else "0";
tmp_240_6_fu_4443_p2 <= "1" when (signed(b0_6_cast_fu_4440_p1) < signed(tmp_239_6_reg_6603)) else "0";
tmp_240_7_fu_4566_p2 <= "1" when (signed(b0_7_cast_fu_4563_p1) < signed(tmp_239_7_reg_6676)) else "0";
tmp_242_1_fu_4659_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_1_fu_140)) else "0";
tmp_242_2_fu_4665_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_2_fu_4620_p1)) else "0";
tmp_245_1_fu_4677_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_1_fu_164)) else "0";
tmp_245_2_fu_4683_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_1_2_fu_4643_p1)) else "0";
tmp_24_fu_1322_p2 <= (tmp_176_1_fu_1302_p2 or tmp_177_1_fu_1308_p2);
tmp_25_fu_1907_p2 <= (tmp_182_1_reg_5441 or tmp_184_1_reg_5447);
tmp_26_fu_4779_p2 <= (tmp22_fu_4775_p2 and tmp18_fu_4771_p2);
tmp_27_fu_1358_p2 <= (tmp_176_2_fu_1338_p2 or tmp_177_2_fu_1344_p2);
tmp_28_fu_1926_p2 <= (tmp_182_2_reg_5461 or tmp_184_2_reg_5467);
tmp_29_fu_1394_p2 <= (tmp_176_3_fu_1374_p2 or tmp_177_3_fu_1380_p2);
tmp_30_fu_1956_p2 <= (tmp_182_3_fu_1938_p2 or tmp_184_3_fu_1943_p2);
tmp_31_fu_1638_p2 <= (tmp_176_4_reg_5337 or tmp_177_4_reg_5343);
tmp_32_fu_2108_p2 <= (tmp_182_4_reg_5638 or tmp_184_4_reg_5644);
tmp_33_fu_1666_p2 <= (tmp_176_5_reg_5357 or tmp_177_5_reg_5363);
tmp_34_fu_2127_p2 <= (tmp_182_5_reg_5649 or tmp_184_5_reg_5655);
tmp_35_fu_1694_p2 <= (tmp_176_6_reg_5377 or tmp_177_6_reg_5383);
tmp_36_fu_2157_p2 <= (tmp_182_6_fu_2139_p2 or tmp_184_6_fu_2144_p2);
tmp_37_fu_1722_p2 <= (tmp_176_7_reg_5397 or tmp_177_7_reg_5403);
tmp_38_fu_2347_p2 <= (tmp_182_7_reg_5722 or tmp_184_7_reg_5728);
tmp_39_fu_1740_p2 <= "1" when (flag_val_V_assign_load_1_s_fu_1521_p3 = ap_const_lv2_0) else "0";
tmp_40_fu_1864_p2 <= (or_cond7_fu_1782_p2 or or_cond6_fu_1764_p2);
tmp_41_fu_2010_p2 <= (or_cond9_reg_5559 or or_cond8_reg_5553);
tmp_42_fu_2030_p2 <= (or_cond3_fu_1994_p2 or or_cond2_fu_1990_p2);
tmp_43_fu_3262_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_612_ap_return) < signed(flag_d_assign_fu_3143_p1)) else "0";
tmp_44_fu_3424_p1 <= a_0_flag_d_assign_load_5_fu_3419_p3(8 - 1 downto 0);
tmp_45_fu_3428_p2 <= "1" when (signed(a_0_flag_d_assign_load_5_fu_3419_p3) < signed(ap_const_lv32_14)) else "0";
tmp_46_fu_3442_p2 <= "1" when (signed(flag_d_min8_1_reg_6029) < signed(flag_d_assign_9_fu_3274_p1)) else "0";
tmp_47_fu_3447_p3 <=
flag_d_min8_1_reg_6029 when (tmp_46_fu_3442_p2(0) = '1') else
flag_d_assign_9_fu_3274_p1;
tmp_48_fu_3454_p1 <= tmp_47_fu_3447_p3(8 - 1 downto 0);
tmp_49_fu_3655_p2 <= "1" when (signed(p_a_0_flag_d_assign_load_5_cast_fu_3652_p1) > signed(tmp_47_reg_6083)) else "0";
tmp_50_fu_4583_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(tmp_79_reg_6697));
tmp_51_fu_4588_p2 <= "1" when (unsigned(a0_7_tmp_232_7_reg_6691) > unsigned(tmp_50_fu_4583_p2)) else "0";
tmp_52_fu_4647_p2 <= "0" when (core_win_val_1_V_1_fu_152 = ap_const_lv16_0) else "1";
tmp_53_fu_4600_p2 <= "1" when (unsigned(ap_reg_ppstg_p_2_reg_515_pp0_it31) > unsigned(ap_const_lv11_6)) else "0";
tmp_54_fu_4689_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_1_V_0_fu_148)) else "0";
tmp_55_fu_4695_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_1_V_2_fu_4623_p1)) else "0";
tmp_56_fu_3703_p1 <= tmp_216_1_fu_3698_p3(8 - 1 downto 0);
tmp_57_fu_3732_p1 <= tmp_232_1_fu_3725_p3(8 - 1 downto 0);
tmp_58_fu_3831_p1 <= tmp_216_2_fu_3826_p3(8 - 1 downto 0);
tmp_59_fu_3860_p1 <= tmp_232_2_fu_3853_p3(8 - 1 downto 0);
tmp_5_fu_796_p2 <= std_logic_vector(unsigned(tmp_fu_782_p1) + unsigned(ap_const_lv11_4));
tmp_60_fu_3959_p1 <= tmp_216_3_fu_3954_p3(8 - 1 downto 0);
tmp_61_fu_3988_p1 <= tmp_232_3_fu_3981_p3(8 - 1 downto 0);
tmp_62_fu_4087_p1 <= tmp_216_4_fu_4082_p3(8 - 1 downto 0);
tmp_63_fu_4116_p1 <= tmp_232_4_fu_4109_p3(8 - 1 downto 0);
tmp_64_fu_4215_p1 <= tmp_216_5_fu_4210_p3(8 - 1 downto 0);
tmp_65_fu_4244_p1 <= tmp_232_5_fu_4237_p3(8 - 1 downto 0);
tmp_66_fu_4343_p1 <= tmp_216_6_fu_4338_p3(8 - 1 downto 0);
tmp_67_fu_3268_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_617_ap_return) > signed(flag_d_assign_fu_3143_p1)) else "0";
tmp_68_fu_3458_p3 <=
flag_d_max8_1_reg_6036 when (tmp_67_reg_6048(0) = '1') else
flag_d_assign_reg_6011;
tmp_69_fu_3467_p2 <= "1" when (signed(tmp_68_fu_3458_p3) > signed(ap_const_lv32_FFFFFFEC)) else "0";
tmp_70_fu_3481_p2 <= "1" when (signed(flag_d_max8_1_reg_6036) > signed(flag_d_assign_9_fu_3274_p1)) else "0";
tmp_71_fu_3486_p3 <=
flag_d_max8_1_reg_6036 when (tmp_70_fu_3481_p2(0) = '1') else
flag_d_assign_9_fu_3274_p1;
tmp_72_fu_3675_p2 <= "1" when (signed(b0_cast_fu_3672_p1) < signed(tmp_71_reg_6099)) else "0";
tmp_73_fu_4653_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_0_fu_136)) else "0";
tmp_74_fu_4671_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_0_fu_160)) else "0";
tmp_75_fu_4372_p1 <= tmp_232_6_fu_4365_p3(8 - 1 downto 0);
tmp_77_fu_4471_p1 <= tmp_216_7_fu_4466_p3(8 - 1 downto 0);
tmp_78_fu_4500_p1 <= tmp_232_7_fu_4493_p3(8 - 1 downto 0);
tmp_79_fu_4571_p3 <=
tmp_95_reg_6681 when (tmp_240_7_fu_4566_p2(0) = '1') else
tmp_96_reg_6686;
tmp_7_fu_813_p2 <= "1" when (unsigned(p_s_reg_504) < unsigned(tmp_reg_5098)) else "0";
tmp_80_fu_3463_p1 <= tmp_68_fu_3458_p3(9 - 1 downto 0);
tmp_81_fu_3493_p1 <= tmp_71_fu_3486_p3(9 - 1 downto 0);
tmp_82_fu_3744_p1 <= tmp_227_1_fu_3739_p3(9 - 1 downto 0);
tmp_83_fu_3773_p1 <= tmp_239_1_fu_3766_p3(9 - 1 downto 0);
tmp_84_fu_3872_p1 <= tmp_227_2_fu_3867_p3(9 - 1 downto 0);
tmp_85_fu_3901_p1 <= tmp_239_2_fu_3894_p3(9 - 1 downto 0);
tmp_86_fu_4000_p1 <= tmp_227_3_fu_3995_p3(9 - 1 downto 0);
tmp_87_fu_4029_p1 <= tmp_239_3_fu_4022_p3(9 - 1 downto 0);
tmp_88_fu_4128_p1 <= tmp_227_4_fu_4123_p3(9 - 1 downto 0);
tmp_89_fu_4157_p1 <= tmp_239_4_fu_4150_p3(9 - 1 downto 0);
tmp_8_fu_818_p2 <= "1" when (unsigned(p_s_reg_504) > unsigned(ap_const_lv11_5)) else "0";
tmp_90_fu_4256_p1 <= tmp_227_5_fu_4251_p3(9 - 1 downto 0);
tmp_91_fu_4285_p1 <= tmp_239_5_fu_4278_p3(9 - 1 downto 0);
tmp_92_fu_4384_p1 <= tmp_227_6_fu_4379_p3(9 - 1 downto 0);
tmp_93_fu_4413_p1 <= tmp_239_6_fu_4406_p3(9 - 1 downto 0);
tmp_94_fu_4512_p1 <= tmp_227_7_fu_4507_p3(9 - 1 downto 0);
tmp_95_fu_4541_p1 <= b0_7_fu_4522_p3(8 - 1 downto 0);
tmp_96_fu_4545_p1 <= tmp_239_7_fu_4534_p3(8 - 1 downto 0);
tmp_97_fu_888_p4 <= p_2_phi_fu_519_p4(10 downto 2);
tmp_9_fu_824_p2 <= "1" when (unsigned(p_s_reg_504) > unsigned(ap_const_lv11_6)) else "0";
tmp_fu_782_p1 <= p_src_rows_V_read(11 - 1 downto 0);
tmp_s_fu_790_p2 <= std_logic_vector(unsigned(tmp_15_fu_786_p1) + unsigned(ap_const_lv11_4));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_FAST_t_opr is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_mask_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_mask_data_stream_V_full_n : IN STD_LOGIC;
p_mask_data_stream_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_FAST_t_opr is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st39_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101";
constant ap_const_lv11_6 : STD_LOGIC_VECTOR (10 downto 0) := "00000000110";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv9_14 : STD_LOGIC_VECTOR (8 downto 0) := "000010100";
constant ap_const_lv9_1EC : STD_LOGIC_VECTOR (8 downto 0) := "111101100";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_const_lv4_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv8_14 : STD_LOGIC_VECTOR (7 downto 0) := "00010100";
constant ap_const_lv32_FFFFFFEC : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111101100";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_true : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal p_2_reg_515 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it1 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_48 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal exitcond_reg_5147 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_5156 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_61 : BOOLEAN;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it27 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it28 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it29 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it30 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it31 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it32 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it33 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it34 : STD_LOGIC := '0';
signal or_cond4_reg_5201 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_136 : BOOLEAN;
signal ap_reg_ppiten_pp0_it35 : STD_LOGIC := '0';
signal ap_reg_ppstg_p_2_reg_515_pp0_it2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it3 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it4 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it5 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it6 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it7 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it8 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it9 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it10 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it11 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it12 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it13 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it14 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it15 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it16 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it17 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it18 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it19 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it20 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it21 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it22 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it23 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it24 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it25 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it26 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it27 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it28 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it29 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it30 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_p_2_reg_515_pp0_it31 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_fu_782_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_reg_5098 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_bdd_180 : BOOLEAN;
signal tmp_15_fu_786_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_15_reg_5103 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_s_fu_790_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_s_reg_5108 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_5_fu_796_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_5_reg_5113 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond1_fu_802_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_196 : BOOLEAN;
signal i_V_fu_807_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_5122 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_7_fu_813_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_5127 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_818_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_5132 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_824_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_5137 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_fu_840_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_reg_5142 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_5147_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_851_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal j_V_reg_5151 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond_reg_5156_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal k_buf_val_0_V_addr_reg_5161 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_addr_reg_5167 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_addr_reg_5173 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_addr_reg_5179 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_addr_reg_5185 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_addr_reg_5191 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond1_fu_883_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond1_reg_5197 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond4_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal win_val_0_V_2_1_reg_5205 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_4_3_reg_5210 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_5_3_reg_5215 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_2_3_reg_5220 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_5_3_reg_5225 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_4_3_reg_5230 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_2_reg_5235 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_fu_1252_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal lhs_V_reg_5240 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_fu_1260_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_reg_5252 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_reg_5252_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp1_fu_1278_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp1_reg_5261 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_20_fu_1286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_reg_5266 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_s_fu_1296_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_s_reg_5271 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_1_fu_1314_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_1_reg_5280 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_24_fu_1322_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_5285 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_2_fu_1332_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_2_reg_5290 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_2_fu_1350_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_2_reg_5299 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_27_fu_1358_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_reg_5304 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_3_fu_1368_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_3_reg_5309 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal phitmp_3_fu_1386_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp_3_reg_5318 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_fu_1394_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_5323 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_4_fu_1404_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_4_reg_5328 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_4_fu_1410_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_4_reg_5337 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_4_fu_1416_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_4_reg_5343 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_5_fu_1426_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_5_reg_5348 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_5_fu_1432_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_5_reg_5357 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_5_fu_1438_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_5_reg_5363 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_6_fu_1448_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_6_reg_5368 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_6_fu_1454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_6_reg_5377 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_6_fu_1460_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_6_reg_5383 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_7_fu_1470_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_7_reg_5388 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_7_fu_1476_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_176_7_reg_5397 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_7_fu_1482_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_7_reg_5403 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_fu_1516_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_reg_5408 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_val_V_assign_load_1_s_fu_1521_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_s_reg_5417 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp3_fu_1539_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal phitmp3_reg_5422 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_23_fu_1547_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_5427 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_1_fu_1557_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_1_reg_5432 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_182_1_fu_1568_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_1_reg_5441 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_1_fu_1574_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_1_reg_5447 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_2_fu_1584_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_2_reg_5452 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_182_2_fu_1595_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_2_reg_5461 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_2_fu_1601_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_2_reg_5467 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_1_3_fu_1611_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_3_reg_5472 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_4_fu_1626_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_4_reg_5483 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_5_fu_1654_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_5_reg_5494 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_6_fu_1682_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_6_reg_5505 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_7_fu_1710_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_7_reg_5516 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_val_V_assign_load_1_13_fu_1726_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_13_reg_5527 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_39_fu_1740_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_39_reg_5532 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_fu_1746_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_reg_5537 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_fu_1764_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_reg_5543 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond7_fu_1782_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond7_reg_5548 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond8_fu_1800_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond8_reg_5553 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond9_fu_1818_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond9_reg_5559 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_not_fu_1824_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_not_reg_5566 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_5_fu_1830_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_5_reg_5572 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_6_not_fu_1836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_6_not_reg_5578 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_6_fu_1842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_6_reg_5584 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_0_op_op87_op_fu_1848_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_0_op_op87_op_reg_5590 : STD_LOGIC_VECTOR (3 downto 0);
signal phitmp43_op_op_cast_cast_cast_fu_1856_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal phitmp43_op_op_cast_cast_cast_reg_5595 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_40_fu_1864_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_40_reg_5600 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_demorgan_fu_1870_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_demorgan_reg_5605 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_demorgan_fu_1876_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_demorgan_reg_5610 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_demorgan_fu_1882_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_demorgan_reg_5615 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_demorgan_fu_1888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_demorgan_reg_5620 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_3_fu_1930_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_3_reg_5625 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_5_fu_1962_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_5_reg_5631 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_4_fu_1970_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_4_reg_5638 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_4_fu_1975_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_4_reg_5644 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_5_fu_1980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_5_reg_5649 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_5_fu_1985_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_5_reg_5655 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_1990_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_5660 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_6_fu_2036_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_6_reg_5665 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond10_fu_2055_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond10_reg_5670 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_7_fu_2061_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_7_reg_5675 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond11_fu_2075_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond11_reg_5681 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_9_fu_2081_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_9_reg_5687 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_9_fu_2087_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_9_reg_5693 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_demorgan_fu_2093_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_demorgan_reg_5699 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_demorgan_fu_2097_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_demorgan_reg_5704 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_10_fu_2131_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_10_reg_5709 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_12_fu_2163_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_12_reg_5715 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_7_fu_2171_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_182_7_reg_5722 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_7_fu_2176_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_7_reg_5728 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond_fu_2186_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond_reg_5733 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_9_fu_2251_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_9_reg_5738 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_9_fu_2257_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_9_reg_5743 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond3_demorgan_fu_2286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond3_demorgan_reg_5748 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_s_fu_2292_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_s_reg_5753 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond14_fu_2310_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond14_reg_5759 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_demorgan_fu_2316_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_demorgan_reg_5764 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_fu_2322_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_reg_5769 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_10_fu_2328_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_10_reg_5775 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_2334_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_reg_5781 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp5_reg_5781_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_1_fu_2391_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_1_reg_5786 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_2_fu_2435_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_2_reg_5791 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_3_fu_2464_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_3_reg_5796 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_demorgan_fu_2470_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_demorgan_reg_5801 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_3_fu_2476_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_3_reg_5806 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond17_fu_2494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond17_reg_5811 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_demorgan_fu_2500_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_demorgan_reg_5816 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond18_fu_2511_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond18_reg_5821 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp6_fu_2516_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp6_reg_5827 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_5_fu_2581_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_5_reg_5832 : STD_LOGIC_VECTOR (0 downto 0);
signal count_3_fu_2594_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_3_reg_5837 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp8_fu_2600_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp8_reg_5842 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp4_fu_2606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_reg_5847 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_fu_2610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_reg_5852 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_fu_2614_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_reg_5857 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_7_fu_2653_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_7_reg_5862 : STD_LOGIC_VECTOR (0 downto 0);
signal count_4_fu_2666_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_4_reg_5867 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_12_fu_2678_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_12_reg_5872 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp3_fu_2689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_reg_5878 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp3_reg_5878_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_fu_2694_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_reg_5883 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp12_reg_5883_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_11_fu_2725_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_11_reg_5888 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_13_fu_2743_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_13_reg_5893 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_14_fu_2755_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_14_reg_5898 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp13_fu_2762_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp13_reg_5904 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_13_fu_2787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_13_reg_5909 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_15_fu_2805_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_15_reg_5914 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_fu_2817_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond11_reg_5919 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_16_fu_2822_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_16_reg_5924 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_2828_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_reg_5929 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_fu_2833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_reg_5934 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp11_reg_5934_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_fu_2837_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_reg_5939 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_fu_2861_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_reg_5944 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_s_fu_2870_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_s_reg_5949 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_image_filter_reg_int_s_fu_542_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_1_reg_5953 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_547_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_1_reg_5959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_572_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_7_reg_5965 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_577_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_7_reg_5971 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_3_fu_3031_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_3_reg_5977 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_3_fu_3045_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_3_reg_5982 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_582_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_1_reg_5987 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_587_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_1_reg_5993 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_592_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_5_reg_5999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_597_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_5_reg_6005 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_fu_3143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_reg_6011 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_602_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min2_9_reg_6017 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_607_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max2_9_reg_6023 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_612_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_1_reg_6029 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_617_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_1_reg_6036 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_fu_3262_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_43_reg_6043 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_67_fu_3268_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_67_reg_6048 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_image_filter_reg_int_s_fu_652_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_3_reg_6053 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_657_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_3_reg_6059 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_662_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min4_7_reg_6065 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_667_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max4_7_reg_6071 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_fu_3434_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_a_0_flag_d_assign_load_5_reg_6077 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_fu_3447_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_reg_6083 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_48_fu_3454_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_48_reg_6088 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_fu_3473_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_reg_6093 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_71_fu_3486_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_71_reg_6099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_3493_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_reg_6104 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_2_fu_3497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_2_reg_6109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_712_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_3_reg_6115 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_717_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_3_reg_6122 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_5_fu_3505_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_5_reg_6129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_5_fu_3517_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_5_reg_6134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_7_fu_3529_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_7_reg_6139 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_7_fu_3541_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_7_reg_6144 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_9_fu_3554_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_9_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_9_fu_3568_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_9_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_s_fu_3582_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_s_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_s_fu_3596_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_s_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_2_fu_3609_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_2_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_2_fu_3621_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_2_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_4_fu_3633_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_210_4_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_4_fu_3645_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_4_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_1_fu_3666_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_1_reg_6195 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_tmp_s_fu_3680_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_tmp_s_reg_6200 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_1_fu_3686_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_1_reg_6206 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_s_fu_3713_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_s_reg_6211 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_1_fu_3725_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_1_reg_6217 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_3732_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_57_reg_6222 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_s_fu_3754_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_s_reg_6227 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_1_fu_3766_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_1_reg_6233 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_fu_3773_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_83_reg_6238 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_4_fu_3777_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_4_reg_6243 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_722_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_5_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_727_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_5_reg_6256 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_tmp_232_1_fu_3788_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_tmp_232_1_reg_6263 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_2_fu_3794_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_2_reg_6269 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_tmp_239_1_fu_3808_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_tmp_239_1_reg_6274 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_2_fu_3814_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_2_reg_6280 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_2_fu_3841_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_2_reg_6285 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_2_fu_3853_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_2_reg_6291 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_fu_3860_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_59_reg_6296 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_2_fu_3882_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_2_reg_6301 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_2_fu_3894_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_2_reg_6307 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_3901_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_85_reg_6312 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_6_fu_3905_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_6_reg_6317 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_732_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_7_reg_6323 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_737_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_7_reg_6330 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_2_tmp_232_2_fu_3916_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_2_tmp_232_2_reg_6337 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_3_fu_3922_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_3_reg_6343 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_2_tmp_239_2_fu_3936_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_2_tmp_239_2_reg_6348 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_3_fu_3942_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_3_reg_6354 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_3_fu_3969_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_3_reg_6359 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_3_fu_3981_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_3_reg_6365 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_fu_3988_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_61_reg_6370 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_3_fu_4010_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_3_reg_6375 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_3_fu_4022_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_3_reg_6381 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_87_fu_4029_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_reg_6386 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_8_fu_4033_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_8_reg_6391 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_742_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_min8_9_reg_6397 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_747_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_max8_9_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_3_tmp_232_3_fu_4044_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_3_tmp_232_3_reg_6411 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_4_fu_4050_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_4_reg_6417 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_3_tmp_239_3_fu_4064_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_3_tmp_239_3_reg_6422 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_4_fu_4070_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_4_reg_6428 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_4_fu_4097_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_4_reg_6433 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_4_fu_4109_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_4_reg_6439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_4116_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_63_reg_6444 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_4_fu_4138_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_4_reg_6449 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_4_fu_4150_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_4_reg_6455 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_89_fu_4157_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_89_reg_6460 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_s_fu_4161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_s_reg_6465 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_752_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_s_reg_6471 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_757_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_s_reg_6478 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_4_tmp_232_4_fu_4172_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_4_tmp_232_4_reg_6485 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_5_fu_4178_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_5_reg_6491 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_4_tmp_239_4_fu_4192_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_4_tmp_239_4_reg_6496 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_5_fu_4198_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_5_reg_6502 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_5_fu_4225_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_5_reg_6507 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_5_fu_4237_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_5_reg_6513 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_fu_4244_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_reg_6518 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_5_fu_4266_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_5_reg_6523 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_5_fu_4278_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_5_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_91_fu_4285_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_91_reg_6534 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_11_fu_4289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_11_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_762_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_1_reg_6545 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_767_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_1_reg_6552 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_5_tmp_232_5_fu_4300_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_5_tmp_232_5_reg_6559 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_6_fu_4306_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_6_reg_6565 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_5_tmp_239_5_fu_4320_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_5_tmp_239_5_reg_6570 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_6_fu_4326_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_6_reg_6576 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_6_fu_4353_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_6_reg_6581 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_6_fu_4365_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_6_reg_6587 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_75_fu_4372_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_reg_6592 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_6_fu_4394_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_6_reg_6597 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_6_fu_4406_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_6_reg_6603 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_93_fu_4413_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_93_reg_6608 : STD_LOGIC_VECTOR (8 downto 0);
signal flag_d_assign_13_fu_4417_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_d_assign_13_reg_6613 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_772_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_2_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_777_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_2_reg_6626 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_6_tmp_232_6_fu_4428_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_6_tmp_232_6_reg_6633 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_7_fu_4434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_209_7_reg_6639 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_6_tmp_239_6_fu_4448_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_6_tmp_239_6_reg_6644 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_221_7_fu_4454_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_221_7_reg_6650 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_7_fu_4481_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_reg_6655 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_7_fu_4493_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_7_reg_6661 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_4500_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_reg_6666 : STD_LOGIC_VECTOR (7 downto 0);
signal b0_7_fu_4522_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal b0_7_reg_6671 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_239_7_fu_4534_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_7_reg_6676 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_95_fu_4541_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_95_reg_6681 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_fu_4545_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_reg_6686 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_tmp_232_7_fu_4557_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal a0_7_tmp_232_7_reg_6691 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_4571_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_reg_6697 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_addr_reg_6702 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_addr_reg_6708 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_100_v_fu_4593_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_100_v_reg_6714 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_53_fu_4600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_53_reg_6719 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal core_buf_val_0_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_load_reg_6724 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_load_reg_6729 : STD_LOGIC_VECTOR (7 downto 0);
signal phitmp2_fu_4606_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp19_fu_4701_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_reg_6739 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_fu_4712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_reg_6744 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_fu_4723_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_reg_6749 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_fu_4735_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_reg_6754 : STD_LOGIC_VECTOR (0 downto 0);
signal k_buf_val_0_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_0_V_ce0 : STD_LOGIC;
signal k_buf_val_0_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_0_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_0_V_ce1 : STD_LOGIC;
signal k_buf_val_0_V_we1 : STD_LOGIC;
signal k_buf_val_0_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_1_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_ce0 : STD_LOGIC;
signal k_buf_val_1_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_1_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_1_V_ce1 : STD_LOGIC;
signal k_buf_val_1_V_we1 : STD_LOGIC;
signal k_buf_val_1_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_2_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_ce0 : STD_LOGIC;
signal k_buf_val_2_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_2_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_2_V_ce1 : STD_LOGIC;
signal k_buf_val_2_V_we1 : STD_LOGIC;
signal k_buf_val_2_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_3_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_ce0 : STD_LOGIC;
signal k_buf_val_3_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_3_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_3_V_ce1 : STD_LOGIC;
signal k_buf_val_3_V_we1 : STD_LOGIC;
signal k_buf_val_3_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_4_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_ce0 : STD_LOGIC;
signal k_buf_val_4_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_4_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_4_V_ce1 : STD_LOGIC;
signal k_buf_val_4_V_we1 : STD_LOGIC;
signal k_buf_val_4_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_5_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_ce0 : STD_LOGIC;
signal k_buf_val_5_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_5_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_val_5_V_ce1 : STD_LOGIC;
signal k_buf_val_5_V_we1 : STD_LOGIC;
signal k_buf_val_5_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_0_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_0_V_ce0 : STD_LOGIC;
signal core_buf_val_0_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_0_V_ce1 : STD_LOGIC;
signal core_buf_val_0_V_we1 : STD_LOGIC;
signal core_buf_val_0_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal core_buf_val_1_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_ce0 : STD_LOGIC;
signal core_buf_val_1_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal core_buf_val_1_V_ce1 : STD_LOGIC;
signal core_buf_val_1_V_we1 : STD_LOGIC;
signal core_buf_val_1_V_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_image_filter_reg_int_s_fu_542_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_542_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_547_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_547_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_552_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_552_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_552_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_557_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_557_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_557_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_562_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_562_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_562_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_567_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_567_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_567_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_572_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_572_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_577_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_577_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_582_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_582_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_587_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_587_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_592_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_592_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_597_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_597_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_602_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_602_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_607_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_607_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_612_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_612_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_617_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_617_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_622_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_622_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_622_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_627_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_627_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_627_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_632_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_632_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_632_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_637_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_637_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_637_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_642_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_642_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_642_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_647_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_647_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_647_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_652_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_652_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_657_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_657_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_662_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_662_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_667_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_667_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_672_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_672_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_672_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_677_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_677_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_677_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_682_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_682_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_682_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_687_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_687_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_687_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_692_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_692_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_692_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_697_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_697_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_697_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_702_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_702_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_702_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_707_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_707_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_707_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_712_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_712_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_717_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_717_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_722_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_722_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_727_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_727_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_732_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_732_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_737_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_737_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_742_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_742_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_747_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_747_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_752_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_752_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_757_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_757_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_762_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_762_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_767_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_767_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_772_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_772_ap_ce : STD_LOGIC;
signal grp_image_filter_reg_int_s_fu_777_in_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_image_filter_reg_int_s_fu_777_ap_ce : STD_LOGIC;
signal p_s_reg_504 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st39_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_2075 : BOOLEAN;
signal p_2_phi_fu_519_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it0 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it6 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it7 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it8 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it9 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it10 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it11 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it12 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it13 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it14 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it15 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it16 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it17 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it18 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it19 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it20 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it21 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it22 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it23 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it24 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it25 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it26 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it27 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it28 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it29 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it30 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it31 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it32 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it33 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_core_1_reg_527pp0_it34 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_12_fu_867_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_fu_4577_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal win_val_6_V_5_fu_132 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_0_V_0_fu_136 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_0_V_1_fu_140 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_0_V_2_fu_4620_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_6_V_4_fu_144 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_1_V_0_fu_148 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_1_V_1_fu_152 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_1_V_2_fu_4623_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_6_V_3_fu_156 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_2_V_0_fu_160 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_2_V_1_fu_164 : STD_LOGIC_VECTOR (15 downto 0);
signal core_win_val_2_V_1_2_fu_4643_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal win_val_0_V_2_3_fu_168 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_2_fu_172 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_3_fu_176 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_4_fu_180 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_V_5_fu_184 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_1_3_fu_188 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_1_fu_192 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_2_fu_196 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_3_fu_200 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_4_fu_204 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_V_5_fu_208 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_0_3_fu_212 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_0_fu_216 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_1_fu_220 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_2_fu_224 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_3_fu_228 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_4_fu_232 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_2_V_5_fu_236 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_0_3_fu_240 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_0_fu_244 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_1_fu_248 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_2_fu_252 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_3_fu_256 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_4_fu_260 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_3_V_5_fu_264 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_0_3_fu_268 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_0_fu_272 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_1_fu_276 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_2_fu_280 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_3_fu_284 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_4_fu_288 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_4_V_5_fu_292 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_1_3_fu_296 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_1_fu_300 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_2_fu_304 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_3_fu_308 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_4_fu_312 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_5_V_5_fu_316 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_3_fu_320 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_6_V_2_fu_324 : STD_LOGIC_VECTOR (7 downto 0);
signal core_win_val_2_V_2_fu_4635_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_830_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_877_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_97_fu_888_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal icmp1_fu_898_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_fu_1256_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_18_fu_1266_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_1272_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_s_fu_1292_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_1_fu_1302_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_1_fu_1308_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_2_fu_1328_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_2_fu_1338_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_2_fu_1344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_3_fu_1364_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_176_3_fu_1374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_177_3_fu_1380_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_4_fu_1400_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_5_fu_1422_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_6_fu_1444_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_7_fu_1466_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_fu_1512_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_fu_1527_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_1533_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rhs_V_1_1_fu_1553_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_2_fu_1580_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_3_fu_1607_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal rhs_V_1_4_fu_1622_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_1638_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_4_fu_1631_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_5_fu_1650_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_fu_1666_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_5_fu_1659_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_6_fu_1678_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_fu_1694_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_6_fu_1687_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal rhs_V_1_7_fu_1706_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_37_fu_1722_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_7_fu_1715_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal flag_val_V_assign_load_1_1_fu_1562_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_0_not_fu_1734_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_2_fu_1589_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_1_fu_1758_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_1_not_fu_1752_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_4_fu_1616_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_2_fu_1776_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_2_not_fu_1770_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_6_fu_1642_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_3_fu_1794_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_3_not_fu_1788_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_8_fu_1670_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_4_fu_1812_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_4_not_fu_1806_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_11_fu_1698_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_25_fu_1907_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_1_fu_1900_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_28_fu_1926_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_2_fu_1919_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_3_fu_1938_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_3_fu_1943_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_1956_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_3_fu_1948_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_41_fu_2010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp42_op_cast_cast_cast_fu_2003_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_2_op_op_fu_1998_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond3_fu_1994_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_42_fu_2030_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp3_cast_cast_cast_fu_2022_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_4_op_fu_2014_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal flag_val_V_assign_load_2_s_fu_1894_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_183_7_fu_2049_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_7_not_fu_2044_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_9_fu_1911_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_8_fu_2069_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_2108_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_4_fu_2101_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_34_fu_2127_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_5_fu_2120_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_182_6_fu_2139_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_184_6_fu_2144_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_2157_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_6_fu_2149_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_185_7_fu_2181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_8_fu_2197_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_185_8_fu_2202_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond1_fu_2213_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp4_fu_2208_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_i_8_fu_2224_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond2_demorgan_fu_2241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_9_fu_2235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond2_fu_2245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond12_fu_2231_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_s_fu_2265_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_s_fu_2269_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond13_fu_2274_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp5_fu_2280_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal flag_val_V_assign_load_1_7_fu_2112_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_1_fu_2300_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_8_fu_2305_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal iscorner_2_i_7_fu_2191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_8_fu_2218_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_38_fu_2347_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp1_7_fu_2340_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal count_s_fu_2359_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_185_s_fu_2364_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond3_fu_2370_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_1_fu_2381_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond4_fu_2386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_1_fu_2397_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal count_1_fu_2407_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal not_or_cond12_demorgan_fu_2425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_2_fu_2413_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond12_fu_2429_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond15_fu_2403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp6_fu_2419_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_181_3_fu_2449_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_11_fu_2453_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_2_fu_2441_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal or_cond16_fu_2458_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal flag_val_V_assign_load_1_14_fu_2351_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_181_4_fu_2484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_183_12_fu_2489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_181_5_fu_2506_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_s_fu_2375_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond13_fu_2521_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_3_cast_fu_2531_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal count_2_fu_2534_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_4_fu_2540_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond14_fu_2552_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp7_fu_2546_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal count_1_i_4_fu_2563_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_5_fu_2570_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond15_fu_2576_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_5_fu_2587_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_3_fu_2526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_4_fu_2557_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_6_fu_2620_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond5_fu_2625_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_10_fu_2636_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_185_10_fu_2642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond6_fu_2648_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_11_fu_2659_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp9_fu_2672_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp7_fu_2685_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_6_fu_2630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_11_fu_2699_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond7_fu_2704_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_12_fu_2715_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond8_fu_2720_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_13_fu_2731_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_5_fu_2737_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp10_fu_2749_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_10_fu_2709_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond9_fu_2767_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_185_14_fu_2777_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_or_cond10_fu_2782_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal count_1_i_15_fu_2793_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal count_6_fu_2799_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal phitmp_fu_2811_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal p_iscorner_0_i_12_fu_2772_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_14_fu_2842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_iscorner_0_i_15_fu_2846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_fu_2850_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp16_fu_2856_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp10_fu_2866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_1_fu_2875_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_1_fu_2879_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_1_fu_2890_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_1_fu_2894_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_3_fu_2905_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_3_fu_2909_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_3_fu_2920_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_3_fu_2924_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_5_fu_2935_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_5_fu_2939_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_5_fu_2950_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_5_fu_2954_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_7_fu_2965_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_7_fu_2969_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_7_fu_2980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_7_fu_2984_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_192_1_fu_2995_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_1_fu_3010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_3_fu_3025_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_3_fu_3039_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_5_fu_3053_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_5_fu_3068_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_9_fu_3083_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_9_fu_3087_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_9_fu_3098_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_9_fu_3102_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_199_1_fu_3113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_1_fu_3128_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_188_s_fu_3146_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_s_fu_3150_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_s_fu_3161_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_s_fu_3165_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_2_fu_3176_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_2_fu_3180_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_2_fu_3191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_2_fu_3195_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_188_4_fu_3206_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_193_4_fu_3210_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_195_4_fu_3221_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_203_4_fu_3225_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_192_7_fu_3236_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_7_fu_3249_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_9_fu_3277_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_9_fu_3290_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_s_fu_3303_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_s_fu_3318_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_2_fu_3333_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_2_fu_3348_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_192_4_fu_3363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_202_4_fu_3376_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_3_fu_3389_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_3_fu_3404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_0_flag_d_assign_load_5_fu_3419_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_fu_3428_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_44_fu_3424_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_9_fu_3274_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_fu_3442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_68_fu_3458_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_fu_3467_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_80_fu_3463_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_3481_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_5_fu_3500_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_5_fu_3512_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_7_fu_3524_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_7_fu_3536_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_9_fu_3548_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_9_fu_3562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_s_fu_3576_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_s_fu_3590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_2_fu_3604_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_2_fu_3616_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_199_4_fu_3628_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_212_4_fu_3640_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_3655_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_cast_fu_3672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_72_fu_3675_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_1_fu_3698_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_1_fu_3707_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_fu_3703_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_10_fu_3692_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_1_fu_3720_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_1_fu_3739_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_tmp_239_cast_fu_3736_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_1_fu_3748_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_82_fu_3744_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_1_fu_3761_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_cast_fu_3780_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_1_fu_3783_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_cast_50_fu_3800_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_1_fu_3803_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_2_fu_3826_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_tmp_232_1_cast_fu_3823_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_2_fu_3835_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_58_fu_3831_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_12_fu_3820_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_2_fu_3848_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_2_fu_3867_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_tmp_239_1_cast_fu_3864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_2_fu_3876_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_84_fu_3872_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_2_fu_3889_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_2_cast_fu_3908_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_2_fu_3911_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_2_cast_fu_3928_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_2_fu_3931_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_3_fu_3954_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_2_tmp_232_2_cast_fu_3951_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_3_fu_3963_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_3959_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_14_fu_3948_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_3_fu_3976_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_3_fu_3995_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_2_tmp_239_2_cast_fu_3992_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_3_fu_4004_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_86_fu_4000_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_3_fu_4017_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_3_cast_fu_4036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_3_fu_4039_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_3_cast_fu_4056_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_3_fu_4059_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_4_fu_4082_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_3_tmp_232_3_cast_fu_4079_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_4_fu_4091_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_4087_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_1_fu_4076_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_4_fu_4104_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_4_fu_4123_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_3_tmp_239_3_cast_fu_4120_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_4_fu_4132_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_88_fu_4128_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_4_fu_4145_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_4_cast_fu_4164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_4_fu_4167_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_4_cast_fu_4184_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_4_fu_4187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_5_fu_4210_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_4_tmp_232_4_cast_fu_4207_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_5_fu_4219_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_4215_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_3_fu_4204_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_5_fu_4232_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_5_fu_4251_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_4_tmp_239_4_cast_fu_4248_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_5_fu_4260_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_90_fu_4256_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_5_fu_4273_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_5_cast_fu_4292_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_5_fu_4295_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_5_cast_fu_4312_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_5_fu_4315_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_6_fu_4338_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_5_tmp_232_5_cast_fu_4335_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_6_fu_4347_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_fu_4343_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_5_fu_4332_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_6_fu_4360_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_6_fu_4379_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_5_tmp_239_5_cast_fu_4376_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_6_fu_4388_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_92_fu_4384_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_6_fu_4401_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_6_cast_fu_4420_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_6_fu_4423_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_6_cast_fu_4440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_6_fu_4443_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_216_7_fu_4466_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal a0_6_tmp_232_6_cast_fu_4463_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_7_fu_4475_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_77_fu_4471_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal flag_d_assign_7_fu_4460_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_7_fu_4488_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_227_7_fu_4507_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal b0_6_tmp_239_6_cast_fu_4504_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_7_fu_4516_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_94_fu_4512_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_236_7_fu_4529_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a0_7_cast_fu_4549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_7_fu_4552_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal b0_7_cast_fu_4563_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_7_fu_4566_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_fu_4583_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_51_fu_4588_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_4647_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_73_fu_4653_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_242_1_fu_4659_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp21_fu_4706_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_74_fu_4671_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_245_1_fu_4677_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp24_fu_4717_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_242_2_fu_4665_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_fu_4695_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_54_fu_4689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_fu_4729_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_245_2_fu_4683_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp22_fu_4775_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_fu_4771_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_4779_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_bdd_2152 : BOOLEAN;
signal ap_sig_bdd_250 : BOOLEAN;
signal ap_sig_bdd_2159 : BOOLEAN;
signal ap_sig_bdd_2108 : BOOLEAN;
signal ap_sig_bdd_2156 : BOOLEAN;
signal ap_sig_bdd_1776 : BOOLEAN;
component image_filter_reg_int_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component image_filter_FAST_t_opr_k_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
component image_filter_FAST_t_opr_core_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
k_buf_val_0_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_0_V_address0,
ce0 => k_buf_val_0_V_ce0,
q0 => k_buf_val_0_V_q0,
address1 => k_buf_val_0_V_address1,
ce1 => k_buf_val_0_V_ce1,
we1 => k_buf_val_0_V_we1,
d1 => k_buf_val_0_V_d1);
k_buf_val_1_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_1_V_address0,
ce0 => k_buf_val_1_V_ce0,
q0 => k_buf_val_1_V_q0,
address1 => k_buf_val_1_V_address1,
ce1 => k_buf_val_1_V_ce1,
we1 => k_buf_val_1_V_we1,
d1 => k_buf_val_1_V_d1);
k_buf_val_2_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_2_V_address0,
ce0 => k_buf_val_2_V_ce0,
q0 => k_buf_val_2_V_q0,
address1 => k_buf_val_2_V_address1,
ce1 => k_buf_val_2_V_ce1,
we1 => k_buf_val_2_V_we1,
d1 => k_buf_val_2_V_d1);
k_buf_val_3_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_3_V_address0,
ce0 => k_buf_val_3_V_ce0,
q0 => k_buf_val_3_V_q0,
address1 => k_buf_val_3_V_address1,
ce1 => k_buf_val_3_V_ce1,
we1 => k_buf_val_3_V_we1,
d1 => k_buf_val_3_V_d1);
k_buf_val_4_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_4_V_address0,
ce0 => k_buf_val_4_V_ce0,
q0 => k_buf_val_4_V_q0,
address1 => k_buf_val_4_V_address1,
ce1 => k_buf_val_4_V_ce1,
we1 => k_buf_val_4_V_we1,
d1 => k_buf_val_4_V_d1);
k_buf_val_5_V_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_5_V_address0,
ce0 => k_buf_val_5_V_ce0,
q0 => k_buf_val_5_V_q0,
address1 => k_buf_val_5_V_address1,
ce1 => k_buf_val_5_V_ce1,
we1 => k_buf_val_5_V_we1,
d1 => k_buf_val_5_V_d1);
core_buf_val_0_V_U : component image_filter_FAST_t_opr_core_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1927,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => core_buf_val_0_V_address0,
ce0 => core_buf_val_0_V_ce0,
q0 => core_buf_val_0_V_q0,
address1 => core_buf_val_0_V_address1,
ce1 => core_buf_val_0_V_ce1,
we1 => core_buf_val_0_V_we1,
d1 => core_buf_val_0_V_d1);
core_buf_val_1_V_U : component image_filter_FAST_t_opr_core_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1927,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => core_buf_val_1_V_address0,
ce0 => core_buf_val_1_V_ce0,
q0 => core_buf_val_1_V_q0,
address1 => core_buf_val_1_V_address1,
ce1 => core_buf_val_1_V_ce1,
we1 => core_buf_val_1_V_we1,
d1 => core_buf_val_1_V_d1);
grp_image_filter_reg_int_s_fu_542 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_542_in_r,
ap_return => grp_image_filter_reg_int_s_fu_542_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_542_ap_ce);
grp_image_filter_reg_int_s_fu_547 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_547_in_r,
ap_return => grp_image_filter_reg_int_s_fu_547_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_547_ap_ce);
grp_image_filter_reg_int_s_fu_552 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_552_in_r,
ap_return => grp_image_filter_reg_int_s_fu_552_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_552_ap_ce);
grp_image_filter_reg_int_s_fu_557 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_557_in_r,
ap_return => grp_image_filter_reg_int_s_fu_557_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_557_ap_ce);
grp_image_filter_reg_int_s_fu_562 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_562_in_r,
ap_return => grp_image_filter_reg_int_s_fu_562_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_562_ap_ce);
grp_image_filter_reg_int_s_fu_567 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_567_in_r,
ap_return => grp_image_filter_reg_int_s_fu_567_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_567_ap_ce);
grp_image_filter_reg_int_s_fu_572 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_572_in_r,
ap_return => grp_image_filter_reg_int_s_fu_572_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_572_ap_ce);
grp_image_filter_reg_int_s_fu_577 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_577_in_r,
ap_return => grp_image_filter_reg_int_s_fu_577_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_577_ap_ce);
grp_image_filter_reg_int_s_fu_582 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_582_in_r,
ap_return => grp_image_filter_reg_int_s_fu_582_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_582_ap_ce);
grp_image_filter_reg_int_s_fu_587 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_587_in_r,
ap_return => grp_image_filter_reg_int_s_fu_587_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_587_ap_ce);
grp_image_filter_reg_int_s_fu_592 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_592_in_r,
ap_return => grp_image_filter_reg_int_s_fu_592_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_592_ap_ce);
grp_image_filter_reg_int_s_fu_597 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_597_in_r,
ap_return => grp_image_filter_reg_int_s_fu_597_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_597_ap_ce);
grp_image_filter_reg_int_s_fu_602 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_602_in_r,
ap_return => grp_image_filter_reg_int_s_fu_602_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_602_ap_ce);
grp_image_filter_reg_int_s_fu_607 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_607_in_r,
ap_return => grp_image_filter_reg_int_s_fu_607_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_607_ap_ce);
grp_image_filter_reg_int_s_fu_612 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_612_in_r,
ap_return => grp_image_filter_reg_int_s_fu_612_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_612_ap_ce);
grp_image_filter_reg_int_s_fu_617 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_617_in_r,
ap_return => grp_image_filter_reg_int_s_fu_617_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_617_ap_ce);
grp_image_filter_reg_int_s_fu_622 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_622_in_r,
ap_return => grp_image_filter_reg_int_s_fu_622_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_622_ap_ce);
grp_image_filter_reg_int_s_fu_627 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_627_in_r,
ap_return => grp_image_filter_reg_int_s_fu_627_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_627_ap_ce);
grp_image_filter_reg_int_s_fu_632 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_632_in_r,
ap_return => grp_image_filter_reg_int_s_fu_632_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_632_ap_ce);
grp_image_filter_reg_int_s_fu_637 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_637_in_r,
ap_return => grp_image_filter_reg_int_s_fu_637_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_637_ap_ce);
grp_image_filter_reg_int_s_fu_642 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_642_in_r,
ap_return => grp_image_filter_reg_int_s_fu_642_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_642_ap_ce);
grp_image_filter_reg_int_s_fu_647 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_647_in_r,
ap_return => grp_image_filter_reg_int_s_fu_647_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_647_ap_ce);
grp_image_filter_reg_int_s_fu_652 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_652_in_r,
ap_return => grp_image_filter_reg_int_s_fu_652_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_652_ap_ce);
grp_image_filter_reg_int_s_fu_657 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_657_in_r,
ap_return => grp_image_filter_reg_int_s_fu_657_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_657_ap_ce);
grp_image_filter_reg_int_s_fu_662 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_662_in_r,
ap_return => grp_image_filter_reg_int_s_fu_662_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_662_ap_ce);
grp_image_filter_reg_int_s_fu_667 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_667_in_r,
ap_return => grp_image_filter_reg_int_s_fu_667_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_667_ap_ce);
grp_image_filter_reg_int_s_fu_672 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_672_in_r,
ap_return => grp_image_filter_reg_int_s_fu_672_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_672_ap_ce);
grp_image_filter_reg_int_s_fu_677 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_677_in_r,
ap_return => grp_image_filter_reg_int_s_fu_677_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_677_ap_ce);
grp_image_filter_reg_int_s_fu_682 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_682_in_r,
ap_return => grp_image_filter_reg_int_s_fu_682_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_682_ap_ce);
grp_image_filter_reg_int_s_fu_687 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_687_in_r,
ap_return => grp_image_filter_reg_int_s_fu_687_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_687_ap_ce);
grp_image_filter_reg_int_s_fu_692 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_692_in_r,
ap_return => grp_image_filter_reg_int_s_fu_692_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_692_ap_ce);
grp_image_filter_reg_int_s_fu_697 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_697_in_r,
ap_return => grp_image_filter_reg_int_s_fu_697_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_697_ap_ce);
grp_image_filter_reg_int_s_fu_702 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_702_in_r,
ap_return => grp_image_filter_reg_int_s_fu_702_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_702_ap_ce);
grp_image_filter_reg_int_s_fu_707 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_707_in_r,
ap_return => grp_image_filter_reg_int_s_fu_707_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_707_ap_ce);
grp_image_filter_reg_int_s_fu_712 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_712_in_r,
ap_return => grp_image_filter_reg_int_s_fu_712_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_712_ap_ce);
grp_image_filter_reg_int_s_fu_717 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_717_in_r,
ap_return => grp_image_filter_reg_int_s_fu_717_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_717_ap_ce);
grp_image_filter_reg_int_s_fu_722 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_722_in_r,
ap_return => grp_image_filter_reg_int_s_fu_722_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_722_ap_ce);
grp_image_filter_reg_int_s_fu_727 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_727_in_r,
ap_return => grp_image_filter_reg_int_s_fu_727_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_727_ap_ce);
grp_image_filter_reg_int_s_fu_732 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_732_in_r,
ap_return => grp_image_filter_reg_int_s_fu_732_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_732_ap_ce);
grp_image_filter_reg_int_s_fu_737 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_737_in_r,
ap_return => grp_image_filter_reg_int_s_fu_737_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_737_ap_ce);
grp_image_filter_reg_int_s_fu_742 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_742_in_r,
ap_return => grp_image_filter_reg_int_s_fu_742_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_742_ap_ce);
grp_image_filter_reg_int_s_fu_747 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_747_in_r,
ap_return => grp_image_filter_reg_int_s_fu_747_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_747_ap_ce);
grp_image_filter_reg_int_s_fu_752 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_752_in_r,
ap_return => grp_image_filter_reg_int_s_fu_752_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_752_ap_ce);
grp_image_filter_reg_int_s_fu_757 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_757_in_r,
ap_return => grp_image_filter_reg_int_s_fu_757_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_757_ap_ce);
grp_image_filter_reg_int_s_fu_762 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_762_in_r,
ap_return => grp_image_filter_reg_int_s_fu_762_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_762_ap_ce);
grp_image_filter_reg_int_s_fu_767 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_767_in_r,
ap_return => grp_image_filter_reg_int_s_fu_767_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_767_ap_ce);
grp_image_filter_reg_int_s_fu_772 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_772_in_r,
ap_return => grp_image_filter_reg_int_s_fu_772_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_772_ap_ce);
grp_image_filter_reg_int_s_fu_777 : component image_filter_reg_int_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
in_r => grp_image_filter_reg_int_s_fu_777_in_r,
ap_return => grp_image_filter_reg_int_s_fu_777_ap_return,
ap_ce => grp_image_filter_reg_int_s_fu_777_ap_ce);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_lv1_0 = exitcond_fu_846_p2)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it23 assign process. --
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it24 assign process. --
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it25 assign process. --
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it26 assign process. --
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it27 assign process. --
ap_reg_ppiten_pp0_it27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it28 assign process. --
ap_reg_ppiten_pp0_it28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it29 assign process. --
ap_reg_ppiten_pp0_it29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it30 assign process. --
ap_reg_ppiten_pp0_it30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it31 assign process. --
ap_reg_ppiten_pp0_it31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it32 assign process. --
ap_reg_ppiten_pp0_it32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it33 assign process. --
ap_reg_ppiten_pp0_it33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it34 assign process. --
ap_reg_ppiten_pp0_it34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it35 assign process. --
ap_reg_ppiten_pp0_it35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2)) or (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33))))) then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it1 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_250) then
if (ap_sig_bdd_2152) then
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_const_lv8_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_reg_phiprechg_core_1_reg_527pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it13 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it13_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_2108) then
if (ap_sig_bdd_2159) then
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_const_lv8_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_reg_phiprechg_core_1_reg_527pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_core_1_reg_527pp0_it34 assign process. --
ap_reg_phiprechg_core_1_reg_527pp0_it34_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_1776) then
if (ap_sig_bdd_2156) then
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= phitmp2_fu_4606_p2;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= ap_reg_phiprechg_core_1_reg_527pp0_it33;
end if;
end if;
end if;
end process;
-- p_2_reg_515 assign process. --
p_2_reg_515_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_2_reg_515 <= j_V_reg_5151;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
p_2_reg_515 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_s_reg_504 assign process. --
p_s_reg_504_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_3)) then
p_s_reg_504 <= i_V_reg_5122;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_180))) then
p_s_reg_504 <= ap_const_lv11_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))) then
a0_2_reg_6285 <= a0_2_fu_3841_p3;
b0_2_reg_6301 <= b0_2_fu_3882_p3;
tmp_232_2_reg_6291 <= tmp_232_2_fu_3853_p3;
tmp_239_2_reg_6307 <= tmp_239_2_fu_3894_p3;
tmp_59_reg_6296 <= tmp_59_fu_3860_p1;
tmp_85_reg_6312 <= tmp_85_fu_3901_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)))) then
a0_2_tmp_232_2_reg_6337 <= a0_2_tmp_232_2_fu_3916_p3;
b0_2_tmp_239_2_reg_6348 <= b0_2_tmp_239_2_fu_3936_p3;
tmp_209_3_reg_6343 <= tmp_209_3_fu_3922_p2;
tmp_221_3_reg_6354 <= tmp_221_3_fu_3942_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))) then
a0_3_reg_6359 <= a0_3_fu_3969_p3;
b0_3_reg_6375 <= b0_3_fu_4010_p3;
tmp_232_3_reg_6365 <= tmp_232_3_fu_3981_p3;
tmp_239_3_reg_6381 <= tmp_239_3_fu_4022_p3;
tmp_61_reg_6370 <= tmp_61_fu_3988_p1;
tmp_87_reg_6386 <= tmp_87_fu_4029_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)))) then
a0_3_tmp_232_3_reg_6411 <= a0_3_tmp_232_3_fu_4044_p3;
b0_3_tmp_239_3_reg_6422 <= b0_3_tmp_239_3_fu_4064_p3;
tmp_209_4_reg_6417 <= tmp_209_4_fu_4050_p2;
tmp_221_4_reg_6428 <= tmp_221_4_fu_4070_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))) then
a0_4_reg_6433 <= a0_4_fu_4097_p3;
b0_4_reg_6449 <= b0_4_fu_4138_p3;
tmp_232_4_reg_6439 <= tmp_232_4_fu_4109_p3;
tmp_239_4_reg_6455 <= tmp_239_4_fu_4150_p3;
tmp_63_reg_6444 <= tmp_63_fu_4116_p1;
tmp_89_reg_6460 <= tmp_89_fu_4157_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)))) then
a0_4_tmp_232_4_reg_6485 <= a0_4_tmp_232_4_fu_4172_p3;
b0_4_tmp_239_4_reg_6496 <= b0_4_tmp_239_4_fu_4192_p3;
tmp_209_5_reg_6491 <= tmp_209_5_fu_4178_p2;
tmp_221_5_reg_6502 <= tmp_221_5_fu_4198_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))) then
a0_5_reg_6507 <= a0_5_fu_4225_p3;
b0_5_reg_6523 <= b0_5_fu_4266_p3;
tmp_232_5_reg_6513 <= tmp_232_5_fu_4237_p3;
tmp_239_5_reg_6529 <= tmp_239_5_fu_4278_p3;
tmp_65_reg_6518 <= tmp_65_fu_4244_p1;
tmp_91_reg_6534 <= tmp_91_fu_4285_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)))) then
a0_5_tmp_232_5_reg_6559 <= a0_5_tmp_232_5_fu_4300_p3;
b0_5_tmp_239_5_reg_6570 <= b0_5_tmp_239_5_fu_4320_p3;
tmp_209_6_reg_6565 <= tmp_209_6_fu_4306_p2;
tmp_221_6_reg_6576 <= tmp_221_6_fu_4326_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))) then
a0_6_reg_6581 <= a0_6_fu_4353_p3;
b0_6_reg_6597 <= b0_6_fu_4394_p3;
tmp_232_6_reg_6587 <= tmp_232_6_fu_4365_p3;
tmp_239_6_reg_6603 <= tmp_239_6_fu_4406_p3;
tmp_75_reg_6592 <= tmp_75_fu_4372_p1;
tmp_93_reg_6608 <= tmp_93_fu_4413_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)))) then
a0_6_tmp_232_6_reg_6633 <= a0_6_tmp_232_6_fu_4428_p3;
b0_6_tmp_239_6_reg_6644 <= b0_6_tmp_239_6_fu_4448_p3;
tmp_209_7_reg_6639 <= tmp_209_7_fu_4434_p2;
tmp_221_7_reg_6650 <= tmp_221_7_fu_4454_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it29) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it29)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it29)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29)))) then
a0_7_reg_6655 <= a0_7_fu_4481_p3;
b0_7_reg_6671 <= b0_7_fu_4522_p3;
tmp_232_7_reg_6661 <= tmp_232_7_fu_4493_p3;
tmp_239_7_reg_6676 <= tmp_239_7_fu_4534_p3;
tmp_78_reg_6666 <= tmp_78_fu_4500_p1;
tmp_95_reg_6681 <= tmp_95_fu_4541_p1;
tmp_96_reg_6686 <= tmp_96_fu_4545_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it30) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it30)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it30)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30)))) then
a0_7_tmp_232_7_reg_6691 <= a0_7_tmp_232_7_fu_4557_p3;
tmp_79_reg_6697 <= tmp_79_fu_4571_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))) then
a0_s_reg_6211 <= a0_s_fu_3713_p3;
b0_s_reg_6227 <= b0_s_fu_3754_p3;
tmp_232_1_reg_6217 <= tmp_232_1_fu_3725_p3;
tmp_239_1_reg_6233 <= tmp_239_1_fu_3766_p3;
tmp_57_reg_6222 <= tmp_57_fu_3732_p1;
tmp_83_reg_6238 <= tmp_83_fu_3773_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)))) then
a0_tmp_232_1_reg_6263 <= a0_tmp_232_1_fu_3788_p3;
b0_tmp_239_1_reg_6274 <= b0_tmp_239_1_fu_3808_p3;
tmp_209_2_reg_6269 <= tmp_209_2_fu_3794_p2;
tmp_221_2_reg_6280 <= tmp_221_2_fu_3814_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it10 <= ap_reg_phiprechg_core_1_reg_527pp0_it9;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it11 <= ap_reg_phiprechg_core_1_reg_527pp0_it10;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it12 <= ap_reg_phiprechg_core_1_reg_527pp0_it11;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it13) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it14 <= ap_reg_phiprechg_core_1_reg_527pp0_it13;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it15 <= ap_reg_phiprechg_core_1_reg_527pp0_it14;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it15) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it16 <= ap_reg_phiprechg_core_1_reg_527pp0_it15;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it16) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it17 <= ap_reg_phiprechg_core_1_reg_527pp0_it16;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it17) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it18 <= ap_reg_phiprechg_core_1_reg_527pp0_it17;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it18) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it19 <= ap_reg_phiprechg_core_1_reg_527pp0_it18;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it2 <= ap_reg_phiprechg_core_1_reg_527pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it19) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it20 <= ap_reg_phiprechg_core_1_reg_527pp0_it19;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it20) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it21 <= ap_reg_phiprechg_core_1_reg_527pp0_it20;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it21) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it22 <= ap_reg_phiprechg_core_1_reg_527pp0_it21;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it22) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it23 <= ap_reg_phiprechg_core_1_reg_527pp0_it22;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it23) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it24 <= ap_reg_phiprechg_core_1_reg_527pp0_it23;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it24) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it25 <= ap_reg_phiprechg_core_1_reg_527pp0_it24;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it25) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it26 <= ap_reg_phiprechg_core_1_reg_527pp0_it25;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it27 <= ap_reg_phiprechg_core_1_reg_527pp0_it26;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it27) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it28 <= ap_reg_phiprechg_core_1_reg_527pp0_it27;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it28) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it29 <= ap_reg_phiprechg_core_1_reg_527pp0_it28;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it3 <= ap_reg_phiprechg_core_1_reg_527pp0_it2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it29) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it30 <= ap_reg_phiprechg_core_1_reg_527pp0_it29;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it30) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it31 <= ap_reg_phiprechg_core_1_reg_527pp0_it30;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it31) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it32 <= ap_reg_phiprechg_core_1_reg_527pp0_it31;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it33 <= ap_reg_phiprechg_core_1_reg_527pp0_it32;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it4 <= ap_reg_phiprechg_core_1_reg_527pp0_it3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it5 <= ap_reg_phiprechg_core_1_reg_527pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it6 <= ap_reg_phiprechg_core_1_reg_527pp0_it5;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it6) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it7 <= ap_reg_phiprechg_core_1_reg_527pp0_it6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it8 <= ap_reg_phiprechg_core_1_reg_527pp0_it7;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_phiprechg_core_1_reg_527pp0_it9 <= ap_reg_phiprechg_core_1_reg_527pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))) then
ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 <= core_buf_val_1_V_addr_reg_6708;
ap_reg_ppstg_exitcond_reg_5147_pp0_it10 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it9;
ap_reg_ppstg_exitcond_reg_5147_pp0_it11 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it10;
ap_reg_ppstg_exitcond_reg_5147_pp0_it12 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it11;
ap_reg_ppstg_exitcond_reg_5147_pp0_it13 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it12;
ap_reg_ppstg_exitcond_reg_5147_pp0_it14 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it13;
ap_reg_ppstg_exitcond_reg_5147_pp0_it15 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it14;
ap_reg_ppstg_exitcond_reg_5147_pp0_it16 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it15;
ap_reg_ppstg_exitcond_reg_5147_pp0_it17 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it16;
ap_reg_ppstg_exitcond_reg_5147_pp0_it18 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it17;
ap_reg_ppstg_exitcond_reg_5147_pp0_it19 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it18;
ap_reg_ppstg_exitcond_reg_5147_pp0_it2 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it1;
ap_reg_ppstg_exitcond_reg_5147_pp0_it20 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it19;
ap_reg_ppstg_exitcond_reg_5147_pp0_it21 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it20;
ap_reg_ppstg_exitcond_reg_5147_pp0_it22 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it21;
ap_reg_ppstg_exitcond_reg_5147_pp0_it23 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it22;
ap_reg_ppstg_exitcond_reg_5147_pp0_it24 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it23;
ap_reg_ppstg_exitcond_reg_5147_pp0_it25 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it24;
ap_reg_ppstg_exitcond_reg_5147_pp0_it26 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it25;
ap_reg_ppstg_exitcond_reg_5147_pp0_it27 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it26;
ap_reg_ppstg_exitcond_reg_5147_pp0_it28 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it27;
ap_reg_ppstg_exitcond_reg_5147_pp0_it29 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it28;
ap_reg_ppstg_exitcond_reg_5147_pp0_it3 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it2;
ap_reg_ppstg_exitcond_reg_5147_pp0_it30 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it29;
ap_reg_ppstg_exitcond_reg_5147_pp0_it31 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it30;
ap_reg_ppstg_exitcond_reg_5147_pp0_it32 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it31;
ap_reg_ppstg_exitcond_reg_5147_pp0_it33 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it32;
ap_reg_ppstg_exitcond_reg_5147_pp0_it4 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it3;
ap_reg_ppstg_exitcond_reg_5147_pp0_it5 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it4;
ap_reg_ppstg_exitcond_reg_5147_pp0_it6 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it5;
ap_reg_ppstg_exitcond_reg_5147_pp0_it7 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it6;
ap_reg_ppstg_exitcond_reg_5147_pp0_it8 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it7;
ap_reg_ppstg_exitcond_reg_5147_pp0_it9 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it8;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 <= flag_d_max2_1_reg_5959;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 <= ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14;
ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 <= flag_d_max2_7_reg_5971;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 <= flag_d_max4_1_reg_5993;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 <= ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 <= flag_d_max4_5_reg_6005;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 <= ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 <= flag_d_min2_1_reg_5953;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 <= ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14;
ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 <= flag_d_min2_7_reg_5965;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 <= flag_d_min4_1_reg_5987;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 <= ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 <= flag_d_min4_5_reg_5999;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 <= ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 <= flag_val_V_assign_load_1_s_reg_5417;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 <= ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 <= iscorner_2_i_s_reg_5949;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 <= not_or_cond10_demorgan_reg_5699;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 <= not_or_cond11_demorgan_reg_5704;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 <= not_or_cond6_demorgan_reg_5605;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 <= not_or_cond7_demorgan_reg_5610;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 <= not_or_cond8_demorgan_reg_5615;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 <= not_or_cond9_demorgan_reg_5620;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 <= not_or_cond_reg_5733;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it9;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it10;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it11;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it12;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it13;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it14;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it15;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it16;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it17;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it18;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it1;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it19;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it20;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it21;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it22;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it23;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it24;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it25;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it26;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it27;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it28;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it2;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it29;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it30;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it31;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it3;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it4;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it5;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it6;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it7;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it8;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 <= or_cond2_reg_5660;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it5;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it6;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it7;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it8;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it9;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it10;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it11;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it12;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it13;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it14;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it15;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it16;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it17;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it18;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it1;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it19;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it20;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it21;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it22;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it23;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it24;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it25;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it26;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it27;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it28;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it2;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it29;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it30;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it31;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it32;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it33;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it3;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it4;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it5;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it6;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it7;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it8;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 <= or_cond5_reg_5537;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it4;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it5;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it6;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 <= or_cond6_reg_5543;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it4;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it5;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it6;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 <= or_cond7_reg_5548;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it4;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it5;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 <= or_cond8_reg_5553;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it4;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it5;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it7;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 <= or_cond9_reg_5559;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it4;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it5;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it6;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it10 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it9;
ap_reg_ppstg_or_cond_reg_5156_pp0_it11 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it10;
ap_reg_ppstg_or_cond_reg_5156_pp0_it12 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it11;
ap_reg_ppstg_or_cond_reg_5156_pp0_it13 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it12;
ap_reg_ppstg_or_cond_reg_5156_pp0_it14 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it13;
ap_reg_ppstg_or_cond_reg_5156_pp0_it15 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it14;
ap_reg_ppstg_or_cond_reg_5156_pp0_it16 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it15;
ap_reg_ppstg_or_cond_reg_5156_pp0_it17 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it16;
ap_reg_ppstg_or_cond_reg_5156_pp0_it18 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it17;
ap_reg_ppstg_or_cond_reg_5156_pp0_it19 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it18;
ap_reg_ppstg_or_cond_reg_5156_pp0_it2 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it1;
ap_reg_ppstg_or_cond_reg_5156_pp0_it20 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it19;
ap_reg_ppstg_or_cond_reg_5156_pp0_it21 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it20;
ap_reg_ppstg_or_cond_reg_5156_pp0_it22 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it21;
ap_reg_ppstg_or_cond_reg_5156_pp0_it23 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it22;
ap_reg_ppstg_or_cond_reg_5156_pp0_it24 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it23;
ap_reg_ppstg_or_cond_reg_5156_pp0_it25 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it24;
ap_reg_ppstg_or_cond_reg_5156_pp0_it26 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it25;
ap_reg_ppstg_or_cond_reg_5156_pp0_it27 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it26;
ap_reg_ppstg_or_cond_reg_5156_pp0_it28 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it27;
ap_reg_ppstg_or_cond_reg_5156_pp0_it29 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it28;
ap_reg_ppstg_or_cond_reg_5156_pp0_it3 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it2;
ap_reg_ppstg_or_cond_reg_5156_pp0_it30 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it29;
ap_reg_ppstg_or_cond_reg_5156_pp0_it31 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it30;
ap_reg_ppstg_or_cond_reg_5156_pp0_it32 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it31;
ap_reg_ppstg_or_cond_reg_5156_pp0_it33 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it32;
ap_reg_ppstg_or_cond_reg_5156_pp0_it4 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it3;
ap_reg_ppstg_or_cond_reg_5156_pp0_it5 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it4;
ap_reg_ppstg_or_cond_reg_5156_pp0_it6 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it5;
ap_reg_ppstg_or_cond_reg_5156_pp0_it7 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it6;
ap_reg_ppstg_or_cond_reg_5156_pp0_it8 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it9 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it8;
ap_reg_ppstg_p_2_reg_515_pp0_it10 <= ap_reg_ppstg_p_2_reg_515_pp0_it9;
ap_reg_ppstg_p_2_reg_515_pp0_it11 <= ap_reg_ppstg_p_2_reg_515_pp0_it10;
ap_reg_ppstg_p_2_reg_515_pp0_it12 <= ap_reg_ppstg_p_2_reg_515_pp0_it11;
ap_reg_ppstg_p_2_reg_515_pp0_it13 <= ap_reg_ppstg_p_2_reg_515_pp0_it12;
ap_reg_ppstg_p_2_reg_515_pp0_it14 <= ap_reg_ppstg_p_2_reg_515_pp0_it13;
ap_reg_ppstg_p_2_reg_515_pp0_it15 <= ap_reg_ppstg_p_2_reg_515_pp0_it14;
ap_reg_ppstg_p_2_reg_515_pp0_it16 <= ap_reg_ppstg_p_2_reg_515_pp0_it15;
ap_reg_ppstg_p_2_reg_515_pp0_it17 <= ap_reg_ppstg_p_2_reg_515_pp0_it16;
ap_reg_ppstg_p_2_reg_515_pp0_it18 <= ap_reg_ppstg_p_2_reg_515_pp0_it17;
ap_reg_ppstg_p_2_reg_515_pp0_it19 <= ap_reg_ppstg_p_2_reg_515_pp0_it18;
ap_reg_ppstg_p_2_reg_515_pp0_it2 <= ap_reg_ppstg_p_2_reg_515_pp0_it1;
ap_reg_ppstg_p_2_reg_515_pp0_it20 <= ap_reg_ppstg_p_2_reg_515_pp0_it19;
ap_reg_ppstg_p_2_reg_515_pp0_it21 <= ap_reg_ppstg_p_2_reg_515_pp0_it20;
ap_reg_ppstg_p_2_reg_515_pp0_it22 <= ap_reg_ppstg_p_2_reg_515_pp0_it21;
ap_reg_ppstg_p_2_reg_515_pp0_it23 <= ap_reg_ppstg_p_2_reg_515_pp0_it22;
ap_reg_ppstg_p_2_reg_515_pp0_it24 <= ap_reg_ppstg_p_2_reg_515_pp0_it23;
ap_reg_ppstg_p_2_reg_515_pp0_it25 <= ap_reg_ppstg_p_2_reg_515_pp0_it24;
ap_reg_ppstg_p_2_reg_515_pp0_it26 <= ap_reg_ppstg_p_2_reg_515_pp0_it25;
ap_reg_ppstg_p_2_reg_515_pp0_it27 <= ap_reg_ppstg_p_2_reg_515_pp0_it26;
ap_reg_ppstg_p_2_reg_515_pp0_it28 <= ap_reg_ppstg_p_2_reg_515_pp0_it27;
ap_reg_ppstg_p_2_reg_515_pp0_it29 <= ap_reg_ppstg_p_2_reg_515_pp0_it28;
ap_reg_ppstg_p_2_reg_515_pp0_it3 <= ap_reg_ppstg_p_2_reg_515_pp0_it2;
ap_reg_ppstg_p_2_reg_515_pp0_it30 <= ap_reg_ppstg_p_2_reg_515_pp0_it29;
ap_reg_ppstg_p_2_reg_515_pp0_it31 <= ap_reg_ppstg_p_2_reg_515_pp0_it30;
ap_reg_ppstg_p_2_reg_515_pp0_it4 <= ap_reg_ppstg_p_2_reg_515_pp0_it3;
ap_reg_ppstg_p_2_reg_515_pp0_it5 <= ap_reg_ppstg_p_2_reg_515_pp0_it4;
ap_reg_ppstg_p_2_reg_515_pp0_it6 <= ap_reg_ppstg_p_2_reg_515_pp0_it5;
ap_reg_ppstg_p_2_reg_515_pp0_it7 <= ap_reg_ppstg_p_2_reg_515_pp0_it6;
ap_reg_ppstg_p_2_reg_515_pp0_it8 <= ap_reg_ppstg_p_2_reg_515_pp0_it7;
ap_reg_ppstg_p_2_reg_515_pp0_it9 <= ap_reg_ppstg_p_2_reg_515_pp0_it8;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 <= r_V_1_1_reg_5432;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 <= r_V_1_2_reg_5452;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 <= r_V_1_3_reg_5472;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 <= r_V_1_4_reg_5483;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 <= r_V_1_5_reg_5494;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 <= r_V_1_6_reg_5505;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 <= r_V_1_7_reg_5516;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it9;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it10;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it12;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it13;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it14;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it15;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it16;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it17;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it18;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it19;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it20;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it21;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 <= r_V_1_reg_5408;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it4;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it5;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it6;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it7;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it8;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it9;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it10;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it12;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it13;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it14;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it15;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 <= r_V_2_reg_5290;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it3;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it4;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it5;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it6;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it7;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it8;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it9;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it10;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it11;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it12;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it13;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it14;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it15;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it16;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it17;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it18;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it19;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it20;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it21;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it22;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it23;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it24;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 <= r_V_3_reg_5309;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it3;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it4;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it5;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it6;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it7;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it8;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it9;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it10;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it12;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it13;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it14;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it15;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it16;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it17;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 <= r_V_4_reg_5328;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it3;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it4;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it5;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it6;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it7;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it8;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it9;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it10;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it11;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it12;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it13;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it14;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it15;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it16;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it17;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it18;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it19;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it20;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it21;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it22;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it23;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it24;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it25;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it26;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 <= r_V_5_reg_5348;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it3;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it4;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it5;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it6;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it7;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it8;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it9;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it10;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it12;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it13;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it14;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it15;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it16;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it17;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it18;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it19;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 <= r_V_6_reg_5368;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it3;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it4;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it5;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it6;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it7;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it8;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it9;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it10;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it11;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it12;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it13;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it14;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it15;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it16;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it17;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it18;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it19;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it20;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it21;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it22;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it23;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it24;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it25;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it26;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it27;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it28;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 <= r_V_7_reg_5388;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it3;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it4;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it5;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it6;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it7;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it8;
ap_reg_ppstg_r_V_reg_5252_pp0_it10 <= ap_reg_ppstg_r_V_reg_5252_pp0_it9;
ap_reg_ppstg_r_V_reg_5252_pp0_it11 <= ap_reg_ppstg_r_V_reg_5252_pp0_it10;
ap_reg_ppstg_r_V_reg_5252_pp0_it12 <= ap_reg_ppstg_r_V_reg_5252_pp0_it11;
ap_reg_ppstg_r_V_reg_5252_pp0_it13 <= ap_reg_ppstg_r_V_reg_5252_pp0_it12;
ap_reg_ppstg_r_V_reg_5252_pp0_it14 <= ap_reg_ppstg_r_V_reg_5252_pp0_it13;
ap_reg_ppstg_r_V_reg_5252_pp0_it3 <= r_V_reg_5252;
ap_reg_ppstg_r_V_reg_5252_pp0_it4 <= ap_reg_ppstg_r_V_reg_5252_pp0_it3;
ap_reg_ppstg_r_V_reg_5252_pp0_it5 <= ap_reg_ppstg_r_V_reg_5252_pp0_it4;
ap_reg_ppstg_r_V_reg_5252_pp0_it6 <= ap_reg_ppstg_r_V_reg_5252_pp0_it5;
ap_reg_ppstg_r_V_reg_5252_pp0_it7 <= ap_reg_ppstg_r_V_reg_5252_pp0_it6;
ap_reg_ppstg_r_V_reg_5252_pp0_it8 <= ap_reg_ppstg_r_V_reg_5252_pp0_it7;
ap_reg_ppstg_r_V_reg_5252_pp0_it9 <= ap_reg_ppstg_r_V_reg_5252_pp0_it8;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it9;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it10;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it11;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it12;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it13;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it14;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it15;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it16;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it17;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it18;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it19;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it20;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it21;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it22;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 <= r_V_s_reg_5271;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it3;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it4;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it5;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it6;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it7;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it8;
ap_reg_ppstg_tmp11_reg_5934_pp0_it11 <= tmp11_reg_5934;
ap_reg_ppstg_tmp12_reg_5883_pp0_it9 <= tmp12_reg_5883;
ap_reg_ppstg_tmp3_reg_5878_pp0_it10 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it9;
ap_reg_ppstg_tmp3_reg_5878_pp0_it11 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it10;
ap_reg_ppstg_tmp3_reg_5878_pp0_it9 <= tmp3_reg_5878;
ap_reg_ppstg_tmp5_reg_5781_pp0_it6 <= tmp5_reg_5781;
ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 <= tmp_200_3_reg_5977;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 <= tmp_210_2_reg_6169;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 <= tmp_210_4_reg_6179;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 <= tmp_210_7_reg_6139;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 <= tmp_210_9_reg_6149;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 <= tmp_210_s_reg_6159;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22;
ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 <= tmp_213_3_reg_5982;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 <= tmp_225_2_reg_6174;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 <= tmp_225_4_reg_6184;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 <= tmp_225_7_reg_6144;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 <= tmp_225_9_reg_6154;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 <= tmp_225_s_reg_6164;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 <= tmp_39_reg_5532;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 <= ap_reg_ppstg_tmp_39_reg_5532_pp0_it4;
ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 <= tmp_53_reg_6719;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
ap_reg_ppstg_exitcond_reg_5147_pp0_it1 <= exitcond_reg_5147;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 <= or_cond1_reg_5197;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 <= or_cond4_reg_5201;
ap_reg_ppstg_or_cond_reg_5156_pp0_it1 <= or_cond_reg_5156;
ap_reg_ppstg_p_2_reg_515_pp0_it1 <= p_2_reg_515;
exitcond_reg_5147 <= exitcond_fu_846_p2;
win_val_0_V_2_1_reg_5205 <= win_val_0_V_2_fu_172;
win_val_1_V_4_3_reg_5210 <= win_val_1_V_4_fu_204;
win_val_2_V_5_3_reg_5215 <= win_val_2_V_5_fu_236;
win_val_3_V_2_3_reg_5220 <= win_val_3_V_2_fu_252;
win_val_4_V_5_3_reg_5225 <= win_val_4_V_5_fu_292;
win_val_5_V_4_3_reg_5230 <= win_val_5_V_4_fu_312;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it15)))) then
b0_reg_6093 <= b0_fu_3473_p3;
p_a_0_flag_d_assign_load_5_reg_6077 <= p_a_0_flag_d_assign_load_5_fu_3434_p3;
tmp_47_reg_6083 <= tmp_47_fu_3447_p3;
tmp_48_reg_6088 <= tmp_48_fu_3454_p1;
tmp_71_reg_6099 <= tmp_71_fu_3486_p3;
tmp_81_reg_6104 <= tmp_81_fu_3493_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))) then
b0_tmp_s_reg_6200 <= b0_tmp_s_fu_3680_p3;
p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 <= p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3;
tmp_209_1_reg_6195 <= tmp_209_1_fu_3666_p2;
tmp_221_1_reg_6206 <= tmp_221_1_fu_3686_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it31))) then
core_buf_val_0_V_addr_reg_6702 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_1_V_addr_reg_6708 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
tmp_53_reg_6719 <= tmp_53_fu_4600_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32))) then
core_buf_val_0_V_load_reg_6724 <= core_buf_val_0_V_q0;
core_buf_val_1_V_load_reg_6729 <= core_buf_val_1_V_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) then
core_win_val_0_V_0_fu_136(0) <= core_win_val_0_V_1_fu_140(0);
core_win_val_0_V_0_fu_136(1) <= core_win_val_0_V_1_fu_140(1);
core_win_val_0_V_0_fu_136(2) <= core_win_val_0_V_1_fu_140(2);
core_win_val_0_V_0_fu_136(3) <= core_win_val_0_V_1_fu_140(3);
core_win_val_0_V_0_fu_136(4) <= core_win_val_0_V_1_fu_140(4);
core_win_val_0_V_0_fu_136(5) <= core_win_val_0_V_1_fu_140(5);
core_win_val_0_V_0_fu_136(6) <= core_win_val_0_V_1_fu_140(6);
core_win_val_0_V_0_fu_136(7) <= core_win_val_0_V_1_fu_140(7);
core_win_val_0_V_1_fu_140(0) <= core_win_val_0_V_2_fu_4620_p1(0);
core_win_val_0_V_1_fu_140(1) <= core_win_val_0_V_2_fu_4620_p1(1);
core_win_val_0_V_1_fu_140(2) <= core_win_val_0_V_2_fu_4620_p1(2);
core_win_val_0_V_1_fu_140(3) <= core_win_val_0_V_2_fu_4620_p1(3);
core_win_val_0_V_1_fu_140(4) <= core_win_val_0_V_2_fu_4620_p1(4);
core_win_val_0_V_1_fu_140(5) <= core_win_val_0_V_2_fu_4620_p1(5);
core_win_val_0_V_1_fu_140(6) <= core_win_val_0_V_2_fu_4620_p1(6);
core_win_val_0_V_1_fu_140(7) <= core_win_val_0_V_2_fu_4620_p1(7);
core_win_val_1_V_0_fu_148(0) <= core_win_val_1_V_1_fu_152(0);
core_win_val_1_V_0_fu_148(1) <= core_win_val_1_V_1_fu_152(1);
core_win_val_1_V_0_fu_148(2) <= core_win_val_1_V_1_fu_152(2);
core_win_val_1_V_0_fu_148(3) <= core_win_val_1_V_1_fu_152(3);
core_win_val_1_V_0_fu_148(4) <= core_win_val_1_V_1_fu_152(4);
core_win_val_1_V_0_fu_148(5) <= core_win_val_1_V_1_fu_152(5);
core_win_val_1_V_0_fu_148(6) <= core_win_val_1_V_1_fu_152(6);
core_win_val_1_V_0_fu_148(7) <= core_win_val_1_V_1_fu_152(7);
core_win_val_1_V_1_fu_152(0) <= core_win_val_1_V_2_fu_4623_p1(0);
core_win_val_1_V_1_fu_152(1) <= core_win_val_1_V_2_fu_4623_p1(1);
core_win_val_1_V_1_fu_152(2) <= core_win_val_1_V_2_fu_4623_p1(2);
core_win_val_1_V_1_fu_152(3) <= core_win_val_1_V_2_fu_4623_p1(3);
core_win_val_1_V_1_fu_152(4) <= core_win_val_1_V_2_fu_4623_p1(4);
core_win_val_1_V_1_fu_152(5) <= core_win_val_1_V_2_fu_4623_p1(5);
core_win_val_1_V_1_fu_152(6) <= core_win_val_1_V_2_fu_4623_p1(6);
core_win_val_1_V_1_fu_152(7) <= core_win_val_1_V_2_fu_4623_p1(7);
core_win_val_2_V_0_fu_160(0) <= core_win_val_2_V_1_fu_164(0);
core_win_val_2_V_0_fu_160(1) <= core_win_val_2_V_1_fu_164(1);
core_win_val_2_V_0_fu_160(2) <= core_win_val_2_V_1_fu_164(2);
core_win_val_2_V_0_fu_160(3) <= core_win_val_2_V_1_fu_164(3);
core_win_val_2_V_0_fu_160(4) <= core_win_val_2_V_1_fu_164(4);
core_win_val_2_V_0_fu_160(5) <= core_win_val_2_V_1_fu_164(5);
core_win_val_2_V_0_fu_160(6) <= core_win_val_2_V_1_fu_164(6);
core_win_val_2_V_0_fu_160(7) <= core_win_val_2_V_1_fu_164(7);
core_win_val_2_V_1_fu_164(0) <= core_win_val_2_V_1_2_fu_4643_p1(0);
core_win_val_2_V_1_fu_164(1) <= core_win_val_2_V_1_2_fu_4643_p1(1);
core_win_val_2_V_1_fu_164(2) <= core_win_val_2_V_1_2_fu_4643_p1(2);
core_win_val_2_V_1_fu_164(3) <= core_win_val_2_V_1_2_fu_4643_p1(3);
core_win_val_2_V_1_fu_164(4) <= core_win_val_2_V_1_2_fu_4643_p1(4);
core_win_val_2_V_1_fu_164(5) <= core_win_val_2_V_1_2_fu_4643_p1(5);
core_win_val_2_V_1_fu_164(6) <= core_win_val_2_V_1_2_fu_4643_p1(6);
core_win_val_2_V_1_fu_164(7) <= core_win_val_2_V_1_2_fu_4643_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it2)))) then
count_1_i_0_op_op87_op_reg_5590(0) <= count_1_i_0_op_op87_op_fu_1848_p3(0);
flag_val_V_assign_load_1_13_reg_5527 <= flag_val_V_assign_load_1_13_fu_1726_p3;
flag_val_V_assign_load_1_s_reg_5417 <= flag_val_V_assign_load_1_s_fu_1521_p3;
not_or_cond6_demorgan_reg_5605 <= not_or_cond6_demorgan_fu_1870_p2;
not_or_cond7_demorgan_reg_5610 <= not_or_cond7_demorgan_fu_1876_p2;
not_or_cond8_demorgan_reg_5615 <= not_or_cond8_demorgan_fu_1882_p2;
not_or_cond9_demorgan_reg_5620 <= not_or_cond9_demorgan_fu_1888_p2;
or_cond5_reg_5537 <= or_cond5_fu_1746_p2;
or_cond6_reg_5543 <= or_cond6_fu_1764_p2;
or_cond7_reg_5548 <= or_cond7_fu_1782_p2;
or_cond8_reg_5553 <= or_cond8_fu_1800_p2;
or_cond9_reg_5559 <= or_cond9_fu_1818_p2;
phitmp3_reg_5422 <= phitmp3_fu_1539_p3;
phitmp43_op_op_cast_cast_cast_reg_5595(0) <= phitmp43_op_op_cast_cast_cast_fu_1856_p3(0);
r_V_1_1_reg_5432 <= r_V_1_1_fu_1557_p2;
r_V_1_2_reg_5452 <= r_V_1_2_fu_1584_p2;
r_V_1_3_reg_5472 <= r_V_1_3_fu_1611_p2;
r_V_1_4_reg_5483 <= r_V_1_4_fu_1626_p2;
r_V_1_5_reg_5494 <= r_V_1_5_fu_1654_p2;
r_V_1_6_reg_5505 <= r_V_1_6_fu_1682_p2;
r_V_1_7_reg_5516 <= r_V_1_7_fu_1710_p2;
r_V_1_reg_5408 <= r_V_1_fu_1516_p2;
tmp_181_5_not_reg_5566 <= tmp_181_5_not_fu_1824_p2;
tmp_181_6_not_reg_5578 <= tmp_181_6_not_fu_1836_p2;
tmp_182_1_reg_5441 <= tmp_182_1_fu_1568_p2;
tmp_182_2_reg_5461 <= tmp_182_2_fu_1595_p2;
tmp_183_5_reg_5572 <= tmp_183_5_fu_1830_p2;
tmp_183_6_reg_5584 <= tmp_183_6_fu_1842_p2;
tmp_184_1_reg_5447 <= tmp_184_1_fu_1574_p2;
tmp_184_2_reg_5467 <= tmp_184_2_fu_1601_p2;
tmp_23_reg_5427 <= tmp_23_fu_1547_p2;
tmp_39_reg_5532 <= tmp_39_fu_1740_p2;
tmp_40_reg_5600 <= tmp_40_fu_1864_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it7) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it7)))) then
count_1_i_12_reg_5872 <= count_1_i_12_fu_2678_p3;
count_4_reg_5867 <= count_4_fu_2666_p2;
p_iscorner_0_i_7_reg_5862 <= p_iscorner_0_i_7_fu_2653_p2;
tmp12_reg_5883 <= tmp12_fu_2694_p2;
tmp3_reg_5878 <= tmp3_fu_2689_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it8) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it8)))) then
count_1_i_14_reg_5898 <= count_1_i_14_fu_2755_p3;
p_iscorner_0_i_11_reg_5888 <= p_iscorner_0_i_11_fu_2725_p2;
tmp13_reg_5904 <= tmp13_fu_2762_p2;
tmp_185_13_reg_5893 <= tmp_185_13_fu_2743_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it5) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it5)))) then
count_1_i_3_reg_5806 <= count_1_i_3_fu_2476_p3;
not_or_cond13_demorgan_reg_5801 <= not_or_cond13_demorgan_fu_2470_p2;
not_or_cond14_demorgan_reg_5816 <= not_or_cond14_demorgan_fu_2500_p2;
or_cond17_reg_5811 <= or_cond17_fu_2494_p2;
or_cond18_reg_5821 <= or_cond18_fu_2511_p2;
p_iscorner_0_i_1_reg_5786 <= p_iscorner_0_i_1_fu_2391_p2;
p_iscorner_0_i_2_reg_5791 <= p_iscorner_0_i_2_fu_2435_p2;
tmp6_reg_5827 <= tmp6_fu_2516_p2;
tmp_185_3_reg_5796 <= tmp_185_3_fu_2464_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it3) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it3)))) then
count_1_i_6_reg_5665 <= count_1_i_6_fu_2036_p3;
count_1_i_7_reg_5675 <= count_1_i_7_fu_2061_p3;
flag_val_V_assign_load_1_3_reg_5625 <= flag_val_V_assign_load_1_3_fu_1930_p3;
flag_val_V_assign_load_1_5_reg_5631 <= flag_val_V_assign_load_1_5_fu_1962_p3;
not_or_cond10_demorgan_reg_5699 <= not_or_cond10_demorgan_fu_2093_p2;
not_or_cond11_demorgan_reg_5704 <= not_or_cond11_demorgan_fu_2097_p2;
or_cond10_reg_5670 <= or_cond10_fu_2055_p2;
or_cond11_reg_5681 <= or_cond11_fu_2075_p2;
or_cond2_reg_5660 <= or_cond2_fu_1990_p2;
tmp_181_9_reg_5687 <= tmp_181_9_fu_2081_p2;
tmp_182_4_reg_5638 <= tmp_182_4_fu_1970_p2;
tmp_182_5_reg_5649 <= tmp_182_5_fu_1980_p2;
tmp_183_9_reg_5693 <= tmp_183_9_fu_2087_p2;
tmp_184_4_reg_5644 <= tmp_184_4_fu_1975_p2;
tmp_184_5_reg_5655 <= tmp_184_5_fu_1985_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it4) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it4)))) then
count_1_i_9_reg_5743 <= count_1_i_9_fu_2257_p3;
count_1_i_s_reg_5753 <= count_1_i_s_fu_2292_p3;
flag_val_V_assign_load_1_10_reg_5709 <= flag_val_V_assign_load_1_10_fu_2131_p3;
flag_val_V_assign_load_1_12_reg_5715 <= flag_val_V_assign_load_1_12_fu_2163_p3;
not_or_cond3_demorgan_reg_5748 <= not_or_cond3_demorgan_fu_2286_p2;
not_or_cond4_demorgan_reg_5764 <= not_or_cond4_demorgan_fu_2316_p2;
not_or_cond_reg_5733 <= not_or_cond_fu_2186_p2;
or_cond14_reg_5759 <= or_cond14_fu_2310_p2;
p_iscorner_0_i_9_reg_5738 <= p_iscorner_0_i_9_fu_2251_p2;
tmp5_reg_5781 <= tmp5_fu_2334_p2;
tmp_181_2_reg_5769 <= tmp_181_2_fu_2322_p2;
tmp_182_7_reg_5722 <= tmp_182_7_fu_2171_p2;
tmp_183_10_reg_5775 <= tmp_183_10_fu_2328_p2;
tmp_184_7_reg_5728 <= tmp_184_7_fu_2176_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it6) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it6)))) then
count_3_reg_5837 <= count_3_fu_2594_p2;
p_iscorner_0_i_5_reg_5832 <= p_iscorner_0_i_5_fu_2581_p2;
tmp4_reg_5847 <= tmp4_fu_2606_p2;
tmp8_reg_5852 <= tmp8_fu_2610_p2;
tmp9_reg_5857 <= tmp9_fu_2614_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)))) then
flag_d_assign_11_reg_6539 <= flag_d_assign_11_fu_4289_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)))) then
flag_d_assign_13_reg_6613 <= flag_d_assign_13_fu_4417_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)))) then
flag_d_assign_2_reg_6109 <= flag_d_assign_2_fu_3497_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)))) then
flag_d_assign_4_reg_6243 <= flag_d_assign_4_fu_3777_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)))) then
flag_d_assign_6_reg_6317 <= flag_d_assign_6_fu_3905_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)))) then
flag_d_assign_8_reg_6391 <= flag_d_assign_8_fu_4033_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)))) then
flag_d_assign_reg_6011 <= flag_d_assign_fu_3143_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)))) then
flag_d_assign_s_reg_6465 <= flag_d_assign_s_fu_4161_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949)))) then
flag_d_max2_1_reg_5959 <= grp_image_filter_reg_int_s_fu_547_ap_return;
flag_d_max2_7_reg_5971 <= grp_image_filter_reg_int_s_fu_577_ap_return;
flag_d_min2_1_reg_5953 <= grp_image_filter_reg_int_s_fu_542_ap_return;
flag_d_min2_7_reg_5965 <= grp_image_filter_reg_int_s_fu_572_ap_return;
tmp_200_3_reg_5977 <= tmp_200_3_fu_3031_p3;
tmp_213_3_reg_5982 <= tmp_213_3_fu_3045_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))) then
flag_d_max2_9_reg_6023 <= grp_image_filter_reg_int_s_fu_607_ap_return;
flag_d_max8_1_reg_6036 <= grp_image_filter_reg_int_s_fu_617_ap_return;
flag_d_min2_9_reg_6017 <= grp_image_filter_reg_int_s_fu_602_ap_return;
flag_d_min8_1_reg_6029 <= grp_image_filter_reg_int_s_fu_612_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))) then
flag_d_max4_1_reg_5993 <= grp_image_filter_reg_int_s_fu_587_ap_return;
flag_d_max4_5_reg_6005 <= grp_image_filter_reg_int_s_fu_597_ap_return;
flag_d_min4_1_reg_5987 <= grp_image_filter_reg_int_s_fu_582_ap_return;
flag_d_min4_5_reg_5999 <= grp_image_filter_reg_int_s_fu_592_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))) then
flag_d_max4_3_reg_6059 <= grp_image_filter_reg_int_s_fu_657_ap_return;
flag_d_max4_7_reg_6071 <= grp_image_filter_reg_int_s_fu_667_ap_return;
flag_d_min4_3_reg_6053 <= grp_image_filter_reg_int_s_fu_652_ap_return;
flag_d_min4_7_reg_6065 <= grp_image_filter_reg_int_s_fu_662_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))) then
flag_d_max8_3_reg_6122 <= grp_image_filter_reg_int_s_fu_717_ap_return;
flag_d_min8_3_reg_6115 <= grp_image_filter_reg_int_s_fu_712_ap_return;
tmp_210_2_reg_6169 <= tmp_210_2_fu_3609_p3;
tmp_210_4_reg_6179 <= tmp_210_4_fu_3633_p3;
tmp_210_5_reg_6129 <= tmp_210_5_fu_3505_p3;
tmp_210_7_reg_6139 <= tmp_210_7_fu_3529_p3;
tmp_210_9_reg_6149 <= tmp_210_9_fu_3554_p3;
tmp_210_s_reg_6159 <= tmp_210_s_fu_3582_p3;
tmp_225_2_reg_6174 <= tmp_225_2_fu_3621_p3;
tmp_225_4_reg_6184 <= tmp_225_4_fu_3645_p3;
tmp_225_5_reg_6134 <= tmp_225_5_fu_3517_p3;
tmp_225_7_reg_6144 <= tmp_225_7_fu_3541_p3;
tmp_225_9_reg_6154 <= tmp_225_9_fu_3568_p3;
tmp_225_s_reg_6164 <= tmp_225_s_fu_3596_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)))) then
flag_d_max8_5_reg_6256 <= grp_image_filter_reg_int_s_fu_727_ap_return;
flag_d_min8_5_reg_6249 <= grp_image_filter_reg_int_s_fu_722_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)))) then
flag_d_max8_7_reg_6330 <= grp_image_filter_reg_int_s_fu_737_ap_return;
flag_d_min8_7_reg_6323 <= grp_image_filter_reg_int_s_fu_732_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)))) then
flag_d_max8_9_reg_6404 <= grp_image_filter_reg_int_s_fu_747_ap_return;
flag_d_min8_9_reg_6397 <= grp_image_filter_reg_int_s_fu_742_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_5122 <= i_V_fu_807_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_802_p2))) then
icmp_reg_5142 <= icmp_fu_840_p2;
tmp_7_reg_5127 <= tmp_7_fu_813_p2;
tmp_8_reg_5132 <= tmp_8_fu_818_p2;
tmp_9_reg_5137 <= tmp_9_fu_824_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)))) then
iscorner_2_i_s_reg_5949 <= iscorner_2_i_s_fu_2870_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
j_V_reg_5151 <= j_V_fu_851_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = exitcond_fu_846_p2) and not((ap_const_lv1_0 = or_cond_fu_862_p2)))) then
k_buf_val_0_V_addr_reg_5161 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_1_V_addr_reg_5167 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_2_V_addr_reg_5173 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_3_V_addr_reg_5179 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_4_V_addr_reg_5185 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_5_V_addr_reg_5191 <= tmp_12_fu_867_p1(11 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it1)))) then
lhs_V_reg_5240(0) <= lhs_V_fu_1252_p1(0);
lhs_V_reg_5240(1) <= lhs_V_fu_1252_p1(1);
lhs_V_reg_5240(2) <= lhs_V_fu_1252_p1(2);
lhs_V_reg_5240(3) <= lhs_V_fu_1252_p1(3);
lhs_V_reg_5240(4) <= lhs_V_fu_1252_p1(4);
lhs_V_reg_5240(5) <= lhs_V_fu_1252_p1(5);
lhs_V_reg_5240(6) <= lhs_V_fu_1252_p1(6);
lhs_V_reg_5240(7) <= lhs_V_fu_1252_p1(7);
phitmp1_reg_5261 <= phitmp1_fu_1278_p3;
phitmp_1_reg_5280 <= phitmp_1_fu_1314_p3;
phitmp_2_reg_5299 <= phitmp_2_fu_1350_p3;
phitmp_3_reg_5318 <= phitmp_3_fu_1386_p3;
r_V_2_reg_5290 <= r_V_2_fu_1332_p2;
r_V_3_reg_5309 <= r_V_3_fu_1368_p2;
r_V_4_reg_5328 <= r_V_4_fu_1404_p2;
r_V_5_reg_5348 <= r_V_5_fu_1426_p2;
r_V_6_reg_5368 <= r_V_6_fu_1448_p2;
r_V_7_reg_5388 <= r_V_7_fu_1470_p2;
r_V_reg_5252 <= r_V_fu_1260_p2;
r_V_s_reg_5271 <= r_V_s_fu_1296_p2;
tmp_176_4_reg_5337 <= tmp_176_4_fu_1410_p2;
tmp_176_5_reg_5357 <= tmp_176_5_fu_1432_p2;
tmp_176_6_reg_5377 <= tmp_176_6_fu_1454_p2;
tmp_176_7_reg_5397 <= tmp_176_7_fu_1476_p2;
tmp_177_4_reg_5343 <= tmp_177_4_fu_1416_p2;
tmp_177_5_reg_5363 <= tmp_177_5_fu_1438_p2;
tmp_177_6_reg_5383 <= tmp_177_6_fu_1460_p2;
tmp_177_7_reg_5403 <= tmp_177_7_fu_1482_p2;
tmp_20_reg_5266 <= tmp_20_fu_1286_p2;
tmp_24_reg_5285 <= tmp_24_fu_1322_p2;
tmp_27_reg_5304 <= tmp_27_fu_1358_p2;
tmp_29_reg_5323 <= tmp_29_fu_1394_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it9) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it9)))) then
not_or_cond11_reg_5919 <= not_or_cond11_fu_2817_p2;
p_iscorner_0_i_13_reg_5909 <= p_iscorner_0_i_13_fu_2787_p2;
tmp11_reg_5934 <= tmp11_fu_2833_p2;
tmp15_reg_5939 <= tmp15_fu_2837_p2;
tmp2_reg_5929 <= tmp2_fu_2828_p2;
tmp_185_15_reg_5914 <= tmp_185_15_fu_2805_p2;
tmp_185_16_reg_5924 <= tmp_185_16_fu_2822_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = exitcond_fu_846_p2))) then
or_cond1_reg_5197 <= or_cond1_fu_883_p2;
or_cond4_reg_5201 <= or_cond4_fu_904_p2;
or_cond_reg_5156 <= or_cond_fu_862_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it6) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it6)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond5_reg_5537_pp0_it6))) then
phitmp8_reg_5842 <= phitmp8_fu_2600_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it10) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it10)))) then
tmp14_reg_5944 <= tmp14_fu_2861_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) then
tmp19_reg_6739 <= tmp19_fu_4701_p2;
tmp20_reg_6744 <= tmp20_fu_4712_p2;
tmp23_reg_6749 <= tmp23_fu_4723_p2;
tmp25_reg_6754 <= tmp25_fu_4735_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it31) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it31)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it31)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31)))) then
tmp_100_v_reg_6714 <= tmp_100_v_fu_4593_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_180))) then
tmp_15_reg_5103 <= tmp_15_fu_786_p1;
tmp_5_reg_5113 <= tmp_5_fu_796_p2;
tmp_reg_5098 <= tmp_fu_782_p1;
tmp_s_reg_5108 <= tmp_s_fu_790_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)))) then
tmp_211_1_reg_6545 <= grp_image_filter_reg_int_s_fu_762_ap_return;
tmp_226_1_reg_6552 <= grp_image_filter_reg_int_s_fu_767_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)))) then
tmp_211_2_reg_6619 <= grp_image_filter_reg_int_s_fu_772_ap_return;
tmp_226_2_reg_6626 <= grp_image_filter_reg_int_s_fu_777_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)))) then
tmp_211_s_reg_6471 <= grp_image_filter_reg_int_s_fu_752_ap_return;
tmp_226_s_reg_6478 <= grp_image_filter_reg_int_s_fu_757_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))) then
tmp_43_reg_6043 <= tmp_43_fu_3262_p2;
tmp_67_reg_6048 <= tmp_67_fu_3268_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond_reg_5156_pp0_it1)))) then
win_val_0_V_2_3_fu_168 <= win_val_0_V_2_1_reg_5205;
win_val_1_V_1_3_fu_188 <= win_val_1_V_1_fu_192;
win_val_1_V_1_fu_192 <= win_val_1_V_2_fu_196;
win_val_1_V_2_fu_196 <= win_val_1_V_3_fu_200;
win_val_1_V_3_fu_200 <= win_val_1_V_4_3_reg_5210;
win_val_2_V_0_3_fu_212 <= win_val_2_V_0_fu_216;
win_val_2_V_0_fu_216 <= win_val_2_V_1_fu_220;
win_val_2_V_1_fu_220 <= win_val_2_V_2_fu_224;
win_val_2_V_2_fu_224 <= win_val_2_V_3_fu_228;
win_val_2_V_3_fu_228 <= win_val_2_V_4_fu_232;
win_val_2_V_4_fu_232 <= win_val_2_V_5_3_reg_5215;
win_val_3_V_0_3_fu_240 <= win_val_3_V_0_fu_244;
win_val_3_V_0_fu_244 <= win_val_3_V_1_fu_248;
win_val_3_V_1_fu_248 <= win_val_3_V_2_3_reg_5220;
win_val_4_V_0_3_fu_268 <= win_val_4_V_0_fu_272;
win_val_4_V_0_fu_272 <= win_val_4_V_1_fu_276;
win_val_4_V_1_fu_276 <= win_val_4_V_2_fu_280;
win_val_4_V_2_fu_280 <= win_val_4_V_3_fu_284;
win_val_4_V_3_fu_284 <= win_val_4_V_4_fu_288;
win_val_4_V_4_fu_288 <= win_val_4_V_5_3_reg_5225;
win_val_5_V_1_3_fu_296 <= win_val_5_V_1_fu_300;
win_val_5_V_1_fu_300 <= win_val_5_V_2_fu_304;
win_val_5_V_2_fu_304 <= win_val_5_V_3_fu_308;
win_val_5_V_3_fu_308 <= win_val_5_V_4_3_reg_5230;
win_val_6_V_2_3_fu_320 <= win_val_6_V_2_fu_324;
win_val_6_V_2_fu_324 <= win_val_6_V_2_2_reg_5235;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
win_val_0_V_2_fu_172 <= win_val_0_V_3_fu_176;
win_val_0_V_3_fu_176 <= win_val_0_V_4_fu_180;
win_val_0_V_4_fu_180 <= win_val_0_V_5_fu_184;
win_val_0_V_5_fu_184 <= k_buf_val_0_V_q0;
win_val_1_V_4_fu_204 <= win_val_1_V_5_fu_208;
win_val_1_V_5_fu_208 <= k_buf_val_1_V_q0;
win_val_2_V_5_fu_236 <= k_buf_val_2_V_q0;
win_val_3_V_2_fu_252 <= win_val_3_V_3_fu_256;
win_val_3_V_3_fu_256 <= win_val_3_V_4_fu_260;
win_val_3_V_4_fu_260 <= win_val_3_V_5_fu_264;
win_val_3_V_5_fu_264 <= k_buf_val_3_V_q0;
win_val_4_V_5_fu_292 <= k_buf_val_4_V_q0;
win_val_5_V_4_fu_312 <= win_val_5_V_5_fu_316;
win_val_5_V_5_fu_316 <= k_buf_val_5_V_q0;
win_val_6_V_3_fu_156 <= win_val_6_V_4_fu_144;
win_val_6_V_4_fu_144 <= win_val_6_V_5_fu_132;
win_val_6_V_5_fu_132 <= p_src_data_stream_V_dout;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
win_val_6_V_2_2_reg_5235 <= win_val_6_V_3_fu_156;
end if;
end if;
end process;
lhs_V_reg_5240(8) <= '0';
count_1_i_0_op_op87_op_reg_5590(3 downto 1) <= "100";
phitmp43_op_op_cast_cast_cast_reg_5595(3 downto 1) <= "011";
core_win_val_0_V_0_fu_136(15 downto 8) <= "00000000";
core_win_val_0_V_1_fu_140(15 downto 8) <= "00000000";
core_win_val_1_V_0_fu_148(15 downto 8) <= "00000000";
core_win_val_1_V_1_fu_152(15 downto 8) <= "00000000";
core_win_val_2_V_0_fu_160(15 downto 8) <= "00000000";
core_win_val_2_V_1_fu_164(15 downto 8) <= "00000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_sig_bdd_180, exitcond1_fu_802_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_180)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = exitcond1_fu_802_p2))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it33)))) then
ap_NS_fsm <= ap_ST_st39_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_st39_fsm_3 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
a0_2_cast_fu_3908_p1 <= std_logic_vector(resize(unsigned(a0_2_reg_6285),32));
a0_2_fu_3841_p3 <=
a0_tmp_232_1_reg_6263 when (tmp_217_2_fu_3835_p2(0) = '1') else
tmp_58_fu_3831_p1;
a0_2_tmp_232_2_cast_fu_3951_p1 <= std_logic_vector(resize(unsigned(a0_2_tmp_232_2_reg_6337),32));
a0_2_tmp_232_2_fu_3916_p3 <=
a0_2_reg_6285 when (tmp_233_2_fu_3911_p2(0) = '1') else
tmp_59_reg_6296;
a0_3_cast_fu_4036_p1 <= std_logic_vector(resize(unsigned(a0_3_reg_6359),32));
a0_3_fu_3969_p3 <=
a0_2_tmp_232_2_reg_6337 when (tmp_217_3_fu_3963_p2(0) = '1') else
tmp_60_fu_3959_p1;
a0_3_tmp_232_3_cast_fu_4079_p1 <= std_logic_vector(resize(unsigned(a0_3_tmp_232_3_reg_6411),32));
a0_3_tmp_232_3_fu_4044_p3 <=
a0_3_reg_6359 when (tmp_233_3_fu_4039_p2(0) = '1') else
tmp_61_reg_6370;
a0_4_cast_fu_4164_p1 <= std_logic_vector(resize(unsigned(a0_4_reg_6433),32));
a0_4_fu_4097_p3 <=
a0_3_tmp_232_3_reg_6411 when (tmp_217_4_fu_4091_p2(0) = '1') else
tmp_62_fu_4087_p1;
a0_4_tmp_232_4_cast_fu_4207_p1 <= std_logic_vector(resize(unsigned(a0_4_tmp_232_4_reg_6485),32));
a0_4_tmp_232_4_fu_4172_p3 <=
a0_4_reg_6433 when (tmp_233_4_fu_4167_p2(0) = '1') else
tmp_63_reg_6444;
a0_5_cast_fu_4292_p1 <= std_logic_vector(resize(unsigned(a0_5_reg_6507),32));
a0_5_fu_4225_p3 <=
a0_4_tmp_232_4_reg_6485 when (tmp_217_5_fu_4219_p2(0) = '1') else
tmp_64_fu_4215_p1;
a0_5_tmp_232_5_cast_fu_4335_p1 <= std_logic_vector(resize(unsigned(a0_5_tmp_232_5_reg_6559),32));
a0_5_tmp_232_5_fu_4300_p3 <=
a0_5_reg_6507 when (tmp_233_5_fu_4295_p2(0) = '1') else
tmp_65_reg_6518;
a0_6_cast_fu_4420_p1 <= std_logic_vector(resize(unsigned(a0_6_reg_6581),32));
a0_6_fu_4353_p3 <=
a0_5_tmp_232_5_reg_6559 when (tmp_217_6_fu_4347_p2(0) = '1') else
tmp_66_fu_4343_p1;
a0_6_tmp_232_6_cast_fu_4463_p1 <= std_logic_vector(resize(unsigned(a0_6_tmp_232_6_reg_6633),32));
a0_6_tmp_232_6_fu_4428_p3 <=
a0_6_reg_6581 when (tmp_233_6_fu_4423_p2(0) = '1') else
tmp_75_reg_6592;
a0_7_cast_fu_4549_p1 <= std_logic_vector(resize(unsigned(a0_7_reg_6655),32));
a0_7_fu_4481_p3 <=
a0_6_tmp_232_6_reg_6633 when (tmp_217_7_fu_4475_p2(0) = '1') else
tmp_77_fu_4471_p1;
a0_7_tmp_232_7_fu_4557_p3 <=
a0_7_reg_6655 when (tmp_233_7_fu_4552_p2(0) = '1') else
tmp_78_reg_6666;
a0_cast_fu_3780_p1 <= std_logic_vector(resize(unsigned(a0_s_reg_6211),32));
a0_s_fu_3713_p3 <=
p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 when (tmp_217_1_fu_3707_p2(0) = '1') else
tmp_56_fu_3703_p1;
a0_tmp_232_1_cast_fu_3823_p1 <= std_logic_vector(resize(unsigned(a0_tmp_232_1_reg_6263),32));
a0_tmp_232_1_fu_3788_p3 <=
a0_s_reg_6211 when (tmp_233_1_fu_3783_p2(0) = '1') else
tmp_57_reg_6222;
a_0_flag_d_assign_load_5_fu_3419_p3 <=
flag_d_min8_1_reg_6029 when (tmp_43_reg_6043(0) = '1') else
flag_d_assign_reg_6011;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond1_fu_802_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond1_fu_802_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_802_p2)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_core_1_reg_527pp0_it0 <= "XXXXXXXX";
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(p_mask_data_stream_V_full_n, ap_reg_ppstg_or_cond4_reg_5201_pp0_it34)
begin
ap_sig_bdd_136 <= ((p_mask_data_stream_V_full_n = ap_const_logic_0) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond4_reg_5201_pp0_it34));
end process;
-- ap_sig_bdd_1776 assign process. --
ap_sig_bdd_1776_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_1776 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_180 assign process. --
ap_sig_bdd_180_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_180 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_196 assign process. --
ap_sig_bdd_196_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_196 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_2075 assign process. --
ap_sig_bdd_2075_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2075 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_2108 assign process. --
ap_sig_bdd_2108_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it12, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_2108 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it12) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_2152 assign process. --
ap_sig_bdd_2152_assign_proc : process(exitcond_fu_846_p2, or_cond1_fu_883_p2)
begin
ap_sig_bdd_2152 <= ((ap_const_lv1_0 = exitcond_fu_846_p2) and (ap_const_lv1_0 = or_cond1_fu_883_p2));
end process;
-- ap_sig_bdd_2156 assign process. --
ap_sig_bdd_2156_assign_proc : process(ap_reg_ppstg_exitcond_reg_5147_pp0_it32, ap_reg_ppstg_or_cond1_reg_5197_pp0_it32, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)
begin
ap_sig_bdd_2156 <= ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it32)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)));
end process;
-- ap_sig_bdd_2159 assign process. --
ap_sig_bdd_2159_assign_proc : process(ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, iscorner_2_i_s_fu_2870_p2)
begin
ap_sig_bdd_2159 <= ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and (ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2));
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_250 assign process. --
ap_sig_bdd_250_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_250 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_48 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_61 assign process. --
ap_sig_bdd_61_assign_proc : process(p_src_data_stream_V_empty_n, exitcond_reg_5147, or_cond_reg_5156)
begin
ap_sig_bdd_61 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_48)
begin
if (ap_sig_bdd_48) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_196)
begin
if (ap_sig_bdd_196) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_3 assign process. --
ap_sig_cseq_ST_st39_fsm_3_assign_proc : process(ap_sig_bdd_2075)
begin
if (ap_sig_bdd_2075) then
ap_sig_cseq_ST_st39_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_3 <= ap_const_logic_0;
end if;
end process;
b0_2_cast_fu_3928_p1 <= std_logic_vector(resize(signed(b0_2_reg_6301),32));
b0_2_fu_3882_p3 <=
b0_tmp_239_1_reg_6274 when (tmp_228_2_fu_3876_p2(0) = '1') else
tmp_84_fu_3872_p1;
b0_2_tmp_239_2_cast_fu_3992_p1 <= std_logic_vector(resize(signed(b0_2_tmp_239_2_reg_6348),32));
b0_2_tmp_239_2_fu_3936_p3 <=
b0_2_reg_6301 when (tmp_240_2_fu_3931_p2(0) = '1') else
tmp_85_reg_6312;
b0_3_cast_fu_4056_p1 <= std_logic_vector(resize(signed(b0_3_reg_6375),32));
b0_3_fu_4010_p3 <=
b0_2_tmp_239_2_reg_6348 when (tmp_228_3_fu_4004_p2(0) = '1') else
tmp_86_fu_4000_p1;
b0_3_tmp_239_3_cast_fu_4120_p1 <= std_logic_vector(resize(signed(b0_3_tmp_239_3_reg_6422),32));
b0_3_tmp_239_3_fu_4064_p3 <=
b0_3_reg_6375 when (tmp_240_3_fu_4059_p2(0) = '1') else
tmp_87_reg_6386;
b0_4_cast_fu_4184_p1 <= std_logic_vector(resize(signed(b0_4_reg_6449),32));
b0_4_fu_4138_p3 <=
b0_3_tmp_239_3_reg_6422 when (tmp_228_4_fu_4132_p2(0) = '1') else
tmp_88_fu_4128_p1;
b0_4_tmp_239_4_cast_fu_4248_p1 <= std_logic_vector(resize(signed(b0_4_tmp_239_4_reg_6496),32));
b0_4_tmp_239_4_fu_4192_p3 <=
b0_4_reg_6449 when (tmp_240_4_fu_4187_p2(0) = '1') else
tmp_89_reg_6460;
b0_5_cast_fu_4312_p1 <= std_logic_vector(resize(signed(b0_5_reg_6523),32));
b0_5_fu_4266_p3 <=
b0_4_tmp_239_4_reg_6496 when (tmp_228_5_fu_4260_p2(0) = '1') else
tmp_90_fu_4256_p1;
b0_5_tmp_239_5_cast_fu_4376_p1 <= std_logic_vector(resize(signed(b0_5_tmp_239_5_reg_6570),32));
b0_5_tmp_239_5_fu_4320_p3 <=
b0_5_reg_6523 when (tmp_240_5_fu_4315_p2(0) = '1') else
tmp_91_reg_6534;
b0_6_cast_fu_4440_p1 <= std_logic_vector(resize(signed(b0_6_reg_6597),32));
b0_6_fu_4394_p3 <=
b0_5_tmp_239_5_reg_6570 when (tmp_228_6_fu_4388_p2(0) = '1') else
tmp_92_fu_4384_p1;
b0_6_tmp_239_6_cast_fu_4504_p1 <= std_logic_vector(resize(signed(b0_6_tmp_239_6_reg_6644),32));
b0_6_tmp_239_6_fu_4448_p3 <=
b0_6_reg_6597 when (tmp_240_6_fu_4443_p2(0) = '1') else
tmp_93_reg_6608;
b0_7_cast_fu_4563_p1 <= std_logic_vector(resize(signed(b0_7_reg_6671),32));
b0_7_fu_4522_p3 <=
b0_6_tmp_239_6_reg_6644 when (tmp_228_7_fu_4516_p2(0) = '1') else
tmp_94_fu_4512_p1;
b0_cast_50_fu_3800_p1 <= std_logic_vector(resize(signed(b0_s_reg_6227),32));
b0_cast_fu_3672_p1 <= std_logic_vector(resize(signed(b0_reg_6093),32));
b0_fu_3473_p3 <=
ap_const_lv9_1EC when (tmp_69_fu_3467_p2(0) = '1') else
tmp_80_fu_3463_p1;
b0_s_fu_3754_p3 <=
b0_tmp_s_reg_6200 when (tmp_228_1_fu_3748_p2(0) = '1') else
tmp_82_fu_3744_p1;
b0_tmp_239_1_cast_fu_3864_p1 <= std_logic_vector(resize(signed(b0_tmp_239_1_reg_6274),32));
b0_tmp_239_1_fu_3808_p3 <=
b0_s_reg_6227 when (tmp_240_1_fu_3803_p2(0) = '1') else
tmp_83_reg_6238;
b0_tmp_239_cast_fu_3736_p1 <= std_logic_vector(resize(signed(b0_tmp_s_reg_6200),32));
b0_tmp_s_fu_3680_p3 <=
b0_reg_6093 when (tmp_72_fu_3675_p2(0) = '1') else
tmp_81_reg_6104;
core_buf_val_0_V_address0 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_0_V_address1 <= core_buf_val_0_V_addr_reg_6702;
-- core_buf_val_0_V_ce0 assign process. --
core_buf_val_0_V_ce0_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it32, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_0_V_ce0 <= ap_const_logic_1;
else
core_buf_val_0_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- core_buf_val_0_V_ce1 assign process. --
core_buf_val_0_V_ce1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_0_V_ce1 <= ap_const_logic_1;
else
core_buf_val_0_V_ce1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_0_V_d1 <= core_buf_val_1_V_q0;
-- core_buf_val_0_V_we1 assign process. --
core_buf_val_0_V_we1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it33, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it32)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it33) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it32)))) then
core_buf_val_0_V_we1 <= ap_const_logic_1;
else
core_buf_val_0_V_we1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_1_V_address0 <= tmp_14_fu_4577_p1(11 - 1 downto 0);
core_buf_val_1_V_address1 <= ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33;
-- core_buf_val_1_V_ce0 assign process. --
core_buf_val_1_V_ce0_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it32, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it32) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_1_V_ce0 <= ap_const_logic_1;
else
core_buf_val_1_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- core_buf_val_1_V_ce1 assign process. --
core_buf_val_1_V_ce1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
core_buf_val_1_V_ce1 <= ap_const_logic_1;
else
core_buf_val_1_V_ce1 <= ap_const_logic_0;
end if;
end process;
core_buf_val_1_V_d1 <= core_win_val_2_V_2_fu_4635_p3;
-- core_buf_val_1_V_we1 assign process. --
core_buf_val_1_V_we1_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it33)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it34) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it33)))) then
core_buf_val_1_V_we1 <= ap_const_logic_1;
else
core_buf_val_1_V_we1 <= ap_const_logic_0;
end if;
end process;
core_win_val_0_V_2_fu_4620_p1 <= std_logic_vector(resize(unsigned(core_buf_val_0_V_load_reg_6724),16));
core_win_val_1_V_2_fu_4623_p1 <= std_logic_vector(resize(unsigned(core_buf_val_1_V_load_reg_6729),16));
core_win_val_2_V_1_2_fu_4643_p1 <= std_logic_vector(resize(unsigned(core_win_val_2_V_2_fu_4635_p3),16));
core_win_val_2_V_2_fu_4635_p3 <=
ap_reg_phiprechg_core_1_reg_527pp0_it34 when (ap_reg_ppstg_or_cond_reg_5156_pp0_it33(0) = '1') else
ap_const_lv8_0;
count_1_fu_2407_p2 <= std_logic_vector(unsigned(count_1_i_1_fu_2397_p3) + unsigned(ap_const_lv4_1));
count_1_i_0_op_op87_op_fu_1848_p3 <=
ap_const_lv4_8 when (or_cond5_fu_1746_p2(0) = '1') else
ap_const_lv4_9;
count_1_i_10_fu_2636_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7(0) = '1') else
phitmp8_reg_5842;
count_1_i_11_fu_2659_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond6_reg_5543_pp0_it7(0) = '1') else
count_1_i_10_fu_2636_p3;
count_1_i_12_fu_2678_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond7_reg_5548_pp0_it7(0) = '1') else
phitmp9_fu_2672_p2;
count_1_i_13_fu_2731_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond8_reg_5553_pp0_it8(0) = '1') else
count_1_i_12_reg_5872;
count_1_i_14_fu_2755_p3 <=
ap_const_lv5_2 when (ap_reg_ppstg_or_cond9_reg_5559_pp0_it8(0) = '1') else
phitmp10_fu_2749_p2;
count_1_i_15_fu_2793_p3 <=
ap_const_lv5_1 when (ap_reg_ppstg_or_cond2_reg_5660_pp0_it9(0) = '1') else
count_1_i_14_reg_5898;
count_1_i_1_fu_2397_p3 <=
ap_const_lv4_1 when (or_cond14_reg_5759(0) = '1') else
count_1_i_s_reg_5753;
count_1_i_2_fu_2441_p3 <=
ap_const_lv4_2 when (or_cond15_fu_2403_p2(0) = '1') else
phitmp6_fu_2419_p2;
count_1_i_2_op_op_fu_1998_p3 <=
phitmp43_op_op_cast_cast_cast_reg_5595 when (tmp_40_reg_5600(0) = '1') else
count_1_i_0_op_op87_op_reg_5590;
count_1_i_3_cast_fu_2531_p1 <= std_logic_vector(resize(unsigned(count_1_i_3_reg_5806),5));
count_1_i_3_fu_2476_p3 <=
ap_const_lv4_1 when (or_cond16_fu_2458_p2(0) = '1') else
count_1_i_2_fu_2441_p3;
count_1_i_4_fu_2563_p3 <=
ap_const_lv5_2 when (or_cond17_reg_5811(0) = '1') else
phitmp7_fu_2546_p2;
count_1_i_4_op_fu_2014_p3 <=
phitmp42_op_cast_cast_cast_fu_2003_p3 when (tmp_41_fu_2010_p2(0) = '1') else
count_1_i_2_op_op_fu_1998_p3;
count_1_i_5_fu_2587_p3 <=
ap_const_lv5_1 when (or_cond18_reg_5821(0) = '1') else
count_1_i_4_fu_2563_p3;
count_1_i_6_fu_2036_p3 <=
phitmp3_cast_cast_cast_fu_2022_p3 when (tmp_42_fu_2030_p2(0) = '1') else
count_1_i_4_op_fu_2014_p3;
count_1_i_7_fu_2061_p3 <=
ap_const_lv4_1 when (or_cond10_fu_2055_p2(0) = '1') else
count_1_i_6_fu_2036_p3;
count_1_i_8_fu_2224_p3 <=
ap_const_lv4_2 when (or_cond11_reg_5681(0) = '1') else
phitmp4_fu_2208_p2;
count_1_i_9_fu_2257_p3 <=
ap_const_lv4_1 when (or_cond12_fu_2231_p2(0) = '1') else
count_1_i_8_fu_2224_p3;
count_1_i_s_fu_2292_p3 <=
ap_const_lv4_2 when (or_cond13_fu_2274_p2(0) = '1') else
phitmp5_fu_2280_p2;
count_2_fu_2534_p2 <= std_logic_vector(unsigned(count_1_i_3_cast_fu_2531_p1) + unsigned(ap_const_lv5_1));
count_3_fu_2594_p2 <= std_logic_vector(unsigned(count_1_i_5_fu_2587_p3) + unsigned(ap_const_lv5_1));
count_4_fu_2666_p2 <= std_logic_vector(unsigned(count_1_i_11_fu_2659_p3) + unsigned(ap_const_lv5_1));
count_5_fu_2737_p2 <= std_logic_vector(unsigned(count_1_i_13_fu_2731_p3) + unsigned(ap_const_lv5_1));
count_6_fu_2799_p2 <= std_logic_vector(unsigned(count_1_i_15_fu_2793_p3) + unsigned(ap_const_lv5_1));
count_8_fu_2197_p2 <= std_logic_vector(unsigned(count_1_i_7_reg_5675) + unsigned(ap_const_lv4_1));
count_s_fu_2359_p2 <= std_logic_vector(unsigned(count_1_i_9_reg_5743) + unsigned(ap_const_lv4_1));
exitcond1_fu_802_p2 <= "1" when (p_s_reg_504 = tmp_5_reg_5113) else "0";
exitcond_fu_846_p2 <= "1" when (p_2_phi_fu_519_p4 = tmp_s_reg_5108) else "0";
flag_d_assign_10_fu_3692_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17),32));
flag_d_assign_11_fu_4289_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26),32));
flag_d_assign_12_fu_3820_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19),32));
flag_d_assign_13_fu_4417_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28),32));
flag_d_assign_14_fu_3948_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21),32));
flag_d_assign_1_fu_4076_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it23),32));
flag_d_assign_2_fu_3497_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it16),32));
flag_d_assign_3_fu_4204_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it25),32));
flag_d_assign_4_fu_3777_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it18),32));
flag_d_assign_5_fu_4332_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it27),32));
flag_d_assign_6_fu_3905_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it20),32));
flag_d_assign_7_fu_4460_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it29),32));
flag_d_assign_8_fu_4033_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it22),32));
flag_d_assign_9_fu_3274_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15),32));
flag_d_assign_fu_3143_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14),32));
flag_d_assign_s_fu_4161_p1 <= std_logic_vector(resize(signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24),32));
flag_val_V_assign_load_1_10_fu_2131_p3 <=
phitmp1_5_fu_2120_p3 when (tmp_34_fu_2127_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_11_fu_1698_p3 <=
phitmp_6_fu_1687_p3 when (tmp_35_fu_1694_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_12_fu_2163_p3 <=
phitmp1_6_fu_2149_p3 when (tmp_36_fu_2157_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_13_fu_1726_p3 <=
phitmp_7_fu_1715_p3 when (tmp_37_fu_1722_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_14_fu_2351_p3 <=
phitmp1_7_fu_2340_p3 when (tmp_38_fu_2347_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_1_fu_1562_p3 <=
phitmp_1_reg_5280 when (tmp_24_reg_5285(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_2_fu_1589_p3 <=
phitmp_2_reg_5299 when (tmp_27_reg_5304(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_3_fu_1930_p3 <=
phitmp1_2_fu_1919_p3 when (tmp_28_fu_1926_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_4_fu_1616_p3 <=
phitmp_3_reg_5318 when (tmp_29_reg_5323(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_5_fu_1962_p3 <=
phitmp1_3_fu_1948_p3 when (tmp_30_fu_1956_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_6_fu_1642_p3 <=
phitmp_4_fu_1631_p3 when (tmp_31_fu_1638_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_7_fu_2112_p3 <=
phitmp1_4_fu_2101_p3 when (tmp_32_fu_2108_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_8_fu_1670_p3 <=
phitmp_5_fu_1659_p3 when (tmp_33_fu_1666_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_9_fu_1911_p3 <=
phitmp1_1_fu_1900_p3 when (tmp_25_fu_1907_p2(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_1_s_fu_1521_p3 <=
phitmp1_reg_5261 when (tmp_20_reg_5266(0) = '1') else
ap_const_lv2_0;
flag_val_V_assign_load_2_s_fu_1894_p3 <=
phitmp3_reg_5422 when (tmp_23_reg_5427(0) = '1') else
ap_const_lv2_0;
-- grp_image_filter_reg_int_s_fu_542_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_542_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_542_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_542_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_542_in_r <= std_logic_vector(resize(signed(tmp_193_1_fu_2879_p3),32));
-- grp_image_filter_reg_int_s_fu_547_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_547_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_547_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_547_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_547_in_r <= std_logic_vector(resize(signed(tmp_203_1_fu_2894_p3),32));
-- grp_image_filter_reg_int_s_fu_552_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_552_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_552_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_552_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_552_in_r <= std_logic_vector(resize(signed(tmp_193_3_fu_2909_p3),32));
-- grp_image_filter_reg_int_s_fu_557_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_557_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_557_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_557_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_557_in_r <= std_logic_vector(resize(signed(tmp_203_3_fu_2924_p3),32));
-- grp_image_filter_reg_int_s_fu_562_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_562_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_562_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_562_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_562_in_r <= std_logic_vector(resize(signed(tmp_193_5_fu_2939_p3),32));
-- grp_image_filter_reg_int_s_fu_567_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_567_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_567_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_567_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_567_in_r <= std_logic_vector(resize(signed(tmp_203_5_fu_2954_p3),32));
-- grp_image_filter_reg_int_s_fu_572_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_572_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_572_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_572_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_572_in_r <= std_logic_vector(resize(signed(tmp_193_7_fu_2969_p3),32));
-- grp_image_filter_reg_int_s_fu_577_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_577_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it11, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it11, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, iscorner_2_i_s_fu_2870_p2, iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it11) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it11)) and not((ap_const_lv1_0 = iscorner_2_i_s_fu_2870_p2)))))) then
grp_image_filter_reg_int_s_fu_577_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_577_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_577_in_r <= std_logic_vector(resize(signed(tmp_203_7_fu_2984_p3),32));
-- grp_image_filter_reg_int_s_fu_582_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_582_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_582_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_582_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_582_in_r <=
grp_image_filter_reg_int_s_fu_542_ap_return when (tmp_192_1_fu_2995_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_552_ap_return;
-- grp_image_filter_reg_int_s_fu_587_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_587_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_587_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_587_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_587_in_r <=
grp_image_filter_reg_int_s_fu_547_ap_return when (tmp_202_1_fu_3010_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_557_ap_return;
-- grp_image_filter_reg_int_s_fu_592_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_592_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_592_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_592_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_592_in_r <=
grp_image_filter_reg_int_s_fu_562_ap_return when (tmp_192_5_fu_3053_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_572_ap_return;
-- grp_image_filter_reg_int_s_fu_597_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_597_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it12, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it12, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, iscorner_2_i_s_reg_5949, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it12) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it12)) and not((ap_const_lv1_0 = iscorner_2_i_s_reg_5949))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)))))) then
grp_image_filter_reg_int_s_fu_597_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_597_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_597_in_r <=
grp_image_filter_reg_int_s_fu_567_ap_return when (tmp_202_5_fu_3068_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_577_ap_return;
-- grp_image_filter_reg_int_s_fu_602_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_602_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_602_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_602_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_602_in_r <= std_logic_vector(resize(signed(tmp_193_9_fu_3087_p3),32));
-- grp_image_filter_reg_int_s_fu_607_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_607_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_607_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_607_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_607_in_r <= std_logic_vector(resize(signed(tmp_203_9_fu_3102_p3),32));
-- grp_image_filter_reg_int_s_fu_612_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_612_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_612_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_612_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_612_in_r <=
grp_image_filter_reg_int_s_fu_582_ap_return when (tmp_199_1_fu_3113_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_592_ap_return;
-- grp_image_filter_reg_int_s_fu_617_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_617_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it13, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it13, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it13) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it13)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)))))) then
grp_image_filter_reg_int_s_fu_617_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_617_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_617_in_r <=
grp_image_filter_reg_int_s_fu_587_ap_return when (tmp_212_1_fu_3128_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_597_ap_return;
-- grp_image_filter_reg_int_s_fu_622_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_622_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_622_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_622_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_622_in_r <= std_logic_vector(resize(signed(tmp_193_s_fu_3150_p3),32));
-- grp_image_filter_reg_int_s_fu_627_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_627_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_627_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_627_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_627_in_r <= std_logic_vector(resize(signed(tmp_203_s_fu_3165_p3),32));
-- grp_image_filter_reg_int_s_fu_632_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_632_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_632_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_632_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_632_in_r <= std_logic_vector(resize(signed(tmp_193_2_fu_3180_p3),32));
-- grp_image_filter_reg_int_s_fu_637_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_637_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_637_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_637_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_637_in_r <= std_logic_vector(resize(signed(tmp_203_2_fu_3195_p3),32));
-- grp_image_filter_reg_int_s_fu_642_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_642_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_642_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_642_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_642_in_r <= std_logic_vector(resize(signed(tmp_193_4_fu_3210_p3),32));
-- grp_image_filter_reg_int_s_fu_647_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_647_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_647_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_647_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_647_in_r <= std_logic_vector(resize(signed(tmp_203_4_fu_3225_p3),32));
-- grp_image_filter_reg_int_s_fu_652_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_652_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_652_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_652_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_652_in_r <= ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14;
-- grp_image_filter_reg_int_s_fu_657_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_657_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_657_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_657_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_657_in_r <= ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14;
-- grp_image_filter_reg_int_s_fu_662_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_662_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_662_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_662_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_662_in_r <=
ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 when (tmp_192_7_fu_3236_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_602_ap_return;
-- grp_image_filter_reg_int_s_fu_667_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_667_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it14, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it14, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it14) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it14)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)))))) then
grp_image_filter_reg_int_s_fu_667_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_667_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_667_in_r <=
ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 when (tmp_202_7_fu_3249_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_607_ap_return;
-- grp_image_filter_reg_int_s_fu_672_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_672_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_672_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_672_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_672_in_r <=
flag_d_min2_9_reg_6017 when (tmp_192_9_fu_3277_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_622_ap_return;
-- grp_image_filter_reg_int_s_fu_677_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_677_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_677_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_677_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_677_in_r <=
flag_d_max2_9_reg_6023 when (tmp_202_9_fu_3290_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_627_ap_return;
-- grp_image_filter_reg_int_s_fu_682_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_682_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_682_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_682_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_682_in_r <=
grp_image_filter_reg_int_s_fu_622_ap_return when (tmp_192_s_fu_3303_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_632_ap_return;
-- grp_image_filter_reg_int_s_fu_687_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_687_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_687_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_687_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_687_in_r <=
grp_image_filter_reg_int_s_fu_627_ap_return when (tmp_202_s_fu_3318_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_637_ap_return;
-- grp_image_filter_reg_int_s_fu_692_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_692_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_692_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_692_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_692_in_r <=
grp_image_filter_reg_int_s_fu_632_ap_return when (tmp_192_2_fu_3333_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_642_ap_return;
-- grp_image_filter_reg_int_s_fu_697_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_697_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_697_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_697_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_697_in_r <=
grp_image_filter_reg_int_s_fu_637_ap_return when (tmp_202_2_fu_3348_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_647_ap_return;
-- grp_image_filter_reg_int_s_fu_702_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_702_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_702_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_702_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_702_in_r <=
grp_image_filter_reg_int_s_fu_642_ap_return when (tmp_192_4_fu_3363_p2(0) = '1') else
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15;
-- grp_image_filter_reg_int_s_fu_707_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_707_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_707_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_707_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_707_in_r <=
grp_image_filter_reg_int_s_fu_647_ap_return when (tmp_202_4_fu_3376_p2(0) = '1') else
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15;
-- grp_image_filter_reg_int_s_fu_712_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_712_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_712_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_712_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_712_in_r <=
grp_image_filter_reg_int_s_fu_652_ap_return when (tmp_199_3_fu_3389_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_662_ap_return;
-- grp_image_filter_reg_int_s_fu_717_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_717_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it15, ap_reg_ppstg_exitcond_reg_5147_pp0_it16, ap_reg_ppstg_or_cond1_reg_5197_pp0_it15, ap_reg_ppstg_or_cond1_reg_5197_pp0_it16, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it15) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it15)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it16) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it16)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)))))) then
grp_image_filter_reg_int_s_fu_717_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_717_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_717_in_r <=
grp_image_filter_reg_int_s_fu_657_ap_return when (tmp_212_3_fu_3404_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_667_ap_return;
-- grp_image_filter_reg_int_s_fu_722_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_722_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it17, ap_reg_ppstg_exitcond_reg_5147_pp0_it18, ap_reg_ppstg_or_cond1_reg_5197_pp0_it17, ap_reg_ppstg_or_cond1_reg_5197_pp0_it18, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))))) then
grp_image_filter_reg_int_s_fu_722_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_722_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_722_in_r <= tmp_210_5_reg_6129;
-- grp_image_filter_reg_int_s_fu_727_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_727_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it17, ap_reg_ppstg_exitcond_reg_5147_pp0_it18, ap_reg_ppstg_or_cond1_reg_5197_pp0_it17, ap_reg_ppstg_or_cond1_reg_5197_pp0_it18, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it18) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it18)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it17) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it17)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17)))))) then
grp_image_filter_reg_int_s_fu_727_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_727_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_727_in_r <= tmp_225_5_reg_6134;
-- grp_image_filter_reg_int_s_fu_732_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_732_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it19, ap_reg_ppstg_exitcond_reg_5147_pp0_it20, ap_reg_ppstg_or_cond1_reg_5197_pp0_it19, ap_reg_ppstg_or_cond1_reg_5197_pp0_it20, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))))) then
grp_image_filter_reg_int_s_fu_732_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_732_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_732_in_r <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19;
-- grp_image_filter_reg_int_s_fu_737_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_737_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it19, ap_reg_ppstg_exitcond_reg_5147_pp0_it20, ap_reg_ppstg_or_cond1_reg_5197_pp0_it19, ap_reg_ppstg_or_cond1_reg_5197_pp0_it20, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it20) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it20)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it19) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it19)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19)))))) then
grp_image_filter_reg_int_s_fu_737_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_737_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_737_in_r <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19;
-- grp_image_filter_reg_int_s_fu_742_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_742_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it21, ap_reg_ppstg_exitcond_reg_5147_pp0_it22, ap_reg_ppstg_or_cond1_reg_5197_pp0_it21, ap_reg_ppstg_or_cond1_reg_5197_pp0_it22, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))))) then
grp_image_filter_reg_int_s_fu_742_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_742_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_742_in_r <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21;
-- grp_image_filter_reg_int_s_fu_747_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_747_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it21, ap_reg_ppstg_exitcond_reg_5147_pp0_it22, ap_reg_ppstg_or_cond1_reg_5197_pp0_it21, ap_reg_ppstg_or_cond1_reg_5197_pp0_it22, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it22) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it22)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it21) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it21)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21)))))) then
grp_image_filter_reg_int_s_fu_747_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_747_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_747_in_r <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21;
-- grp_image_filter_reg_int_s_fu_752_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_752_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it23, ap_reg_ppstg_exitcond_reg_5147_pp0_it24, ap_reg_ppstg_or_cond1_reg_5197_pp0_it23, ap_reg_ppstg_or_cond1_reg_5197_pp0_it24, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))))) then
grp_image_filter_reg_int_s_fu_752_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_752_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_752_in_r <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23;
-- grp_image_filter_reg_int_s_fu_757_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_757_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it23, ap_reg_ppstg_exitcond_reg_5147_pp0_it24, ap_reg_ppstg_or_cond1_reg_5197_pp0_it23, ap_reg_ppstg_or_cond1_reg_5197_pp0_it24, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it24) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it24)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it23) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it23)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23)))))) then
grp_image_filter_reg_int_s_fu_757_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_757_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_757_in_r <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23;
-- grp_image_filter_reg_int_s_fu_762_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_762_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it25, ap_reg_ppstg_exitcond_reg_5147_pp0_it26, ap_reg_ppstg_or_cond1_reg_5197_pp0_it25, ap_reg_ppstg_or_cond1_reg_5197_pp0_it26, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))))) then
grp_image_filter_reg_int_s_fu_762_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_762_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_762_in_r <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25;
-- grp_image_filter_reg_int_s_fu_767_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_767_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it25, ap_reg_ppstg_exitcond_reg_5147_pp0_it26, ap_reg_ppstg_or_cond1_reg_5197_pp0_it25, ap_reg_ppstg_or_cond1_reg_5197_pp0_it26, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it26) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it26)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it25) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it25)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25)))))) then
grp_image_filter_reg_int_s_fu_767_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_767_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_767_in_r <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25;
-- grp_image_filter_reg_int_s_fu_772_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_772_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it27, ap_reg_ppstg_exitcond_reg_5147_pp0_it28, ap_reg_ppstg_or_cond1_reg_5197_pp0_it27, ap_reg_ppstg_or_cond1_reg_5197_pp0_it28, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))))) then
grp_image_filter_reg_int_s_fu_772_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_772_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_772_in_r <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27;
-- grp_image_filter_reg_int_s_fu_777_ap_ce assign process. --
grp_image_filter_reg_int_s_fu_777_ap_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35, ap_reg_ppstg_exitcond_reg_5147_pp0_it27, ap_reg_ppstg_exitcond_reg_5147_pp0_it28, ap_reg_ppstg_or_cond1_reg_5197_pp0_it27, ap_reg_ppstg_or_cond1_reg_5197_pp0_it28, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27, ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))) and (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it28) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it28)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_5147_pp0_it27) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond1_reg_5197_pp0_it27)) and not((ap_const_lv1_0 = ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27)))))) then
grp_image_filter_reg_int_s_fu_777_ap_ce <= ap_const_logic_1;
else
grp_image_filter_reg_int_s_fu_777_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_image_filter_reg_int_s_fu_777_in_r <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27;
i_V_fu_807_p2 <= std_logic_vector(unsigned(p_s_reg_504) + unsigned(ap_const_lv11_1));
icmp1_fu_898_p2 <= "1" when (tmp_97_fu_888_p4 = ap_const_lv9_0) else "0";
icmp_fu_840_p2 <= "1" when (tmp_16_fu_830_p4 = ap_const_lv9_0) else "0";
iscorner_2_i_7_fu_2191_p2 <= (tmp_185_7_fu_2181_p2 and not_or_cond_fu_2186_p2);
iscorner_2_i_s_fu_2870_p2 <= (tmp10_fu_2866_p2 or ap_reg_ppstg_tmp3_reg_5878_pp0_it11);
j_V_fu_851_p2 <= std_logic_vector(unsigned(p_2_phi_fu_519_p4) + unsigned(ap_const_lv11_1));
k_buf_val_0_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_0_V_address1 <= k_buf_val_0_V_addr_reg_5161;
-- k_buf_val_0_V_ce0 assign process. --
k_buf_val_0_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_0_V_ce0 <= ap_const_logic_1;
else
k_buf_val_0_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_0_V_ce1 assign process. --
k_buf_val_0_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_0_V_ce1 <= ap_const_logic_1;
else
k_buf_val_0_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_0_V_d1 <= k_buf_val_1_V_q0;
-- k_buf_val_0_V_we1 assign process. --
k_buf_val_0_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_0_V_we1 <= ap_const_logic_1;
else
k_buf_val_0_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_1_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_1_V_address1 <= k_buf_val_1_V_addr_reg_5167;
-- k_buf_val_1_V_ce0 assign process. --
k_buf_val_1_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_1_V_ce0 <= ap_const_logic_1;
else
k_buf_val_1_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_1_V_ce1 assign process. --
k_buf_val_1_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_1_V_ce1 <= ap_const_logic_1;
else
k_buf_val_1_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_1_V_d1 <= k_buf_val_2_V_q0;
-- k_buf_val_1_V_we1 assign process. --
k_buf_val_1_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_1_V_we1 <= ap_const_logic_1;
else
k_buf_val_1_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_2_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_2_V_address1 <= k_buf_val_2_V_addr_reg_5173;
-- k_buf_val_2_V_ce0 assign process. --
k_buf_val_2_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_2_V_ce0 <= ap_const_logic_1;
else
k_buf_val_2_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_2_V_ce1 assign process. --
k_buf_val_2_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_2_V_ce1 <= ap_const_logic_1;
else
k_buf_val_2_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_2_V_d1 <= k_buf_val_3_V_q0;
-- k_buf_val_2_V_we1 assign process. --
k_buf_val_2_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_2_V_we1 <= ap_const_logic_1;
else
k_buf_val_2_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_3_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_3_V_address1 <= k_buf_val_3_V_addr_reg_5179;
-- k_buf_val_3_V_ce0 assign process. --
k_buf_val_3_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_3_V_ce0 <= ap_const_logic_1;
else
k_buf_val_3_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_3_V_ce1 assign process. --
k_buf_val_3_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_3_V_ce1 <= ap_const_logic_1;
else
k_buf_val_3_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_3_V_d1 <= k_buf_val_4_V_q0;
-- k_buf_val_3_V_we1 assign process. --
k_buf_val_3_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_3_V_we1 <= ap_const_logic_1;
else
k_buf_val_3_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_4_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_4_V_address1 <= k_buf_val_4_V_addr_reg_5185;
-- k_buf_val_4_V_ce0 assign process. --
k_buf_val_4_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_4_V_ce0 <= ap_const_logic_1;
else
k_buf_val_4_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_4_V_ce1 assign process. --
k_buf_val_4_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_4_V_ce1 <= ap_const_logic_1;
else
k_buf_val_4_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_4_V_d1 <= k_buf_val_5_V_q0;
-- k_buf_val_4_V_we1 assign process. --
k_buf_val_4_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_4_V_we1 <= ap_const_logic_1;
else
k_buf_val_4_V_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_5_V_address0 <= tmp_12_fu_867_p1(11 - 1 downto 0);
k_buf_val_5_V_address1 <= k_buf_val_5_V_addr_reg_5191;
-- k_buf_val_5_V_ce0 assign process. --
k_buf_val_5_V_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_5_V_ce0 <= ap_const_logic_1;
else
k_buf_val_5_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_val_5_V_ce1 assign process. --
k_buf_val_5_V_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
k_buf_val_5_V_ce1 <= ap_const_logic_1;
else
k_buf_val_5_V_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_5_V_d1 <= p_src_data_stream_V_dout;
-- k_buf_val_5_V_we1 assign process. --
k_buf_val_5_V_we1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35))))))) then
k_buf_val_5_V_we1 <= ap_const_logic_1;
else
k_buf_val_5_V_we1 <= ap_const_logic_0;
end if;
end process;
lhs_V_fu_1252_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_2_fu_252),9));
not_or_cond10_demorgan_fu_2093_p2 <= (tmp_183_5_reg_5572 or tmp_181_5_not_reg_5566);
not_or_cond10_fu_2782_p2 <= (ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 xor ap_const_lv1_1);
not_or_cond11_demorgan_fu_2097_p2 <= (tmp_183_6_reg_5584 or tmp_181_6_not_reg_5578);
not_or_cond11_fu_2817_p2 <= (ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 xor ap_const_lv1_1);
not_or_cond12_demorgan_fu_2425_p2 <= (tmp_181_2_reg_5769 or tmp_183_10_reg_5775);
not_or_cond12_fu_2429_p2 <= (not_or_cond12_demorgan_fu_2425_p2 xor ap_const_lv1_1);
not_or_cond13_demorgan_fu_2470_p2 <= (tmp_181_3_fu_2449_p2 or tmp_183_11_fu_2453_p2);
not_or_cond13_fu_2521_p2 <= (not_or_cond13_demorgan_reg_5801 xor ap_const_lv1_1);
not_or_cond14_demorgan_fu_2500_p2 <= (tmp_181_4_fu_2484_p2 or tmp_183_12_fu_2489_p2);
not_or_cond14_fu_2552_p2 <= (not_or_cond14_demorgan_reg_5816 xor ap_const_lv1_1);
not_or_cond15_fu_2576_p2 <= (or_cond18_reg_5821 xor ap_const_lv1_1);
not_or_cond1_fu_2213_p2 <= (or_cond11_reg_5681 xor ap_const_lv1_1);
not_or_cond2_demorgan_fu_2241_p2 <= (tmp_181_9_reg_5687 or tmp_183_9_reg_5693);
not_or_cond2_fu_2245_p2 <= (not_or_cond2_demorgan_fu_2241_p2 xor ap_const_lv1_1);
not_or_cond3_demorgan_fu_2286_p2 <= (tmp_181_s_fu_2265_p2 or tmp_183_s_fu_2269_p2);
not_or_cond3_fu_2370_p2 <= (not_or_cond3_demorgan_reg_5748 xor ap_const_lv1_1);
not_or_cond4_demorgan_fu_2316_p2 <= (tmp_181_1_fu_2300_p2 or tmp_183_8_fu_2305_p2);
not_or_cond4_fu_2386_p2 <= (not_or_cond4_demorgan_reg_5764 xor ap_const_lv1_1);
not_or_cond5_fu_2625_p2 <= (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 xor ap_const_lv1_1);
not_or_cond6_demorgan_fu_1870_p2 <= (tmp_183_1_fu_1758_p2 or tmp_181_1_not_fu_1752_p2);
not_or_cond6_fu_2648_p2 <= (ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 xor ap_const_lv1_1);
not_or_cond7_demorgan_fu_1876_p2 <= (tmp_183_2_fu_1776_p2 or tmp_181_2_not_fu_1770_p2);
not_or_cond7_fu_2704_p2 <= (ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 xor ap_const_lv1_1);
not_or_cond8_demorgan_fu_1882_p2 <= (tmp_183_3_fu_1794_p2 or tmp_181_3_not_fu_1788_p2);
not_or_cond8_fu_2720_p2 <= (ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 xor ap_const_lv1_1);
not_or_cond9_demorgan_fu_1888_p2 <= (tmp_183_4_fu_1812_p2 or tmp_181_4_not_fu_1806_p2);
not_or_cond9_fu_2767_p2 <= (ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 xor ap_const_lv1_1);
not_or_cond_fu_2186_p2 <= (or_cond10_reg_5670 xor ap_const_lv1_1);
or_cond10_fu_2055_p2 <= (tmp_183_7_fu_2049_p2 or tmp_181_7_not_fu_2044_p2);
or_cond11_fu_2075_p2 <= (tmp_181_8_fu_2069_p2 or tmp_183_7_fu_2049_p2);
or_cond12_fu_2231_p2 <= (tmp_181_9_reg_5687 or tmp_183_9_reg_5693);
or_cond13_fu_2274_p2 <= (tmp_181_s_fu_2265_p2 or tmp_183_s_fu_2269_p2);
or_cond14_fu_2310_p2 <= (tmp_181_1_fu_2300_p2 or tmp_183_8_fu_2305_p2);
or_cond15_fu_2403_p2 <= (tmp_181_2_reg_5769 or tmp_183_10_reg_5775);
or_cond16_fu_2458_p2 <= (tmp_181_3_fu_2449_p2 or tmp_183_11_fu_2453_p2);
or_cond17_fu_2494_p2 <= (tmp_181_4_fu_2484_p2 or tmp_183_12_fu_2489_p2);
or_cond18_fu_2511_p2 <= (tmp_181_5_fu_2506_p2 or ap_reg_ppstg_tmp_39_reg_5532_pp0_it5);
or_cond1_fu_883_p2 <= (tmp_8_reg_5132 and tmp_17_fu_877_p2);
or_cond2_fu_1990_p2 <= (tmp_183_5_reg_5572 or tmp_181_5_not_reg_5566);
or_cond3_fu_1994_p2 <= (tmp_183_6_reg_5584 or tmp_181_6_not_reg_5578);
or_cond4_fu_904_p2 <= (icmp_reg_5142 or icmp1_fu_898_p2);
or_cond5_fu_1746_p2 <= (tmp_39_fu_1740_p2 or tmp_181_0_not_fu_1734_p2);
or_cond6_fu_1764_p2 <= (tmp_183_1_fu_1758_p2 or tmp_181_1_not_fu_1752_p2);
or_cond7_fu_1782_p2 <= (tmp_183_2_fu_1776_p2 or tmp_181_2_not_fu_1770_p2);
or_cond8_fu_1800_p2 <= (tmp_183_3_fu_1794_p2 or tmp_181_3_not_fu_1788_p2);
or_cond9_fu_1818_p2 <= (tmp_183_4_fu_1812_p2 or tmp_181_4_not_fu_1806_p2);
or_cond_fu_862_p2 <= (tmp_7_reg_5127 and tmp_11_fu_857_p2);
-- p_2_phi_fu_519_p4 assign process. --
p_2_phi_fu_519_p4_assign_proc : process(p_2_reg_515, ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, ap_reg_ppiten_pp0_it1, j_V_reg_5151)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) then
p_2_phi_fu_519_p4 <= j_V_reg_5151;
else
p_2_phi_fu_519_p4 <= p_2_reg_515;
end if;
end process;
p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 <= std_logic_vector(resize(unsigned(p_a_0_flag_d_assign_load_5_reg_6077),32));
p_a_0_flag_d_assign_load_5_fu_3434_p3 <=
ap_const_lv8_14 when (tmp_45_fu_3428_p2(0) = '1') else
tmp_44_fu_3424_p1;
p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 <= std_logic_vector(resize(unsigned(p_a_0_flag_d_assign_load_5_tmp_s_reg_6189),32));
p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 <=
p_a_0_flag_d_assign_load_5_reg_6077 when (tmp_49_fu_3655_p2(0) = '1') else
tmp_48_reg_6088;
p_iscorner_0_i_10_fu_2709_p2 <= (tmp_185_11_fu_2699_p2 and not_or_cond7_fu_2704_p2);
p_iscorner_0_i_11_fu_2725_p2 <= (tmp_185_12_fu_2715_p2 and not_or_cond8_fu_2720_p2);
p_iscorner_0_i_12_fu_2772_p2 <= (tmp_185_13_reg_5893 and not_or_cond9_fu_2767_p2);
p_iscorner_0_i_13_fu_2787_p2 <= (tmp_185_14_fu_2777_p2 and not_or_cond10_fu_2782_p2);
p_iscorner_0_i_14_fu_2842_p2 <= (tmp_185_15_reg_5914 and not_or_cond11_reg_5919);
p_iscorner_0_i_15_fu_2846_p2 <= (tmp2_reg_5929 and tmp_185_16_reg_5924);
p_iscorner_0_i_1_fu_2391_p2 <= (tmp_185_1_fu_2381_p2 and not_or_cond4_fu_2386_p2);
p_iscorner_0_i_2_fu_2435_p2 <= (tmp_185_2_fu_2413_p2 and not_or_cond12_fu_2429_p2);
p_iscorner_0_i_3_fu_2526_p2 <= (tmp_185_3_reg_5796 and not_or_cond13_fu_2521_p2);
p_iscorner_0_i_4_fu_2557_p2 <= (tmp_185_4_fu_2540_p2 and not_or_cond14_fu_2552_p2);
p_iscorner_0_i_5_fu_2581_p2 <= (tmp_185_5_fu_2570_p2 and not_or_cond15_fu_2576_p2);
p_iscorner_0_i_6_fu_2630_p2 <= (tmp_185_6_fu_2620_p2 and not_or_cond5_fu_2625_p2);
p_iscorner_0_i_7_fu_2653_p2 <= (tmp_185_10_fu_2642_p2 and not_or_cond6_fu_2648_p2);
p_iscorner_0_i_8_fu_2218_p2 <= (tmp_185_8_fu_2202_p2 and not_or_cond1_fu_2213_p2);
p_iscorner_0_i_9_fu_2251_p2 <= (tmp_185_9_fu_2235_p2 and not_or_cond2_fu_2245_p2);
p_iscorner_0_i_s_fu_2375_p2 <= (tmp_185_s_fu_2364_p2 and not_or_cond3_fu_2370_p2);
p_mask_data_stream_V_din <=
ap_const_lv8_FF when (tmp_26_fu_4779_p2(0) = '1') else
ap_const_lv8_0;
-- p_mask_data_stream_V_write assign process. --
p_mask_data_stream_V_write_assign_proc : process(ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_or_cond4_reg_5201_pp0_it34, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_lv1_0 = ap_reg_ppstg_or_cond4_reg_5201_pp0_it34) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_mask_data_stream_V_write <= ap_const_logic_1;
else
p_mask_data_stream_V_write <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_V_read assign process. --
p_src_data_stream_V_read_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, exitcond_reg_5147, or_cond_reg_5156, ap_sig_bdd_61, ap_reg_ppiten_pp0_it1, ap_sig_bdd_136, ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_5147 = ap_const_lv1_0) and not((ap_const_lv1_0 = or_cond_reg_5156)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_61 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_136 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it35)))))) then
p_src_data_stream_V_read <= ap_const_logic_1;
else
p_src_data_stream_V_read <= ap_const_logic_0;
end if;
end process;
phitmp10_fu_2749_p2 <= std_logic_vector(unsigned(count_1_i_13_fu_2731_p3) + unsigned(ap_const_lv5_2));
phitmp1_1_fu_1900_p3 <=
ap_const_lv2_1 when (tmp_182_1_reg_5441(0) = '1') else
ap_const_lv2_2;
phitmp1_2_fu_1919_p3 <=
ap_const_lv2_1 when (tmp_182_2_reg_5461(0) = '1') else
ap_const_lv2_2;
phitmp1_3_fu_1948_p3 <=
ap_const_lv2_1 when (tmp_182_3_fu_1938_p2(0) = '1') else
ap_const_lv2_2;
phitmp1_4_fu_2101_p3 <=
ap_const_lv2_1 when (tmp_182_4_reg_5638(0) = '1') else
ap_const_lv2_2;
phitmp1_5_fu_2120_p3 <=
ap_const_lv2_1 when (tmp_182_5_reg_5649(0) = '1') else
ap_const_lv2_2;
phitmp1_6_fu_2149_p3 <=
ap_const_lv2_1 when (tmp_182_6_fu_2139_p2(0) = '1') else
ap_const_lv2_2;
phitmp1_7_fu_2340_p3 <=
ap_const_lv2_1 when (tmp_182_7_reg_5722(0) = '1') else
ap_const_lv2_2;
phitmp1_fu_1278_p3 <=
ap_const_lv2_1 when (tmp_18_fu_1266_p2(0) = '1') else
ap_const_lv2_2;
phitmp2_fu_4606_p2 <= std_logic_vector(unsigned(tmp_100_v_reg_6714) + unsigned(ap_const_lv8_FF));
phitmp3_cast_cast_cast_fu_2022_p3 <=
ap_const_lv4_2 when (or_cond3_fu_1994_p2(0) = '1') else
ap_const_lv4_3;
phitmp3_fu_1539_p3 <=
ap_const_lv2_1 when (tmp_21_fu_1527_p2(0) = '1') else
ap_const_lv2_2;
phitmp42_op_cast_cast_cast_fu_2003_p3 <=
ap_const_lv4_4 when (or_cond9_reg_5559(0) = '1') else
ap_const_lv4_5;
phitmp43_op_op_cast_cast_cast_fu_1856_p3 <=
ap_const_lv4_6 when (or_cond7_fu_1782_p2(0) = '1') else
ap_const_lv4_7;
phitmp4_fu_2208_p2 <= std_logic_vector(unsigned(count_1_i_7_reg_5675) + unsigned(ap_const_lv4_2));
phitmp5_fu_2280_p2 <= std_logic_vector(unsigned(count_1_i_9_fu_2257_p3) + unsigned(ap_const_lv4_2));
phitmp6_fu_2419_p2 <= std_logic_vector(unsigned(count_1_i_1_fu_2397_p3) + unsigned(ap_const_lv4_2));
phitmp7_fu_2546_p2 <= std_logic_vector(unsigned(count_1_i_3_cast_fu_2531_p1) + unsigned(ap_const_lv5_2));
phitmp8_fu_2600_p2 <= std_logic_vector(unsigned(count_1_i_5_fu_2587_p3) + unsigned(ap_const_lv5_2));
phitmp9_fu_2672_p2 <= std_logic_vector(unsigned(count_1_i_11_fu_2659_p3) + unsigned(ap_const_lv5_2));
phitmp_1_fu_1314_p3 <=
ap_const_lv2_1 when (tmp_176_1_fu_1302_p2(0) = '1') else
ap_const_lv2_2;
phitmp_2_fu_1350_p3 <=
ap_const_lv2_1 when (tmp_176_2_fu_1338_p2(0) = '1') else
ap_const_lv2_2;
phitmp_3_fu_1386_p3 <=
ap_const_lv2_1 when (tmp_176_3_fu_1374_p2(0) = '1') else
ap_const_lv2_2;
phitmp_4_fu_1631_p3 <=
ap_const_lv2_1 when (tmp_176_4_reg_5337(0) = '1') else
ap_const_lv2_2;
phitmp_5_fu_1659_p3 <=
ap_const_lv2_1 when (tmp_176_5_reg_5357(0) = '1') else
ap_const_lv2_2;
phitmp_6_fu_1687_p3 <=
ap_const_lv2_1 when (tmp_176_6_reg_5377(0) = '1') else
ap_const_lv2_2;
phitmp_7_fu_1715_p3 <=
ap_const_lv2_1 when (tmp_176_7_reg_5397(0) = '1') else
ap_const_lv2_2;
phitmp_fu_2811_p2 <= std_logic_vector(unsigned(count_1_i_15_fu_2793_p3) + unsigned(ap_const_lv5_2));
r_V_1_1_fu_1557_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_1_fu_1553_p1));
r_V_1_2_fu_1584_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_2_fu_1580_p1));
r_V_1_3_fu_1611_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_3_fu_1607_p1));
r_V_1_4_fu_1626_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_4_fu_1622_p1));
r_V_1_5_fu_1654_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_5_fu_1650_p1));
r_V_1_6_fu_1682_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_6_fu_1678_p1));
r_V_1_7_fu_1710_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_7_fu_1706_p1));
r_V_1_fu_1516_p2 <= std_logic_vector(unsigned(lhs_V_reg_5240) - unsigned(rhs_V_1_fu_1512_p1));
r_V_2_fu_1332_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_2_fu_1328_p1));
r_V_3_fu_1368_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_3_fu_1364_p1));
r_V_4_fu_1404_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_4_fu_1400_p1));
r_V_5_fu_1426_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_5_fu_1422_p1));
r_V_6_fu_1448_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_6_fu_1444_p1));
r_V_7_fu_1470_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_7_fu_1466_p1));
r_V_fu_1260_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_fu_1256_p1));
r_V_s_fu_1296_p2 <= std_logic_vector(unsigned(lhs_V_fu_1252_p1) - unsigned(rhs_V_s_fu_1292_p1));
rhs_V_1_1_fu_1553_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_2_3_fu_320),9));
rhs_V_1_2_fu_1580_p1 <= std_logic_vector(resize(unsigned(win_val_5_V_1_3_fu_296),9));
rhs_V_1_3_fu_1607_p1 <= std_logic_vector(resize(unsigned(win_val_4_V_0_3_fu_268),9));
rhs_V_1_4_fu_1622_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_0_3_fu_240),9));
rhs_V_1_5_fu_1650_p1 <= std_logic_vector(resize(unsigned(win_val_2_V_0_3_fu_212),9));
rhs_V_1_6_fu_1678_p1 <= std_logic_vector(resize(unsigned(win_val_1_V_1_3_fu_188),9));
rhs_V_1_7_fu_1706_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_2_3_fu_168),9));
rhs_V_1_fu_1512_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_2_fu_324),9));
rhs_V_2_fu_1328_p1 <= std_logic_vector(resize(unsigned(win_val_1_V_4_fu_204),9));
rhs_V_3_fu_1364_p1 <= std_logic_vector(resize(unsigned(win_val_2_V_5_fu_236),9));
rhs_V_4_fu_1400_p1 <= std_logic_vector(resize(unsigned(win_val_3_V_5_fu_264),9));
rhs_V_5_fu_1422_p1 <= std_logic_vector(resize(unsigned(win_val_4_V_5_fu_292),9));
rhs_V_6_fu_1444_p1 <= std_logic_vector(resize(unsigned(win_val_5_V_4_fu_312),9));
rhs_V_7_fu_1466_p1 <= std_logic_vector(resize(unsigned(win_val_6_V_3_fu_156),9));
rhs_V_fu_1256_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_2_fu_172),9));
rhs_V_s_fu_1292_p1 <= std_logic_vector(resize(unsigned(win_val_0_V_3_fu_176),9));
tmp10_fu_2866_p2 <= (tmp14_reg_5944 or ap_reg_ppstg_tmp11_reg_5934_pp0_it11);
tmp11_fu_2833_p2 <= (tmp13_reg_5904 or ap_reg_ppstg_tmp12_reg_5883_pp0_it9);
tmp12_fu_2694_p2 <= (p_iscorner_0_i_5_reg_5832 or p_iscorner_0_i_6_fu_2630_p2);
tmp13_fu_2762_p2 <= (p_iscorner_0_i_7_reg_5862 or p_iscorner_0_i_10_fu_2709_p2);
tmp14_fu_2861_p2 <= (tmp16_fu_2856_p2 or tmp15_reg_5939);
tmp15_fu_2837_p2 <= (p_iscorner_0_i_11_reg_5888 or p_iscorner_0_i_12_fu_2772_p2);
tmp16_fu_2856_p2 <= (tmp17_fu_2850_p2 or p_iscorner_0_i_13_reg_5909);
tmp17_fu_2850_p2 <= (p_iscorner_0_i_14_fu_2842_p2 or p_iscorner_0_i_15_fu_2846_p2);
tmp18_fu_4771_p2 <= (tmp20_reg_6744 and tmp19_reg_6739);
tmp19_fu_4701_p2 <= (tmp_52_fu_4647_p2 and tmp_9_reg_5137);
tmp20_fu_4712_p2 <= (tmp21_fu_4706_p2 and ap_reg_ppstg_tmp_53_reg_6719_pp0_it33);
tmp21_fu_4706_p2 <= (tmp_73_fu_4653_p2 and tmp_242_1_fu_4659_p2);
tmp22_fu_4775_p2 <= (tmp25_reg_6754 and tmp23_reg_6749);
tmp23_fu_4723_p2 <= (tmp24_fu_4717_p2 and tmp_242_2_fu_4665_p2);
tmp24_fu_4717_p2 <= (tmp_74_fu_4671_p2 and tmp_245_1_fu_4677_p2);
tmp25_fu_4735_p2 <= (tmp26_fu_4729_p2 and tmp_245_2_fu_4683_p2);
tmp26_fu_4729_p2 <= (tmp_55_fu_4695_p2 and tmp_54_fu_4689_p2);
tmp2_fu_2828_p2 <= (not_or_cond11_fu_2817_p2 and ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9);
tmp3_fu_2689_p2 <= (tmp7_fu_2685_p2 or tmp4_reg_5847);
tmp4_fu_2606_p2 <= (tmp6_reg_5827 or ap_reg_ppstg_tmp5_reg_5781_pp0_it6);
tmp5_fu_2334_p2 <= (iscorner_2_i_7_fu_2191_p2 or p_iscorner_0_i_8_fu_2218_p2);
tmp6_fu_2516_p2 <= (p_iscorner_0_i_9_reg_5738 or p_iscorner_0_i_s_fu_2375_p2);
tmp7_fu_2685_p2 <= (tmp9_reg_5857 or tmp8_reg_5852);
tmp8_fu_2610_p2 <= (p_iscorner_0_i_1_reg_5786 or p_iscorner_0_i_2_reg_5791);
tmp9_fu_2614_p2 <= (p_iscorner_0_i_3_fu_2526_p2 or p_iscorner_0_i_4_fu_2557_p2);
tmp_100_v_fu_4593_p3 <=
a0_7_tmp_232_7_reg_6691 when (tmp_51_fu_4588_p2(0) = '1') else
tmp_50_fu_4583_p2;
tmp_11_fu_857_p2 <= "1" when (unsigned(p_2_phi_fu_519_p4) < unsigned(tmp_15_reg_5103)) else "0";
tmp_12_fu_867_p1 <= std_logic_vector(resize(unsigned(p_2_phi_fu_519_p4),64));
tmp_14_fu_4577_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_p_2_reg_515_pp0_it31),64));
tmp_15_fu_786_p1 <= p_src_cols_V_read(11 - 1 downto 0);
tmp_16_fu_830_p4 <= p_s_reg_504(10 downto 2);
tmp_176_1_fu_1302_p2 <= "1" when (signed(r_V_s_fu_1296_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_2_fu_1338_p2 <= "1" when (signed(r_V_2_fu_1332_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_3_fu_1374_p2 <= "1" when (signed(r_V_3_fu_1368_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_4_fu_1410_p2 <= "1" when (signed(r_V_4_fu_1404_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_5_fu_1432_p2 <= "1" when (signed(r_V_5_fu_1426_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_6_fu_1454_p2 <= "1" when (signed(r_V_6_fu_1448_p2) > signed(ap_const_lv9_14)) else "0";
tmp_176_7_fu_1476_p2 <= "1" when (signed(r_V_7_fu_1470_p2) > signed(ap_const_lv9_14)) else "0";
tmp_177_1_fu_1308_p2 <= "1" when (signed(r_V_s_fu_1296_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_2_fu_1344_p2 <= "1" when (signed(r_V_2_fu_1332_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_3_fu_1380_p2 <= "1" when (signed(r_V_3_fu_1368_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_4_fu_1416_p2 <= "1" when (signed(r_V_4_fu_1404_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_5_fu_1438_p2 <= "1" when (signed(r_V_5_fu_1426_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_6_fu_1460_p2 <= "1" when (signed(r_V_6_fu_1448_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_177_7_fu_1482_p2 <= "1" when (signed(r_V_7_fu_1470_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_17_fu_877_p2 <= "1" when (unsigned(p_2_phi_fu_519_p4) > unsigned(ap_const_lv11_5)) else "0";
tmp_181_0_not_fu_1734_p2 <= "0" when (flag_val_V_assign_load_1_s_fu_1521_p3 = flag_val_V_assign_load_1_1_fu_1562_p3) else "1";
tmp_181_1_fu_2300_p2 <= "0" when (flag_val_V_assign_load_1_5_reg_5631 = flag_val_V_assign_load_1_7_fu_2112_p3) else "1";
tmp_181_1_not_fu_1752_p2 <= "0" when (flag_val_V_assign_load_1_1_fu_1562_p3 = flag_val_V_assign_load_1_2_fu_1589_p3) else "1";
tmp_181_2_fu_2322_p2 <= "0" when (flag_val_V_assign_load_1_7_fu_2112_p3 = flag_val_V_assign_load_1_10_fu_2131_p3) else "1";
tmp_181_2_not_fu_1770_p2 <= "0" when (flag_val_V_assign_load_1_2_fu_1589_p3 = flag_val_V_assign_load_1_4_fu_1616_p3) else "1";
tmp_181_3_fu_2449_p2 <= "0" when (flag_val_V_assign_load_1_10_reg_5709 = flag_val_V_assign_load_1_12_reg_5715) else "1";
tmp_181_3_not_fu_1788_p2 <= "0" when (flag_val_V_assign_load_1_4_fu_1616_p3 = flag_val_V_assign_load_1_6_fu_1642_p3) else "1";
tmp_181_4_fu_2484_p2 <= "0" when (flag_val_V_assign_load_1_12_reg_5715 = flag_val_V_assign_load_1_14_fu_2351_p3) else "1";
tmp_181_4_not_fu_1806_p2 <= "0" when (flag_val_V_assign_load_1_6_fu_1642_p3 = flag_val_V_assign_load_1_8_fu_1670_p3) else "1";
tmp_181_5_fu_2506_p2 <= "0" when (flag_val_V_assign_load_1_14_fu_2351_p3 = ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5) else "1";
tmp_181_5_not_fu_1824_p2 <= "0" when (flag_val_V_assign_load_1_8_fu_1670_p3 = flag_val_V_assign_load_1_11_fu_1698_p3) else "1";
tmp_181_6_not_fu_1836_p2 <= "0" when (flag_val_V_assign_load_1_11_fu_1698_p3 = flag_val_V_assign_load_1_13_fu_1726_p3) else "1";
tmp_181_7_not_fu_2044_p2 <= "0" when (flag_val_V_assign_load_1_13_reg_5527 = flag_val_V_assign_load_2_s_fu_1894_p3) else "1";
tmp_181_8_fu_2069_p2 <= "0" when (flag_val_V_assign_load_2_s_fu_1894_p3 = flag_val_V_assign_load_1_9_fu_1911_p3) else "1";
tmp_181_9_fu_2081_p2 <= "0" when (flag_val_V_assign_load_1_9_fu_1911_p3 = flag_val_V_assign_load_1_3_fu_1930_p3) else "1";
tmp_181_s_fu_2265_p2 <= "0" when (flag_val_V_assign_load_1_3_reg_5625 = flag_val_V_assign_load_1_5_reg_5631) else "1";
tmp_182_1_fu_1568_p2 <= "1" when (signed(r_V_1_1_fu_1557_p2) > signed(ap_const_lv9_14)) else "0";
tmp_182_2_fu_1595_p2 <= "1" when (signed(r_V_1_2_fu_1584_p2) > signed(ap_const_lv9_14)) else "0";
tmp_182_3_fu_1938_p2 <= "1" when (signed(r_V_1_3_reg_5472) > signed(ap_const_lv9_14)) else "0";
tmp_182_4_fu_1970_p2 <= "1" when (signed(r_V_1_4_reg_5483) > signed(ap_const_lv9_14)) else "0";
tmp_182_5_fu_1980_p2 <= "1" when (signed(r_V_1_5_reg_5494) > signed(ap_const_lv9_14)) else "0";
tmp_182_6_fu_2139_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) > signed(ap_const_lv9_14)) else "0";
tmp_182_7_fu_2171_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) > signed(ap_const_lv9_14)) else "0";
tmp_183_10_fu_2328_p2 <= "1" when (flag_val_V_assign_load_1_7_fu_2112_p3 = ap_const_lv2_0) else "0";
tmp_183_11_fu_2453_p2 <= "1" when (flag_val_V_assign_load_1_10_reg_5709 = ap_const_lv2_0) else "0";
tmp_183_12_fu_2489_p2 <= "1" when (flag_val_V_assign_load_1_12_reg_5715 = ap_const_lv2_0) else "0";
tmp_183_1_fu_1758_p2 <= "1" when (flag_val_V_assign_load_1_1_fu_1562_p3 = ap_const_lv2_0) else "0";
tmp_183_2_fu_1776_p2 <= "1" when (flag_val_V_assign_load_1_2_fu_1589_p3 = ap_const_lv2_0) else "0";
tmp_183_3_fu_1794_p2 <= "1" when (flag_val_V_assign_load_1_4_fu_1616_p3 = ap_const_lv2_0) else "0";
tmp_183_4_fu_1812_p2 <= "1" when (flag_val_V_assign_load_1_6_fu_1642_p3 = ap_const_lv2_0) else "0";
tmp_183_5_fu_1830_p2 <= "1" when (flag_val_V_assign_load_1_8_fu_1670_p3 = ap_const_lv2_0) else "0";
tmp_183_6_fu_1842_p2 <= "1" when (flag_val_V_assign_load_1_11_fu_1698_p3 = ap_const_lv2_0) else "0";
tmp_183_7_fu_2049_p2 <= "1" when (flag_val_V_assign_load_2_s_fu_1894_p3 = ap_const_lv2_0) else "0";
tmp_183_8_fu_2305_p2 <= "1" when (flag_val_V_assign_load_1_5_reg_5631 = ap_const_lv2_0) else "0";
tmp_183_9_fu_2087_p2 <= "1" when (flag_val_V_assign_load_1_9_fu_1911_p3 = ap_const_lv2_0) else "0";
tmp_183_s_fu_2269_p2 <= "1" when (flag_val_V_assign_load_1_3_reg_5625 = ap_const_lv2_0) else "0";
tmp_184_1_fu_1574_p2 <= "1" when (signed(r_V_1_1_fu_1557_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_2_fu_1601_p2 <= "1" when (signed(r_V_1_2_fu_1584_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_3_fu_1943_p2 <= "1" when (signed(r_V_1_3_reg_5472) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_4_fu_1975_p2 <= "1" when (signed(r_V_1_4_reg_5483) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_5_fu_1985_p2 <= "1" when (signed(r_V_1_5_reg_5494) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_6_fu_2144_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) < signed(ap_const_lv9_1EC)) else "0";
tmp_184_7_fu_2176_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) < signed(ap_const_lv9_1EC)) else "0";
tmp_185_10_fu_2642_p2 <= "1" when (unsigned(count_1_i_10_fu_2636_p3) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_11_fu_2699_p2 <= "1" when (unsigned(count_4_reg_5867) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_12_fu_2715_p2 <= "1" when (unsigned(count_1_i_12_reg_5872) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_13_fu_2743_p2 <= "1" when (unsigned(count_5_fu_2737_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_14_fu_2777_p2 <= "1" when (unsigned(count_1_i_14_reg_5898) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_15_fu_2805_p2 <= "1" when (unsigned(count_6_fu_2799_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_16_fu_2822_p2 <= "1" when (unsigned(phitmp_fu_2811_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_1_fu_2381_p2 <= "1" when (unsigned(count_1_i_s_reg_5753) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_2_fu_2413_p2 <= "1" when (unsigned(count_1_fu_2407_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_3_fu_2464_p2 <= "1" when (unsigned(count_1_i_2_fu_2441_p3) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_4_fu_2540_p2 <= "1" when (unsigned(count_2_fu_2534_p2) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_5_fu_2570_p2 <= "1" when (unsigned(count_1_i_4_fu_2563_p3) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_6_fu_2620_p2 <= "1" when (unsigned(count_3_reg_5837) > unsigned(ap_const_lv5_8)) else "0";
tmp_185_7_fu_2181_p2 <= "1" when (unsigned(count_1_i_6_reg_5665) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_8_fu_2202_p2 <= "1" when (unsigned(count_8_fu_2197_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_9_fu_2235_p2 <= "1" when (unsigned(count_1_i_8_fu_2224_p3) > unsigned(ap_const_lv4_8)) else "0";
tmp_185_s_fu_2364_p2 <= "1" when (unsigned(count_s_fu_2359_p2) > unsigned(ap_const_lv4_8)) else "0";
tmp_188_1_fu_2875_p2 <= "1" when (signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) < signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)) else "0";
tmp_188_2_fu_3176_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) < signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)) else "0";
tmp_188_3_fu_2905_p2 <= "1" when (signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) < signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)) else "0";
tmp_188_4_fu_3206_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) < signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)) else "0";
tmp_188_5_fu_2935_p2 <= "1" when (signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) < signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)) else "0";
tmp_188_7_fu_2965_p2 <= "1" when (signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) < signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)) else "0";
tmp_188_9_fu_3083_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) < signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)) else "0";
tmp_188_s_fu_3146_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) < signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)) else "0";
tmp_18_fu_1266_p2 <= "1" when (signed(r_V_fu_1260_p2) > signed(ap_const_lv9_14)) else "0";
tmp_192_1_fu_2995_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_542_ap_return) < signed(grp_image_filter_reg_int_s_fu_552_ap_return)) else "0";
tmp_192_2_fu_3333_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_632_ap_return) < signed(grp_image_filter_reg_int_s_fu_642_ap_return)) else "0";
tmp_192_3_fu_3025_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_552_ap_return) < signed(grp_image_filter_reg_int_s_fu_562_ap_return)) else "0";
tmp_192_4_fu_3363_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_642_ap_return) < signed(ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15)) else "0";
tmp_192_5_fu_3053_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_562_ap_return) < signed(grp_image_filter_reg_int_s_fu_572_ap_return)) else "0";
tmp_192_7_fu_3236_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14) < signed(grp_image_filter_reg_int_s_fu_602_ap_return)) else "0";
tmp_192_9_fu_3277_p2 <= "1" when (signed(flag_d_min2_9_reg_6017) < signed(grp_image_filter_reg_int_s_fu_622_ap_return)) else "0";
tmp_192_s_fu_3303_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_622_ap_return) < signed(grp_image_filter_reg_int_s_fu_632_ap_return)) else "0";
tmp_193_1_fu_2879_p3 <=
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 when (tmp_188_1_fu_2875_p2(0) = '1') else
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
tmp_193_2_fu_3180_p3 <=
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 when (tmp_188_2_fu_3176_p2(0) = '1') else
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
tmp_193_3_fu_2909_p3 <=
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 when (tmp_188_3_fu_2905_p2(0) = '1') else
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
tmp_193_4_fu_3210_p3 <=
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 when (tmp_188_4_fu_3206_p2(0) = '1') else
ap_reg_ppstg_r_V_reg_5252_pp0_it14;
tmp_193_5_fu_2939_p3 <=
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 when (tmp_188_5_fu_2935_p2(0) = '1') else
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
tmp_193_7_fu_2969_p3 <=
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 when (tmp_188_7_fu_2965_p2(0) = '1') else
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
tmp_193_9_fu_3087_p3 <=
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 when (tmp_188_9_fu_3083_p2(0) = '1') else
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
tmp_193_s_fu_3150_p3 <=
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 when (tmp_188_s_fu_3146_p2(0) = '1') else
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
tmp_195_1_fu_2890_p2 <= "1" when (signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) > signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)) else "0";
tmp_195_2_fu_3191_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) > signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)) else "0";
tmp_195_3_fu_2920_p2 <= "1" when (signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) > signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)) else "0";
tmp_195_4_fu_3221_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) > signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)) else "0";
tmp_195_5_fu_2950_p2 <= "1" when (signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) > signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)) else "0";
tmp_195_7_fu_2980_p2 <= "1" when (signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) > signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)) else "0";
tmp_195_9_fu_3098_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) > signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)) else "0";
tmp_195_s_fu_3161_p2 <= "1" when (signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) > signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)) else "0";
tmp_199_1_fu_3113_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_582_ap_return) < signed(grp_image_filter_reg_int_s_fu_592_ap_return)) else "0";
tmp_199_2_fu_3604_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_692_ap_return) < signed(ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16)) else "0";
tmp_199_3_fu_3389_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_652_ap_return) < signed(grp_image_filter_reg_int_s_fu_662_ap_return)) else "0";
tmp_199_4_fu_3628_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_702_ap_return) < signed(flag_d_min4_3_reg_6053)) else "0";
tmp_199_5_fu_3500_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16) < signed(grp_image_filter_reg_int_s_fu_672_ap_return)) else "0";
tmp_199_7_fu_3524_p2 <= "1" when (signed(flag_d_min4_7_reg_6065) < signed(grp_image_filter_reg_int_s_fu_682_ap_return)) else "0";
tmp_199_9_fu_3548_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_672_ap_return) < signed(grp_image_filter_reg_int_s_fu_692_ap_return)) else "0";
tmp_199_s_fu_3576_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_682_ap_return) < signed(grp_image_filter_reg_int_s_fu_702_ap_return)) else "0";
tmp_19_fu_1272_p2 <= "1" when (signed(r_V_fu_1260_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_200_3_fu_3031_p3 <=
grp_image_filter_reg_int_s_fu_552_ap_return when (tmp_192_3_fu_3025_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_562_ap_return;
tmp_202_1_fu_3010_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_547_ap_return) > signed(grp_image_filter_reg_int_s_fu_557_ap_return)) else "0";
tmp_202_2_fu_3348_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_637_ap_return) > signed(grp_image_filter_reg_int_s_fu_647_ap_return)) else "0";
tmp_202_3_fu_3039_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_557_ap_return) > signed(grp_image_filter_reg_int_s_fu_567_ap_return)) else "0";
tmp_202_4_fu_3376_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_647_ap_return) > signed(ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15)) else "0";
tmp_202_5_fu_3068_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_567_ap_return) > signed(grp_image_filter_reg_int_s_fu_577_ap_return)) else "0";
tmp_202_7_fu_3249_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14) > signed(grp_image_filter_reg_int_s_fu_607_ap_return)) else "0";
tmp_202_9_fu_3290_p2 <= "1" when (signed(flag_d_max2_9_reg_6023) > signed(grp_image_filter_reg_int_s_fu_627_ap_return)) else "0";
tmp_202_s_fu_3318_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_627_ap_return) > signed(grp_image_filter_reg_int_s_fu_637_ap_return)) else "0";
tmp_203_1_fu_2894_p3 <=
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 when (tmp_195_1_fu_2890_p2(0) = '1') else
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
tmp_203_2_fu_3195_p3 <=
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 when (tmp_195_2_fu_3191_p2(0) = '1') else
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
tmp_203_3_fu_2924_p3 <=
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 when (tmp_195_3_fu_2920_p2(0) = '1') else
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
tmp_203_4_fu_3225_p3 <=
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 when (tmp_195_4_fu_3221_p2(0) = '1') else
ap_reg_ppstg_r_V_reg_5252_pp0_it14;
tmp_203_5_fu_2954_p3 <=
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 when (tmp_195_5_fu_2950_p2(0) = '1') else
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
tmp_203_7_fu_2984_p3 <=
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 when (tmp_195_7_fu_2980_p2(0) = '1') else
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
tmp_203_9_fu_3102_p3 <=
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 when (tmp_195_9_fu_3098_p2(0) = '1') else
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
tmp_203_s_fu_3165_p3 <=
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 when (tmp_195_s_fu_3161_p2(0) = '1') else
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
tmp_209_1_fu_3666_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_712_ap_return) < signed(flag_d_assign_2_fu_3497_p1)) else "0";
tmp_209_2_fu_3794_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_722_ap_return) < signed(flag_d_assign_4_fu_3777_p1)) else "0";
tmp_209_3_fu_3922_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_732_ap_return) < signed(flag_d_assign_6_fu_3905_p1)) else "0";
tmp_209_4_fu_4050_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_742_ap_return) < signed(flag_d_assign_8_fu_4033_p1)) else "0";
tmp_209_5_fu_4178_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_752_ap_return) < signed(flag_d_assign_s_fu_4161_p1)) else "0";
tmp_209_6_fu_4306_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_762_ap_return) < signed(flag_d_assign_11_fu_4289_p1)) else "0";
tmp_209_7_fu_4434_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_772_ap_return) < signed(flag_d_assign_13_fu_4417_p1)) else "0";
tmp_20_fu_1286_p2 <= (tmp_18_fu_1266_p2 or tmp_19_fu_1272_p2);
tmp_210_2_fu_3609_p3 <=
grp_image_filter_reg_int_s_fu_692_ap_return when (tmp_199_2_fu_3604_p2(0) = '1') else
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16;
tmp_210_4_fu_3633_p3 <=
grp_image_filter_reg_int_s_fu_702_ap_return when (tmp_199_4_fu_3628_p2(0) = '1') else
flag_d_min4_3_reg_6053;
tmp_210_5_fu_3505_p3 <=
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 when (tmp_199_5_fu_3500_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_672_ap_return;
tmp_210_7_fu_3529_p3 <=
flag_d_min4_7_reg_6065 when (tmp_199_7_fu_3524_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_682_ap_return;
tmp_210_9_fu_3554_p3 <=
grp_image_filter_reg_int_s_fu_672_ap_return when (tmp_199_9_fu_3548_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_692_ap_return;
tmp_210_s_fu_3582_p3 <=
grp_image_filter_reg_int_s_fu_682_ap_return when (tmp_199_s_fu_3576_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_702_ap_return;
tmp_212_1_fu_3128_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_587_ap_return) > signed(grp_image_filter_reg_int_s_fu_597_ap_return)) else "0";
tmp_212_2_fu_3616_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_697_ap_return) > signed(ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16)) else "0";
tmp_212_3_fu_3404_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_657_ap_return) > signed(grp_image_filter_reg_int_s_fu_667_ap_return)) else "0";
tmp_212_4_fu_3640_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_707_ap_return) > signed(flag_d_max4_3_reg_6059)) else "0";
tmp_212_5_fu_3512_p2 <= "1" when (signed(ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16) > signed(grp_image_filter_reg_int_s_fu_677_ap_return)) else "0";
tmp_212_7_fu_3536_p2 <= "1" when (signed(flag_d_max4_7_reg_6071) > signed(grp_image_filter_reg_int_s_fu_687_ap_return)) else "0";
tmp_212_9_fu_3562_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_677_ap_return) > signed(grp_image_filter_reg_int_s_fu_697_ap_return)) else "0";
tmp_212_s_fu_3590_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_687_ap_return) > signed(grp_image_filter_reg_int_s_fu_707_ap_return)) else "0";
tmp_213_3_fu_3045_p3 <=
grp_image_filter_reg_int_s_fu_557_ap_return when (tmp_202_3_fu_3039_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_567_ap_return;
tmp_216_1_fu_3698_p3 <=
flag_d_min8_3_reg_6115 when (tmp_209_1_reg_6195(0) = '1') else
flag_d_assign_2_reg_6109;
tmp_216_2_fu_3826_p3 <=
flag_d_min8_5_reg_6249 when (tmp_209_2_reg_6269(0) = '1') else
flag_d_assign_4_reg_6243;
tmp_216_3_fu_3954_p3 <=
flag_d_min8_7_reg_6323 when (tmp_209_3_reg_6343(0) = '1') else
flag_d_assign_6_reg_6317;
tmp_216_4_fu_4082_p3 <=
flag_d_min8_9_reg_6397 when (tmp_209_4_reg_6417(0) = '1') else
flag_d_assign_8_reg_6391;
tmp_216_5_fu_4210_p3 <=
tmp_211_s_reg_6471 when (tmp_209_5_reg_6491(0) = '1') else
flag_d_assign_s_reg_6465;
tmp_216_6_fu_4338_p3 <=
tmp_211_1_reg_6545 when (tmp_209_6_reg_6565(0) = '1') else
flag_d_assign_11_reg_6539;
tmp_216_7_fu_4466_p3 <=
tmp_211_2_reg_6619 when (tmp_209_7_reg_6639(0) = '1') else
flag_d_assign_13_reg_6613;
tmp_217_1_fu_3707_p2 <= "1" when (signed(p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1) > signed(tmp_216_1_fu_3698_p3)) else "0";
tmp_217_2_fu_3835_p2 <= "1" when (signed(a0_tmp_232_1_cast_fu_3823_p1) > signed(tmp_216_2_fu_3826_p3)) else "0";
tmp_217_3_fu_3963_p2 <= "1" when (signed(a0_2_tmp_232_2_cast_fu_3951_p1) > signed(tmp_216_3_fu_3954_p3)) else "0";
tmp_217_4_fu_4091_p2 <= "1" when (signed(a0_3_tmp_232_3_cast_fu_4079_p1) > signed(tmp_216_4_fu_4082_p3)) else "0";
tmp_217_5_fu_4219_p2 <= "1" when (signed(a0_4_tmp_232_4_cast_fu_4207_p1) > signed(tmp_216_5_fu_4210_p3)) else "0";
tmp_217_6_fu_4347_p2 <= "1" when (signed(a0_5_tmp_232_5_cast_fu_4335_p1) > signed(tmp_216_6_fu_4338_p3)) else "0";
tmp_217_7_fu_4475_p2 <= "1" when (signed(a0_6_tmp_232_6_cast_fu_4463_p1) > signed(tmp_216_7_fu_4466_p3)) else "0";
tmp_21_fu_1527_p2 <= "1" when (signed(r_V_1_fu_1516_p2) > signed(ap_const_lv9_14)) else "0";
tmp_221_1_fu_3686_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_717_ap_return) > signed(flag_d_assign_2_fu_3497_p1)) else "0";
tmp_221_2_fu_3814_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_727_ap_return) > signed(flag_d_assign_4_fu_3777_p1)) else "0";
tmp_221_3_fu_3942_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_737_ap_return) > signed(flag_d_assign_6_fu_3905_p1)) else "0";
tmp_221_4_fu_4070_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_747_ap_return) > signed(flag_d_assign_8_fu_4033_p1)) else "0";
tmp_221_5_fu_4198_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_757_ap_return) > signed(flag_d_assign_s_fu_4161_p1)) else "0";
tmp_221_6_fu_4326_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_767_ap_return) > signed(flag_d_assign_11_fu_4289_p1)) else "0";
tmp_221_7_fu_4454_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_777_ap_return) > signed(flag_d_assign_13_fu_4417_p1)) else "0";
tmp_225_2_fu_3621_p3 <=
grp_image_filter_reg_int_s_fu_697_ap_return when (tmp_212_2_fu_3616_p2(0) = '1') else
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16;
tmp_225_4_fu_3645_p3 <=
grp_image_filter_reg_int_s_fu_707_ap_return when (tmp_212_4_fu_3640_p2(0) = '1') else
flag_d_max4_3_reg_6059;
tmp_225_5_fu_3517_p3 <=
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 when (tmp_212_5_fu_3512_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_677_ap_return;
tmp_225_7_fu_3541_p3 <=
flag_d_max4_7_reg_6071 when (tmp_212_7_fu_3536_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_687_ap_return;
tmp_225_9_fu_3568_p3 <=
grp_image_filter_reg_int_s_fu_677_ap_return when (tmp_212_9_fu_3562_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_697_ap_return;
tmp_225_s_fu_3596_p3 <=
grp_image_filter_reg_int_s_fu_687_ap_return when (tmp_212_s_fu_3590_p2(0) = '1') else
grp_image_filter_reg_int_s_fu_707_ap_return;
tmp_227_1_fu_3739_p3 <=
flag_d_max8_3_reg_6122 when (tmp_221_1_reg_6206(0) = '1') else
flag_d_assign_2_reg_6109;
tmp_227_2_fu_3867_p3 <=
flag_d_max8_5_reg_6256 when (tmp_221_2_reg_6280(0) = '1') else
flag_d_assign_4_reg_6243;
tmp_227_3_fu_3995_p3 <=
flag_d_max8_7_reg_6330 when (tmp_221_3_reg_6354(0) = '1') else
flag_d_assign_6_reg_6317;
tmp_227_4_fu_4123_p3 <=
flag_d_max8_9_reg_6404 when (tmp_221_4_reg_6428(0) = '1') else
flag_d_assign_8_reg_6391;
tmp_227_5_fu_4251_p3 <=
tmp_226_s_reg_6478 when (tmp_221_5_reg_6502(0) = '1') else
flag_d_assign_s_reg_6465;
tmp_227_6_fu_4379_p3 <=
tmp_226_1_reg_6552 when (tmp_221_6_reg_6576(0) = '1') else
flag_d_assign_11_reg_6539;
tmp_227_7_fu_4507_p3 <=
tmp_226_2_reg_6626 when (tmp_221_7_reg_6650(0) = '1') else
flag_d_assign_13_reg_6613;
tmp_228_1_fu_3748_p2 <= "1" when (signed(b0_tmp_239_cast_fu_3736_p1) < signed(tmp_227_1_fu_3739_p3)) else "0";
tmp_228_2_fu_3876_p2 <= "1" when (signed(b0_tmp_239_1_cast_fu_3864_p1) < signed(tmp_227_2_fu_3867_p3)) else "0";
tmp_228_3_fu_4004_p2 <= "1" when (signed(b0_2_tmp_239_2_cast_fu_3992_p1) < signed(tmp_227_3_fu_3995_p3)) else "0";
tmp_228_4_fu_4132_p2 <= "1" when (signed(b0_3_tmp_239_3_cast_fu_4120_p1) < signed(tmp_227_4_fu_4123_p3)) else "0";
tmp_228_5_fu_4260_p2 <= "1" when (signed(b0_4_tmp_239_4_cast_fu_4248_p1) < signed(tmp_227_5_fu_4251_p3)) else "0";
tmp_228_6_fu_4388_p2 <= "1" when (signed(b0_5_tmp_239_5_cast_fu_4376_p1) < signed(tmp_227_6_fu_4379_p3)) else "0";
tmp_228_7_fu_4516_p2 <= "1" when (signed(b0_6_tmp_239_6_cast_fu_4504_p1) < signed(tmp_227_7_fu_4507_p3)) else "0";
tmp_22_fu_1533_p2 <= "1" when (signed(r_V_1_fu_1516_p2) < signed(ap_const_lv9_1EC)) else "0";
tmp_231_1_fu_3720_p2 <= "1" when (signed(flag_d_min8_3_reg_6115) < signed(flag_d_assign_10_fu_3692_p1)) else "0";
tmp_231_2_fu_3848_p2 <= "1" when (signed(flag_d_min8_5_reg_6249) < signed(flag_d_assign_12_fu_3820_p1)) else "0";
tmp_231_3_fu_3976_p2 <= "1" when (signed(flag_d_min8_7_reg_6323) < signed(flag_d_assign_14_fu_3948_p1)) else "0";
tmp_231_4_fu_4104_p2 <= "1" when (signed(flag_d_min8_9_reg_6397) < signed(flag_d_assign_1_fu_4076_p1)) else "0";
tmp_231_5_fu_4232_p2 <= "1" when (signed(tmp_211_s_reg_6471) < signed(flag_d_assign_3_fu_4204_p1)) else "0";
tmp_231_6_fu_4360_p2 <= "1" when (signed(tmp_211_1_reg_6545) < signed(flag_d_assign_5_fu_4332_p1)) else "0";
tmp_231_7_fu_4488_p2 <= "1" when (signed(tmp_211_2_reg_6619) < signed(flag_d_assign_7_fu_4460_p1)) else "0";
tmp_232_1_fu_3725_p3 <=
flag_d_min8_3_reg_6115 when (tmp_231_1_fu_3720_p2(0) = '1') else
flag_d_assign_10_fu_3692_p1;
tmp_232_2_fu_3853_p3 <=
flag_d_min8_5_reg_6249 when (tmp_231_2_fu_3848_p2(0) = '1') else
flag_d_assign_12_fu_3820_p1;
tmp_232_3_fu_3981_p3 <=
flag_d_min8_7_reg_6323 when (tmp_231_3_fu_3976_p2(0) = '1') else
flag_d_assign_14_fu_3948_p1;
tmp_232_4_fu_4109_p3 <=
flag_d_min8_9_reg_6397 when (tmp_231_4_fu_4104_p2(0) = '1') else
flag_d_assign_1_fu_4076_p1;
tmp_232_5_fu_4237_p3 <=
tmp_211_s_reg_6471 when (tmp_231_5_fu_4232_p2(0) = '1') else
flag_d_assign_3_fu_4204_p1;
tmp_232_6_fu_4365_p3 <=
tmp_211_1_reg_6545 when (tmp_231_6_fu_4360_p2(0) = '1') else
flag_d_assign_5_fu_4332_p1;
tmp_232_7_fu_4493_p3 <=
tmp_211_2_reg_6619 when (tmp_231_7_fu_4488_p2(0) = '1') else
flag_d_assign_7_fu_4460_p1;
tmp_233_1_fu_3783_p2 <= "1" when (signed(a0_cast_fu_3780_p1) > signed(tmp_232_1_reg_6217)) else "0";
tmp_233_2_fu_3911_p2 <= "1" when (signed(a0_2_cast_fu_3908_p1) > signed(tmp_232_2_reg_6291)) else "0";
tmp_233_3_fu_4039_p2 <= "1" when (signed(a0_3_cast_fu_4036_p1) > signed(tmp_232_3_reg_6365)) else "0";
tmp_233_4_fu_4167_p2 <= "1" when (signed(a0_4_cast_fu_4164_p1) > signed(tmp_232_4_reg_6439)) else "0";
tmp_233_5_fu_4295_p2 <= "1" when (signed(a0_5_cast_fu_4292_p1) > signed(tmp_232_5_reg_6513)) else "0";
tmp_233_6_fu_4423_p2 <= "1" when (signed(a0_6_cast_fu_4420_p1) > signed(tmp_232_6_reg_6587)) else "0";
tmp_233_7_fu_4552_p2 <= "1" when (signed(a0_7_cast_fu_4549_p1) > signed(tmp_232_7_reg_6661)) else "0";
tmp_236_1_fu_3761_p2 <= "1" when (signed(flag_d_max8_3_reg_6122) > signed(flag_d_assign_10_fu_3692_p1)) else "0";
tmp_236_2_fu_3889_p2 <= "1" when (signed(flag_d_max8_5_reg_6256) > signed(flag_d_assign_12_fu_3820_p1)) else "0";
tmp_236_3_fu_4017_p2 <= "1" when (signed(flag_d_max8_7_reg_6330) > signed(flag_d_assign_14_fu_3948_p1)) else "0";
tmp_236_4_fu_4145_p2 <= "1" when (signed(flag_d_max8_9_reg_6404) > signed(flag_d_assign_1_fu_4076_p1)) else "0";
tmp_236_5_fu_4273_p2 <= "1" when (signed(tmp_226_s_reg_6478) > signed(flag_d_assign_3_fu_4204_p1)) else "0";
tmp_236_6_fu_4401_p2 <= "1" when (signed(tmp_226_1_reg_6552) > signed(flag_d_assign_5_fu_4332_p1)) else "0";
tmp_236_7_fu_4529_p2 <= "1" when (signed(tmp_226_2_reg_6626) > signed(flag_d_assign_7_fu_4460_p1)) else "0";
tmp_239_1_fu_3766_p3 <=
flag_d_max8_3_reg_6122 when (tmp_236_1_fu_3761_p2(0) = '1') else
flag_d_assign_10_fu_3692_p1;
tmp_239_2_fu_3894_p3 <=
flag_d_max8_5_reg_6256 when (tmp_236_2_fu_3889_p2(0) = '1') else
flag_d_assign_12_fu_3820_p1;
tmp_239_3_fu_4022_p3 <=
flag_d_max8_7_reg_6330 when (tmp_236_3_fu_4017_p2(0) = '1') else
flag_d_assign_14_fu_3948_p1;
tmp_239_4_fu_4150_p3 <=
flag_d_max8_9_reg_6404 when (tmp_236_4_fu_4145_p2(0) = '1') else
flag_d_assign_1_fu_4076_p1;
tmp_239_5_fu_4278_p3 <=
tmp_226_s_reg_6478 when (tmp_236_5_fu_4273_p2(0) = '1') else
flag_d_assign_3_fu_4204_p1;
tmp_239_6_fu_4406_p3 <=
tmp_226_1_reg_6552 when (tmp_236_6_fu_4401_p2(0) = '1') else
flag_d_assign_5_fu_4332_p1;
tmp_239_7_fu_4534_p3 <=
tmp_226_2_reg_6626 when (tmp_236_7_fu_4529_p2(0) = '1') else
flag_d_assign_7_fu_4460_p1;
tmp_23_fu_1547_p2 <= (tmp_21_fu_1527_p2 or tmp_22_fu_1533_p2);
tmp_240_1_fu_3803_p2 <= "1" when (signed(b0_cast_50_fu_3800_p1) < signed(tmp_239_1_reg_6233)) else "0";
tmp_240_2_fu_3931_p2 <= "1" when (signed(b0_2_cast_fu_3928_p1) < signed(tmp_239_2_reg_6307)) else "0";
tmp_240_3_fu_4059_p2 <= "1" when (signed(b0_3_cast_fu_4056_p1) < signed(tmp_239_3_reg_6381)) else "0";
tmp_240_4_fu_4187_p2 <= "1" when (signed(b0_4_cast_fu_4184_p1) < signed(tmp_239_4_reg_6455)) else "0";
tmp_240_5_fu_4315_p2 <= "1" when (signed(b0_5_cast_fu_4312_p1) < signed(tmp_239_5_reg_6529)) else "0";
tmp_240_6_fu_4443_p2 <= "1" when (signed(b0_6_cast_fu_4440_p1) < signed(tmp_239_6_reg_6603)) else "0";
tmp_240_7_fu_4566_p2 <= "1" when (signed(b0_7_cast_fu_4563_p1) < signed(tmp_239_7_reg_6676)) else "0";
tmp_242_1_fu_4659_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_1_fu_140)) else "0";
tmp_242_2_fu_4665_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_2_fu_4620_p1)) else "0";
tmp_245_1_fu_4677_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_1_fu_164)) else "0";
tmp_245_2_fu_4683_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_1_2_fu_4643_p1)) else "0";
tmp_24_fu_1322_p2 <= (tmp_176_1_fu_1302_p2 or tmp_177_1_fu_1308_p2);
tmp_25_fu_1907_p2 <= (tmp_182_1_reg_5441 or tmp_184_1_reg_5447);
tmp_26_fu_4779_p2 <= (tmp22_fu_4775_p2 and tmp18_fu_4771_p2);
tmp_27_fu_1358_p2 <= (tmp_176_2_fu_1338_p2 or tmp_177_2_fu_1344_p2);
tmp_28_fu_1926_p2 <= (tmp_182_2_reg_5461 or tmp_184_2_reg_5467);
tmp_29_fu_1394_p2 <= (tmp_176_3_fu_1374_p2 or tmp_177_3_fu_1380_p2);
tmp_30_fu_1956_p2 <= (tmp_182_3_fu_1938_p2 or tmp_184_3_fu_1943_p2);
tmp_31_fu_1638_p2 <= (tmp_176_4_reg_5337 or tmp_177_4_reg_5343);
tmp_32_fu_2108_p2 <= (tmp_182_4_reg_5638 or tmp_184_4_reg_5644);
tmp_33_fu_1666_p2 <= (tmp_176_5_reg_5357 or tmp_177_5_reg_5363);
tmp_34_fu_2127_p2 <= (tmp_182_5_reg_5649 or tmp_184_5_reg_5655);
tmp_35_fu_1694_p2 <= (tmp_176_6_reg_5377 or tmp_177_6_reg_5383);
tmp_36_fu_2157_p2 <= (tmp_182_6_fu_2139_p2 or tmp_184_6_fu_2144_p2);
tmp_37_fu_1722_p2 <= (tmp_176_7_reg_5397 or tmp_177_7_reg_5403);
tmp_38_fu_2347_p2 <= (tmp_182_7_reg_5722 or tmp_184_7_reg_5728);
tmp_39_fu_1740_p2 <= "1" when (flag_val_V_assign_load_1_s_fu_1521_p3 = ap_const_lv2_0) else "0";
tmp_40_fu_1864_p2 <= (or_cond7_fu_1782_p2 or or_cond6_fu_1764_p2);
tmp_41_fu_2010_p2 <= (or_cond9_reg_5559 or or_cond8_reg_5553);
tmp_42_fu_2030_p2 <= (or_cond3_fu_1994_p2 or or_cond2_fu_1990_p2);
tmp_43_fu_3262_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_612_ap_return) < signed(flag_d_assign_fu_3143_p1)) else "0";
tmp_44_fu_3424_p1 <= a_0_flag_d_assign_load_5_fu_3419_p3(8 - 1 downto 0);
tmp_45_fu_3428_p2 <= "1" when (signed(a_0_flag_d_assign_load_5_fu_3419_p3) < signed(ap_const_lv32_14)) else "0";
tmp_46_fu_3442_p2 <= "1" when (signed(flag_d_min8_1_reg_6029) < signed(flag_d_assign_9_fu_3274_p1)) else "0";
tmp_47_fu_3447_p3 <=
flag_d_min8_1_reg_6029 when (tmp_46_fu_3442_p2(0) = '1') else
flag_d_assign_9_fu_3274_p1;
tmp_48_fu_3454_p1 <= tmp_47_fu_3447_p3(8 - 1 downto 0);
tmp_49_fu_3655_p2 <= "1" when (signed(p_a_0_flag_d_assign_load_5_cast_fu_3652_p1) > signed(tmp_47_reg_6083)) else "0";
tmp_50_fu_4583_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(tmp_79_reg_6697));
tmp_51_fu_4588_p2 <= "1" when (unsigned(a0_7_tmp_232_7_reg_6691) > unsigned(tmp_50_fu_4583_p2)) else "0";
tmp_52_fu_4647_p2 <= "0" when (core_win_val_1_V_1_fu_152 = ap_const_lv16_0) else "1";
tmp_53_fu_4600_p2 <= "1" when (unsigned(ap_reg_ppstg_p_2_reg_515_pp0_it31) > unsigned(ap_const_lv11_6)) else "0";
tmp_54_fu_4689_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_1_V_0_fu_148)) else "0";
tmp_55_fu_4695_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_1_V_2_fu_4623_p1)) else "0";
tmp_56_fu_3703_p1 <= tmp_216_1_fu_3698_p3(8 - 1 downto 0);
tmp_57_fu_3732_p1 <= tmp_232_1_fu_3725_p3(8 - 1 downto 0);
tmp_58_fu_3831_p1 <= tmp_216_2_fu_3826_p3(8 - 1 downto 0);
tmp_59_fu_3860_p1 <= tmp_232_2_fu_3853_p3(8 - 1 downto 0);
tmp_5_fu_796_p2 <= std_logic_vector(unsigned(tmp_fu_782_p1) + unsigned(ap_const_lv11_4));
tmp_60_fu_3959_p1 <= tmp_216_3_fu_3954_p3(8 - 1 downto 0);
tmp_61_fu_3988_p1 <= tmp_232_3_fu_3981_p3(8 - 1 downto 0);
tmp_62_fu_4087_p1 <= tmp_216_4_fu_4082_p3(8 - 1 downto 0);
tmp_63_fu_4116_p1 <= tmp_232_4_fu_4109_p3(8 - 1 downto 0);
tmp_64_fu_4215_p1 <= tmp_216_5_fu_4210_p3(8 - 1 downto 0);
tmp_65_fu_4244_p1 <= tmp_232_5_fu_4237_p3(8 - 1 downto 0);
tmp_66_fu_4343_p1 <= tmp_216_6_fu_4338_p3(8 - 1 downto 0);
tmp_67_fu_3268_p2 <= "1" when (signed(grp_image_filter_reg_int_s_fu_617_ap_return) > signed(flag_d_assign_fu_3143_p1)) else "0";
tmp_68_fu_3458_p3 <=
flag_d_max8_1_reg_6036 when (tmp_67_reg_6048(0) = '1') else
flag_d_assign_reg_6011;
tmp_69_fu_3467_p2 <= "1" when (signed(tmp_68_fu_3458_p3) > signed(ap_const_lv32_FFFFFFEC)) else "0";
tmp_70_fu_3481_p2 <= "1" when (signed(flag_d_max8_1_reg_6036) > signed(flag_d_assign_9_fu_3274_p1)) else "0";
tmp_71_fu_3486_p3 <=
flag_d_max8_1_reg_6036 when (tmp_70_fu_3481_p2(0) = '1') else
flag_d_assign_9_fu_3274_p1;
tmp_72_fu_3675_p2 <= "1" when (signed(b0_cast_fu_3672_p1) < signed(tmp_71_reg_6099)) else "0";
tmp_73_fu_4653_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_0_V_0_fu_136)) else "0";
tmp_74_fu_4671_p2 <= "1" when (signed(core_win_val_1_V_1_fu_152) > signed(core_win_val_2_V_0_fu_160)) else "0";
tmp_75_fu_4372_p1 <= tmp_232_6_fu_4365_p3(8 - 1 downto 0);
tmp_77_fu_4471_p1 <= tmp_216_7_fu_4466_p3(8 - 1 downto 0);
tmp_78_fu_4500_p1 <= tmp_232_7_fu_4493_p3(8 - 1 downto 0);
tmp_79_fu_4571_p3 <=
tmp_95_reg_6681 when (tmp_240_7_fu_4566_p2(0) = '1') else
tmp_96_reg_6686;
tmp_7_fu_813_p2 <= "1" when (unsigned(p_s_reg_504) < unsigned(tmp_reg_5098)) else "0";
tmp_80_fu_3463_p1 <= tmp_68_fu_3458_p3(9 - 1 downto 0);
tmp_81_fu_3493_p1 <= tmp_71_fu_3486_p3(9 - 1 downto 0);
tmp_82_fu_3744_p1 <= tmp_227_1_fu_3739_p3(9 - 1 downto 0);
tmp_83_fu_3773_p1 <= tmp_239_1_fu_3766_p3(9 - 1 downto 0);
tmp_84_fu_3872_p1 <= tmp_227_2_fu_3867_p3(9 - 1 downto 0);
tmp_85_fu_3901_p1 <= tmp_239_2_fu_3894_p3(9 - 1 downto 0);
tmp_86_fu_4000_p1 <= tmp_227_3_fu_3995_p3(9 - 1 downto 0);
tmp_87_fu_4029_p1 <= tmp_239_3_fu_4022_p3(9 - 1 downto 0);
tmp_88_fu_4128_p1 <= tmp_227_4_fu_4123_p3(9 - 1 downto 0);
tmp_89_fu_4157_p1 <= tmp_239_4_fu_4150_p3(9 - 1 downto 0);
tmp_8_fu_818_p2 <= "1" when (unsigned(p_s_reg_504) > unsigned(ap_const_lv11_5)) else "0";
tmp_90_fu_4256_p1 <= tmp_227_5_fu_4251_p3(9 - 1 downto 0);
tmp_91_fu_4285_p1 <= tmp_239_5_fu_4278_p3(9 - 1 downto 0);
tmp_92_fu_4384_p1 <= tmp_227_6_fu_4379_p3(9 - 1 downto 0);
tmp_93_fu_4413_p1 <= tmp_239_6_fu_4406_p3(9 - 1 downto 0);
tmp_94_fu_4512_p1 <= tmp_227_7_fu_4507_p3(9 - 1 downto 0);
tmp_95_fu_4541_p1 <= b0_7_fu_4522_p3(8 - 1 downto 0);
tmp_96_fu_4545_p1 <= tmp_239_7_fu_4534_p3(8 - 1 downto 0);
tmp_97_fu_888_p4 <= p_2_phi_fu_519_p4(10 downto 2);
tmp_9_fu_824_p2 <= "1" when (unsigned(p_s_reg_504) > unsigned(ap_const_lv11_6)) else "0";
tmp_fu_782_p1 <= p_src_rows_V_read(11 - 1 downto 0);
tmp_s_fu_790_p2 <= std_logic_vector(unsigned(tmp_15_fu_786_p1) + unsigned(ap_const_lv11_4));
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cl/HLzVgyRnD4dIDv8/w+2T7tlVTDQUm45+fEH3A+7B6E88j5IkOFVCNsr73Z11DDXlyasFCXXqS
YKiDoI3YDw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
YbmO4sECCQcFA6CNo6ibUPIpFsm2UaY69GSwxRywuhc2zyCzydUss4x4HdonLikyFoCO3fjPK3ON
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15264)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity g_eth is
generic(
RAM_RD_CYCLE : natural := 1;
RAM_WR_CYCLE : natural := 1;
RAM_RD_DELAY : natural := 1 ; --1
RAM_AWIDTH : natural := 32
);
port(
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( RX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Empty : out std_logic;
localtime : in std_logic_vector(31 downto 0);
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
debugIO_port_id : out std_logic_vector(15 downto 0);
debugIO_write_strobe: out std_logic;
debugIO_out_port : out std_logic_vector(15 downto 0);
debugIO_read_strobe : out std_logic;
debugIO_in_port : in std_logic_vector(15 downto 0);
------------------------------------------------------------------------
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_wdata : out std_logic_vector(31 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
--
test : out std_logic_vector(1 downto 0);
s_HighPri_Tx_Req : in std_logic;
m48_HighPri_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_HighPri_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_HighPri_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0)
);
end entity;
architecture arch_eth of g_eth is
component g_ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0));
end component;
component ethrx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethrx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 8;
TASKFIFO_BLOCK_AWIDTH : natural := 3;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component dma2rxtask
port(
reset : in std_logic;
zcpsm_clk : in std_logic;
busy : in std_logic;
lastframe : in std_logic;
rxtask_wr_block : out std_logic
);
end component;
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
component g_ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component ethtx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethtx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
TxFIFO_Empty : out std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component Eth_Tx_HighPriority
port(
reset : in std_logic;
clk : in std_logic;
clk_zcpsm : in std_logic;
s_Tx_Req : in std_logic;
m48_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0)
);
end component;
component db_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0));
end component;
component zcpsmIO2bus16
port(
reset : in std_logic;
debug_port_id : out std_logic_vector(15 downto 0);
debug_write_strobe : out std_logic;
debug_out_port : out std_logic_vector(15 downto 0);
debug_read_strobe : out std_logic;
debug_in_port : in std_logic_vector(15 downto 0);
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
signal ethrx_port_id : std_logic_vector(7 downto 0);
signal ethrx_write_strobe : std_logic;
signal ethrx_out_port : std_logic_vector(7 downto 0);
signal ethrx_read_strobe : std_logic;
signal ethrx_in_port : std_logic_vector(7 downto 0);
signal ethtx_port_id : std_logic_vector(7 downto 0);
signal ethtx_write_strobe : std_logic;
signal ethtx_out_port : std_logic_vector(7 downto 0);
signal ethtx_read_strobe : std_logic;
signal ethtx_in_port : std_logic_vector(7 downto 0);
signal db_port_id : std_logic_vector(7 downto 0);
signal db_write_strobe : std_logic;
signal db_out_port : std_logic_vector(7 downto 0);
signal db_read_strobe : std_logic;
signal db_in_port : std_logic_vector(7 downto 0);
signal debug_port_id : std_logic_vector(15 downto 0);
signal debug_write_strobe : std_logic;
signal debug_out_port : std_logic_vector(15 downto 0);
signal debug_read_strobe : std_logic;
signal debug_in_port : std_logic_vector(15 downto 0);
signal debug_in_port_pro : std_logic_vector(15 downto 0);
signal lastframe_flag : std_logic;
signal ethrx_busy : std_logic;
signal rxtask_wr_block : std_logic;
signal rxtask_wr_block_Reg : std_logic;
signal ethtx_task_ce : std_logic;
signal eth_tx_ce : std_logic;
signal eth_rx_ce : std_logic;
signal eth_rxdma_ce : std_logic;
signal ethrx_task_ce : std_logic;
signal db_rx_ce : std_logic;
signal db_tx_ce : std_logic;
signal db_debug_ce : std_logic;
signal debug_prog_ce : std_logic;
-- signal test_0 : std_logic_vector(3 downto 0);
signal txen_buf : std_logic;
begin
test(0) <= not rxdv;
test(1) <= not txen_buf;
-- test(2) <= test_0(2);
-- test(3) <= test_0(3);
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
u_rx : g_ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
-- test => test_0,
ram_wdata => ram_wdata
);
db_rx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_RX else '0';
eth_rx_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX else '0';
eth_rxdma_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RXDMA else '0';
u_ethrx_zcpsm : ethrx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethrx_port_id,
write_strobe => ethrx_write_strobe,
out_port => ethrx_out_port,
read_strobe => ethrx_read_strobe,
in_port => ethrx_in_port
);
u_ethrx_task : ethrx_task
generic map (
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => RX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => RX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => RX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => RX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => RX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
RxFIFO_R_Clk => RxFIFO_R_Clk,
RxFIFO_R_Block => RxFIFO_R_Block,
RxFIFO_RAddr => RxFIFO_RAddr,
RxFIFO_RData => RxFIFO_RData,
RxFIFO_Full => open,
-- RxFIFO_Full => RxFIFO_Full,
RxFIFO_Empty => RxFIFO_Empty,
fifo_wr_block => rxtask_wr_block,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethrx_task_ce,
zcpsm_port_id => ethrx_port_id(3 downto 0),
zcpsm_write_strobe => ethrx_write_strobe,
zcpsm_out_port => ethrx_out_port,
zcpsm_read_strobe => ethrx_read_strobe,
zcpsm_in_port => ethrx_in_port
);
ethrx_task_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX_TASK else '0';
u_dma2rxtask: dma2rxtask
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
busy => ethrx_busy,
lastframe => lastframe_flag,
rxtask_wr_block => rxtask_wr_block_Reg
);
ethrx_in_port <= local_id_MAC0_A when ethrx_port_id = PORT_ETH_LOCAL_ID_0_A else
local_id_MAC0_B when ethrx_port_id = PORT_ETH_LOCAL_ID_0_B else
local_id( 39 downto 32 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_1 else
local_id( 31 downto 24 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_2 else
local_id( 23 downto 16 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_3 else
local_id( 15 downto 8 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_4 else
local_id( 7 downto 0 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_5 else
(others => 'Z');
u_wr_block : asyncwrite -- rxtask_wr_block must be synchronized with clk
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => rxtask_wr_block_Reg,
trigger => '1',
sync_wren => rxtask_wr_block,
over => open,
flag => open
);
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
u_tx : g_ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
txen <= txen_buf;
db_tx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_TX else '0';
eth_tx_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX else '0';
-- eth tx zcpsm
u_ethtx_zcpsm : ethtx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
mo_Eth_Tx_HighPriority : Eth_Tx_HighPriority
port map(
reset => reset,
clk => clk,
clk_zcpsm => zcpsm_clk,
s_Tx_Req => s_HighPri_Tx_Req,
m48_Tx_Req_DesMac => m48_HighPri_Tx_Req_DesMac,
m16_Tx_Req_Addr => m16_HighPri_Tx_Req_Addr,
m16_Tx_Req_Data => m16_HighPri_Tx_Req_Data,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_task : ethtx_task
generic map(
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => TX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => TX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => TX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => TX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => TX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
TxFIFO_W_Clk => TxFIFO_W_Clk,
TxFIFO_Clr => TxFIFO_Clr,
TxFIFO_W_Block => TxFIFO_W_Block,
TxFIFO_WE => TxFIFO_WE,
TxFIFO_WAddr => TxFIFO_WAddr,
TxFIFO_WData => TxFIFO_WData,
TxFIFO_Full => TxFIFO_Full,
-- TxFIFO_Empty => TxFIFO_Empty,
TxFIFO_Empty => open,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethtx_task_ce,
zcpsm_port_id => ethtx_port_id(3 downto 0),
zcpsm_write_strobe => ethtx_write_strobe,
zcpsm_out_port => ethtx_out_port,
zcpsm_read_strobe => ethtx_read_strobe,
zcpsm_in_port => ethtx_in_port
);
ethtx_task_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX_TASK else '0';
ethtx_in_port <= local_id_MAC0_Req when ethtx_port_id = PORT_ETH_LOCAL_ID_0_REQ else
local_id_MAC0_A when ethtx_port_id = PORT_ETH_LOCAL_ID_0_A else
local_id_MAC0_B when ethtx_port_id = PORT_ETH_LOCAL_ID_0_B else
local_id( 39 downto 32 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_1 else
local_id( 31 downto 24 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_2 else
local_id( 23 downto 16 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_3 else
local_id( 15 downto 8 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_4 else
local_id( 7 downto 0 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_5 else
(others => 'Z');
------------------------------------------------------------------------------
-- DB zcpsm
------------------------------------------------------------------------------
u_db_zcpsm : db_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => db_port_id,
write_strobe => db_write_strobe,
out_port => db_out_port,
read_strobe => db_read_strobe,
in_port => db_in_port
);
------------------------------------------------------------------------------
-- DEBUG & PROG
------------------------------------------------------------------------------
u_zcpsmIO2bus16 : zcpsmIO2bus16
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
debug_port_id => debug_port_id,
debug_write_strobe => debug_write_strobe,
debug_out_port => debug_out_port,
debug_read_strobe => debug_read_strobe,
debug_in_port => debug_in_port,
zcpsm_ce => db_debug_ce,
zcpsm_port_id => db_port_id(3 downto 0),
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
db_debug_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_DEBUG else '0';
------------------------------------------------------------------------------
-- IO
------------------------------------------------------------------------------
debugIO_port_id <= debug_port_id;
debugIO_write_strobe<= debug_write_strobe;
debugIO_out_port <= debug_out_port;
debugIO_read_strobe <= debug_read_strobe;
debug_in_port <= debug_in_port_pro when debug_port_id(15 downto 12) = PORTS_DEBUG_PROG else
debugIO_in_port;
------------------------------------------------------------------------------
-- LOCAL ID
------------------------------------------------------------------------------
db_in_port <= local_id_MAC0_A when db_port_id = PORT_DB_LOCAL_ID_0_A else
local_id_MAC0_B when db_port_id = PORT_DB_LOCAL_ID_0_B else
local_id( 39 downto 32 ) when db_port_id = PORT_DB_LOCAL_ID_1 else
local_id( 31 downto 24 ) when db_port_id = PORT_DB_LOCAL_ID_2 else
local_id( 23 downto 16 ) when db_port_id = PORT_DB_LOCAL_ID_3 else
local_id( 15 downto 8 ) when db_port_id = PORT_DB_LOCAL_ID_4 else
local_id( 7 downto 0 ) when db_port_id = PORT_DB_LOCAL_ID_5 else
(others => 'Z');
end arch_eth;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:13:04 11/19/2016
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port ( Inst : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Imm : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
OP : out STD_LOGIC_VECTOR (3 downto 0);
PCctrl : out STD_LOGIC_VECTOR (1 downto 0);
RFctrl : out STD_LOGIC_VECTOR (2 downto 0);
Immctrl : out STD_LOGIC_VECTOR (3 downto 0);
Rs : out STD_LOGIC_VECTOR (3 downto 0);
Rt : out STD_LOGIC_VECTOR (3 downto 0);
Rd : out STD_LOGIC_VECTOR (3 downto 0);
AccMEM : out STD_LOGIC;
memWE : out STD_LOGIC;
regWE : out STD_LOGIC;
DataIN : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
newT : out STD_LOGIC;
TE : out STD_LOGIC);
end control;
architecture Behavioral of control is
begin
process(Inst, A, B, Imm, T, NPC)
variable tmp : STD_LOGIC_VECTOR (15 downto 0);
begin
case Inst(15 downto 11) is
when "00001" => --NOP
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00010" => --B
OP <= "1111";
PCctrl <= "01";
RFctrl <= "000";
Immctrl <= "0011";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00100" => --BEQZ
OP <= "1111";
if (A="0000000000000000") then
PCctrl <= "01";
else
PCctrl <= "00";
end if;
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00101" => --BNEZ
OP <= "1111";
if (A="0000000000000000") then
PCctrl <= "00";
else
PCctrl <= "01";
end if;
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00110" => --SLL|SRA
case Inst(1 downto 0) is
when "00" => --SLL
OP <= "0110";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0111";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11" => --SRA
OP <= "1000";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0111";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01000" => --ADDIU3
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0010";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(7 downto 5);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01001" => --ADDIU
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01010" => --SLTI
OP <= "1111";
tmp := A - Imm;
newT <= tmp(15);
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
TE <= '1';
when "01100" => --ADDSP|BTEQZ|MTSP
case Inst(10 downto 8) is
when "011" => --ADDSP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "100";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "1111";
Rd <= "1000";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "000" => --BTEQZ
OP <= "1111";
if (T='0') then
PCctrl <= "01";
else
PCctrl <= "00";
end if;
RFctrl <= "000";
Immctrl <= "0001";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "100" => --MTSP
OP <= "1010";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "1000";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01101" => --LI
OP <= "1011";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0100";
Rs <= "1111";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01111" => --MOVE
OP <= "1010";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "10010" => --LW_SP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "100";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '1';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "10011" => --LW
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0101";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(7 downto 5);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '1';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11010" => --SW_SP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "111";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "0" & Inst(10 downto 8);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '1';
regWE <= '0';
DataIN <= B;
newT <= '0';
TE <= '0';
when "11011" => --SW
OP <= "0000";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0101";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '1';
regWE <= '0';
DataIN <= B;
newT <= '0';
TE <= '0';
when "11100" => --ADDU|SUBU
case Inst(1 downto 0) is
when "01" => --ADDU
OP <= "0000";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(4 downto 2);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11" => --SUBU
OP <= "0001";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(4 downto 2);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "11101" => --AND|CMP|JR|JALR|JRRA|MFPC|NOT|OR
case Inst(4 downto 0) is
when "01100" => --AND
OP <= "0010";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01010" => --CMP
OP <= "1111";
if (A=B) then
newT <= '0';
else
newT <= '1';
end if;
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
TE <= '1';
when "00000" => --JR|JALR|JRRA|MFPC
case Inst(7 downto 5) is
when "000" => --JR
OP <= "1111";
PCctrl <= "11";
RFctrl <= "001";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "110" => --JALR
OP <= "0000";
PCctrl <= "11";
RFctrl <= "001";
Immctrl <= "1000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1010";
ALUIN1 <= NPC;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "001" => --JRRA
OP <= "1111";
PCctrl <= "11";
RFctrl <= "101";
Immctrl <= "0000";
Rs <= "1010";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "010" => --MFPC
OP <= "1010";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "1000";
Rs <= "1111";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= NPC;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01111" => --NOT
OP <= "0101";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01101" => --OR
OP <= "0011";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "11110" => --MFIH|MTIH
case Inst(0) is
when '0' => --MFIH
OP <= "1010";
PCctrl <= "00";
RFctrl <= "110";
Immctrl <= "0000";
Rs <= "1001";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when '1' => --MTIH
OP <= "1010";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1001";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
end process;
end Behavioral; |
-- $Id: tb_s3board_fusp.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_fusp - sim
-- Description: Test bench for s3board (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- tb_s3board_core
-- s3board_fusp_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8
-- 2010-05-01 286 1.0 Initial version (derived from tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board_fusp is
end tb_s3board_fusp;
architecture sim of tb_s3board_fusp is
signal CLK : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back pressure for data flow to tb
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : s3board_fusp_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
-- VHDL de um mapeador entrada de caractere paralelo
library ieee;
use ieee.std_logic_1164.all;
entity mapeador_entrada_caractere is
port(
jogador: in std_logic_vector(6 downto 0);
oponente: in std_logic_vector(6 downto 0);
jogador_atual: in std_logic;
entrada_caractere: out std_logic_vector(6 downto 0)
);
end mapeador_entrada_caractere;
architecture estrutural of mapeador_entrada_caractere is
begin
process (jogador_atual)
begin
if jogador_atual='0' then
entrada_caractere <= jogador;
else
entrada_caractere <= oponente;
end if;
end process;
end estrutural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := nbrmaxmigcmds(AHBDW);
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(512*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(64*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(512*maxmigcmds-1 downto 0);
rd_buffer : unsigned(512*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(511 downto 0);
wdf_mask_buffer : std_logic_vector(63 downto 0);
migcommands : integer;
nxt : std_logic;
end record;
type mig_in_type is record
app_addr : std_logic_vector(27 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(511 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(63 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(511 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
signal debug : std_logic := '0';
signal size_to_watch : std_logic_vector(2 downto 0) := HSIZE_4WORD;
component mig is
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
component mig_interface_model is
port (
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig_interface_model;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-3 downto 8)) & "00000"),startaddress'length);
-- Adjust offset in memory buffer
startaddress := resize(startaddress + unsigned(unsigned(ahbsi.haddr(7 downto 6))&"000"),startaddress'length);
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 6))&"000000");
step_offset := resize(unsigned(haddr_offset(7 downto 6)&"0000"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(511 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(1023 downto 512) := unsigned(migout.app_rd_data);
elsif (AHBDW > 64) then
if (r.rd_count = 2) then
v.int_buffer(1535 downto 1024) := unsigned(migout.app_rd_data);
else
v.int_buffer(2047 downto 1536) := unsigned(migout.app_rd_data);
end if;
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit/64bit/128bit to output
v.hrdata := ahbselectdatanoreplicaoutput(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,true);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Check if this was the last transaction
if (r.wr_count >= maxburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= maxburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0';
--v.wdf_mask_buffer := (others => '0'); v.wdf_data_buffer := (others => '0'); v.haddr := (others => '0');
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(27 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(63 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(511 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
elsif (AHBDW > 64) then
if (r.wr_count = 1) then
r.wdf_mask_buffer <= not r.mask_burst(191 downto 128);
r.wdf_data_buffer <= r.hwdata_burst(1535 downto 1024);
else
r.wdf_mask_buffer <= not r.mask_burst(255 downto 192);
r.wdf_data_buffer <= r.hwdata_burst(2047 downto 1536);
end if;
else
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
MCB_inst : mig
port map (
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
MCB_model_inst : mig_interface_model
port map (
-- user interface signals
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
end generate gen_mig_model;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity ddr4_dimm_ad8k5_wrapper is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(1 downto 0);
c0_ddr4_cke : in std_logic_vector(0 downto 0);
c0_ddr4_odt : in std_logic_vector(0 downto 0);
c0_ddr4_cs_n : in std_logic_vector(0 downto 0);
c0_ddr4_ck_t : in std_logic_vector(0 downto 0);
c0_ddr4_ck_c : in std_logic_vector(0 downto 0);
c0_ddr4_reset_n : in std_logic;
c0_ddr4_dm_dbi_n : inout std_logic_vector(8 downto 0);
c0_ddr4_dq : inout std_logic_vector(71 downto 0);
c0_ddr4_dqs_t : inout std_logic_vector(8 downto 0);
c0_ddr4_dqs_c : inout std_logic_vector(8 downto 0)
);
end;
architecture arch of ddr4_dimm_ad8k5_wrapper is
component ddr4_dimm_ad8k5 is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(1 downto 0);
c0_ddr4_cke : in std_logic_vector(0 downto 0);
c0_ddr4_odt : in std_logic_vector(0 downto 0);
c0_ddr4_cs_n : in std_logic_vector(0 downto 0);
c0_ddr4_ck_t : in std_logic_vector(0 downto 0);
c0_ddr4_ck_c : in std_logic_vector(0 downto 0);
c0_ddr4_reset_n : in std_logic;
c0_ddr4_dm_dbi_n : inout std_logic_vector(8 downto 0);
c0_ddr4_dq : inout std_logic_vector(71 downto 0);
c0_ddr4_dqs_t : inout std_logic_vector(8 downto 0);
c0_ddr4_dqs_c : inout std_logic_vector(8 downto 0)
);
end component;
begin
I1 : ddr4_dimm_ad8k5 port map (
sys_reset ,
c0_ddr4_act_n ,
c0_ddr4_adr ,
c0_ddr4_ba ,
c0_ddr4_bg ,
c0_ddr4_cke ,
c0_ddr4_odt ,
c0_ddr4_cs_n ,
c0_ddr4_ck_t ,
c0_ddr4_ck_c ,
c0_ddr4_reset_n ,
c0_ddr4_dm_dbi_n ,
c0_ddr4_dq ,
c0_ddr4_dqs_t ,
c0_ddr4_dqs_c );
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_led_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END system_axi_gpio_led_0;
ARCHITECTURE system_axi_gpio_led_0_arch OF system_axi_gpio_led_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 12,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i,
gpio2_io_o => gpio2_io_o,
gpio2_io_t => gpio2_io_t
);
END system_axi_gpio_led_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package tbu_text_out_pkg is
procedure put(text: string);
procedure print(text: string; newline: boolean := true);
procedure put(value: real);
procedure putv(value: std_logic_vector);
procedure putv(value: unsigned);
end;
package body tbu_text_out_pkg is
procedure put(text: string) is
variable s: line;
begin
write(s, text);
writeline(output,s);
end;
shared variable current_line: line;
procedure print(text: string; newline: boolean := true) is
--variable s: line;
begin
write(current_line, text);
if (newline) then
writeline(output, current_line);
end if;
end;
procedure put(value: real) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure putv(value: std_logic_vector) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure putv(value: unsigned) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM64K36 is port(
DEPTH3, DEPTH2, DEPTH1, DEPTH0,
WRAD15, WRAD14, WRAD13, WRAD12, WRAD11, WRAD10, WRAD9 ,
WRAD8 , WRAD7 , WRAD6 , WRAD5 , WRAD4 , WRAD3 , WRAD2 ,
WRAD1 , WRAD0 , WD35 , WD34 , WD33 , WD32 , WD31 ,
WD30 , WD29 , WD28 , WD27 , WD26 , WD25 , WD24 ,
WD23 , WD22 , WD21 , WD20 , WD19 , WD18 , WD17 ,
WD16 , WD15 , WD14 , WD13 , WD12 , WD11 , WD10 ,
WD9 , WD8 , WD7 , WD6 , WD5 , WD4 , WD3 ,
WD2 , WD1 , WD0 , WW2 , WW1 , WW0 , WEN ,
WCLK , RDAD15, RDAD14, RDAD13, RDAD12, RDAD11, RDAD10,
RDAD9 , RDAD8 , RDAD7 , RDAD6 , RDAD5 , RDAD4 , RDAD3 ,
RDAD2 , RDAD1 , RDAD0 , RW2 , RW1 , RW0 , REN ,
RCLK : in std_ulogic ;
RD35 , RD34 , RD33 , RD32 , RD31 , RD30 , RD29 ,
RD28 , RD27 , RD26 , RD25 , RD24 , RD23 , RD22 ,
RD21 , RD20 , RD19 , RD18 , RD17 , RD16 , RD15 ,
RD14 , RD13 , RD12 , RD11 , RD10 , RD9 , RD8 ,
RD7 , RD6 , RD5 , RD4 , RD3 , RD2 , RD1 ,
RD0 : out std_ulogic);
end;
architecture rtl of RAM64K36 is
signal re : std_ulogic;
begin
rp : process(RCLK, WCLK)
constant words : integer := 2**16;
subtype word is std_logic_vector(35 downto 0);
type dregtype is array (0 to words - 1) of word;
variable rfd : dregtype;
variable wa, ra : std_logic_vector(15 downto 0);
variable q : std_logic_vector(35 downto 0);
begin
if rising_edge(RCLK) then
ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
if not (is_x (ra)) and REN = '1' then
q := rfd(to_integer(unsigned(ra)) mod words);
else q := (others => 'X'); end if;
end if;
if rising_edge(WCLK) and (wen = '1') then
wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
if not is_x (wa) then
rfd(to_integer(unsigned(wa)) mod words) :=
WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
end if;
if ra = wa then q := (others => 'X'); end if; -- no write-through
end if;
RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
RD0 <= q(0);
end process;
end;
-- PCI PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf_pci is begin y <= to_X01(pad) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf_pci is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf_pci is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff_pci is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff_pci is begin
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_pci is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_pci is begin pad <= d after 5 ns; end;
-- STANDARD PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_8 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_8 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_12 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_12 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_16 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_16 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_24 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_24 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_lvds is port( y : out std_logic; padp, padn : in std_logic); end;
architecture struct of inbuf_lvds is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(padp) after 1 ns when to_x01(padp xor padn) = '1' else yn after 1 ns;
y <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_lvds is port (d : in std_logic; padp, padn : out std_logic ); end;
architecture struct of outbuf_lvds is begin
padp <= d after 1 ns;
padn <= not d after 1 ns;
end;
-- clock buffers ----------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of hclkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of clkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end add1;
architecture beh of add1 is
signal un1_fco : std_logic;
signal un2_fco : std_logic;
signal un3_fco : std_logic;
begin
s <= a xor b xor fci;
un1_fco <= a and b;
un2_fco <= a and fci;
un3_fco <= b and fci;
fco <= un1_fco or un2_fco or un3_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2;
architecture beh of and2 is
begin
y <= b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2a;
architecture beh of and2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2b;
architecture beh of and2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3;
architecture beh of and3 is
begin
y <= c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3a;
architecture beh of and3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3b;
architecture beh of and3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3c;
architecture beh of and3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4;
architecture beh of and4 is
begin
y <= d and c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4a;
architecture beh of and4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d and c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4b;
architecture beh of and4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d and c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4c;
architecture beh of and4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d and ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity buff is
port(
a : in std_logic;
y : out std_logic);
end buff;
architecture beh of buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end cm8;
architecture beh of cm8 is
signal s0 : std_logic;
signal s1 : std_logic;
signal m0 : std_logic;
signal m1 : std_logic;
begin
s0 <= s01 and s00;
s1 <= s11 or s10;
m0 <= d0 when s0 = '0' else d1;
m1 <= d2 when s0 = '0' else d3;
y <= m0 when s1 = '0' else m1;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8inv is
port(
a : in std_logic;
y : out std_logic);
end cm8inv;
architecture beh of cm8inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1;
architecture beh of df1 is
begin
ff : process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1b;
architecture beh of dfc1b is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1c;
architecture beh of dfc1c is
begin
ff : process (clk, clr)
begin
if clr = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= not d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1d;
architecture beh of dfc1d is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end dfe1b;
architecture beh of dfe1b is
signal q_int_1 : std_logic;
signal nq : std_logic;
begin
nq <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk)
begin
if rising_edge(clk) then
q_int_1 <= nq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfe3c;
architecture beh of dfe3c is
signal q_int_0 : std_logic;
signal md : std_logic;
begin
md <= d when e = '0' else q_int_0;
q <= q_int_0;
ff : process (clk, clr)
begin
if clr = '0' then
q_int_0 <= '0';
elsif rising_edge(clk) then
q_int_0 <= md;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfe4f;
architecture beh of dfe4f is
signal q_int_1 : std_logic;
signal un1 : std_logic;
begin
un1 <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk, pre)
begin
if pre = '0' then
q_int_1 <= '1';
elsif rising_edge(clk) then
q_int_1 <= un1;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1;
architecture beh of dfp1 is
begin
ff : process (clk, pre)
begin
if pre = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1b;
architecture beh of dfp1b is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1d;
architecture beh of dfp1d is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity gnd is
port(
y : out std_logic);
end gnd;
architecture beh of gnd is
begin
y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfm is
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end dfm;
architecture beh of dfm is
begin
ff : process (clk)
begin
if rising_edge(clk) then
if s = '0' then q <= a;
else q <= b; end if;
end if;
end process ff;
end beh;
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity hclkbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end hclkbuf;
--architecture beh of hclkbuf is
--begin
-- y <= pad;
--end beh;
--
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity inbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end inbuf;
--architecture beh of inbuf is
--begin
-- y <= pad;
--end beh;
library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(
a : in std_logic;
y : out std_logic);
end inv;
architecture beh of inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end nand4;
architecture beh of nand4 is
signal yx : std_logic;
begin
yx <= d and c and b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2;
architecture beh of or2 is
begin
y <= b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2a;
architecture beh of or2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2b;
architecture beh of or2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3;
architecture beh of or3 is
begin
y <= c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3a;
architecture beh of or3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3b;
architecture beh of or3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3c;
architecture beh of or3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4;
architecture beh of or4 is
begin
y <= d or c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4a;
architecture beh of or4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d or c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4b;
architecture beh of or4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d or c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4c;
architecture beh of or4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4d;
architecture beh of or4d is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
signal di : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
di <= not d;
y <= di or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end sub1;
architecture beh of sub1 is
signal un1_b : std_logic;
signal un3_fco : std_logic;
signal un1_fco : std_logic;
signal un4_fco : std_logic;
begin
un1_b <= not b;
un3_fco <= a and fci;
s <= a xor fci xor un1_b;
un1_fco <= a and un1_b;
un4_fco <= fci and un1_b;
fco <= un1_fco or un3_fco or un4_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity vcc is
port(
y : out std_logic);
end vcc;
architecture beh of vcc is
begin
y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xa1;
architecture beh of xa1 is
signal xab : std_logic;
begin
xab <= b xor a;
y <= c and xab;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xnor2;
architecture beh of xnor2 is
signal yi : std_logic;
begin
yi <= b xor a;
y <= not yi;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor2;
architecture beh of xor2 is
begin
y <= b xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end xor4;
architecture beh of xor4 is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor d;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx2 is
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end mx2;
architecture beh of mx2 is
signal xab : std_logic;
begin
y <= b when s = '0' else a;
end beh;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM64K36 is port(
DEPTH3, DEPTH2, DEPTH1, DEPTH0,
WRAD15, WRAD14, WRAD13, WRAD12, WRAD11, WRAD10, WRAD9 ,
WRAD8 , WRAD7 , WRAD6 , WRAD5 , WRAD4 , WRAD3 , WRAD2 ,
WRAD1 , WRAD0 , WD35 , WD34 , WD33 , WD32 , WD31 ,
WD30 , WD29 , WD28 , WD27 , WD26 , WD25 , WD24 ,
WD23 , WD22 , WD21 , WD20 , WD19 , WD18 , WD17 ,
WD16 , WD15 , WD14 , WD13 , WD12 , WD11 , WD10 ,
WD9 , WD8 , WD7 , WD6 , WD5 , WD4 , WD3 ,
WD2 , WD1 , WD0 , WW2 , WW1 , WW0 , WEN ,
WCLK , RDAD15, RDAD14, RDAD13, RDAD12, RDAD11, RDAD10,
RDAD9 , RDAD8 , RDAD7 , RDAD6 , RDAD5 , RDAD4 , RDAD3 ,
RDAD2 , RDAD1 , RDAD0 , RW2 , RW1 , RW0 , REN ,
RCLK : in std_ulogic ;
RD35 , RD34 , RD33 , RD32 , RD31 , RD30 , RD29 ,
RD28 , RD27 , RD26 , RD25 , RD24 , RD23 , RD22 ,
RD21 , RD20 , RD19 , RD18 , RD17 , RD16 , RD15 ,
RD14 , RD13 , RD12 , RD11 , RD10 , RD9 , RD8 ,
RD7 , RD6 , RD5 , RD4 , RD3 , RD2 , RD1 ,
RD0 : out std_ulogic);
end;
architecture rtl of RAM64K36 is
signal re : std_ulogic;
begin
rp : process(RCLK, WCLK)
constant words : integer := 2**16;
subtype word is std_logic_vector(35 downto 0);
type dregtype is array (0 to words - 1) of word;
variable rfd : dregtype;
variable wa, ra : std_logic_vector(15 downto 0);
variable q : std_logic_vector(35 downto 0);
begin
if rising_edge(RCLK) then
ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
if not (is_x (ra)) and REN = '1' then
q := rfd(to_integer(unsigned(ra)) mod words);
else q := (others => 'X'); end if;
end if;
if rising_edge(WCLK) and (wen = '1') then
wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
if not is_x (wa) then
rfd(to_integer(unsigned(wa)) mod words) :=
WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
end if;
if ra = wa then q := (others => 'X'); end if; -- no write-through
end if;
RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
RD0 <= q(0);
end process;
end;
-- PCI PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf_pci is begin y <= to_X01(pad) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf_pci is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf_pci is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff_pci is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff_pci is begin
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_pci is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_pci is begin pad <= d after 5 ns; end;
-- STANDARD PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_8 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_8 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_12 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_12 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_16 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_16 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_24 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_24 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_lvds is port( y : out std_logic; padp, padn : in std_logic); end;
architecture struct of inbuf_lvds is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(padp) after 1 ns when to_x01(padp xor padn) = '1' else yn after 1 ns;
y <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_lvds is port (d : in std_logic; padp, padn : out std_logic ); end;
architecture struct of outbuf_lvds is begin
padp <= d after 1 ns;
padn <= not d after 1 ns;
end;
-- clock buffers ----------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of hclkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of clkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end add1;
architecture beh of add1 is
signal un1_fco : std_logic;
signal un2_fco : std_logic;
signal un3_fco : std_logic;
begin
s <= a xor b xor fci;
un1_fco <= a and b;
un2_fco <= a and fci;
un3_fco <= b and fci;
fco <= un1_fco or un2_fco or un3_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2;
architecture beh of and2 is
begin
y <= b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2a;
architecture beh of and2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2b;
architecture beh of and2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3;
architecture beh of and3 is
begin
y <= c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3a;
architecture beh of and3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3b;
architecture beh of and3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3c;
architecture beh of and3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4;
architecture beh of and4 is
begin
y <= d and c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4a;
architecture beh of and4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d and c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4b;
architecture beh of and4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d and c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4c;
architecture beh of and4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d and ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity buff is
port(
a : in std_logic;
y : out std_logic);
end buff;
architecture beh of buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end cm8;
architecture beh of cm8 is
signal s0 : std_logic;
signal s1 : std_logic;
signal m0 : std_logic;
signal m1 : std_logic;
begin
s0 <= s01 and s00;
s1 <= s11 or s10;
m0 <= d0 when s0 = '0' else d1;
m1 <= d2 when s0 = '0' else d3;
y <= m0 when s1 = '0' else m1;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8inv is
port(
a : in std_logic;
y : out std_logic);
end cm8inv;
architecture beh of cm8inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1;
architecture beh of df1 is
begin
ff : process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1b;
architecture beh of dfc1b is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1c;
architecture beh of dfc1c is
begin
ff : process (clk, clr)
begin
if clr = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= not d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1d;
architecture beh of dfc1d is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end dfe1b;
architecture beh of dfe1b is
signal q_int_1 : std_logic;
signal nq : std_logic;
begin
nq <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk)
begin
if rising_edge(clk) then
q_int_1 <= nq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfe3c;
architecture beh of dfe3c is
signal q_int_0 : std_logic;
signal md : std_logic;
begin
md <= d when e = '0' else q_int_0;
q <= q_int_0;
ff : process (clk, clr)
begin
if clr = '0' then
q_int_0 <= '0';
elsif rising_edge(clk) then
q_int_0 <= md;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfe4f;
architecture beh of dfe4f is
signal q_int_1 : std_logic;
signal un1 : std_logic;
begin
un1 <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk, pre)
begin
if pre = '0' then
q_int_1 <= '1';
elsif rising_edge(clk) then
q_int_1 <= un1;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1;
architecture beh of dfp1 is
begin
ff : process (clk, pre)
begin
if pre = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1b;
architecture beh of dfp1b is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1d;
architecture beh of dfp1d is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity gnd is
port(
y : out std_logic);
end gnd;
architecture beh of gnd is
begin
y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfm is
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end dfm;
architecture beh of dfm is
begin
ff : process (clk)
begin
if rising_edge(clk) then
if s = '0' then q <= a;
else q <= b; end if;
end if;
end process ff;
end beh;
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity hclkbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end hclkbuf;
--architecture beh of hclkbuf is
--begin
-- y <= pad;
--end beh;
--
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity inbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end inbuf;
--architecture beh of inbuf is
--begin
-- y <= pad;
--end beh;
library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(
a : in std_logic;
y : out std_logic);
end inv;
architecture beh of inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end nand4;
architecture beh of nand4 is
signal yx : std_logic;
begin
yx <= d and c and b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2;
architecture beh of or2 is
begin
y <= b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2a;
architecture beh of or2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2b;
architecture beh of or2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3;
architecture beh of or3 is
begin
y <= c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3a;
architecture beh of or3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3b;
architecture beh of or3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3c;
architecture beh of or3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4;
architecture beh of or4 is
begin
y <= d or c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4a;
architecture beh of or4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d or c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4b;
architecture beh of or4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d or c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4c;
architecture beh of or4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4d;
architecture beh of or4d is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
signal di : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
di <= not d;
y <= di or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end sub1;
architecture beh of sub1 is
signal un1_b : std_logic;
signal un3_fco : std_logic;
signal un1_fco : std_logic;
signal un4_fco : std_logic;
begin
un1_b <= not b;
un3_fco <= a and fci;
s <= a xor fci xor un1_b;
un1_fco <= a and un1_b;
un4_fco <= fci and un1_b;
fco <= un1_fco or un3_fco or un4_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity vcc is
port(
y : out std_logic);
end vcc;
architecture beh of vcc is
begin
y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xa1;
architecture beh of xa1 is
signal xab : std_logic;
begin
xab <= b xor a;
y <= c and xab;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xnor2;
architecture beh of xnor2 is
signal yi : std_logic;
begin
yi <= b xor a;
y <= not yi;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor2;
architecture beh of xor2 is
begin
y <= b xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end xor4;
architecture beh of xor4 is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor d;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx2 is
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end mx2;
architecture beh of mx2 is
signal xab : std_logic;
begin
y <= b when s = '0' else a;
end beh;
-- pragma translate_on
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_k7_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_k7_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pulse_regen_k7_top;
architecture xilinx of pulse_regen_k7_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_k7 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pulse_regen_k7 PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 03
-- Project :
-------------------------------------------------------------------------------
-- File : adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- Created : 4.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Third excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 4.11.2015 1.0 tuhu Created
-- 18.11.2015 1.1 tuhu Modified process.
-- 20.11.2015 1.1 nikulaj Added bonus feature
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic(
operand_width_g : integer -- Width of input and output. Note, that if the definition of the input width
-- is i.e 8, the definition below must be (8 - 1) because the vector starts from 0.
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, active low.
a_in : in std_logic_vector(operand_width_g - 1 downto 0); -- Input a.
b_in : in std_logic_vector(operand_width_g - 1 downto 0); -- Input b.
sum_out : out std_logic_vector(operand_width_g downto 0) -- Sum output.
);
end adder;
architecture rtl of adder is
SIGNAL result_r : signed((operand_width_g) downto 0); -- Result register.
begin -- rtl
sum_out <= std_logic_vector(result_r); -- Assign register to output.
calculate : process (clk, rst_n) -- Handle the actual calculation of values and reset.
begin
if(rst_n = '0') then -- Reset
result_r <= (others => '0');
elsif(clk'event and clk = '1') then -- Calculate on rising edge of clock.
result_r <= resize(signed(a_in), operand_width_g + 1) + resize(signed(b_in), operand_width_g + 1);
end if;
end process calculate;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ProgramCounter is
generic(
WIDTH : integer := 16
);
Port(
inval : in std_ulogic_vector(WIDTH - 1 downto 0);
comp : in std_ulogic_vector(WIDTH - 1 downto 0);
jump : in std_ulogic_vector(2 downto 0);
reset : in std_ulogic;
clock : in std_ulogic;
outval : out std_ulogic_vector(WIDTH - 1 downto 0)
);
end ProgramCounter;
architecture Behavioral of ProgramCounter is
begin
process(clock, set)
begin
if reset = '1' then
outval <= (others => '0');
else
if (j(0) = '1' and signed(comp) < 0) or
(j(1) = '1' and signed(comp) = 0) or
(j(2) = '1' and signed(comp) > 0) then
outval <= inval;
else
outval <= outval + 1;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- reg_H_minus_1.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all; -- std_logic
use ieee.std_logic_arith.all; -- signed/unsigned, conv_integer(), conv_std_logic_vector(signal, no. bit)
use ieee.numeric_std.all; -- to_integer()
entity reg_H_minus_1 is
port (
clk : in std_ulogic; -- clock
rstn : in std_ulogic; -- asynchronous active low reset
reg_H_minus_1_en : in std_ulogic; -- enable signal for the H(i-1) registers
reg_H_minus_1_sel : in std_ulogic; -- select signal for the H(i-1) registers
H_i_A,
H_i_B,
H_i_C,
H_i_D,
H_i_E,
H_i_F,
H_i_G,
H_i_H : in std_ulogic_vector(31 downto 0); -- resulting hash value H_(i) from datapath (to be stored)
H_iminus1_A,
H_iminus1_B,
H_iminus1_C,
H_iminus1_D,
H_iminus1_E,
H_iminus1_F,
H_iminus1_G,
H_iminus1_H : out std_ulogic_vector(31 downto 0) -- intermediate hash value H_(i-1)
);
end entity reg_H_minus_1;
architecture behav of reg_H_minus_1 is
type H_array_type is array(0 to 7) of std_ulogic_vector(31 downto 0);
constant H0 : H_array_type := (
x"6a09e667", x"bb67ae85", x"3c6ef372", x"a54ff53a",
x"510e527f", x"9b05688c", x"1f83d9ab", x"5be0cd19"
);
signal H_iminus1 : H_array_type;
begin
process (clk, rstn) -- asynchronous reset
begin
if rstn = '0' then
H_iminus1 <= (others => x"00000000");
elsif clk'event and clk = '1' then
if reg_H_minus_1_en = '1' then
if reg_H_minus_1_sel = '0' then
H_iminus1(0) <= H0(0);
H_iminus1(1) <= H0(1);
H_iminus1(2) <= H0(2);
H_iminus1(3) <= H0(3);
H_iminus1(4) <= H0(4);
H_iminus1(5) <= H0(5);
H_iminus1(6) <= H0(6);
H_iminus1(7) <= H0(7);
elsif reg_H_minus_1_sel = '1' then
H_iminus1(0) <= H_i_A;
H_iminus1(1) <= H_i_B;
H_iminus1(2) <= H_i_C;
H_iminus1(3) <= H_i_D;
H_iminus1(4) <= H_i_E;
H_iminus1(5) <= H_i_F;
H_iminus1(6) <= H_i_G;
H_iminus1(7) <= H_i_H;
end if;
end if;
end if;
end process;
H_iminus1_A <= H_iminus1(0);
H_iminus1_B <= H_iminus1(1);
H_iminus1_C <= H_iminus1(2);
H_iminus1_D <= H_iminus1(3);
H_iminus1_E <= H_iminus1(4);
H_iminus1_F <= H_iminus1(5);
H_iminus1_G <= H_iminus1(6);
H_iminus1_H <= H_iminus1(7);
end architecture behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity ROM is
port ( address : in std_logic_vector(3 downto 0);
data : out std_logic_vector(19 downto 0) );
end entity ROM;
architecture behavioral of ROM is
type mem is array ( 0 to 2**4 - 1) of std_logic_vector(19 downto 0);
constant my_Rom : mem := (
0 => "01010100110111001100",--ALEC
1 => "01010101011010101010",--ANNA
2 => "01011010101100011001",--BART
3 => "01011011101100110000",--BETH
4 => "01001000001001011010",--GOKU
5 => "10000110100100100000",--HUGO
6 => "10001000001010110000",--JONH
7 => "10001110101001100001",--JULI
8 => "10011000010110100001",--LIDY
9 => "10011000010010101010",--LISA
10 => "10011110101001101010",--LULA
11 => "10100010101100011100",--MARY
12 => "11000000010110010010",--RICK
13 => "11000000000010101110",--ROSE
14 => "11000110100101111100",--RUBY
15 => "00101110100001011100"--SUZY
);
begin
process (address)
begin
case address is
when "0000" => data <= my_rom(0);
when "0001" => data <= my_rom(1);
when "0010" => data <= my_rom(2);
when "0011" => data <= my_rom(3);
when "0100" => data <= my_rom(4);
when "0101" => data <= my_rom(5);
when "0110" => data <= my_rom(6);
when "0111" => data <= my_rom(7);
when "1000" => data <= my_rom(8);
when "1001" => data <= my_rom(9);
when "1010" => data <= my_rom(10);
when "1011" => data <= my_rom(11);
when "1100" => data <= my_rom(12);
when "1101" => data <= my_rom(13);
when "1110" => data <= my_rom(14);
when "1111" => data <= my_rom(15);
when others => data <= "00000000000000000000";
end case;
end process;
end architecture behavioral; |
-- $Id: serport_master_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: serport_master_tb - sim
-- Description: serial port: serial port module, master side (SIM only!)
--
-- Dependencies: serport_uart_rxtx_ab_tb
-- serport_xonrx_tb
-- serport_xontx_tb
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1087 1.1 add 100 ps RXSD,TXSD delay to allow clock jitter
-- 2016-01-03 724 1.0 Initial version (copied from serport_master)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_master_tb is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
ENAXON : in slbit := '0'; -- enable xon/xoff handling
ENAESC : in slbit := '0'; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXOK : in slbit := '1'; -- rx channel ok
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit := '0' -- transmit cts (uart view, act.low)
);
end serport_master_tb;
architecture sim of serport_master_tb is
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal UART_RXSD : slbit := '0';
signal UART_TXSD : slbit := '0';
signal TXOK : slbit := '0';
begin
UART : entity work.serport_uart_rxtx_tb -- uart, rx+tx combo
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => open,
TXSD => UART_TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
-- add some minor (100 ps) delay in the serial data path.
-- this makes transmission immune against small clock jitter between test
-- bench and UUT (e.g. from sfs re-phasing done differently in tb and UUT).
TXSD <= UART_TXSD after 100 ps;
UART_RXSD <= RXSD after 100 ps;
XONRX : entity work.serport_xonrx_tb -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => '0',
RXOVR => open,
TXOK => TXOK
);
XONTX : entity work.serport_xontx_tb -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => RXOK,
TXOK => TXOK
);
RXRTS_N <= not RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
end sim;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Polynomial_Syndrome_Computing_N
-- Module Name: Polynomial_Syndrome_Computing_N
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Decoding.
--
-- This circuit can find the roots of polynomial sigma and compute the syndrome from
-- the received ciphertext. The algorithm run by the circuit is chosen from one of the inputs.
-- Both circuits were joined into the same, because several computing parts are reused in
-- the computations, therefore this circuit needs less area than two apart.
--
-- For the computation this circuit applies the Horner scheme during finding roots, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- In syndrome generation it is applied alternant syndrome generation, where at each pipeline
-- stage is computed one syndrome iteration. A syndrome iteration is the multiplication of
-- one powering element by one support element.
--
-- For area reduction this circuit were optimized in version polynomial_syndrome_computing_n_v2.
--
-- The circuits parameters
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages the pipeline has. More stages means more values of value_sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the pipeline_size.
-- This number is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- polynomial_degree :
--
-- The polynomial degree to be evaluated. Therefore the polynomial has
-- polynomial_degree+1 coefficients. This parameters depends of the Goppa code used.
--
-- size_polynomial_degree :
--
-- The number of bits necessary to store polynomial_degree.
-- This number is ceil(log2(polynomial_degree+1))
--
-- number_of_values_x :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
--
-- size_number_of_values_x :
-- The number of bits necessary to store all support elements.
-- this number is ceil(log2(number_of_values_x)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- pipeline_polynomial_calc_v3 Rev 1.0
-- controller_polynomial_computing Rev 1.0
-- controller_syndrome_computing Rev 1.0
-- pow2_gf_2_m Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- shift_register_nbits Rev 1.0
-- register_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_increment_decrement_load_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity polynomial_syndrome_computing_n is
Generic (
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 28;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5;
-- number_of_support_elements: integer := 2048;
-- size_number_of_support_elements : integer := 11
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 51;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6;
-- number_of_support_elements: integer := 2048;
-- size_number_of_support_elements : integer := 11
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 67;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements : integer := 3307;
-- size_number_of_support_elements : integer := 12;
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 33;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6;
-- number_of_support_elements: integer := 2528;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements: integer := 2816;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements: integer := 3328;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end polynomial_syndrome_computing_n;
architecture RTL of polynomial_syndrome_computing_n is
component pipeline_polynomial_calc_v3
Generic (
gf_2_m : integer range 1 to 20;
size : integer
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((size - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component pow2_gf_2_m
Generic(
gf_2_m : integer range 1 to 20
);
Port(
a : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component shift_register_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_increment_decrement_load_rst_nbits
Generic (
size : integer;
increment_value : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
increment_decrement : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component controller_polynomial_computing
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end component;
component controller_syndrome_computing
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
last_syndrome_value : in STD_LOGIC;
final_syndrome_evaluation : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_syndrome_ce : out STD_LOGIC;
ctr_address_syndrome_load : out STD_LOGIC;
ctr_address_syndrome_increment_decrement : out STD_LOGIC;
ctr_address_syndrome_rst : out STD_LOGIC;
reg_store_temporary_syndrome_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_rst : out STD_LOGIC;
finalize_syndrome : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
shift_syndrome_data_in : out STD_LOGIC;
shift_syndrome_mode_rst : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
calculation_finalized : out STD_LOGIC
);
end component;
signal pipeline_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_polynomial : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_codeword : STD_LOGIC_VECTOR(((pipeline_size)*(number_of_pipelines) - 1) downto 0);
signal square_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal new_value_intermediate_syndrome : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size)*(number_of_pipelines) - 1) downto 0);
constant coefficient_zero : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_acc : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_x_pow : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_polynomial_coefficients_d : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal reg_polynomial_coefficients_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_polynomial_coefficients_q : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal reg_x_rst_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_x_rst_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst_rst : STD_LOGIC;
signal reg_x_rst_q : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal shift_polynomial_ce_data_in : STD_LOGIC;
signal shift_polynomial_ce_ce : STD_LOGIC;
signal shift_polynomial_ce_rst : STD_LOGIC;
constant shift_polynomial_ce_rst_value : STD_LOGIC_VECTOR(pipeline_size downto 0) := std_logic_vector(to_unsigned(1, pipeline_size+1));
signal shift_polynomial_ce_q : STD_LOGIC_VECTOR(pipeline_size downto 0);
signal finalize_syndrome : STD_LOGIC;
signal shift_syndrome_mode_data_in : STD_LOGIC;
signal shift_syndrome_mode_rst : STD_LOGIC;
constant shift_syndrome_mode_rst_value : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0) := std_logic_vector(to_unsigned(1, pipeline_size));
signal shift_syndrome_mode_q : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal ctr_load_x_address_ce : STD_LOGIC;
signal ctr_load_x_address_rst : STD_LOGIC;
constant ctr_load_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_support_elements));
signal ctr_load_x_address_q : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
signal ctr_store_x_address_ce : STD_LOGIC;
signal ctr_store_x_address_rst : STD_LOGIC;
constant ctr_store_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_support_elements));
signal ctr_store_x_address_q : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
signal ctr_address_polynomial_syndrome_d : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal ctr_address_polynomial_syndrome_ce : STD_LOGIC;
signal ctr_address_polynomial_syndrome_load : STD_LOGIC;
signal ctr_address_polynomial_syndrome_increment_decrement : STD_LOGIC;
signal ctr_address_polynomial_syndrome_rst : STD_LOGIC;
signal ctr_address_polynomial_syndrome_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors*2, size_number_of_errors+1));
signal ctr_address_polynomial_syndrome_q : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_store_temporary_syndrome_d : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_store_temporary_syndrome_ce : STD_LOGIC;
signal reg_store_temporary_syndrome_q : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_first_values_ce : STD_LOGIC;
signal reg_first_values_rst : STD_LOGIC;
constant reg_first_values_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_values_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_final_syndrome_evaluation_ce : STD_LOGIC;
signal reg_final_syndrome_evaluation_rst : STD_LOGIC;
constant reg_final_syndrome_evaluation_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_final_syndrome_evaluation_q : STD_LOGIC_VECTOR(0 downto 0);
signal evaluation_data_in : STD_LOGIC;
signal evaluation_data_out : STD_LOGIC;
signal reg_write_enable_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_write_enable_rst : STD_LOGIC;
constant reg_write_enable_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_write_enable_q : STD_LOGIC_VECTOR(0 downto 0);
signal pipeline_ready : STD_LOGIC;
signal limit_polynomial_degree : STD_LOGIC;
signal last_syndrome_value : STD_LOGIC;
signal final_syndrome_evaluation : STD_LOGIC;
signal last_coefficients : STD_LOGIC;
signal last_load_x_values : STD_LOGIC;
signal last_store_x_values : STD_LOGIC;
signal value_evaluated : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal last_evaluations : STD_LOGIC;
signal is_error_position : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant error_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal message_data_in : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal message_data_q : STD_LOGIC_VECTOR((((number_of_pipelines)*(pipeline_size+1)) - 1) downto 0);
signal message_data_out : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal poly_reg_polynomial_coefficients_d : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size) - 1) downto 0);
constant poly_ctr_address_polynomial_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors, size_number_of_errors+1));
signal poly_evaluation_data_in : STD_LOGIC;
signal poly_reg_write_enable_rst : STD_LOGIC;
signal poly_ctr_load_x_address_ce : STD_LOGIC;
signal poly_ctr_load_x_address_rst : STD_LOGIC;
signal poly_ctr_store_x_address_ce : STD_LOGIC;
signal poly_ctr_store_x_address_rst : STD_LOGIC;
signal poly_reg_first_values_ce : STD_LOGIC;
signal poly_reg_first_values_rst : STD_LOGIC;
signal poly_ctr_address_polynomial_ce : STD_LOGIC;
signal poly_ctr_address_polynomial_rst : STD_LOGIC;
signal poly_reg_x_rst_rst : STD_LOGIC;
signal poly_shift_polynomial_ce_ce : STD_LOGIC;
signal poly_shift_polynomial_ce_rst : STD_LOGIC;
signal poly_last_coefficients : STD_LOGIC;
signal poly_evaluation_finalized : STD_LOGIC;
signal synd_reg_polynomial_coefficients_d : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size) - 1) downto 0);
constant synd_ctr_address_syndrome_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors*2, size_number_of_errors+1));
signal synd_evaluation_data_in : STD_LOGIC;
signal synd_reg_write_enable_rst : STD_LOGIC;
signal synd_ctr_load_x_address_ce : STD_LOGIC;
signal synd_ctr_load_x_address_rst : STD_LOGIC;
signal synd_ctr_store_x_address_ce : STD_LOGIC;
signal synd_ctr_store_x_address_rst : STD_LOGIC;
signal synd_reg_first_values_ce : STD_LOGIC;
signal synd_reg_first_values_rst : STD_LOGIC;
signal synd_ctr_address_syndrome_load : STD_LOGIC;
signal synd_ctr_address_syndrome_ce : STD_LOGIC;
signal synd_ctr_address_syndrome_increment_decrement : STD_LOGIC;
signal synd_ctr_address_syndrome_rst : STD_LOGIC;
signal synd_reg_store_temporary_syndrome_ce : STD_LOGIC;
signal synd_reg_final_syndrome_evaluation_ce : STD_LOGIC;
signal synd_reg_final_syndrome_evaluation_rst : STD_LOGIC;
signal synd_finalize_syndrome : STD_LOGIC;
signal synd_shift_polynomial_ce_ce : STD_LOGIC;
signal synd_shift_polynomial_ce_rst : STD_LOGIC;
signal synd_shift_syndrome_mode_data_in : STD_LOGIC;
signal synd_shift_syndrome_mode_rst : STD_LOGIC;
signal synd_write_enable_new_value_syndrome : STD_LOGIC;
signal synd_calculation_finalized : STD_LOGIC;
begin
pipelines : for I in 0 to (number_of_pipelines - 1) generate
square_I : entity work.pow2_gf_2_m(Software_POLYNOMIAL)
Generic Map(gf_2_m => gf_2_m)
Port Map(
a => value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
o => square_value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
pipeline_I : pipeline_polynomial_calc_v3
Generic Map (
gf_2_m => gf_2_m,
size => pipeline_size
)
Port Map(
value_x => value_x(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_polynomial => pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I + 1)) - 1) downto (((gf_2_m)*pipeline_size*(I)))),
value_acc => pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_codeword => pipeline_value_codeword(((pipeline_size)*(I + 1) - 1) downto ((pipeline_size)*(I))),
reg_x_rst => reg_x_rst,
mode_polynomial_syndrome => mode_polynomial_syndrome,
clk => clk,
new_value_acc => value_evaluated(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
new_value_syndrome => new_value_intermediate_syndrome((((gf_2_m)*pipeline_size*(I + 1)) - 1) downto (((gf_2_m)*pipeline_size*(I))))
);
pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) when (reg_first_values_q(0) = '0') else
square_value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) when (mode_polynomial_syndrome = '1') else
first_acc;
shift_message : shift_register_nbits
Generic Map(size => pipeline_size + 1)
Port Map(
data_in => message_data_in(I),
clk => clk,
ce => '1',
q => message_data_q(((pipeline_size + 1)*(I + 1) - 1) downto ((pipeline_size + 1)*(I))),
data_out => message_data_out(I)
);
pipeline_value_codeword(((pipeline_size)*(I + 1) - 1) downto ((pipeline_size)*(I))) <= message_data_q(((pipeline_size + 1)*(I + 1) - 2) downto ((pipeline_size + 1)*(I)));
is_error_position(I) <= '1' when value_evaluated(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) = error_value else '0';
message_data_in(I) <= value_message(I);
new_value_message(I) <= (not message_data_out(I)) when is_error_position(I) = '1' else message_data_out(I);
value_error(I) <= is_error_position(I);
first_case : if I = 0 generate
pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I+1)) - 1) downto (((gf_2_m)*pipeline_size*I))) <= reg_polynomial_coefficients_q;
end generate first_case;
other_cases : if I > 0 generate
pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I+1)) - 1) downto (((gf_2_m)*pipeline_size*I))) <= new_value_intermediate_syndrome((((gf_2_m)*pipeline_size*(I)) - 1) downto (((gf_2_m)*pipeline_size*(I - 1)))) when mode_polynomial_syndrome = '1' else
reg_polynomial_coefficients_q;
end generate other_cases;
end generate;
polynomial : for I in 0 to (pipeline_size - 1) generate
reg_polynomial_coefficients_I : register_nbits
Generic Map (size => gf_2_m)
Port Map(
d => reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
clk => clk,
ce => reg_polynomial_coefficients_ce(I),
q => reg_polynomial_coefficients_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
reg_x_rst_I : register_rst_nbits
Generic Map (size => 1)
Port Map(
d => reg_x_rst_d,
clk => clk,
ce => reg_x_rst_ce(I),
rst => reg_x_rst_rst,
rst_value => "0",
q => reg_x_rst_q(I downto I)
);
reg_x_rst(I) <= (reg_x_rst_q(I) or (limit_polynomial_degree and shift_polynomial_ce_q(I)));
poly_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (last_coefficients = '1') else
value_polynomial;
first_case : if I = 0 generate
synd_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (shift_polynomial_ce_q(I) = '1') else
new_value_intermediate_syndrome(((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I + 1) - 1) downto ((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I)));
end generate first_case;
other_cases : if I > 0 generate
synd_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (shift_polynomial_ce_q(I) = '1') else
reg_polynomial_coefficients_q(((gf_2_m)*(I) - 1) downto ((gf_2_m)*(I - 1))) when (shift_syndrome_mode_q(I) = '0') else
new_value_intermediate_syndrome(((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I + 1) - 1) downto ((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I)));
end generate other_cases;
reg_polynomial_coefficients_ce(I) <= ((shift_syndrome_mode_q(I)) or finalize_syndrome) when mode_polynomial_syndrome = '1' else
shift_polynomial_ce_q(I);
end generate;
controller_poly : controller_polynomial_computing
Port Map(
clk => clk,
rst => rst,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
limit_polynomial_degree => limit_polynomial_degree,
pipeline_ready => pipeline_ready,
evaluation_data_in => poly_evaluation_data_in,
reg_write_enable_rst => poly_reg_write_enable_rst,
ctr_load_x_address_ce => poly_ctr_load_x_address_ce,
ctr_load_x_address_rst => poly_ctr_load_x_address_rst,
ctr_store_x_address_ce => poly_ctr_store_x_address_ce,
ctr_store_x_address_rst => poly_ctr_store_x_address_rst,
reg_first_values_ce => poly_reg_first_values_ce,
reg_first_values_rst => poly_reg_first_values_rst,
ctr_address_polynomial_ce => poly_ctr_address_polynomial_ce,
ctr_address_polynomial_rst => poly_ctr_address_polynomial_rst,
reg_x_rst_rst => poly_reg_x_rst_rst,
shift_polynomial_ce_ce => poly_shift_polynomial_ce_ce,
shift_polynomial_ce_rst => poly_shift_polynomial_ce_rst,
last_coefficients => poly_last_coefficients,
evaluation_finalized => poly_evaluation_finalized
);
controller_synd : controller_syndrome_computing
Port Map(
clk => clk,
rst => rst,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
last_syndrome_value => last_syndrome_value,
final_syndrome_evaluation => final_syndrome_evaluation,
pipeline_ready => pipeline_ready,
evaluation_data_in => synd_evaluation_data_in,
reg_write_enable_rst => synd_reg_write_enable_rst,
ctr_load_x_address_ce => synd_ctr_load_x_address_ce,
ctr_load_x_address_rst => synd_ctr_load_x_address_rst,
ctr_store_x_address_ce => synd_ctr_store_x_address_ce,
ctr_store_x_address_rst => synd_ctr_store_x_address_rst,
reg_first_values_ce => synd_reg_first_values_ce,
reg_first_values_rst => synd_reg_first_values_rst,
ctr_address_syndrome_ce => synd_ctr_address_syndrome_ce,
ctr_address_syndrome_load => synd_ctr_address_syndrome_load,
ctr_address_syndrome_increment_decrement => synd_ctr_address_syndrome_increment_decrement,
ctr_address_syndrome_rst => synd_ctr_address_syndrome_rst,
reg_store_temporary_syndrome_ce => synd_reg_store_temporary_syndrome_ce,
reg_final_syndrome_evaluation_ce => synd_reg_final_syndrome_evaluation_ce,
reg_final_syndrome_evaluation_rst => synd_reg_final_syndrome_evaluation_rst,
finalize_syndrome => synd_finalize_syndrome,
shift_polynomial_ce_ce => synd_shift_polynomial_ce_ce,
shift_polynomial_ce_rst => synd_shift_polynomial_ce_rst,
shift_syndrome_data_in => synd_shift_syndrome_mode_data_in,
shift_syndrome_mode_rst => synd_shift_syndrome_mode_rst,
write_enable_new_value_syndrome => synd_write_enable_new_value_syndrome,
calculation_finalized => synd_calculation_finalized
);
shift_polynomial_ce : shift_register_rst_nbits
Generic Map(
size => pipeline_size + 1
)
Port Map(
data_in => shift_polynomial_ce_data_in,
clk => clk,
ce => shift_polynomial_ce_ce,
rst => shift_polynomial_ce_rst,
rst_value => shift_polynomial_ce_rst_value,
q => shift_polynomial_ce_q,
data_out => shift_polynomial_ce_data_in
);
shift_syndrome_mode : shift_register_rst_nbits
Generic Map(
size => pipeline_size
)
Port Map(
data_in => shift_syndrome_mode_data_in,
clk => clk,
ce => '1',
rst => shift_syndrome_mode_rst,
rst_value => shift_syndrome_mode_rst_value,
q => shift_syndrome_mode_q,
data_out => open
);
evaluation : shift_register_nbits
Generic Map(
size => pipeline_size
)
Port Map(
data_in => evaluation_data_in,
clk => clk,
ce => '1',
q => open,
data_out => evaluation_data_out
);
reg_write_enable : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_write_enable_d,
clk => clk,
ce => '1',
rst => reg_write_enable_rst,
rst_value => reg_write_enable_rst_value,
q => reg_write_enable_q
);
ctr_address_polynomial_syndrome : counter_increment_decrement_load_rst_nbits
Generic Map(
size => size_number_of_errors+1,
increment_value => 1,
decrement_value => 1
)
Port Map(
d => ctr_address_polynomial_syndrome_d,
clk => clk,
ce => ctr_address_polynomial_syndrome_ce,
load => ctr_address_polynomial_syndrome_load,
increment_decrement => ctr_address_polynomial_syndrome_increment_decrement,
rst => ctr_address_polynomial_syndrome_rst,
rst_value => ctr_address_polynomial_syndrome_rst_value,
q => ctr_address_polynomial_syndrome_q
);
reg_store_temporary_syndrome : register_nbits
Generic Map(
size => size_number_of_errors+1
)
Port Map(
d => reg_store_temporary_syndrome_d,
clk => clk,
ce => reg_store_temporary_syndrome_ce,
q => reg_store_temporary_syndrome_q
);
ctr_load_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_support_elements,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_load_x_address_ce,
rst => ctr_load_x_address_rst,
rst_value => ctr_load_x_address_rst_value,
q => ctr_load_x_address_q
);
ctr_store_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_support_elements,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_store_x_address_ce,
rst => ctr_store_x_address_rst,
rst_value => ctr_store_x_address_rst_value,
q => ctr_store_x_address_q
);
reg_first_values : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "0",
clk => clk,
ce => reg_first_values_ce,
rst => reg_first_values_rst,
rst_value => reg_first_values_rst_value,
q => reg_first_values_q
);
reg_final_syndrome_evaluation : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "1",
clk => clk,
ce => reg_final_syndrome_evaluation_ce,
rst => reg_final_syndrome_evaluation_rst,
rst_value => reg_final_syndrome_evaluation_rst_value,
q => reg_final_syndrome_evaluation_q
);
new_value_acc <= value_evaluated;
evaluation_data_in <= synd_evaluation_data_in when mode_polynomial_syndrome = '1' else
poly_evaluation_data_in;
reg_write_enable_rst <= synd_reg_write_enable_rst when mode_polynomial_syndrome = '1' else
poly_reg_write_enable_rst;
ctr_load_x_address_ce <= synd_ctr_load_x_address_ce when mode_polynomial_syndrome = '1' else
poly_ctr_load_x_address_ce;
ctr_load_x_address_rst <= synd_ctr_load_x_address_rst when mode_polynomial_syndrome = '1' else
poly_ctr_load_x_address_rst;
ctr_store_x_address_ce <= synd_ctr_store_x_address_ce when mode_polynomial_syndrome = '1' else
poly_ctr_store_x_address_ce;
ctr_store_x_address_rst <= synd_ctr_store_x_address_rst when mode_polynomial_syndrome = '1' else
poly_ctr_store_x_address_rst;
reg_first_values_ce <= synd_reg_first_values_ce when mode_polynomial_syndrome = '1' else
poly_reg_first_values_ce;
reg_first_values_rst <= synd_reg_first_values_rst when mode_polynomial_syndrome = '1' else
poly_reg_first_values_rst;
ctr_address_polynomial_syndrome_ce <= synd_ctr_address_syndrome_ce when mode_polynomial_syndrome = '1' else
poly_ctr_address_polynomial_ce;
ctr_address_polynomial_syndrome_load <= synd_ctr_address_syndrome_load when mode_polynomial_syndrome = '1' else
'0';
ctr_address_polynomial_syndrome_increment_decrement <= synd_ctr_address_syndrome_increment_decrement when mode_polynomial_syndrome = '1' else
'1';
ctr_address_polynomial_syndrome_rst <= synd_ctr_address_syndrome_rst when mode_polynomial_syndrome = '1' else
poly_ctr_address_polynomial_rst;
ctr_address_polynomial_syndrome_rst_value <= synd_ctr_address_syndrome_rst_value when mode_polynomial_syndrome = '1' else
poly_ctr_address_polynomial_rst_value;
reg_store_temporary_syndrome_ce <= synd_reg_store_temporary_syndrome_ce when mode_polynomial_syndrome = '1' else
'0';
reg_x_rst_rst <= '1' when mode_polynomial_syndrome = '1' else
poly_reg_x_rst_rst;
reg_final_syndrome_evaluation_ce <= synd_reg_final_syndrome_evaluation_ce when mode_polynomial_syndrome = '1' else
'0';
reg_final_syndrome_evaluation_rst <= synd_reg_final_syndrome_evaluation_rst when mode_polynomial_syndrome = '1' else
'0';
finalize_syndrome <= synd_finalize_syndrome when mode_polynomial_syndrome = '1' else
'1';
shift_polynomial_ce_ce <= synd_shift_polynomial_ce_ce when mode_polynomial_syndrome = '1' else
poly_shift_polynomial_ce_ce;
shift_polynomial_ce_rst <= synd_shift_polynomial_ce_rst when mode_polynomial_syndrome = '1' else
poly_shift_polynomial_ce_rst;
shift_syndrome_mode_data_in <= synd_shift_syndrome_mode_data_in when mode_polynomial_syndrome = '1' else
'0';
shift_syndrome_mode_rst <= synd_shift_syndrome_mode_rst when mode_polynomial_syndrome = '1' else
'0';
last_coefficients <= '0' when mode_polynomial_syndrome = '1' else
poly_last_coefficients;
computation_finalized <= synd_calculation_finalized when mode_polynomial_syndrome = '1' else
poly_evaluation_finalized;
reg_x_rst_d(0) <= limit_polynomial_degree;
reg_x_rst_ce <= shift_polynomial_ce_q((pipeline_size - 1) downto 0);
reg_polynomial_coefficients_d <= synd_reg_polynomial_coefficients_d when mode_polynomial_syndrome = '1' else
poly_reg_polynomial_coefficients_d;
write_enable_new_value_syndrome <= synd_write_enable_new_value_syndrome when mode_polynomial_syndrome = '1' else
'0';
address_value_polynomial <= ctr_address_polynomial_syndrome_q((size_number_of_errors - 1) downto 0);
address_value_x <= ctr_load_x_address_q;
address_value_acc <= ctr_load_x_address_q;
address_value_message <= ctr_load_x_address_q;
address_new_value_acc <= ctr_store_x_address_q;
address_new_value_message <= ctr_store_x_address_q;
address_value_error <= ctr_store_x_address_q;
address_new_value_syndrome <= ctr_address_polynomial_syndrome_q;
reg_store_temporary_syndrome_d <= ctr_address_polynomial_syndrome_q;
ctr_address_polynomial_syndrome_d <= reg_store_temporary_syndrome_q;
pipeline_ready <= shift_polynomial_ce_q(pipeline_size-1);
limit_polynomial_degree <= '1' when (signed(ctr_address_polynomial_syndrome_q) = to_signed(-1, ctr_address_polynomial_syndrome_q'length)) else '0';
last_syndrome_value <= '1' when (ctr_address_polynomial_syndrome_q = std_logic_vector(to_signed(0, ctr_address_polynomial_syndrome_q'Length))) else '0';
last_evaluations <= limit_polynomial_degree and shift_polynomial_ce_q(pipeline_size);
final_syndrome_evaluation <= reg_final_syndrome_evaluation_q(0);
reg_write_enable_d(0) <= evaluation_data_out;
new_value_syndrome <= reg_polynomial_coefficients_q(((gf_2_m)*(pipeline_size) - 1) downto ((gf_2_m)*(pipeline_size - 1)));
write_enable_new_value_acc <= reg_write_enable_q(0);
write_enable_new_value_message <= '0' when mode_polynomial_syndrome = '1' else
reg_write_enable_q(0) and last_evaluations;
write_enable_value_error <= '0' when mode_polynomial_syndrome = '1' else
reg_write_enable_q(0) and last_evaluations;
last_load_x_values <= '1' when ctr_load_x_address_q = std_logic_vector(to_unsigned(((number_of_support_elements - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
last_store_x_values <= '1' when ctr_store_x_address_q = std_logic_vector(to_unsigned(((number_of_support_elements - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
end RTL; |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY XEVIOUS_BROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END XEVIOUS_BROM;
ARCHITECTURE XEVIOUS_BROM_arch OF XEVIOUS_BROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF XEVIOUS_BROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF XEVIOUS_BROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF XEVIOUS_BROM_arch : ARCHITECTURE IS "XEVIOUS_BROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF XEVIOUS_BROM_arch: ARCHITECTURE IS "XEVIOUS_BROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=XEVIOUS_BROM.mif,C_INIT_FILE=XEVIOUS_BROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "XEVIOUS_BROM.mif",
C_INIT_FILE => "XEVIOUS_BROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END XEVIOUS_BROM_arch;
|
----------------------------------------------------------------------------------
--
-- Lab session #4: Player
--
-- Block with everything needed for a player
--
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity player is
Port (
-- User controls
Right : in STD_LOGIC;
Left : in STD_LOGIC;
Start : in STD_LOGIC;
Shoot : in STD_LOGIC;
-- Control signals
clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Clear : in STD_LOGIC;
ScoreClear : in STD_LOGIC;
Enable: in STD_LOGIC;
-- Internal signals
hit : in STD_LOGIC;
posShip : out STD_LOGIC_VECTOR (4 downto 0);
startPulse : out STD_LOGIC;
BulletX : out STD_LOGIC_VECTOR (4 downto 0);
BulletY : out STD_LOGIC_VECTOR (3 downto 0);
BulletActive : out STD_LOGIC;
Score : out STD_LOGIC_VECTOR (7 downto 0));
end player;
architecture Structural of player is
-- Component declaration for player spaceship control block:
COMPONENT spaceship
PORT (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear: in STD_LOGIC;
left : in STD_LOGIC;
right : in STD_LOGIC;
enable : in STD_LOGIC;
posH : out STD_LOGIC_VECTOR (4 downto 0)
);
END COMPONENT;
-- Component declaration for button edge detector (without debouncing )
COMPONENT edgeDetector
PORT (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
clear: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
END COMPONENT;
-- Component declaration for button edge detector (with/ debouncing )
COMPONENT edgeDetectorDebounce
PORT (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
clear: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
END COMPONENT;
-- Component declaration for bullet shooting control
COMPONENT bullet
PORT (
clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
enable : in std_logic;
hit : in std_logic;
shoot : in std_logic;
posH : in std_logic_vector(4 downto 0);
flying : out std_logic;
bullX : out std_logic_vector(4 downto 0);
bullY : out std_logic_vector(3 downto 0)
);
END COMPONENT;
-- Signals to connect things internally
signal leftDetected: std_logic;
signal rightDetected: std_logic;
signal posHBus: std_logic_vector( 4 downto 0);
begin
spaceshipControl: spaceship
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
left => leftDetected,
right => rightDetected,
enable => enable,
posH => posHBus
);
leftEdgeDetector: edgeDetectorDebounce
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
enable => enable,
input => Left,
detected => leftDetected
);
rightEdgeDetector: edgeDetectorDebounce
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
enable => enable,
input => Right,
detected => rightDetected
);
startEdgeDetector: edgeDetectorDebounce
PORT MAP(
clk => clk,
reset => Reset,
clear => '0',
enable => '1',
input => Start,
detected => startPulse
);
laserGun: bullet
PORT MAP(
clk => clk,
reset => Reset,
clear => clear,
enable => enable,
hit => hit,
shoot => Shoot,
posH => posHBus,
flying => BulletActive,
bullX => BulletX,
bullY => BulletY
);
posShip <= posHBus;
process( clk, reset )
variable intScore: integer range 0 to 255;
begin
if Reset = '1' then
intScore := 0;
elsif clk'event and clk = '1' then
-- Erase score
if ScoreClear = '1' then
intScore := 0;
-- Increase score when alien is hit
elsif hit = '1' then
intScore := intScore + 1;
end if;
end if;
score <= std_logic_vector( to_unsigned( intScore, 8));
end process;
end Structural;
|
entity leftofrightof is
end entity;
architecture subclass_variable of leftofrightof is
begin
process
variable i: character := 'e';
begin
report "i = " & character'image(i);
report "leftof(i) = " & character'image(character'leftof(i));
report "rightof(i) = " & character'image(character'rightof(i));
wait;
end process;
end architecture;
|
entity leftofrightof is
end entity;
architecture subclass_variable of leftofrightof is
begin
process
variable i: character := 'e';
begin
report "i = " & character'image(i);
report "leftof(i) = " & character'image(character'leftof(i));
report "rightof(i) = " & character'image(character'rightof(i));
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity tb_output07 is
end tb_output07;
architecture behav of tb_output07 is
signal i : std_logic;
signal clk : std_logic;
signal o : std_logic_vector (1 downto 0);
begin
inst: entity work.output07
port map (clk => clk, i => i, o => o);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
wait for 1 ns;
assert o = "10" severity failure;
i <= '1';
pulse;
assert o = "01" severity failure;
i <= '0';
pulse;
assert o = "10" severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_swap_left_right_64_bits is
end test_swap_left_right_64_bits;
architecture behavior of test_swap_left_right_64_bits is
signal data_in_left: std_logic_vector(0 to 31);
signal data_in_right: std_logic_vector(0 to 31);
signal data_out_left: std_logic_vector(0 to 31);
signal data_out_right: std_logic_vector(0 to 31);
begin
uut: entity swap_left_right_64_bits port map(data_in_left,data_in_right,data_out_left,data_out_right);
testprocess: process is
begin
data_in_left<="11111111111111111111111111111111";
data_in_right<="00000000000000000000000000000000";
wait for 10 ns;
end process testprocess;
end architecture behavior;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use STD.textio.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY nco_tb IS
END nco_tb;
ARCHITECTURE behavior OF nco_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nco
PORT(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '0';
signal phase_offset : signed(31 downto 0) := (others => '0');
signal phase_incr : signed(31 downto 0) := (others => '0');
constant C_MAX_SAMPLE_COUNT : integer := 1024;
constant FPGA_FREQUENCY : integer := 100000000;
--Outputs
signal data : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 10;
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
shared variable local_ram : LOCAL_MEMORY_T;-- := ( others => (others => '0'));
signal o_RAMAddr_nco : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others => '0');
signal o_RAMData_nco : std_logic_vector(0 to 31); -- nco to local ram
signal o_RAMWE_nco : std_logic := '0';
BEGIN
phase_incr <= Get_Cordic_Phase_Increment(FPGA_FREQUENCY, 1999);
-- Instantiate the Unit Under Test (UUT)
uut: nco PORT MAP (
clk => clk,
rst => rst,
ce => ce,
phase_offset => phase_offset,
phase_incr => phase_incr,
data => data
);
o_RAMData_nco <= std_logic_vector(data);
local_ram_ctrl_2 : process (clk) is
begin
if rising_edge(clk) then
if (o_RAMWE_nco = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco))) := o_RAMData_nco;
end if;
end if;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
wait;
end process;
process(clk)
begin
if(rising_edge(clk) )then
ce <= '1';
o_RAMWE_nco <= '1';
o_RAMAddr_nco <= std_logic_vector(unsigned(o_RAMAddr_nco) + 1);
end if;
end process;
write_data_proc : process
file sine_file : TEXT open WRITE_MODE is "sine.out";
variable wline : line;
begin
write(wline, to_integer(data));
writeline(sine_file, wline);
wait for clk_period;
end process;
END;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
context bitvis_vip_sbi.vvc_context;
library bitvis_vip_gmii;
context bitvis_vip_gmii.vvc_context;
library bitvis_vip_ethernet;
context bitvis_vip_ethernet.vvc_context;
use work.ethernet_mac_pkg.all;
--hdlunit:tb
-- Test case entity
entity ethernet_sbi_gmii_demo_tb is
end entity ethernet_sbi_gmii_demo_tb;
-- Test case architecture
architecture func of ethernet_sbi_gmii_demo_tb is
--------------------------------------------------------------------------------
-- Types and constants declarations
--------------------------------------------------------------------------------
constant C_CLK_PERIOD : time := 8 ns;
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant C_VVC_ETH_SBI : natural := 1;
constant C_VVC_SBI : natural := 1;
constant C_VVC_ETH_GMII : natural := 2;
constant C_VVC_GMII : natural := 2;
constant C_ETH_SBI_MAC_ADDR : unsigned(47 downto 0) := x"00_00_00_00_00_01";
constant C_ETH_GMII_MAC_ADDR : unsigned(47 downto 0) := x"00_00_00_00_00_02";
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Instantiate test harness, containing DUT and VVCs
-----------------------------------------------------------------------------
i_test_harness : entity bitvis_vip_ethernet.ethernet_sbi_gmii_demo_th
generic map(
GC_CLK_PERIOD => C_CLK_PERIOD
);
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
variable v_payload_len : integer := 0;
variable v_payload_data : t_byte_array(0 to C_MAX_PAYLOAD_LENGTH-1);
variable v_expected_frame : t_ethernet_frame;
impure function make_ethernet_frame(
constant mac_destination : in unsigned(47 downto 0);
constant mac_source : in unsigned(47 downto 0);
constant payload : in t_byte_array
) return t_ethernet_frame is
variable v_frame : t_ethernet_frame := C_ETHERNET_FRAME_DEFAULT;
variable v_packet : t_byte_array(0 to C_MAX_PACKET_LENGTH-1) := (others => (others => '0'));
variable v_payload_length : positive := payload'length;
begin
-- MAC destination
v_frame.mac_destination := mac_destination;
v_packet(0 to 5) := convert_slv_to_byte_array(std_logic_vector(v_frame.mac_destination), LOWER_BYTE_LEFT);
-- MAC source
v_frame.mac_source := mac_source;
v_packet(6 to 11) := convert_slv_to_byte_array(std_logic_vector(v_frame.mac_source), LOWER_BYTE_LEFT);
-- Payload length
v_frame.payload_length := v_payload_length;
v_packet(12 to 13) := convert_slv_to_byte_array(std_logic_vector(to_unsigned(v_frame.payload_length, 16)), LOWER_BYTE_LEFT);
-- Payload
v_frame.payload(0 to v_payload_length-1) := payload;
v_packet(14 to 14+v_payload_length-1) := payload;
-- Add padding if needed
if v_payload_length < C_MIN_PAYLOAD_LENGTH then
v_payload_length := C_MIN_PAYLOAD_LENGTH;
end if;
-- FCS
v_frame.fcs := not generate_crc_32(v_packet(0 to 14+v_payload_length-1));
return v_frame;
end function make_ethernet_frame;
begin
-- Wait for UVVM to finish initialization
await_uvvm_initialization(VOID);
-- Verbosity control
disable_log_msg(ID_UVVM_CMD_ACK);
-- Set Ethernet VVC config for this testbench
shared_ethernet_vvc_config(TX, C_VVC_ETH_SBI).bfm_config.mac_destination := C_ETH_GMII_MAC_ADDR;
shared_ethernet_vvc_config(TX, C_VVC_ETH_SBI).bfm_config.mac_source := C_ETH_SBI_MAC_ADDR;
shared_ethernet_vvc_config(RX, C_VVC_ETH_GMII).bfm_config.mac_destination := C_ETH_SBI_MAC_ADDR;
shared_ethernet_vvc_config(RX, C_VVC_ETH_GMII).bfm_config.mac_source := C_ETH_GMII_MAC_ADDR;
-- Set the receiving VVC timeout long enough to handle a packet going through the DUT
shared_gmii_vvc_config(RX, C_VVC_GMII).bfm_config.max_wait_cycles := C_MAX_PACKET_LENGTH;
---------------------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "START SIMULATION OF ETHERNET VVC");
---------------------------------------------------------------------------
v_payload_len := 10;
for i in 0 to v_payload_len-1 loop
v_payload_data(i) := random(8);
end loop;
log(ID_LOG_HDR, "Transmit " & to_string(v_payload_len) & " bytes of data from CPU to Ethernet MAC (need padding)");
ethernet_transmit(ETHERNET_VVCT, C_VVC_ETH_SBI, TX, v_payload_data(0 to v_payload_len-1), "Transmit a frame from the CPU.");
v_expected_frame := make_ethernet_frame(C_ETH_GMII_MAC_ADDR, C_ETH_SBI_MAC_ADDR, v_payload_data(0 to v_payload_len-1));
ETHERNET_VVC_SB.add_expected(C_VVC_ETH_GMII, v_expected_frame);
ethernet_receive(ETHERNET_VVCT, C_VVC_ETH_GMII, RX, TO_SB, "Receive a frame in the PHY and put it in the Scoreboard.");
await_completion(ETHERNET_VVCT, C_VVC_ETH_SBI, TX, 1 ms, "Wait for transmit to finish.");
await_completion(ETHERNET_VVCT, C_VVC_ETH_GMII, RX, 1 ms, "Wait for receive to finish.");
v_payload_len := 46;
for i in 0 to v_payload_len-1 loop
v_payload_data(i) := random(8);
end loop;
log(ID_LOG_HDR, "Transmit " & to_string(v_payload_len) & " bytes of data from CPU to Ethernet MAC (minimum size)");
ethernet_transmit(ETHERNET_VVCT, C_VVC_ETH_SBI, TX, v_payload_data(0 to v_payload_len-1), "Transmit a frame from the CPU.");
v_expected_frame := make_ethernet_frame(C_ETH_GMII_MAC_ADDR, C_ETH_SBI_MAC_ADDR, v_payload_data(0 to v_payload_len-1));
ETHERNET_VVC_SB.add_expected(C_VVC_ETH_GMII, v_expected_frame);
ethernet_receive(ETHERNET_VVCT, C_VVC_ETH_GMII, RX, TO_SB, "Receive a frame in the PHY and put it in the Scoreboard.");
await_completion(ETHERNET_VVCT, C_VVC_ETH_SBI, TX, 1 ms, "Wait for transmit to finish.");
await_completion(ETHERNET_VVCT, C_VVC_ETH_GMII, RX, 1 ms, "Wait for receive to finish.");
v_payload_len := C_MAX_PAYLOAD_LENGTH;
for i in 0 to v_payload_len-1 loop
v_payload_data(i) := random(8);
end loop;
log(ID_LOG_HDR, "Transmit " & to_string(v_payload_len) & " bytes of data from CPU to Ethernet MAC (maximum size)");
ethernet_transmit(ETHERNET_VVCT, C_VVC_ETH_SBI, TX, v_payload_data(0 to v_payload_len-1), "Transmit a frame from the CPU.");
v_expected_frame := make_ethernet_frame(C_ETH_GMII_MAC_ADDR, C_ETH_SBI_MAC_ADDR, v_payload_data(0 to v_payload_len-1));
ETHERNET_VVC_SB.add_expected(C_VVC_ETH_GMII, v_expected_frame);
ethernet_receive(ETHERNET_VVCT, C_VVC_ETH_GMII, RX, TO_SB, "Receive a frame in the PHY and put it in the Scoreboard.");
await_completion(ETHERNET_VVCT, C_VVC_ETH_SBI, TX, 1 ms, "Wait for transmit to finish.");
await_completion(ETHERNET_VVCT, C_VVC_ETH_GMII, RX, 1 ms, "Wait for receive to finish.");
---------------------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "TEST DIRECT ACCESS TO INTERFACE VVCs");
---------------------------------------------------------------------------
log(ID_LOG_HDR, "Write and read data on SBI level");
for i in 0 to 9 loop
v_payload_data(0) := random(8);
sbi_write(SBI_VVCT, C_VVC_SBI, C_ETH_ADDR_DUMMY, v_payload_data(0), "Write byte " & to_string(i) & " to dummy register");
sbi_check(SBI_VVCT, C_VVC_SBI, C_ETH_ADDR_DUMMY, v_payload_data(0), "Check byte " & to_string(i) & " from dummy register");
end loop;
await_completion(SBI_VVCT, C_VVC_SBI, 1 ms, "Wait for check to finish");
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- Allow some time for completion
ETHERNET_VVC_SB.report_counters(ALL_INSTANCES);
report_alert_counters(FINAL); -- Report final counters and print conclusion (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end architecture func; |
-- ####################################
-- # Project: Yarr
-- # Author: Vyassa Baratham
-- # E-Mail: vbaratham at berkeley.edu
-- # Comments: Allows configurable delay of up to N clk cycles
-- # Data: 09/2017
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delayer is
generic (N : integer); -- shift register width
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
dat_i : in std_logic;
dat_o : out std_logic;
delay : in std_logic_vector(N-1 downto 0)
);
end delayer;
architecture rtl of delayer is
signal shift_reg : std_logic_vector(2**N-1 downto 0);
begin
proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dat_o <= '0';
shift_reg <= (others => '0');
elsif rising_edge(clk_i) then
shift_reg(2**N-1 downto 1) <= shift_reg(2**N-2 downto 0);
shift_reg(0) <= dat_i;
dat_o <= shift_reg(to_integer(unsigned(delay)));
end if;
end process proc;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
package pack is
type rec is record
f : std_logic_vector;
end record;
subtype rec4 is rec(f(1 to 4));
end package;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pack.all;
entity record31 is
port ( r : inout rec4 );
end entity;
architecture test of record31 is
begin
p1: process is
begin
r.f <= "ZZZZ";
wait for 1 ns;
assert r.f = "1010";
r.f <= "Z1ZZ";
wait for 1 ns;
assert r.f = "1X10";
wait;
end process;
p2: process is
begin
r.f <= "1010";
wait for 1 ns;
assert r.f = "1010";
wait for 1 ns;
assert r.f = "1X10";
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file VGA_BUFFER_RAM.vhd when simulating
-- the core, VGA_BUFFER_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY VGA_BUFFER_RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END VGA_BUFFER_RAM;
ARCHITECTURE VGA_BUFFER_RAM_a OF VGA_BUFFER_RAM IS
-- synthesis translate_off
COMPONENT wrapped_VGA_BUFFER_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_VGA_BUFFER_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "VGA_BUFFER_RAM.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_VGA_BUFFER_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END VGA_BUFFER_RAM_a;
|
entity length_tb1 is
end length_tb1;
architecture tb of length_tb1 is
begin
process
variable s : string (1 to 4);
constant c : string := "hello";
begin
-- Behaves like 32-bit arithmetic with modular truncation
s := c;
wait; -- forever
end process;
end tb;
|
entity length_tb1 is
end length_tb1;
architecture tb of length_tb1 is
begin
process
variable s : string (1 to 4);
constant c : string := "hello";
begin
-- Behaves like 32-bit arithmetic with modular truncation
s := c;
wait; -- forever
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MWE is
port (
a : in std_logic_vector(0 to 3);
b : in std_logic_vector(0 to 3);
sel : in std_logic_vector(0 to 1);
o : out std_logic_vector(0 to 1)
);
end MWE;
architecture behavioral of MWE is
signal cnt : integer range 0 to 1;
begin
cnt <= to_integer(unsigned(sel));
o <= a(cnt*o'length to (cnt + 1)*o'length - 1) xor b(cnt*o'length to (cnt + 1)*o'length - 1);
end architecture behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_data_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM is
port (
clock : in std_logic;
-- Port a has read and write
a_addr : in std_logic_vector(9 downto 0);
a_write : in std_logic;
a_din : in std_logic_vector(7 downto 0);
a_dout : out std_logic_vector(7 downto 0);
-- Port b is read only
b_addr : in std_logic_vector(9 downto 0);
b_dout : out std_logic_vector(7 downto 0)
);
end entity RAM;
architecture behavioural of RAM is
type memory is array(0 to 1023) of std_logic_vector(7 downto 0);
signal storage : memory := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
a_dout <= storage(to_integer(unsigned(a_addr)));
b_dout <= storage(to_integer(unsigned(b_addr)));
if a_write = '1' then
storage(to_integer(unsigned(a_addr))) <= a_din;
end if;
end if;
end process;
end behavioural;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity kirkman_nov is
port(
clock: in std_logic;
input: in std_logic_vector(11 downto 0);
output: out std_logic_vector(5 downto 0)
);
end kirkman_nov;
architecture behaviour of kirkman_nov is
constant rst0: std_logic_vector(4 downto 0) := "00000";
constant bit1: std_logic_vector(4 downto 0) := "00001";
constant bit2: std_logic_vector(4 downto 0) := "00010";
constant bit3: std_logic_vector(4 downto 0) := "01011";
constant bit4: std_logic_vector(4 downto 0) := "01101";
constant bit5: std_logic_vector(4 downto 0) := "01110";
constant bit6: std_logic_vector(4 downto 0) := "01111";
constant bit7: std_logic_vector(4 downto 0) := "01000";
constant bit8: std_logic_vector(4 downto 0) := "01001";
constant bit9: std_logic_vector(4 downto 0) := "01010";
constant bitA: std_logic_vector(4 downto 0) := "01100";
constant bitB: std_logic_vector(4 downto 0) := "00100";
constant bitC: std_logic_vector(4 downto 0) := "00101";
constant bitD: std_logic_vector(4 downto 0) := "00110";
constant bitE: std_logic_vector(4 downto 0) := "00111";
constant bitF: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
if std_match(input, "--------1---") then next_state <= rst0; output <= "1-----";
else
case current_state is
when rst0 =>
if std_match(input, "--------0000") then next_state <= rst0; output <= "0----0";
elsif std_match(input, "--------0001") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit1; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit1; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit1; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit1; output <= "0---00";
end if;
when bit1 =>
if std_match(input, "--------0001") then next_state <= bit2; output <= "0---10";
elsif std_match(input, "-----0--0111") then next_state <= bit2; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= bit2; output <= "0--110";
elsif std_match(input, "--------0010") then next_state <= bit2; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bit2; output <= "0---00";
end if;
when bit2 =>
if std_match(input, "--------0001") then next_state <= bit3; output <= "0---00";
elsif std_match(input, "-----0--0111") then next_state <= bit3; output <= "0--000";
elsif std_match(input, "-----1--0111") then next_state <= bit3; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bit3; output <= "0---10";
elsif std_match(input, "--------0100") then next_state <= bit3; output <= "0---10";
end if;
when bit3 =>
if std_match(input, "0-------0001") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "-00--00-0111") then next_state <= bit4; output <= "100000";
elsif std_match(input, "-01--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--00-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--00-0111") then next_state <= bit4; output <= "110000";
elsif std_match(input, "-00--01-0111") then next_state <= bit4; output <= "101000";
elsif std_match(input, "-01--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-10--01-0111") then next_state <= bit4; output <= "100010";
elsif std_match(input, "-11--01-0111") then next_state <= bit4; output <= "111000";
elsif std_match(input, "-----10-0111") then next_state <= bit4; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit4; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit4; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit4; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit4; output <= "1---10";
end if;
when bit4 =>
if std_match(input, "0-------0001") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit5; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit5; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit5; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit5; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit5; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit5; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit5; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit5; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit5; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit5; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit5; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit5; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit5; output <= "1---10";
end if;
when bit5 =>
if std_match(input, "0-------0001") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit6; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit6; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit6; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit6; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit6; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit6; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit6; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit6; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit6; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit6; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit6; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit6; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit6; output <= "1---10";
end if;
when bit6 =>
if std_match(input, "0-------0001") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit7; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit7; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit7; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit7; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit7; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit7; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit7; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit7; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit7; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit7; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit7; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit7; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit7; output <= "1---10";
end if;
when bit7 =>
if std_match(input, "0-------0001") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit8; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit8; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit8; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit8; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit8; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit8; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit8; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit8; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit8; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit8; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit8; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit8; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit8; output <= "1---10";
end if;
when bit8 =>
if std_match(input, "0-------0001") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bit9; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bit9; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bit9; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bit9; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bit9; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bit9; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bit9; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bit9; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bit9; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bit9; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bit9; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bit9; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bit9; output <= "1---10";
end if;
when bit9 =>
if std_match(input, "0-------0001") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitA; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitA; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitA; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitA; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitA; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitA; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitA; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitA; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitA; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitA; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitA; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitA; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitA; output <= "1---10";
end if;
when bitA =>
if std_match(input, "0-------0001") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "1-------0001") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "-000000-0111") then next_state <= bitB; output <= "100000";
elsif std_match(input, "-001000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-100000-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-110000-0111") then next_state <= bitB; output <= "110000";
elsif std_match(input, "-111000-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000100-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100100-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110100-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111100-0111") then next_state <= bitB; output <= "110010";
elsif std_match(input, "-000001-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-010001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-011001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100001-0111") then next_state <= bitB; output <= "100010";
elsif std_match(input, "-101001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110001-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111001-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-000101-0111") then next_state <= bitB; output <= "101000";
elsif std_match(input, "-001101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-010101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-011101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-100101-0111") then next_state <= bitB; output <= "101010";
elsif std_match(input, "-101101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-110101-0111") then next_state <= bitB; output <= "111000";
elsif std_match(input, "-111101-0111") then next_state <= bitB; output <= "111010";
elsif std_match(input, "-----10-0111") then next_state <= bitB; output <= "1--100";
elsif std_match(input, "-----11-0111") then next_state <= bitB; output <= "1--110";
elsif std_match(input, "-------00010") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "-------10010") then next_state <= bitB; output <= "1---10";
elsif std_match(input, "------0-0100") then next_state <= bitB; output <= "1---00";
elsif std_match(input, "------1-0100") then next_state <= bitB; output <= "1---10";
end if;
when bitB =>
if std_match(input, "--------0001") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitC; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitC; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitC; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitC; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitC; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitC; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitC; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitC; output <= "0---00";
end if;
when bitC =>
if std_match(input, "--------0001") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitD; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitD; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitD; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitD; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitD; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitD; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitD; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitD; output <= "0---00";
end if;
when bitD =>
if std_match(input, "--------0001") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--0000--0111") then next_state <= bitE; output <= "000000";
elsif std_match(input, "--0100--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1000--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1100--0111") then next_state <= bitE; output <= "010000";
elsif std_match(input, "--0010--0111") then next_state <= bitE; output <= "001000";
elsif std_match(input, "--0110--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1010--0111") then next_state <= bitE; output <= "000010";
elsif std_match(input, "--1110--0111") then next_state <= bitE; output <= "011000";
elsif std_match(input, "-----1--0111") then next_state <= bitE; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= bitE; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= bitE; output <= "0---00";
end if;
when bitE =>
if std_match(input, "--------0001") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--0000--0111") then next_state <= bitF; output <= "000001";
elsif std_match(input, "--0100--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1000--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1100--0111") then next_state <= bitF; output <= "010001";
elsif std_match(input, "--0010--0111") then next_state <= bitF; output <= "001100";
elsif std_match(input, "--0110--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1010--0111") then next_state <= bitF; output <= "000011";
elsif std_match(input, "--1110--0111") then next_state <= bitF; output <= "011001";
elsif std_match(input, "-----1--0111") then next_state <= bitF; output <= "0--001";
elsif std_match(input, "--------0010") then next_state <= bitF; output <= "0---01";
elsif std_match(input, "--------0100") then next_state <= bitF; output <= "0---01";
end if;
when bitF =>
if std_match(input, "--------0001") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "---0-0--0111") then next_state <= rst0; output <= "0--000";
elsif std_match(input, "---1-0--0111") then next_state <= rst0; output <= "0--010";
elsif std_match(input, "-----1--0111") then next_state <= rst0; output <= "0--100";
elsif std_match(input, "--------0010") then next_state <= rst0; output <= "0---00";
elsif std_match(input, "--------0100") then next_state <= rst0; output <= "0---00";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end if;
end process;
end behaviour;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc475.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00475ent IS
END c03s02b01x01p19n01i00475ent;
ARCHITECTURE c03s02b01x01p19n01i00475arch OF c03s02b01x01p19n01i00475ent IS
type boolean_vector is array (natural range <>) of boolean;
function resolution1(i:in boolean_vector) return boolean is
variable temp : boolean:= true;
begin
return temp;
end resolution1;
subtype boolean_state is resolution1 boolean;
constant C66 : boolean_state := true;
function complex_scalar(s : boolean_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_state;
signal S2 : boolean_state;
signal S3 : boolean_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00475"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00475 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00475arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc475.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00475ent IS
END c03s02b01x01p19n01i00475ent;
ARCHITECTURE c03s02b01x01p19n01i00475arch OF c03s02b01x01p19n01i00475ent IS
type boolean_vector is array (natural range <>) of boolean;
function resolution1(i:in boolean_vector) return boolean is
variable temp : boolean:= true;
begin
return temp;
end resolution1;
subtype boolean_state is resolution1 boolean;
constant C66 : boolean_state := true;
function complex_scalar(s : boolean_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_state;
signal S2 : boolean_state;
signal S3 : boolean_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00475"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00475 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00475arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc475.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00475ent IS
END c03s02b01x01p19n01i00475ent;
ARCHITECTURE c03s02b01x01p19n01i00475arch OF c03s02b01x01p19n01i00475ent IS
type boolean_vector is array (natural range <>) of boolean;
function resolution1(i:in boolean_vector) return boolean is
variable temp : boolean:= true;
begin
return temp;
end resolution1;
subtype boolean_state is resolution1 boolean;
constant C66 : boolean_state := true;
function complex_scalar(s : boolean_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_state;
signal S2 : boolean_state;
signal S3 : boolean_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00475"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00475 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00475arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:28:36 01/30/2017
-- Design Name:
-- Module Name: PWM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PWM is
Port(
clk : IN STD_LOGIC;
pwm_output : OUT STD_LOGIC ;
pwm_input : STD_LOGIC_VECTOR ( 7 downto 0)
);
end PWM;
architecture Behavioral of PWM is
signal counter : STD_LOGIC_VECTOR ( 7 downto 0) := "00000000";
begin
Count_Process : process (clk)
begin
if rising_edge( clk ) then
if to_integer(unsigned(counter)) < to_integer(unsigned(pwm_input)) then
pwm_output <= '1';
else
pwm_output <= '0';
end if;
if to_integer(unsigned(counter)) < 255 then
counter <= counter+1;
else
counter <= "00000000";
end if;
end if;
--pwm_output <= '1' when to_integer(unsigned(counter)) > to_integer(unsigned(pwm_input)) else '0';
end process;
end Behavioral;
|
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
procedure_call_label : POSTPONED wr_en(a, b);
end architecture rtl;
|
architecture ARCH of ENTITY1 is
begin
assert boolean report "Something" severity FAILURE;
process begin
LABEL : assert boolean report "Something" severity FAILURE;
LABEL : assert boolean
report "Something" severity FAILURE;
LABEL : assert boolean report "Something"
severity FAILURE;
LABEL : assert boolean
report "Something"
severity FAILURE;
assert boolean report "Something" severity FAILURE;
assert boolean
report "Something" severity FAILURE;
assert boolean report "Something"
severity FAILURE;
assert boolean
report "Something"
severity FAILURE;
end process;
assert boolean report "Something" severity FAILURE;
end architecture ARCH;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer range 0 to 2 := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
tbo_2p : in tracebuf_2p_out_type;
tbi_2p : out tracebuf_2p_in_type;
sclk : in std_ulogic
);
attribute sync_set_reset of rstn : signal is "true";
end;
architecture rtl of iu3 is
function get_tbuf(tracebuf_2p: boolean; tbuf: integer) return integer is
begin
if (TRACEBUF_2P) then
return(tbuf-64);
else
return(tbuf);
end if;
end function get_tbuf;
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TRACEBUF_2P : boolean := (tbuf > 64);
constant TBUFBITS : integer := 10 + log2(get_tbuf(TRACEBUF_2P, tbuf)) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := (pwd /= 0); --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
constant DYNRST : boolean := (rstaddr = 16#FFFFF#);
constant CASAEN : boolean := (notag = 0) and (lddel = 1);
signal BPRED : std_logic;
signal BLOCKBPMISS: std_logic;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock, dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
divrdy: std_ulogic;
pcheld: std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
bp, nobp : std_ulogic;
bpimiss : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
bp : std_ulogic;
rfe1, rfe2 : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
casa : std_ulogic;
casaz : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
ipmask : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
tfilt : std_logic_vector(3 downto 0); -- trace filter
cfc : std_logic_vector(6 downto 0); -- control-flow change
tlim : std_logic_vector(2 downto 0);
tov : std_ulogic;
tovb : std_ulogic;
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
dbp : std_ulogic; -- disable branch prediction
dbprepl: std_ulogic; -- Disable speculative Icache miss/replacement
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
function dbgexc(
r : registers; dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector(7 downto 0);
dsur : dsu_registers) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
tfilt : out std_logic_vector(3 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0'; tfilt := dsur.tfilt;
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1' and dbg.daddr(2) = '0' ) and TRACEBUF then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
tfilt := dbg.ddata(31 downto 28);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
if bp = 2 then s.dbp := dbg.ddata(27); end if;
if bp = 2 then s.dbprepl := dbg.ddata(25); end if;
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if bp = 2 then asr17(27) := r.w.s.dbp; end if;
if notag = 0 then asr17(26) := '1'; end if; -- CASA and tagged arith
if bp = 2 then asr17(25) := r.w.s.dbprepl; end if;
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
tbufo_2p : in tracebuf_2p_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if TRACEBUF then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if dbgi.daddr(2) = '0' then
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
data(31 downto 28) := dsur.tfilt;
else
data(23) := dsur.tov;
data(26 downto 24) := dsur.tlim;
data(27) := dsur.tovb;
end if;
else
if TRACEBUF_2P then
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo_2p.data(127 downto 96);
when "01" => data := tbufo_2p.data(95 downto 64);
when "10" => data := tbufo_2p.data(63 downto 32);
when others => data := tbufo_2p.data(31 downto 0);
end case;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
if dbgi.daddr(11) = '0' then
data := rfo.data1(31 downto 0);
else data := rfo.data2(31 downto 0); end if;
else
data := fpo.dbg.data;
end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
function itfilt (inst : word; filter : std_logic_vector(3 downto 0); trap, cfc : std_logic) return std_ulogic is
variable tren : std_ulogic;
begin
tren := '0';
case filter is
when "0001" => -- Bicc, SETHI
if inst(31 downto 30) = "00" then tren := '1'; end if;
when "0010" => -- Control-flow change
if (inst(31 downto 30) = "01") -- Call
or ((inst(31 downto 30) = "00") and (inst(23 downto 22) /= "00")) --Bicc
or ((inst(31 downto 30) = "10") and (inst(24 downto 19) = JMPL)) --Jmpl
or ((inst(31 downto 30) = "10") and (inst(24 downto 19) = RETT)) --Rett
or (trap = '1') or (cfc = '1')
then tren := '1'; end if;
when "0100" => -- Call
if inst(31 downto 30) = "01" then tren := '1'; end if;
when "1000" => -- Normal instructions
if inst(31 downto 30) = "10" then tren := '1'; end if;
when "1100" => -- LDST
if inst(31 downto 30) = "11" then tren := '1'; end if;
when "1101" => -- LDST from alternate space
if inst(31 downto 30) = "11" and inst(24 downto 23) = "01" then tren := '1'; end if;
when "1110" => -- LDST from alternate space 0x80 - 0xFF
if inst(31 downto 30) = "11" and inst(24 downto 23) = "01" and inst(12) = '1' then tren := '1'; end if;
when others => tren := '1';
end case;
return(tren);
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
ov : out std_ulogic;
di : out tracebuf_in_type;
di_2p : out tracebuf_2p_in_type;
ierr : in std_ulogic;
derr : in std_ulogic
) is
variable meminst : std_ulogic;
variable tfen : std_ulogic;
variable vdi_2p : tracebuf_2p_in_type;
variable vdi : tracebuf_in_type;
variable indata : std_logic_vector(255 downto 0);
variable write : std_logic_vector(7 downto 0);
variable tov : std_ulogic;
begin
vdi_2p := tracebuf_2p_in_type_none;
vdi := tracebuf_in_type_none;
indata := (others => '0');
write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
tov := vdsu.tov;
if TRACEBUF then
if dbgi.tenable = '1' then
if dsur.tbufcnt(TBUFBITS-1 downto TBUFBITS-3) = dsur.tlim(2 downto 0) then
tov := '1';
end if;
end if;
indata(127) := tov;
indata(126) := not r.x.ctrl.pv;
indata(125 downto 96) := dbgi.timer(29 downto 0);
indata(95 downto 64) := res;
indata(63 downto 34) := r.x.ctrl.pc(31 downto 2);
indata(33) := trap;
indata(32) := error;
indata(31 downto 0) := r.x.ctrl.inst;
vdi.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
vdi.data := indata;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
vdi.enable := '1';
vdi.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
vdi_2p.renable := '1';
vdi_2p.raddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => write(3) := '1';
when "01" => write(2) := '1';
when "10" => write(1) := '1';
when others => write(0) := '1';
end case;
indata(127 downto 0) := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
vdi.write := write;
vdi.data := indata;
vdi_2p.renable := '0';
vdi_2p.write := write;
vdi_2p.waddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
vdi_2p.data := indata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug and
itfilt(r.x.ctrl.inst, dsur.tfilt, trap, dsur.cfc(4))) = '1' then
vdi.enable := holdn;
vdi.write := (others => '1');
vdi_2p.write := (others => '1');
vdi_2p.waddr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
vdi_2p.data := indata;
tbufcnt := dsur.tbufcnt + 1;
end if;
if TRACEBUF_2P and ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
vdi_2p.renable := '1';
vdi_2p.raddr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
end if;
end if;
ov := tov;
di := vdi;
di_2p := vdi_2p;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if (r.x.rstate = dsu2)
then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant dc_in_res : dc_in_type := (
signed => '0',
enaddr => '0',
read => '0',
write => '0',
lock => '0',
dsuen => '0',
size => (others => '0'),
asi => (others => '0'));
constant pipeline_ctrl_res : pipeline_ctrl_type := (
pc => (others => '0'),
inst => (others => '0'),
cnt => (others => '0'),
rd => (others => '0'),
tt => (others => '0'),
trap => '0',
annul => '1',
wreg => '0',
wicc => '0',
wy => '0',
ld => '0',
pv => '0',
rett => '0');
constant fpc_res : pctype := conv_std_logic_vector(rstaddr, 20) & zero32(11 downto PCLOW);
constant fetch_reg_res : fetch_reg_type := (
pc => fpc_res, -- Needs special handling
branch => '0'
);
constant decode_reg_res : decode_reg_type := (
pc => (others => '0'),
inst => (others => (others => '0')),
cwp => (others => '0'),
set => (others => '0'),
mexc => '0',
cnt => (others => '0'),
pv => '0',
annul => '1',
inull => '0',
step => '0',
divrdy => '0',
pcheld => '0'
);
constant regacc_reg_res : regacc_reg_type := (
ctrl => pipeline_ctrl_res,
rs1 => (others => '0'),
rfa1 => (others => '0'),
rfa2 => (others => '0'),
rsel1 => (others => '0'),
rsel2 => (others => '0'),
rfe1 => '0',
rfe2 => '0',
cwp => (others => '0'),
imm => (others => '0'),
ldcheck1 => '0',
ldcheck2 => '0',
ldchkra => '1',
ldchkex => '1',
su => '1',
et => '0',
wovf => '0',
wunf => '0',
ticc => '0',
jmpl => '0',
step => '0',
mulstart => '0',
divstart => '0',
bp => '0',
nobp => '0',
bpimiss => '0'
);
constant execute_reg_res : execute_reg_type := (
ctrl => pipeline_ctrl_res,
op1 => (others => '0'),
op2 => (others => '0'),
aluop => (others => '0'),
alusel => "11",
aluadd => '1',
alucin => '0',
ldbp1 => '0',
ldbp2 => '0',
invop2 => '0',
shcnt => (others => '0'),
sari => '0',
shleft => '0',
ymsb => '0',
rd => (others => '0'),
jmpl => '0',
su => '0',
et => '0',
cwp => (others => '0'),
icc => (others => '0'),
mulstep => '0',
mul => '0',
mac => '0',
bp => '0',
rfe1 => '0',
rfe2 => '0'
);
constant memory_reg_res : memory_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
nalign => '0',
dci => dc_in_res,
werr => '0',
wcwp => '0',
irqen => '0',
irqen2 => '0',
mac => '0',
divz => '0',
su => '0',
mul => '0',
casa => '0',
casaz => '0'
);
function xnpc_res return std_logic_vector is
begin
if v8 /= 0 then return "100"; end if;
return "011";
end function xnpc_res;
constant exception_reg_res : exception_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
annul_all => '1',
data => (others => (others => '0')),
set => (others => '0'),
mexc => '0',
dci => dc_in_res,
laddr => (others => '0'),
rstate => run, -- Has special handling
npc => xnpc_res,
intack => '0',
ipend => '0',
mac => '0',
debug => '0', -- Has special handling
nerror => '0',
ipmask => '0'
);
constant DRES : dsu_registers := (
tt => (others => '0'),
err => '0',
tbufcnt => (others => '0'),
asi => (others => '0'),
crdy => (others => '0'),
tfilt => (others => '0'),
cfc => (others => '0'),
tlim => (others => '0'),
tov => '0',
tovb => '0'
);
constant IRES : irestart_register := (
addr => (others => '0'), pwd => '0'
);
constant PRES : pwd_register_type := (
pwd => '0', -- Needs special handling
error => '0'
);
--constant special_register_res : special_register_type := (
-- cwp => zero32(NWINLOG2-1 downto 0),
-- icc => (others => '0'),
-- tt => (others => '0'),
-- tba => fpc_res(31 downto 12),
-- wim => (others => '0'),
-- pil => (others => '0'),
-- ec => '0',
-- ef => '0',
-- ps => '1',
-- s => '1',
-- et => '0',
-- y => (others => '0'),
-- asr18 => (others => '0'),
-- svt => '0',
-- dwt => '0',
-- dbp => '0'
-- );
--XST workaround:
function special_register_res return special_register_type is
variable s : special_register_type;
begin
s.cwp := zero32(NWINLOG2-1 downto 0);
s.icc := (others => '0');
s.tt := (others => '0');
s.tba := fpc_res(31 downto 12);
s.wim := (others => '0');
s.pil := (others => '0');
s.ec := '0';
s.ef := '0';
s.ps := '1';
s.s := '1';
s.et := '0';
s.y := (others => '0');
s.asr18 := (others => '0');
s.svt := '0';
s.dwt := '0';
s.dbp := '0';
s.dbprepl := '1';
return s;
end function special_register_res;
--constant write_reg_res : write_reg_type := (
-- s => special_register_res,
-- result => (others => '0'),
-- wa => (others => '0'),
-- wreg => '0',
-- except => '0'
-- );
-- XST workaround:
function write_reg_res return write_reg_type is
variable w : write_reg_type;
begin
w.s := special_register_res;
w.result := (others => '0');
w.wa := (others => '0');
w.wreg := '0';
w.except := '0';
return w;
end function write_reg_res;
constant RRES : registers := (
f => fetch_reg_res,
d => decode_reg_res,
a => regacc_reg_res,
e => execute_reg_res,
m => memory_reg_res,
x => exception_reg_res,
w => write_reg_res
);
constant exception_res : exception_type := (
pri => '0',
ill => '0',
fpdis => '0',
cpdis => '0',
wovf => '0',
wunf => '0',
ticc => '0'
);
constant wpr_none : watchpoint_register := (
addr => zero32(31 downto 2),
mask => zero32(31 downto 2),
exec => '0',
load => '0',
store => '0');
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type;
dsur : dsu_registers)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((((debug.dbreak and debug.bwatch) or r.a.step)) or
(debug.bwatch and dsur.tovb and dsur.tov)));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY =>
if rd(4) = '1' and rd(3 downto 0) /= "0010" then -- %ASR16-17, %ASR19-31
privileged_inst := not r.a.su;
end if;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0);
if (npasi = 0) or (inst(12) = '0') then
privileged_inst := not r.a.su;
end if;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13);
if (npasi = 0) or (inst(12) = '0') then
privileged_inst := not r.a.su;
end if;
when CASA =>
if CASAEN then
illegal_inst := inst(13);
if (inst(12 downto 5) /= X"0A") then privileged_inst := not r.a.su; end if;
else illegal_inst := '1'; end if;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi, dsur);
trap := '1';
if r.a.ctrl.trap = '1' then tt := r.a.ctrl.tt;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
function icc_valid(r : registers) return std_logic is
variable not_valid : std_logic;
begin
not_valid := '0';
if MULEN or DIVEN then
not_valid := r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul);
end if;
not_valid := not_valid or (r.a.ctrl.wicc or r.e.ctrl.wicc);
return(not not_valid);
end;
procedure bp_miss_ex(r : registers; icc : std_logic_vector(3 downto 0);
ex_bpmiss, ra_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
ra_bpannul := miss and r.e.ctrl.inst(29);
ex_bpmiss := miss;
end;
procedure bp_miss_ra(r : registers; ra_bpmiss, de_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := ((not r.a.ctrl.annul) and r.a.bp and icc_valid(r) and not branch_true(r.m.icc, r.a.ctrl.inst));
de_bpannul := miss and r.a.ctrl.inst(29);
ra_bpmiss := miss;
end;
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn, de_wcwp : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex, bp, nobp, de_fins_hold : out std_ulogic;
iperr : std_logic; icbpmiss: std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_logic;
variable icc_check_bp, y_hold, mul_hold, bicc_hold_bp, fins, call_hold : std_ulogic;
variable de_fins_holdx : std_ulogic;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0'; y_hold := '0'; bp := '0'; mul_hold := '0';
icc_check_bp := '0'; nobp := '0'; fins := '0'; call_hold := '0';
if (r.d.annul = '0') and (icbpmiss='0')
then
case op is
when CALL =>
call_hold := '1'; nobp := BPRED;
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check_bp := '1';
end if;
if (op2 = BICC) then nobp := BPRED; end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
nobp := BPRED;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; nobp := op3(4); end if; -- no BP on divcc
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0'; fins := BPRED;
when JMPL => call_hold := '1'; nobp := BPRED;
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') and (op3(5) = '0') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" =>
ldcheck2 := not i;
if (op3(5) and op3(2) and not op3(3)) = '1' then ldcheck1 := '0'; ldcheck2 := '0'; end if; -- STF/STC
when others => ldchkex := '0';
if CASAEN and (op3(5 downto 3) = "111") then
ldcheck2 := '1';
elsif (op3(5) = '1') or ((op3(5) & op3(3 downto 1)) = "0110") -- LDST
then ldcheck1 := '0'; ldcheck2 := '0'; end if;
end case;
if op3(5) = '1' then fins := BPRED; end if; -- no BP on FPU/CP LD/ST
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
mul_hold := (r.a.mulstart and r.a.ctrl.wicc) or (r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
if (MULTYPE = 0) and ((icc_check_bp and BPRED and r.a.ctrl.wicc and r.a.ctrl.wy) = '1')
then mul_hold := '1'; end if;
else chkmul := '0'; end if;
if DIVEN then
y_hold := y_check and (r.a.ctrl.wy or r.e.ctrl.wy);
chkmul := chkmul or divinsn;
end if;
bicc_hold := icc_check and not icc_valid(r);
bicc_hold_bp := icc_check_bp and not icc_valid(r);
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
de_fins_holdx := BPRED and fins and (r.a.bp or r.e.bp); -- skip BP on FPU inst in branch target address
de_fins_hold := de_fins_holdx;
ldlock := ldlock or y_hold or fpc_lock or (BPRED and r.a.bp and r.a.ctrl.inst(29) and de_wcwp) or de_fins_holdx;
if ((icc_check_bp and BPRED) = '1') and ((r.a.nobp or mul_hold) = '0') then
bp := bicc_hold_bp;
else ldlock := ldlock or bicc_hold or bicc_hold_bp; end if;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic; rabpmiss, exbpmiss, iperr : std_logic;
icbpmiss, eocl: std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl, inhibit_current : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0'; inhibit_current := '0';
if (r.d.annul = '0') and not (icbpmiss = '1' and r.d.pcheld='0')
then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true or (BPRED and orv(cond) and not icc_valid(r)); end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul_next or annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
hold_pc := '1'; pv := '0';
if r.d.divrdy = '0' then
cnt := "01"; divstart := '1';
end if;
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
if (BLOCKBPMISS and (eocl or r.f.branch) and r.e.bp)='1' then
hold_pc := '1'; annul_current := '1';
end if;
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD/CASA
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
(CASAEN and (op3(5 downto 4) = "11")) or -- CASA
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if icbpmiss='1' and r.d.annul='0' then
annul_current := '1'; annul_next := '1'; pv := '0'; hold_pc := '0';
end if;
if ((exbpmiss and r.a.ctrl.annul and r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and not r.a.ctrl.annul and r.d.pv) = '1') then
annul_next := '1'; pv := '0'; annul_current := '1';
end if;
if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and r.e.ctrl.inst(29) and not r.a.ctrl.annul and not r.d.pv ) = '1')
and (r.d.cnt = "01") then
annul_next := '1'; annul_current := '1'; pv := '0';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and r.a.ctrl.annul and r.d.pv) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and BLOCKBPMISS and r.a.bpimiss) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and not r.a.ctrl.inst(29) and not r.d.annul and r.d.pv and not hold_pc) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and r.a.ctrl.inst(29) and not r.d.annul and r.d.pv ) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or (ldlock and not inhibit_current) or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current or inhibit_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current and not inhibit_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_logic
) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0, i : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
rs1 := r.a.ctrl.inst(18 downto 14); i := r.a.ctrl.inst(13);
rs2 := r.a.ctrl.inst(4 downto 0); rd := r.a.ctrl.inst(29 downto 25);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(5) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB
end if;
if CASAEN and (r.m.casa = '1') then
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word; id : std_logic) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
if CASAEN and (r.a.ctrl.cnt = "10") and ((r.m.casa and not id) = '1') then ldbp := '1'; end if;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif (r.m.ctrl.wreg = '1') and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and (r.x.ctrl.wreg = '1') and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when LDST =>
if CASAEN and (r.m.casa = '1') and (r.a.ctrl.cnt = "10") then
cin := '1';
end if;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
function st_align(size : std_logic_vector(1 downto 0); bpdata : word) return word is
variable edata : word;
begin
case size is
when "01" => edata := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
when "10" => edata := bpdata(15 downto 0) & bpdata(15 downto 0);
when others => edata := bpdata;
end case;
return(edata);
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz, mzero : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
variable azero : std_logic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
if addout(32 downto 1) = zero32 then azero := '1'; else azero := '0'; end if;
mzero := azero;
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
-- if aluresult = zero32 then icc(2) := '1'; end if;
icc(2) := azero;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load, mcasa : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su, lock : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
mcasa := '0';
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when CASA => if CASAEN then dci.size := SZWORD; dci.lock := '1'; end if;
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul or r.e.ctrl.trap) = '0' then
case op is
when CALL => link_pc := '1';
when FMT3 =>
if r.e.ctrl.trap = '0' then
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
end if;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP/CASA
load := op3(3) or not op3(2);
--dci.enaddr := '1';
dci.enaddr := (not op3(2)) or op3(2)
or (op3(3) and op3(2));
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) or -- CASA
(op3(3 downto 2) = "11") then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP/CASA
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) then mcasa := '1'; end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
if r.e.ctrl.inst(12 downto 10) /= "000" then dci.enaddr := '0'; end if;
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
if CASAEN and (r.m.casa = '1') and (r.e.ctrl.cnt = "10") then
edata2 := r.e.op1; eres2 := r.e.op1;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if (trap = '1') and (r.m.ctrl.pv = '1') then
if op = LDST then nullify := '1'; end if;
end if;
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA | CASA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd
;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
if bp = 2 then s.dbp := r.x.result(27); end if;
if bp = 2 then s.dbprepl := r.x.result(25); end if;
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
if pwrpsr = 0 or rd = "00000" then
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
end if;
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
BPRED <= '0' when bp = 0 else '1' when bp = 1 else not r.w.s.dbp;
BLOCKBPMISS <= '0' when bp = 0 else '1' when bp = 1 else r.w.s.dbprepl;
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, tbo_2p,
mulo, divo, dummy, rp, BPRED, BLOCKBPMISS)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable fe_pc, fe_npc : std_logic_vector(31 downto PCLOW);
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable de_bpannul : std_ulogic;
variable de_fins_hold : std_ulogic;
variable de_iperr : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ra_bpmiss : std_ulogic;
variable ra_bpannul : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, ex_result3, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable ex_bpmiss : std_ulogic;
variable ex_cdata : std_logic_vector(31 downto 0);
variable ex_mulop1, ex_mulop2 : std_logic_vector(32 downto 0);
variable me_bp_res : word;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_newtt, xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable tbufi_2p : tracebuf_2p_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable xc_dflushl : std_ulogic;
variable xc_dcperr : std_ulogic;
variable st : std_ulogic;
variable icnt, fcnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
variable tovx : std_ulogic;
variable bpmiss : std_ulogic;
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0'; fcnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error; xc_dflushl := '0';
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 2) := r.w.s.tba & xc_vectt & "00";
else
xc_trap_address(31 downto 2) := r.w.s.tba & "00000000" & "00";
end if;
xc_trap_address(2 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (not r.x.ctrl.annul and r.x.ctrl.ld) = '1' then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
elsif MACEN and MACPIPE and ((not r.x.ctrl.annul and r.x.mac) = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT
then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt, dsur);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (dbgm
) /= '0' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
if (r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
if (r.x.ctrl.inst(31 downto 30) = FMT3) and
((r.x.ctrl.inst(24 downto 19) = FPOP1) or
(r.x.ctrl.inst(24 downto 19) = FPOP2))
then fcnt := holdn; end if;
end if;
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if r.w.s.et = '1' then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, vdsu.tfilt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
if DBGUNIT and TRACEBUF then
if (dbgi.dsuen and dbgi.denable and dbgi.dwrite) = '1' then
if (dbgi.daddr(23 downto 20) = "0001" and dbgi.daddr(16) = '1' and
dbgi.daddr(2) = '1') then
vdsu.tov := dbgi.ddata(23);
vdsu.tlim := dbgi.ddata(26 downto 24);
vdsu.tovb := dbgi.ddata(27);
end if;
end if;
end if;
dci.flushl <= xc_dflushl;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tovx, tbufi, tbufi_2p, '0', xc_dcperr);
vdsu.tbufcnt := tbufcntx; vdsu.tov := tovx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
irqo.idle <= '0';
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dbgo.fcnt <= fcnt;
dbgo.optype <= r.x.ctrl.inst(31 downto 30) & r.x.ctrl.inst(24 downto 21);
dci.intack <= r.x.intack and holdn;
if (not RESET_ALL) and (xc_rstn = '0') then
v.w.except := RRES.w.except; v.w.s.et := RRES.w.s.et;
v.w.s.svt := RRES.w.s.svt; v.w.s.dwt := RRES.w.s.dwt;
v.w.s.ef := RRES.w.s.ef;
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := RRES.w.s.cwp;
v.w.s.icc := RRES.w.s.icc;
end if;
v.w.s.dbp := RRES.w.s.dbp;
v.w.s.dbprepl := RRES.w.s.dbprepl;
v.x.ipmask := RRES.x.ipmask;
v.w.s.tba := RRES.w.s.tba;
v.x.annul_all := RRES.x.annul_all;
v.x.rstate := RRES.x.rstate; vir.pwd := IRES.pwd;
vp.pwd := PRES.pwd; v.x.debug := RRES.x.debug;
v.x.nerror := RRES.x.nerror;
if svt = 1 then v.w.s.tt := RRES.w.s.tt; end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
vdsu.tfilt := DRES.tfilt; vdsu.tovb := DRES.tovb;
end if;
if (index /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
v.x.npc := "100";
end if;
-- kill off unused regs
if not FPEN then v.w.s.ef := '0'; end if;
if not CPEN then v.w.s.ec := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
st := '0';
if CASAEN and (r.m.casa = '1') and (r.m.ctrl.cnt = "00") then
v.x.ctrl.inst(4 downto 0) := r.a.ctrl.inst(4 downto 0); -- restore rs2 for trace log
end if;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or st or not dco.mds) = '1' then
for i in 0 to dsets-1 loop
v.x.data(i) := dco.data(i);
end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if (lddel /= 2) then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
if (not RESET_ALL) and (is_fpga(fabtech) = 0) and (xc_rstn = '0') then
v.x.data := (others => (others => '0')); --v.x.ldc := '0';
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2)
then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
if (not RESET_ALL) and (xc_rstn = '0') then
v.x.ctrl.trap := '0'; v.x.ctrl.annul := '1';
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.lock <= (r.m.dci.lock and not r.m.ctrl.annul);
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz, v.m.casaz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, ex_result3);
v.m.result := ex_result3;
cwp_ex(r, v.m.wcwp);
if CASAEN and (r.e.ctrl.cnt = "10") and ((r.m.casa and not v.m.casaz) = '1') then
me_nullify2 := '1';
end if;
dci.nullify <= me_nullify2;
ex_mulop1 := (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
ex_mulop2 := (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
if is_fpga(fabtech) = 0 and (r.e.mul = '0') then -- power-save for mul
-- if (r.e.mul = '0') then
ex_mulop1 := (others => '0'); ex_mulop2 := (others => '0');
end if;
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
bp_miss_ex(r, r.m.icc, ex_bpmiss, ra_bpannul);
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl and not r.a.ctrl.trap;
v.e.ctrl.annul := r.a.ctrl.annul or ra_bpannul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul and not r.a.ctrl.trap;
v.e.ctrl.wreg := r.a.ctrl.wreg and not (ra_bpannul or v.x.annul_all);
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not (ra_bpannul or v.x.annul_all);
v.e.rfe1 := r.a.rfe1; v.e.rfe2 := r.a.rfe2;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, ex_result3, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1, '0');
op_mux(r, rfo.data2, ex_result3, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2, '1');
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2
);
cin_gen(r, v.m.icc(0), v.e.alucin);
bp_miss_ra(r, ra_bpmiss, de_bpannul);
v.e.bp := r.a.bp and not ra_bpmiss;
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
if CASAEN and (de_inst(31 downto 30) = LDST) and (de_inst(24 downto 19) = CASA) then
case r.d.cnt is
when "00" | "01" => de_inst(4 downto 0) := "00000"; -- rs2=0
when others =>
end case;
end if;
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0'); de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
de_iperr := '0';
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, de_wcwp, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex, v.a.bp, v.a.nobp, de_fins_hold, de_iperr, ico.bpmiss);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart,
ra_bpmiss, ex_bpmiss, de_iperr, ico.bpmiss, ico.eocl);
v.d.pcheld := de_hold_pc;
v.a.bp := v.a.bp and not v.a.ctrl.annul;
v.a.nobp := v.a.nobp and not v.a.ctrl.annul;
v.a.ctrl.inst := de_inst;
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
v.a.ctrl.wicc := v.a.ctrl.wicc and (not v.a.ctrl.annul)
;
v.a.ctrl.wreg := v.a.ctrl.wreg and (not v.a.ctrl.annul)
;
v.a.ctrl.rett := v.a.ctrl.rett and (not v.a.ctrl.annul)
;
v.a.ctrl.wy := v.a.ctrl.wy and (not v.a.ctrl.annul)
;
v.a.ctrl.trap := r.d.mexc
;
v.a.ctrl.tt := "000000";
if r.d.mexc = '1' then
v.a.ctrl.tt := "000001";
end if;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if (dbgi.denable = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2); de_ren1 := '1';
de_raddr2 := de_raddr1; de_ren2 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.wren <= (xc_wreg and holdn);
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1;
rfi.ren2 <= de_ren2;
ici.inull <= de_inull
;
ici.flush <= me_iflush;
v.d.divrdy := divo.nready;
ici.fline <= r.x.ctrl.pc(31 downto 3);
ici.nobpmiss <= (r.a.bp or r.e.bp) and BLOCKBPMISS;
dbgo.bpmiss <= bpmiss and holdn;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := (others => '0');
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
bpmiss := ex_bpmiss or ra_bpmiss;
npc := r.f.pc; fe_pc := r.f.pc;
if ra_bpmiss = '1' then fe_pc := r.d.pc; end if;
if ex_bpmiss = '1' then fe_pc := r.a.ctrl.pc; end if;
fe_npc := zero32(31 downto PCLOW);
fe_npc(31 downto 2) := fe_pc(31 downto 2) + 1; -- Address incrementer
v.a.bpimiss := '0';
if (xc_rstn = '0') then
if (not RESET_ALL) then
v.f.pc := (others => '0'); v.f.branch := '0';
if DYNRST then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if bpmiss = '1' then
v.f.pc := fe_npc; v.f.branch := '1';
npc := v.f.pc;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif (ex_jump and not bpmiss) = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif (((ico.bpmiss and not r.d.annul) or r.a.bpimiss) and not bpmiss) = '1' then
v.f.pc := r.d.pc; v.f.branch := '1';
npc := v.f.pc;
v.a.bpimiss := ico.bpmiss and not r.d.annul;
elsif (de_branch and not bpmiss
) = '1'
then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := bpmiss; v.f.pc := fe_npc; npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, tbo_2p, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
vdsu.cfc := dsur.cfc(5 downto 0) & r.f.branch;
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= ex_mulop1; --(ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= ex_mulop2; --(mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then
tbi <= tbufi;
if TRACEBUF_2P then tbi_2p <= tbufi_2p; else tbi_2p <= tracebuf_2p_in_type_none; end if;
else
tbi <= tracebuf_in_type_none;
tbi_2p <= tracebuf_2p_in_type_none;
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0'; tbi.addr <= (others => '0');
tbi.data <= (others => '0'); tbi.enable <= '0';
tbi.write <= (others => '0');
end if;
dbgo.error <= dummy and not r.x.nerror;
dbgo.istat <= ico.cstat;
dbgo.dstat <= dco.cstat;
dbgo.wbhold <= dco.wbhold;
dbgo.su <= r.w.s.s;
if FPEN then
if (r.x.rstate = dsu2) then vfpi.flush := '1'; else vfpi.flush := v.x.annul_all and holdn; end if;
vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or de_bpannul or r.d.annul or de_fins_hold or (ico.bpmiss and not r.d.pcheld)
;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul or (ex_bpmiss and r.e.ctrl.inst(29))
;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv;
if (lddel = 2) then vfpi.lddata := r.x.data(conv_integer(r.x.set)); else vfpi.lddata := r.x.data(0); end if;
if (r.x.rstate = dsu2)
then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
end if;
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= PRES.error;
if RESET_ALL then
if (index /= 0) and (irqi.run = '0') then
rp.pwd <= '1';
else
rp.pwd <= '0';
end if;
end if;
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
if RESET_ALL then
r <= RRES;
if DYNRST then
r.f.pc(31 downto 12) <= irqi.rstvec;
r.w.s.tba <= irqi.rstvec;
end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
r.x.rstate <= dsu1; r.x.debug <= '1';
end if;
end if;
if (index /= 0) and irqi.run = '0' then
r.x.rstate <= dsu1;
end if;
else
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if rstn = '0' then
if RESET_ALL then
dsur <= DRES;
elsif need_extra_sync_reset(fabtech) /= 0 then
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end if;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
dsur.tfilt <= (others => '0'); dsur.cfc <= (others => '0');
dsur.tlim <= (others => '0'); dsur.tov <= '0'; dsur.tovb <= '0';
end generate;
irreg : if DBGUNIT or PWRD2
generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
if RESET_ALL and rstn = '0' then ir <= IRES; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2
)
generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then wpr(i) <= wprin(i); end if;
if rstn = '0' then
if RESET_ALL then
wpr(i) <= wpr_none;
else
wpr(i).exec <= '0'; wpr(i).load <= '0'; wpr(i).store <= '0';
end if;
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and (not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1',
rin.x.ipmask = '1');
end if;
end process;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
|
--------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO
-- Version : 1.2
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
-- The top level wrapper consists of individual FIFOs on the
-- transmitter path and on the receiver path.
--
-- Each path consists of an 8 bit local link to 8 bit client
-- interface FIFO.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo;
architecture RTL of tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
component tri_mode_ethernet_mac_0_rx_client_fifo
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_tx_client_fifo
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end component;
begin
------------------------------------------------------------------------------
-- Instantiate the Transmitter FIFO
------------------------------------------------------------------------------
tx_fifo_i : tri_mode_ethernet_mac_0_tx_client_fifo
generic map(
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY
)
port map(
tx_fifo_aclk => tx_fifo_aclk,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
fifo_overflow => tx_fifo_overflow,
fifo_status => tx_fifo_status,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit
);
------------------------------------------------------------------------------
-- Instantiate the Receiver FIFO
------------------------------------------------------------------------------
rx_fifo_i : tri_mode_ethernet_mac_0_rx_client_fifo
port map(
rx_fifo_aclk => rx_fifo_aclk,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
fifo_status => rx_fifo_status,
fifo_overflow => rx_fifo_overflow
);
end RTL;
|
--------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO
-- Version : 1.2
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
-- The top level wrapper consists of individual FIFOs on the
-- transmitter path and on the receiver path.
--
-- Each path consists of an 8 bit local link to 8 bit client
-- interface FIFO.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo;
architecture RTL of tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
component tri_mode_ethernet_mac_0_rx_client_fifo
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_tx_client_fifo
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end component;
begin
------------------------------------------------------------------------------
-- Instantiate the Transmitter FIFO
------------------------------------------------------------------------------
tx_fifo_i : tri_mode_ethernet_mac_0_tx_client_fifo
generic map(
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY
)
port map(
tx_fifo_aclk => tx_fifo_aclk,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
fifo_overflow => tx_fifo_overflow,
fifo_status => tx_fifo_status,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit
);
------------------------------------------------------------------------------
-- Instantiate the Receiver FIFO
------------------------------------------------------------------------------
rx_fifo_i : tri_mode_ethernet_mac_0_rx_client_fifo
port map(
rx_fifo_aclk => rx_fifo_aclk,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
fifo_status => rx_fifo_status,
fifo_overflow => rx_fifo_overflow
);
end RTL;
|
--------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO
-- Version : 1.2
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
-- The top level wrapper consists of individual FIFOs on the
-- transmitter path and on the receiver path.
--
-- Each path consists of an 8 bit local link to 8 bit client
-- interface FIFO.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo;
architecture RTL of tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
component tri_mode_ethernet_mac_0_rx_client_fifo
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_tx_client_fifo
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end component;
begin
------------------------------------------------------------------------------
-- Instantiate the Transmitter FIFO
------------------------------------------------------------------------------
tx_fifo_i : tri_mode_ethernet_mac_0_tx_client_fifo
generic map(
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY
)
port map(
tx_fifo_aclk => tx_fifo_aclk,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
fifo_overflow => tx_fifo_overflow,
fifo_status => tx_fifo_status,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit
);
------------------------------------------------------------------------------
-- Instantiate the Receiver FIFO
------------------------------------------------------------------------------
rx_fifo_i : tri_mode_ethernet_mac_0_rx_client_fifo
port map(
rx_fifo_aclk => rx_fifo_aclk,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
fifo_status => rx_fifo_status,
fifo_overflow => rx_fifo_overflow
);
end RTL;
|
--------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO
-- Version : 1.2
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
-- The top level wrapper consists of individual FIFOs on the
-- transmitter path and on the receiver path.
--
-- Each path consists of an 8 bit local link to 8 bit client
-- interface FIFO.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo;
architecture RTL of tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
component tri_mode_ethernet_mac_0_rx_client_fifo
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_tx_client_fifo
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end component;
begin
------------------------------------------------------------------------------
-- Instantiate the Transmitter FIFO
------------------------------------------------------------------------------
tx_fifo_i : tri_mode_ethernet_mac_0_tx_client_fifo
generic map(
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY
)
port map(
tx_fifo_aclk => tx_fifo_aclk,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
fifo_overflow => tx_fifo_overflow,
fifo_status => tx_fifo_status,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit
);
------------------------------------------------------------------------------
-- Instantiate the Receiver FIFO
------------------------------------------------------------------------------
rx_fifo_i : tri_mode_ethernet_mac_0_rx_client_fifo
port map(
rx_fifo_aclk => rx_fifo_aclk,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
fifo_status => rx_fifo_status,
fifo_overflow => rx_fifo_overflow
);
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT2D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT2D.VHD
-- Created : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCT_PKG.all;
entity DCT2D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao : in T_ROM2DATAO;
romodatao : in T_ROM2DATAO;
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM2ADDRO;
romoaddro : out T_ROM2ADDRO;
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end DCT2D;
architecture RTL of DCT2D is
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
signal databuf_reg : input_data2;
signal latchbuf_reg : input_data2;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rmemsel_reg : STD_LOGIC;
signal stage1_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal dataready_2_reg : STD_LOGIC;
signal even_not_odd : std_logic;
signal even_not_odd_d1 : std_logic;
signal even_not_odd_d2 : std_logic;
signal even_not_odd_d3 : std_logic;
signal even_not_odd_d4 : std_logic;
signal odv_d0 : std_logic;
signal odv_d1 : std_logic;
signal odv_d2 : std_logic;
signal odv_d3 : std_logic;
signal odv_d4 : std_logic;
signal odv_d5 : std_logic;
signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
signal romedatao_d1 : T_ROM2DATAO;
signal romodatao_d1 : T_ROM2DATAO;
signal romedatao_d2 : T_ROM2DATAO;
signal romodatao_d2 : T_ROM2DATAO;
signal romedatao_d3 : T_ROM2DATAO;
signal romodatao_d3 : T_ROM2DATAO;
signal romedatao_d4 : T_ROM2DATAO;
signal romodatao_d4 : T_ROM2DATAO;
signal odv_s : std_logic;
signal dcto_s : std_logic_vector(OP_W-1 downto 0);
component FinitePrecRndNrst is
generic
(
C_IN_SZ : natural := 37;
C_OUT_SZ : natural := 16;
C_FRAC_SZ : natural := 15
);
port (
CLK : in std_logic;
RST : in std_logic;
datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);
dataval : in std_logic;
dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);
clip_inc : out std_logic;
dval_out : out std_logic
);
end component;
begin
ramraddro_sg:
ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
rmemsel_sg:
rmemsel <= rmemsel_reg;
process(clk,rst)
begin
if rst = '1' then
stage2_cnt_reg <= (others => '1');
rmemsel_reg <= '0';
stage1_reg <= '0';
stage2_reg <= '0';
colram_reg <= (others => '0');
rowram_reg <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
odv_d0 <= '0';
colr_reg <= (others => '0');
rowr_reg <= (others => '0');
dataready_2_reg <= '0';
elsif clk='1' and clk'event then
stage2_reg <= '0';
odv_d0 <= '0';
datareadyack <= '0';
dataready_2_reg <= dataready;
----------------------------------
-- read DCT 1D to barrel shifer
----------------------------------
if stage1_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
colram_reg <= colram_reg + 1;
colr_reg <= colr_reg + 1;
if colram_reg = N-2 then
rowr_reg <= rowr_reg + 1;
end if;
if colram_reg = N-1 then
rowram_reg <= rowram_reg + 1;
if rowram_reg = N-1 then
stage1_reg <= '0';
colr_reg <= (others => '0');
-- release memory
rmemsel_reg <= not rmemsel_reg;
end if;
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
-- 8 point input latched
stage2_reg <= '1';
end if;
end if;
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- output data valid
odv_d0 <= '1';
-- increment column counter
col_reg <= col_reg + 1;
-- finished processing one input row
if col_reg = N - 1 then
row_reg <= row_reg + 1;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
end if;
--------------------------------
----------------------------------
-- wait for new data
----------------------------------
-- one of ram buffers has new data, process it
if dataready = '1' and dataready_2_reg = '0' then
stage1_reg <= '1';
-- to account for 1T RAM delay, increment RAM address counter
colram_reg <= (others => '0');
colr_reg <= (0=>'1',others => '0');
datareadyack <= '1';
end if;
----------------------------------
end if;
end process;
p_data_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
even_not_odd_d4 <= '0';
odv_d1 <= '0';
odv_d2 <= '0';
odv_d3 <= '0';
odv_d4 <= '0';
odv_d5 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
dcto_5 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
even_not_odd_d4 <= even_not_odd_d3;
odv_d1 <= odv_d0;
odv_d2 <= odv_d1;
odv_d3 <= odv_d2;
odv_d4 <= odv_d3;
odv_d5 <= odv_d4;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA2_W) +
(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
DA2_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA2_W) +
(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
DA2_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
DA2_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
DA2_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
DA2_W));
end if;
if even_not_odd_d4 = '0' then
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
else
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_4) +
(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
DA2_W));
end if;
end if;
end process;
dcto <= dcto_s;
odv <= odv_s;
U_FinitePrecRndNrst : FinitePrecRndNrst
generic map(
C_IN_SZ => DA2_W,
C_OUT_SZ => DA2_W-12,
C_FRAC_SZ => 12
)
port map(
CLK => clk,
RST => rst,
datain => dcto_5,
dataval => odv_d5,
dataout => dcto_s,
clip_inc => open,
dval_out => odv_s
);
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 10 loop
-- read precomputed MAC results from LUT
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_dly : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
romedatao_d4 <= (others => (others => '0'));
romodatao_d4 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
romedatao_d4 <= romedatao_d3;
romodatao_d4 <= romodatao_d3;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
entity univ2 is
end entity;
architecture foo of univ2 is
begin
assert False
report "Time'HIGH = " & Time'IMAGE(Time'VAL(Time'POS(Time'HIGH)))
severity NOTE;
assert False
report "should produce 9223372036854775807"
severity NOTE;
end architecture;
-- 'POS returns universal integer
-- 'VAL parameter is any integer type (including universal integer) |
entity univ2 is
end entity;
architecture foo of univ2 is
begin
assert False
report "Time'HIGH = " & Time'IMAGE(Time'VAL(Time'POS(Time'HIGH)))
severity NOTE;
assert False
report "should produce 9223372036854775807"
severity NOTE;
end architecture;
-- 'POS returns universal integer
-- 'VAL parameter is any integer type (including universal integer) |
entity univ2 is
end entity;
architecture foo of univ2 is
begin
assert False
report "Time'HIGH = " & Time'IMAGE(Time'VAL(Time'POS(Time'HIGH)))
severity NOTE;
assert False
report "should produce 9223372036854775807"
severity NOTE;
end architecture;
-- 'POS returns universal integer
-- 'VAL parameter is any integer type (including universal integer) |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of madd_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
prod_tmp1 : std_ulogic_vector(src1_bits+src2_bits+1 downto 0);
prod_tmp2 : std_ulogic_vector(src1_bits+src2_bits downto 0);
acc_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_msb_carryin : std_ulogic;
result_msb : std_ulogic;
carryout : std_ulogic;
end record;
signal c : comb_type;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.prod_tmp1 <= std_ulogic_vector(signed(c.src1_tmp) * signed(c.src2_tmp));
c.prod_tmp2 <= (('0' & c.prod_tmp1(src1_bits+src2_bits-2 downto 0) & '0') xor
(src1_bits+src2_bits downto 0 => sub));
c.acc_tmp <= '0' & acc(src1_bits+src2_bits-2 downto 0) & '1';
c.result_tmp <= std_ulogic_vector(signed(c.acc_tmp) +
signed(c.prod_tmp2));
c.result_msb_carryin <= c.result_tmp(src1_bits+src2_bits);
c.result_msb <= (acc(src1_bits+src2_bits-1) xor
c.prod_tmp1(src1_bits+src2_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor acc(src1_bits+src2_bits-1)) and (c.prod_tmp1(src1_bits+src2_bits-1) or c.result_msb_carryin)) or
(c.prod_tmp1(src1_bits+src2_bits-1) and c.result_msb_carryin));
overflow <= c.carryout xor (not unsgnd and c.result_msb_carryin);
result <= c.result_msb & c.result_tmp(src1_bits+src2_bits-1 downto 1);
end;
|
-- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------
-- clocked butterfly operation
----------------------
-- Description
-- This design unit `cbf` is for performing clocked butterfly operation on complex
-- fixed point numbers with configurable data width. The value of the inputs are
-- limited to (+1, -1]. MSB is sign bit and the rest bits are all decimal part.
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
entity cbf is
generic (
-- data width of the real and imaginary part
data_width : integer range 0 to 128 := 16
);
port (
-- clock
clk : in std_logic;
nrst : in std_logic;
-- x0, input 0
x0_re : in sfixed (0 downto 1 - data_width);
x0_im : in sfixed (0 downto 1 - data_width);
-- x1, input 1
x1_re : in sfixed (0 downto 1 - data_width);
x1_im : in sfixed (0 downto 1 - data_width);
-- wk, twiddle factor
wk_re : in sfixed (0 downto 1 - data_width);
wk_im : in sfixed (0 downto 1 - data_width);
-- y0, output 0
y0_re : out sfixed(0 downto 1 - data_width);
y0_im : out sfixed(0 downto 1 - data_width);
-- y1, output 1
y1_re : out sfixed(0 downto 1 - data_width);
y1_im : out sfixed(0 downto 1 - data_width)
);
end cbf;
-- Function Implementation 0
architecture FIMP_0 of cbf is
-- internal signals for x
signal x0_re_int : sfixed (0 downto 1 - data_width);
signal x0_im_int : sfixed (0 downto 1 - data_width);
signal x1_re_int : sfixed (0 downto 1 - data_width);
signal x1_im_int : sfixed (0 downto 1 - data_width);
-- internal signals for twiddle factor
signal wk_re_int : sfixed (0 downto 1 - data_width);
signal wk_im_int : sfixed (0 downto 1 - data_width);
-- combinatorial butterfly operation
component bf is
generic (
-- data width of the real and imaginary part
data_width : integer range 0 to 128 := 16
);
port (
-- x0, input 0
x0_re : in sfixed (0 downto 1 - data_width);
x0_im : in sfixed (0 downto 1 - data_width);
-- x1, input 1
x1_re : in sfixed (0 downto 1 - data_width);
x1_im : in sfixed (0 downto 1 - data_width);
-- wk, twiddle factor
wk_re : in sfixed (0 downto 1 - data_width);
wk_im : in sfixed (0 downto 1 - data_width);
-- y0, output 0
y0_re : out sfixed(0 downto 1 - data_width);
y0_im : out sfixed(0 downto 1 - data_width);
-- y1, output 1
y1_re : out sfixed(0 downto 1 - data_width);
y1_im : out sfixed(0 downto 1 - data_width)
);
end component;
begin
-- registered inputs
process(clk, nrst)
begin
if (nrst = '0') then
x0_re_int <= (others => '0');
x0_im_int <= (others => '0');
x1_re_int <= (others => '0');
x1_im_int <= (others => '0');
wk_re_int <= (others => '0');
wk_im_int <= (others => '0');
elsif (clk'event and clk = '1') then
x0_re_int <= x0_re;
x0_im_int <= x0_im;
x1_re_int <= x1_re;
x1_im_int <= x1_im;
wk_re_int <= wk_re;
wk_im_int <= wk_im;
end if;
end process;
-- connect the combinatorial butterfly operation
bf_0: bf
generic map (data_width)
port map (x0_re_int, x0_im_int, x1_re_int, x1_im_int,
wk_re_int, wk_im_int,
y0_re, y0_im, y1_re, y1_im);
end FIMP_0;
|
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