content stringlengths 1 1.04M ⌀ |
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:59:06 04/04/2011
-- Design Name:
-- Module Name: LocalRst - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LocalRst is
Generic ( RESET_PERIOD : natural := 4);
Port ( RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SRST_O : out STD_LOGIC);
end LocalRst;
architecture Behavioral of LocalRst is
signal RstQ : std_logic_vector(RESET_PERIOD downto 0) := (others => '1');
begin
RstQ(0) <= '0';
RESET_LINE: for i in 1 to RESET_PERIOD generate
process(CLK_I, RST_I)
begin
if (RST_I = '1') then
RstQ(i) <= '1';
elsif Rising_Edge(CLK_I) then
RstQ(i) <= RstQ(i-1);
end if;
end process;
end generate;
SRST_O <= RstQ(RESET_PERIOD);
end Behavioral;
|
architecture RTL of FIFO is
begin
process
begin
loop
end loop;
-- Violations below
loop
end loop;
end process;
end;
|
architecture RTL of FIFO is
begin
process
begin
loop
end loop;
-- Violations below
loop
end loop;
end process;
end;
|
-------------------------------------------------------------------------------
-- system_ac1_mb_bridge_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_plbv46_bridge_v1_04_a;
use plbv46_plbv46_bridge_v1_04_a.all;
entity system_ac1_mb_bridge_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 3);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 14);
Sl_MWrErr : out std_logic_vector(0 to 14);
Sl_MRdErr : out std_logic_vector(0 to 14);
Sl_MIRQ : out std_logic_vector(0 to 14);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_ac1_mb_bridge_wrapper : entity is "plbv46_plbv46_bridge_v1_04_a";
end system_ac1_mb_bridge_wrapper;
architecture STRUCTURE of system_ac1_mb_bridge_wrapper is
component plbv46_plbv46_bridge is
generic (
C_NUM_ADDR_RNG : INTEGER;
C_BRIDGE_BASEADDR : std_logic_vector;
C_BRIDGE_HIGHADDR : std_logic_vector;
C_RNG0_BASEADDR : std_logic_vector;
C_RNG0_HIGHADDR : std_logic_vector;
C_RNG1_BASEADDR : std_logic_vector;
C_RNG1_HIGHADDR : std_logic_vector;
C_RNG2_BASEADDR : std_logic_vector;
C_RNG2_HIGHADDR : std_logic_vector;
C_RNG3_BASEADDR : std_logic_vector;
C_RNG3_HIGHADDR : std_logic_vector;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_SPLB_BIGGEST_MASTER : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_SMALLEST_SLAVE : INTEGER;
C_BUS_CLOCK_RATIO : INTEGER;
C_PREFETCH_TIMEOUT : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end component;
begin
ac1_mb_bridge : plbv46_plbv46_bridge
generic map (
C_NUM_ADDR_RNG => 1,
C_BRIDGE_BASEADDR => X"00000000",
C_BRIDGE_HIGHADDR => X"FFFFFFFF",
C_RNG0_BASEADDR => X"00000000",
C_RNG0_HIGHADDR => X"FFFFFFFF",
C_RNG1_BASEADDR => X"ffffffff",
C_RNG1_HIGHADDR => X"00000000",
C_RNG2_BASEADDR => X"ffffffff",
C_RNG2_HIGHADDR => X"00000000",
C_RNG3_BASEADDR => X"ffffffff",
C_RNG3_HIGHADDR => X"00000000",
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 4,
C_SPLB_NUM_MASTERS => 15,
C_SPLB_SMALLEST_MASTER => 64,
C_SPLB_BIGGEST_MASTER => 32,
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_SMALLEST_SLAVE => 32,
C_BUS_CLOCK_RATIO => 1,
C_PREFETCH_TIMEOUT => 10,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
IP2INTC_Irpt => IP2INTC_Irpt,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_ABus => M_ABus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
M_wrDBus => M_wrDBus,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
PLB_MBusy => PLB_MBusy,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdWdAddr => PLB_MRdWdAddr
);
end architecture STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eww is
port(
entrada1_or: in std_logic;
entrada2_or: in std_logic;
salida_or: out std_logic);
end;
-- Arquitectura
architecture aww of eww is
begin
salida_or <= entrada1_or OR entrada2_or;
end aww;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: BuzzerFa.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY BuzzerFa IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END BuzzerFa;
ARCHITECTURE SYN OF buzzerfa IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 71023,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "71023"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "71023"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerFa_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: memmory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : memmory.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY memmory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END memmory_prod;
ARCHITECTURE xilinx OF memmory_prod IS
COMPONENT memmory_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : memmory_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity s4_box is
port( data_in: in std_logic_vector(0 to 5);
data_out: out std_logic_vector(0 to 3));
end s4_box;
architecture behavior of s4_box is
type s4box is array(0 to 3, 0 to 15) of integer range 0 to 15;
constant box: s4box:=
((7,13,14,3,0,6,9,10,1,2,8,5,11,12,4,15),
(13,8,11,5,6,15,0,3,4,7,2,12,1,10,14,9),
(10,6,9,0,12,11,7,13,15,1,3,14,5,2,8,4),
(3,15,0,6,10,1,13,8,9,4,5,11,12,7,2,14));
begin
process(data_in) is
variable column: integer range 0 to 15;
variable row: integer range 0 to 3;
variable tmp: std_logic_vector(0 to 1); --this variable holds the first and last bit of the input that represents the row. It is usedto cast two separate bits into one vector of size two.
variable data_out_decimal: integer range 0 to 15; --this variable contains the output data in decimal representation
begin
column:=to_integer(unsigned(data_in(1 to 4)));
tmp:=data_in(0)&data_in(5);
row:=to_integer(unsigned(tmp));
data_out_decimal:=box(row,column);
data_out<=std_logic_vector(to_unsigned(data_out_decimal,data_out'length));
end process;
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_191 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_191;
architecture augh of cmp_191 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_191 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_191;
architecture augh of cmp_191 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- internal_osc.vhd
-- Generated using ACDS version 17.1 590
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity internal_osc is
port (
clkout : out std_logic; -- clkout.clk
oscena : in std_logic := '0' -- oscena.oscena
);
end entity internal_osc;
architecture rtl of internal_osc is
component altera_int_osc is
generic (
DEVICE_FAMILY : string := "";
DEVICE_ID : string := "UNKNOWN";
CLOCK_FREQUENCY : string := "UNKNOWN"
);
port (
oscena : in std_logic := 'X'; -- oscena
clkout : out std_logic -- clk
);
end component altera_int_osc;
begin
int_osc_0 : component altera_int_osc
generic map (
DEVICE_FAMILY => "MAX 10",
DEVICE_ID => "04",
CLOCK_FREQUENCY => "116"
)
port map (
oscena => oscena, -- oscena.oscena
clkout => clkout -- clkout.clk
);
end architecture rtl; -- of internal_osc
|
-- internal_osc.vhd
-- Generated using ACDS version 17.1 590
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity internal_osc is
port (
clkout : out std_logic; -- clkout.clk
oscena : in std_logic := '0' -- oscena.oscena
);
end entity internal_osc;
architecture rtl of internal_osc is
component altera_int_osc is
generic (
DEVICE_FAMILY : string := "";
DEVICE_ID : string := "UNKNOWN";
CLOCK_FREQUENCY : string := "UNKNOWN"
);
port (
oscena : in std_logic := 'X'; -- oscena
clkout : out std_logic -- clk
);
end component altera_int_osc;
begin
int_osc_0 : component altera_int_osc
generic map (
DEVICE_FAMILY => "MAX 10",
DEVICE_ID => "04",
CLOCK_FREQUENCY => "116"
)
port map (
oscena => oscena, -- oscena.oscena
clkout => clkout -- clkout.clk
);
end architecture rtl; -- of internal_osc
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLHWQIRQK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLHWQIRQK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 + 1 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
xin(3) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLHWQIRQK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLHWQIRQK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 + 1 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
xin(3) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLHWQIRQK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLHWQIRQK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 + 1 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
xin(3) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLHWQIRQK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLHWQIRQK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 + 1 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
xin(3) => '0', yout => output
);
end architecture; |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_vld_dly3 : IN std_logic;
twdl_3_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block;
ARCHITECTURE rtl OF Complex3Multiply_block IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_3_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_3_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_3_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_3_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_3_re_signed <= signed(twdl_3_3_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_3_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_3_im_signed <= signed(twdl_3_3_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_3_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_3_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_3_re <= std_logic_vector(twdlXdin_3_re_tmp);
twdlXdin_3_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_3_im <= std_logic_vector(twdlXdin_3_im_tmp);
END rtl;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:51:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.3 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.3 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba
-- No Generated Generics
-- Generated Generics for Entity ent_ba
-- End of Generated Generics for Entity ent_ba
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0_2
-- srl_fifo_f refered from proc_common_v4_0_2
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_uartlite_v2_0_10;
-- uartlite_core refered from axi_uartlite_v2_0_10
use axi_uartlite_v2_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0_10.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
|
-- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: Simple terminal interface to monitor and manipulate
-- basic IO components such as buttons, slide switches, LED
-- and hexadecimal displays.
--
-- A typical transport would be a UART connection using a terminal application.
-- A command line starts with a single letter identifying the addressed
-- resource type:
--
-- R .. Reset - strobed input to the design
-- P .. Pulse - strobed input to the design
-- S .. Switch - stateful input to the design
-- L .. Light - (bit) output from the design
-- D .. Digit - (hex) output from the design
--
-- This letter may be followed by a hexadecimal input vector, which triggers
--
-- R - a strobe on the corresponding inputs,
-- P - a strobe on the corresponding inputs, and
-- S - a state toggle of the corresponding inputs.
--
-- The input vector is ignored for outputs from the design.
-- The command line may contain an arbitrary amount of spaces.
--
-- The terminal interface will echo with:
--
-- <resource character>[<bit count>'<hex output vector>]
--
-- The <bit count> and <hex output vector> will only be present if, at least,
-- a single instance of the addressed resource type is available.
-- In particular, the resource characters of lines starting with other than
-- the listed resource types will simply be echoed.
-- The <bit count> describes how many bits of the addressed resource are
-- available, which may be used to explore the resources using a command line
-- with no or a zero input argument. The <bit count> is typically provided in
-- decimal (default) but may be changed to hexadecimal through the generic
-- parameter COUNT_DECIMAL.
-- The <hex output vector> acknowledges the input (R and P) and informs about
-- the current state (S, L and D).
--
-- Example:
-- > L
-- L10'21D
-- > D
-- D8'5E
-- > A
-- A
-- > S
-- S6'00
-- > S3A
-- S6'3A
-- > S 1
-- S6'3B
-- > P8
-- P4'8
-- > P
-- P4'0
-- Authors: Thomas B. Preußer <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library poc;
use poc.functions.all;
entity remote_terminal_control is
generic (
RESET_COUNT : natural;
PULSE_COUNT : natural;
SWITCH_COUNT : natural;
LIGHT_COUNT : natural;
DIGIT_COUNT : natural;
COUNT_DECIMAL : boolean := true
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- UART Connectivity
idat : in std_logic_vector(6 downto 0);
istb : in std_logic;
odat : out std_logic_vector(6 downto 0);
ordy : in std_logic;
oput : out std_logic;
-- Control Outputs
resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0);
pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0);
switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0);
-- Monitor Inputs
lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0);
digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0)
);
end remote_terminal_control;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of remote_terminal_control is
type tKind is (KIND_NONE,
KIND_RESET, KIND_PULSE, KIND_SWITCH,
KIND_LIGHT, KIND_DIGIT);
--constant KIND_NONE : natural := 0;
--constant KIND_RESET : natural := 1;
--constant KIND_PULSE : natural := 2;
--constant KIND_SWITCH : natural := 3;
--constant KIND_LIGHT : natural := 4;
--constant KIND_DIGIT : natural := 5;
--subtype tKind is natural range KIND_NONE to KIND_DIGIT;
subtype tActual is tKind range KIND_RESET to KIND_DIGIT;
subtype tInput is tActual range KIND_RESET to KIND_SWITCH;
subtype tOutput is tActual range KIND_LIGHT to KIND_DIGIT;
-----------------------------------------------------------------------------
-- Counts
type tCounts is array(tKind range<>) of natural;
constant COUNTS : tCounts := (0,
RESET_COUNT, PULSE_COUNT, SWITCH_COUNT,
LIGHT_COUNT, 4*DIGIT_COUNT);
function max_count(arr : tCounts) return natural is
-- Without this copy of arr, ISE (as of version 14.7) will choke.
variable a : tCounts(arr'range) := (others => 0);
variable res : natural;
begin
a(arr'range) := arr;
res := 0;
for i in a'range loop
if a(i) > res then
res := a(i);
end if;
end loop;
return res;
end max_count;
constant PAR_BITS : natural := max_count(COUNTS(tInput));
constant RES_BITS : natural := max_count(COUNTS(tActual));
constant ECO_BITS : natural := 4*((RES_BITS+3)/4);
function log10ceil(x : natural) return positive is
variable scale, res : positive;
begin
scale := 10;
res := 1;
while x >= scale loop
scale := 10*scale;
res := res+1;
end loop;
return res;
end log10ceil;
function makeCntBits return positive is
begin
if COUNT_DECIMAL then
return 4*log10ceil(RES_BITS);
end if;
return log2ceil(RES_BITS);
end makeCntBits;
constant CNT_BITS : positive := makeCntBits;
subtype tOutCount is unsigned(CNT_BITS-1 downto 0);
type tOutCounts is array(tKind range<>) of tOutCount;
function makeOutCounts return tOutCounts is
variable res : tOutCounts(COUNTS'range);
variable ele : tOutCount;
variable rmd : natural;
begin
for i in COUNTS'range loop
if COUNT_DECIMAL then
rmd := COUNTS(i);
for j in 0 to ele'length/4-1 loop
ele(4*j+3 downto 4*j) := to_unsigned(rmd mod 10, 4);
rmd := rmd/10;
end loop;
else
ele := to_unsigned(COUNTS(i), CNT_BITS);
end if;
res(i) := ele;
end loop;
return res;
end;
constant OUT_COUNTS : tOutCounts(COUNTS'range) := makeOutCounts;
subtype tCode is std_logic_vector(4 downto 0);
type tCodes is array(tKind range<>) of tCode;
constant CODES : tCodes(tActual) := ("10010", "10000", "10011", "01100", "00100");
type tStrobes is array(tKind range<>) of boolean;
constant STROBES : tStrobes(tInput) := (true, true, false);
signal BufVld : std_logic := '0';
signal BufCmd : std_logic_vector(4 downto 0) := (others => '-');
signal BufCnt : unsigned(CNT_BITS-1 downto 0) := (others => '-');
signal BufEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal BufAck : std_logic;
begin
-- Reading the UART input stream
blkReader: block
type tState is (Idle, Command);
signal State : tState := Idle;
signal NextState : tState;
signal Cmd : std_logic_vector(4 downto 0) := (others => '-');
signal Arg : std_logic_vector(PAR_BITS-1 downto 0) := (others => '-');
signal Sel : tKind := KIND_NONE;
signal Load : std_logic;
signal Shift : std_logic;
signal Commit : std_logic;
subtype tEcho is std_logic_vector(0 to ECO_BITS-1);
type tEchos is array(tKind range<>) of tEcho;
signal echos : tEchos(tKind);
function leftAlignedBCD(x : std_logic_vector) return tEcho is
constant MY_BITS : positive := 4*((x'length+3)/4);
variable res : tEcho;
begin
res := (others => '-');
res(0 to 3) := x"0";
res(MY_BITS-x'length to MY_BITS-1) := x;
return res;
end leftAlignedBCD;
begin
-- State Registers
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
Cmd <= (others => '-');
Arg <= (others => '-');
else
State <= NextState;
if Load = '1' then
Cmd <= idat(4 downto 0);
Arg <= (others => '0');
Sel <= KIND_NONE;
for i in CODES'range loop
if CODES(i) = idat(4 downto 0) then
Sel <= i;
end if;
end loop;
elsif Shift = '1' then
Arg <= Arg(Arg'left-4 downto 0) &
std_logic_vector(unsigned(idat(3 downto 0)) + (idat(6)&"00"&idat(6)));
end if;
end if;
end if;
end process;
-- Common Reader State Machine
process(State, istb, idat)
begin
NextState <= State;
Load <= '0';
Shift <= '0';
Commit <= '0';
if istb = '1' then
case State is
when Idle =>
if idat(6) = '1' then
Load <= '1';
NextState <= Command;
end if;
when Command =>
if idat(6) = '1' or (idat(5) = '1' and idat(4) = '1') then
Shift <= '1';
elsif idat(6) = '0' and idat(5) = '0' and idat(4) = '0' then
Commit <= '1';
NextState <= Idle;
end if;
end case;
end if;
end process;
echos(KIND_NONE) <= (others => '-');
-- Generate Control Inputs
genInputs: for i in tInput generate
-- Control not used
genNone: if COUNTS(i) = 0 generate
genReset: if i = KIND_RESET generate
resets <= "X";
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= "X";
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= "X";
end generate genSwitch;
echos(i) <= (others => '-');
end generate genNone;
-- Controls available
genAvail: if COUNTS(i) > 0 generate
signal Outputs : std_logic_vector(COUNTS(i)-1 downto 0) := (others => '0');
signal onxt : std_logic_vector(Outputs'range);
begin
-- Output Computation: Strobed
genStrobed: if STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Outputs <= (others => '0');
else
if Commit = '1' and Sel = i then
Outputs <= onxt;
else
Outputs <= (others => '0');
end if;
end if;
end if;
end process;
onxt <= Arg(Outputs'range);
end generate genStrobed;
-- Output Computation: State
genState: if not STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if Commit = '1' and Sel = i then
Outputs <= onxt;
end if;
end if;
end process;
onxt <= Outputs xor Arg(Outputs'range);
end generate genState;
echos(i) <= leftAlignedBCD(onxt);
-- Assign to Output Pins
genReset: if i = KIND_RESET generate
resets <= Outputs;
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= Outputs;
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= Outputs;
end generate genSwitch;
end generate genAvail;
end generate genInputs;
process(lights, digits)
begin
echos(KIND_LIGHT) <= (others => '-');
echos(KIND_DIGIT) <= (others => '-');
if LIGHT_COUNT > 0 then
echos(KIND_LIGHT) <= leftAlignedBCD(lights);
end if;
if DIGIT_COUNT > 0 then
echos(KIND_DIGIT) <= leftAlignedBCD(digits);
end if;
end process;
-- Build Data Record for Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
else
if Commit = '1' then
BufVld <= '1';
BufCmd <= Cmd;
BufCnt <= OUT_COUNTS(Sel);
BufEco <= echos(Sel);
elsif BufAck = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
end if;
end if;
end if;
end process;
end block blkReader;
blkWrite: block
type tState is (Idle, OutCommand, OutCount, OutTick, OutEcho, OutEOL);
signal State : tState := Idle;
signal NextState : tState;
signal OutCmd : std_logic_vector(4 downto 0) := (others => '-');
signal OutCnt : unsigned(4*((BufCnt'length+3)/4)-1 downto 0) := (others => '-');
signal OutEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal Locked : std_logic := '-';
signal NextLocked : std_logic;
signal OutCntDone : std_logic;
signal OutCntDecr : unsigned(2 downto 0);
signal NextOutCnt : unsigned(OutCnt'length downto 0);
signal ShiftCnt : std_logic;
signal ShiftEco : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
OutCmd <= (others => '-');
OutCnt <= (others => '-');
OutEco <= (others => '-');
Locked <= '-';
else
State <= NextState;
if BufAck = '1' then
OutCmd <= BufCmd;
OutCnt <= (others => '0');
OutCnt(BufCnt'length-1 downto 0) <= unsigned(BufCnt);
OutEco <= BufEco;
Locked <= '0';
else
-- OutCnt Register
if OutCnt'length > 4 and ShiftCnt = '1' then
OutCnt <= OutCnt(OutCnt'left-4 downto 0) & OutCnt(OutCnt'left downto OutCnt'left-3);
else
OutCnt <= NextOutCnt(OutCnt'range);
end if;
Locked <= NextLocked;
-- OutEco Register
if ShiftEco = '1' then
OutEco <= OutEco(4 to OutEco'right) & "----";
end if;
end if;
end if;
end if;
end process;
NextLocked <= 'X' when Is_x(std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3))) else
'1' when OutCnt(OutCnt'left downto OutCnt'left-3) /= x"0" else
Locked;
genSingleDig: if OutCnt'length = 4 generate
OutCntDone <= '1';
end generate;
genMultiDig: if OutCnt'length > 4 generate
signal Cnt : unsigned(log2ceil(OutCnt'length/4)-1 downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if BufAck = '1' then
Cnt <= (others => '0');
elsif ShiftCnt = '1' then
Cnt <= Cnt + 1;
end if;
end if;
end if;
end process;
OutCntDone <= 'X' when Is_X(std_logic_vector(Cnt)) else
'1' when (Cnt or not to_unsigned(OutCnt'length/4-1, Cnt'length)) = (Cnt'range => '1') else
'0';
end generate;
genDec: if COUNT_DECIMAL generate
process(OutCnt, OutCntDecr)
variable sub : unsigned(2 downto 0);
variable d : unsigned(4 downto 0);
begin
sub := OutCntDecr;
for i in 0 to OutCnt'length/4-1 loop
d := ('0'&OutCnt(4*i+3 downto 4*i)) - sub;
if d(4) = '0' then
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0);
sub := to_unsigned(0, sub'length);
else
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0) - 6;
sub := to_unsigned(1, sub'length);
end if;
end loop;
NextOutCnt(OutCnt'length) <= sub(0);
end process;
end generate genDec;
genHex: if not COUNT_DECIMAL generate
NextOutCnt <= ('0'&OutCnt) - OutCntDecr;
end generate genHex;
process(State, ordy, BufVld, OutCmd, OutCnt, OutEco, OutCntDone, NextLocked, NextOutCnt)
begin
NextState <= State;
BufAck <= '0';
ShiftCnt <= '0';
ShiftEco <= '0';
OutCntDecr <= (others => '0');
odat <= (others => '-');
oput <= '0';
case State is
when Idle =>
if BufVld = '1' then
BufAck <= '1';
NextState <= OutCommand;
end if;
when OutCommand =>
odat <= "10" & OutCmd;
oput <= '1';
if ordy = '1' then
NextState <= OutCount;
end if;
when OutCount =>
if COUNT_DECIMAL or OutCnt(OutCnt'left downto OutCnt'left-3) < 10 then
odat <= "011" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3));
else
odat <= "100" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)+7);
end if;
oput <= NextLocked;
if ordy = '1' then
ShiftCnt <= '1';
if OutCntDone = '1' then
if NextLocked = '1' then
NextState <= OutTick;
else
NextState <= OutEOL;
end if;
end if;
end if;
when OutTick =>
odat <= "0100111";
oput <= '1';
if ordy = '1' then
OutCntDecr <= to_unsigned(1, OutCntDecr'length);
NextState <= OutEcho;
end if;
when OutEcho =>
if unsigned(OutEco(0 to 3)) < 10 then
odat <= "011" & OutEco(0 to 3);
else
odat <= "100" & std_logic_vector(unsigned(OutEco(0 to 3))+7);
end if;
oput <= '1';
if ordy = '1' then
ShiftEco <= '1';
OutCntDecr <= "100";
if NextOutCnt(OutCnt'length) = '1' then
NextState <= OutEOL;
end if;
end if;
when OutEOL =>
odat <= "0001010";
oput <= '1';
if ordy = '1' then
NextState <= Idle;
end if;
end case;
end process;
end block blkWrite;
end rtl;
|
-- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: Simple terminal interface to monitor and manipulate
-- basic IO components such as buttons, slide switches, LED
-- and hexadecimal displays.
--
-- A typical transport would be a UART connection using a terminal application.
-- A command line starts with a single letter identifying the addressed
-- resource type:
--
-- R .. Reset - strobed input to the design
-- P .. Pulse - strobed input to the design
-- S .. Switch - stateful input to the design
-- L .. Light - (bit) output from the design
-- D .. Digit - (hex) output from the design
--
-- This letter may be followed by a hexadecimal input vector, which triggers
--
-- R - a strobe on the corresponding inputs,
-- P - a strobe on the corresponding inputs, and
-- S - a state toggle of the corresponding inputs.
--
-- The input vector is ignored for outputs from the design.
-- The command line may contain an arbitrary amount of spaces.
--
-- The terminal interface will echo with:
--
-- <resource character>[<bit count>'<hex output vector>]
--
-- The <bit count> and <hex output vector> will only be present if, at least,
-- a single instance of the addressed resource type is available.
-- In particular, the resource characters of lines starting with other than
-- the listed resource types will simply be echoed.
-- The <bit count> describes how many bits of the addressed resource are
-- available, which may be used to explore the resources using a command line
-- with no or a zero input argument. The <bit count> is typically provided in
-- decimal (default) but may be changed to hexadecimal through the generic
-- parameter COUNT_DECIMAL.
-- The <hex output vector> acknowledges the input (R and P) and informs about
-- the current state (S, L and D).
--
-- Example:
-- > L
-- L10'21D
-- > D
-- D8'5E
-- > A
-- A
-- > S
-- S6'00
-- > S3A
-- S6'3A
-- > S 1
-- S6'3B
-- > P8
-- P4'8
-- > P
-- P4'0
-- Authors: Thomas B. Preußer <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library poc;
use poc.functions.all;
entity remote_terminal_control is
generic (
RESET_COUNT : natural;
PULSE_COUNT : natural;
SWITCH_COUNT : natural;
LIGHT_COUNT : natural;
DIGIT_COUNT : natural;
COUNT_DECIMAL : boolean := true
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- UART Connectivity
idat : in std_logic_vector(6 downto 0);
istb : in std_logic;
odat : out std_logic_vector(6 downto 0);
ordy : in std_logic;
oput : out std_logic;
-- Control Outputs
resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0);
pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0);
switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0);
-- Monitor Inputs
lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0);
digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0)
);
end remote_terminal_control;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of remote_terminal_control is
type tKind is (KIND_NONE,
KIND_RESET, KIND_PULSE, KIND_SWITCH,
KIND_LIGHT, KIND_DIGIT);
--constant KIND_NONE : natural := 0;
--constant KIND_RESET : natural := 1;
--constant KIND_PULSE : natural := 2;
--constant KIND_SWITCH : natural := 3;
--constant KIND_LIGHT : natural := 4;
--constant KIND_DIGIT : natural := 5;
--subtype tKind is natural range KIND_NONE to KIND_DIGIT;
subtype tActual is tKind range KIND_RESET to KIND_DIGIT;
subtype tInput is tActual range KIND_RESET to KIND_SWITCH;
subtype tOutput is tActual range KIND_LIGHT to KIND_DIGIT;
-----------------------------------------------------------------------------
-- Counts
type tCounts is array(tKind range<>) of natural;
constant COUNTS : tCounts := (0,
RESET_COUNT, PULSE_COUNT, SWITCH_COUNT,
LIGHT_COUNT, 4*DIGIT_COUNT);
function max_count(arr : tCounts) return natural is
-- Without this copy of arr, ISE (as of version 14.7) will choke.
variable a : tCounts(arr'range) := (others => 0);
variable res : natural;
begin
a(arr'range) := arr;
res := 0;
for i in a'range loop
if a(i) > res then
res := a(i);
end if;
end loop;
return res;
end max_count;
constant PAR_BITS : natural := max_count(COUNTS(tInput));
constant RES_BITS : natural := max_count(COUNTS(tActual));
constant ECO_BITS : natural := 4*((RES_BITS+3)/4);
function log10ceil(x : natural) return positive is
variable scale, res : positive;
begin
scale := 10;
res := 1;
while x >= scale loop
scale := 10*scale;
res := res+1;
end loop;
return res;
end log10ceil;
function makeCntBits return positive is
begin
if COUNT_DECIMAL then
return 4*log10ceil(RES_BITS);
end if;
return log2ceil(RES_BITS);
end makeCntBits;
constant CNT_BITS : positive := makeCntBits;
subtype tOutCount is unsigned(CNT_BITS-1 downto 0);
type tOutCounts is array(tKind range<>) of tOutCount;
function makeOutCounts return tOutCounts is
variable res : tOutCounts(COUNTS'range);
variable ele : tOutCount;
variable rmd : natural;
begin
for i in COUNTS'range loop
if COUNT_DECIMAL then
rmd := COUNTS(i);
for j in 0 to ele'length/4-1 loop
ele(4*j+3 downto 4*j) := to_unsigned(rmd mod 10, 4);
rmd := rmd/10;
end loop;
else
ele := to_unsigned(COUNTS(i), CNT_BITS);
end if;
res(i) := ele;
end loop;
return res;
end;
constant OUT_COUNTS : tOutCounts(COUNTS'range) := makeOutCounts;
subtype tCode is std_logic_vector(4 downto 0);
type tCodes is array(tKind range<>) of tCode;
constant CODES : tCodes(tActual) := ("10010", "10000", "10011", "01100", "00100");
type tStrobes is array(tKind range<>) of boolean;
constant STROBES : tStrobes(tInput) := (true, true, false);
signal BufVld : std_logic := '0';
signal BufCmd : std_logic_vector(4 downto 0) := (others => '-');
signal BufCnt : unsigned(CNT_BITS-1 downto 0) := (others => '-');
signal BufEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal BufAck : std_logic;
begin
-- Reading the UART input stream
blkReader: block
type tState is (Idle, Command);
signal State : tState := Idle;
signal NextState : tState;
signal Cmd : std_logic_vector(4 downto 0) := (others => '-');
signal Arg : std_logic_vector(PAR_BITS-1 downto 0) := (others => '-');
signal Sel : tKind := KIND_NONE;
signal Load : std_logic;
signal Shift : std_logic;
signal Commit : std_logic;
subtype tEcho is std_logic_vector(0 to ECO_BITS-1);
type tEchos is array(tKind range<>) of tEcho;
signal echos : tEchos(tKind);
function leftAlignedBCD(x : std_logic_vector) return tEcho is
constant MY_BITS : positive := 4*((x'length+3)/4);
variable res : tEcho;
begin
res := (others => '-');
res(0 to 3) := x"0";
res(MY_BITS-x'length to MY_BITS-1) := x;
return res;
end leftAlignedBCD;
begin
-- State Registers
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
Cmd <= (others => '-');
Arg <= (others => '-');
else
State <= NextState;
if Load = '1' then
Cmd <= idat(4 downto 0);
Arg <= (others => '0');
Sel <= KIND_NONE;
for i in CODES'range loop
if CODES(i) = idat(4 downto 0) then
Sel <= i;
end if;
end loop;
elsif Shift = '1' then
Arg <= Arg(Arg'left-4 downto 0) &
std_logic_vector(unsigned(idat(3 downto 0)) + (idat(6)&"00"&idat(6)));
end if;
end if;
end if;
end process;
-- Common Reader State Machine
process(State, istb, idat)
begin
NextState <= State;
Load <= '0';
Shift <= '0';
Commit <= '0';
if istb = '1' then
case State is
when Idle =>
if idat(6) = '1' then
Load <= '1';
NextState <= Command;
end if;
when Command =>
if idat(6) = '1' or (idat(5) = '1' and idat(4) = '1') then
Shift <= '1';
elsif idat(6) = '0' and idat(5) = '0' and idat(4) = '0' then
Commit <= '1';
NextState <= Idle;
end if;
end case;
end if;
end process;
echos(KIND_NONE) <= (others => '-');
-- Generate Control Inputs
genInputs: for i in tInput generate
-- Control not used
genNone: if COUNTS(i) = 0 generate
genReset: if i = KIND_RESET generate
resets <= "X";
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= "X";
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= "X";
end generate genSwitch;
echos(i) <= (others => '-');
end generate genNone;
-- Controls available
genAvail: if COUNTS(i) > 0 generate
signal Outputs : std_logic_vector(COUNTS(i)-1 downto 0) := (others => '0');
signal onxt : std_logic_vector(Outputs'range);
begin
-- Output Computation: Strobed
genStrobed: if STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Outputs <= (others => '0');
else
if Commit = '1' and Sel = i then
Outputs <= onxt;
else
Outputs <= (others => '0');
end if;
end if;
end if;
end process;
onxt <= Arg(Outputs'range);
end generate genStrobed;
-- Output Computation: State
genState: if not STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if Commit = '1' and Sel = i then
Outputs <= onxt;
end if;
end if;
end process;
onxt <= Outputs xor Arg(Outputs'range);
end generate genState;
echos(i) <= leftAlignedBCD(onxt);
-- Assign to Output Pins
genReset: if i = KIND_RESET generate
resets <= Outputs;
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= Outputs;
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= Outputs;
end generate genSwitch;
end generate genAvail;
end generate genInputs;
process(lights, digits)
begin
echos(KIND_LIGHT) <= (others => '-');
echos(KIND_DIGIT) <= (others => '-');
if LIGHT_COUNT > 0 then
echos(KIND_LIGHT) <= leftAlignedBCD(lights);
end if;
if DIGIT_COUNT > 0 then
echos(KIND_DIGIT) <= leftAlignedBCD(digits);
end if;
end process;
-- Build Data Record for Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
else
if Commit = '1' then
BufVld <= '1';
BufCmd <= Cmd;
BufCnt <= OUT_COUNTS(Sel);
BufEco <= echos(Sel);
elsif BufAck = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
end if;
end if;
end if;
end process;
end block blkReader;
blkWrite: block
type tState is (Idle, OutCommand, OutCount, OutTick, OutEcho, OutEOL);
signal State : tState := Idle;
signal NextState : tState;
signal OutCmd : std_logic_vector(4 downto 0) := (others => '-');
signal OutCnt : unsigned(4*((BufCnt'length+3)/4)-1 downto 0) := (others => '-');
signal OutEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal Locked : std_logic := '-';
signal NextLocked : std_logic;
signal OutCntDone : std_logic;
signal OutCntDecr : unsigned(2 downto 0);
signal NextOutCnt : unsigned(OutCnt'length downto 0);
signal ShiftCnt : std_logic;
signal ShiftEco : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
OutCmd <= (others => '-');
OutCnt <= (others => '-');
OutEco <= (others => '-');
Locked <= '-';
else
State <= NextState;
if BufAck = '1' then
OutCmd <= BufCmd;
OutCnt <= (others => '0');
OutCnt(BufCnt'length-1 downto 0) <= unsigned(BufCnt);
OutEco <= BufEco;
Locked <= '0';
else
-- OutCnt Register
if OutCnt'length > 4 and ShiftCnt = '1' then
OutCnt <= OutCnt(OutCnt'left-4 downto 0) & OutCnt(OutCnt'left downto OutCnt'left-3);
else
OutCnt <= NextOutCnt(OutCnt'range);
end if;
Locked <= NextLocked;
-- OutEco Register
if ShiftEco = '1' then
OutEco <= OutEco(4 to OutEco'right) & "----";
end if;
end if;
end if;
end if;
end process;
NextLocked <= 'X' when Is_x(std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3))) else
'1' when OutCnt(OutCnt'left downto OutCnt'left-3) /= x"0" else
Locked;
genSingleDig: if OutCnt'length = 4 generate
OutCntDone <= '1';
end generate;
genMultiDig: if OutCnt'length > 4 generate
signal Cnt : unsigned(log2ceil(OutCnt'length/4)-1 downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if BufAck = '1' then
Cnt <= (others => '0');
elsif ShiftCnt = '1' then
Cnt <= Cnt + 1;
end if;
end if;
end if;
end process;
OutCntDone <= 'X' when Is_X(std_logic_vector(Cnt)) else
'1' when (Cnt or not to_unsigned(OutCnt'length/4-1, Cnt'length)) = (Cnt'range => '1') else
'0';
end generate;
genDec: if COUNT_DECIMAL generate
process(OutCnt, OutCntDecr)
variable sub : unsigned(2 downto 0);
variable d : unsigned(4 downto 0);
begin
sub := OutCntDecr;
for i in 0 to OutCnt'length/4-1 loop
d := ('0'&OutCnt(4*i+3 downto 4*i)) - sub;
if d(4) = '0' then
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0);
sub := to_unsigned(0, sub'length);
else
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0) - 6;
sub := to_unsigned(1, sub'length);
end if;
end loop;
NextOutCnt(OutCnt'length) <= sub(0);
end process;
end generate genDec;
genHex: if not COUNT_DECIMAL generate
NextOutCnt <= ('0'&OutCnt) - OutCntDecr;
end generate genHex;
process(State, ordy, BufVld, OutCmd, OutCnt, OutEco, OutCntDone, NextLocked, NextOutCnt)
begin
NextState <= State;
BufAck <= '0';
ShiftCnt <= '0';
ShiftEco <= '0';
OutCntDecr <= (others => '0');
odat <= (others => '-');
oput <= '0';
case State is
when Idle =>
if BufVld = '1' then
BufAck <= '1';
NextState <= OutCommand;
end if;
when OutCommand =>
odat <= "10" & OutCmd;
oput <= '1';
if ordy = '1' then
NextState <= OutCount;
end if;
when OutCount =>
if COUNT_DECIMAL or OutCnt(OutCnt'left downto OutCnt'left-3) < 10 then
odat <= "011" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3));
else
odat <= "100" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)+7);
end if;
oput <= NextLocked;
if ordy = '1' then
ShiftCnt <= '1';
if OutCntDone = '1' then
if NextLocked = '1' then
NextState <= OutTick;
else
NextState <= OutEOL;
end if;
end if;
end if;
when OutTick =>
odat <= "0100111";
oput <= '1';
if ordy = '1' then
OutCntDecr <= to_unsigned(1, OutCntDecr'length);
NextState <= OutEcho;
end if;
when OutEcho =>
if unsigned(OutEco(0 to 3)) < 10 then
odat <= "011" & OutEco(0 to 3);
else
odat <= "100" & std_logic_vector(unsigned(OutEco(0 to 3))+7);
end if;
oput <= '1';
if ordy = '1' then
ShiftEco <= '1';
OutCntDecr <= "100";
if NextOutCnt(OutCnt'length) = '1' then
NextState <= OutEOL;
end if;
end if;
when OutEOL =>
odat <= "0001010";
oput <= '1';
if ordy = '1' then
NextState <= Idle;
end if;
end case;
end process;
end block blkWrite;
end rtl;
|
architecture RTL of FIFO is
begin
process
BEGIN
end process;
-- Violations below
process
BEGIN
end process;
end architecture RTL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END system_axi_gpio_0_1;
ARCHITECTURE system_axi_gpio_0_1_arch OF system_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_0_1_arch : ARCHITECTURE IS "system_axi_gpio_0_1,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "system_axi_gpio_0_1,axi_gpio,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=5,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_1_arch;
|
--------------------------------------------------------------------------------
-- FILE: Shifter
-- DESC: Shift A by B bits
--
-- Author:
-- Create: 2015-05-25
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Shifter is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
l_r : in std_logic; -- LEFT/RIGHT
l_a : in std_logic; -- LOGIC/ARITHMETIC
s_r : in std_logic; -- SHIFT/ROTATE
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0')
);
end Shifter;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture shifter_arch of Shifter is
constant B_SIZE : integer := MyLog2Ceil(DATA_SIZE);
begin
P0: process (a, b, l_r, l_a, s_r) is
begin
if s_r = '1' then
if l_r = '1' then
o <= to_StdLogicVector((to_bitvector(a)) ror (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) rol (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
else
if l_r = '1' then
if l_a = '1' then
o <= to_StdLogicVector((to_bitvector(a)) sra (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) srl (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
else
if l_a = '1' then
o <= to_StdLogicVector((to_bitvector(a)) sla (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) sll (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
end if;
end if;
end process;
end shifter_arch;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.C_SB_CONFIG_DEFAULT;
use work.avalon_st_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--================================================================================================================================
entity avalon_st_vvc is
generic (
-- When true: This VVC is an Avalon-Stream master. Data is output from BFM.
-- When false: This VVC is an Avalon-Stream slave. Data is input to BFM.
GC_VVC_IS_MASTER : boolean;
GC_CHANNEL_WIDTH : integer := 1;
GC_DATA_WIDTH : integer;
GC_DATA_ERROR_WIDTH : integer := 1;
GC_EMPTY_WIDTH : integer := 1;
GC_INSTANCE_IDX : natural;
GC_AVALON_ST_BFM_CONFIG : t_avalon_st_bfm_config := C_AVALON_ST_BFM_CONFIG_DEFAULT;
-- Common VVC fields
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
avalon_st_vvc_if : inout t_avalon_st_if := init_avalon_st_if_signals(GC_VVC_IS_MASTER, GC_CHANNEL_WIDTH, GC_DATA_WIDTH, GC_DATA_ERROR_WIDTH, GC_EMPTY_WIDTH)
);
end entity avalon_st_vvc;
--================================================================================================================================
--================================================================================================================================
architecture behave of avalon_st_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated executor
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_avalon_st_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_avalon_st_vvc_status(GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_avalon_st_vvc_transaction_trigger(GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_avalon_st_vvc_transaction_info(GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
--UVVM: temporary fix for HVVC, remove function below in v3.0
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel is
begin
-- If the parent_msg_id_panel is set then use it,
-- otherwise use the VVCs msg_id_panel from its config.
if command.msg(1 to 5) = "HVVC:" then
return vvc_config.parent_msg_id_panel;
else
return vvc_config.msg_id_panel;
end if;
end function;
begin
--==========================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--==========================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AVALON_ST_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--==========================================================================================
--==========================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--==========================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
variable v_temp_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc( name => C_VVC_NAME,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- Update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the executor if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
--UVVM: temporary fix for HVVC, remove two lines below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
v_temp_msg_id_panel := vvc_config.msg_id_panel;
vvc_config.msg_id_panel := v_msg_id_panel;
end if;
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor executor
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
--UVVM: temporary fix for HVVC, remove line below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
vvc_config.msg_id_panel := v_temp_msg_id_panel;
end if;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command executor
-- - Fetch and execute the commands
--==========================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_result : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_data_array_ptr : t_slv_array_ptr;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = TRANSMIT or v_cmd.operation = RECEIVE or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when TRANSMIT =>
if GC_VVC_IS_MASTER then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
v_data_array_ptr := new t_slv_array(0 to v_cmd.data_array_length-1)(v_cmd.data_array_word_size-1 downto 0);
for i in 0 to v_cmd.data_array_length-1 loop
v_data_array_ptr(i) := v_cmd.data_array(i)(v_cmd.data_array_word_size-1 downto 0);
end loop;
avalon_st_transmit(channel_value => v_cmd.channel_value(GC_CHANNEL_WIDTH-1 downto 0),
data_array => v_data_array_ptr.all,
msg => format_msg(v_cmd),
clk => clk,
avalon_st_if => avalon_st_vvc_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
deallocate(v_data_array_ptr);
else
alert(TB_ERROR, "Sanity check: Method call only makes sense for master (source) VVC", C_SCOPE);
end if;
when RECEIVE =>
if not GC_VVC_IS_MASTER then
-- Set vvc_transaction_info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
v_data_array_ptr := new t_slv_array(0 to v_cmd.data_array_length-1)(v_cmd.data_array_word_size-1 downto 0);
avalon_st_receive(channel_value => v_result.channel_value(GC_CHANNEL_WIDTH-1 downto 0),
data_array => v_data_array_ptr.all,
msg => format_msg(v_cmd),
clk => clk,
avalon_st_if => avalon_st_vvc_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
for i in 0 to v_cmd.data_array_length-1 loop
v_result.data_array(i)(v_cmd.data_array_word_size-1 downto 0) := v_data_array_ptr(i);
end loop;
v_result.data_array_length := v_cmd.data_array_length;
v_result.data_array_word_size := v_cmd.data_array_word_size;
deallocate(v_data_array_ptr);
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
alert(tb_warning, "Scoreboard type for Avalon-Stream RECEIVE data not implemented");
else
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result);
end if;
else
alert(TB_ERROR, "Sanity check: Method call only makes sense for slave (sink) VVC", C_SCOPE);
end if;
when EXPECT =>
if not GC_VVC_IS_MASTER then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
v_data_array_ptr := new t_slv_array(0 to v_cmd.data_array_length-1)(v_cmd.data_array_word_size-1 downto 0);
for i in 0 to v_cmd.data_array_length-1 loop
v_data_array_ptr(i) := v_cmd.data_array(i)(v_cmd.data_array_word_size-1 downto 0);
end loop;
avalon_st_expect(channel_exp => v_cmd.channel_value(GC_CHANNEL_WIDTH-1 downto 0),
data_exp => v_data_array_ptr.all,
msg => format_msg(v_cmd),
clk => clk,
avalon_st_if => avalon_st_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
deallocate(v_data_array_ptr);
else
alert(TB_ERROR, "Sanity check: Method call only makes sense for slave (sink) VVC", C_SCOPE);
end if;
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
check_value(vvc_config.bfm_config.clock_period > -1 ns, TB_ERROR, "Check that clock_period is configured when using insert_delay().",
C_SCOPE, ID_NEVER, v_msg_id_panel);
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--==========================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--==========================================================================================
end behave; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_189 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(13 downto 0)
);
end mul_189;
architecture augh of mul_189 is
signal tmp_res : signed(44 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_189 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(13 downto 0)
);
end mul_189;
architecture augh of mul_189 is
signal tmp_res : signed(44 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
-- Comment added.
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
-- Comment added.
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
-- Comment added.
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_1 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_1;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_1_arch OF DemoInterconnect_uart_transceiver_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_uart_transceiver_0_1_arch: ARCHITECTURE IS "uart_top,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_uart_transceiver_0_1_arch : ARCHITECTURE IS "DemoInterconnect_uart_transceiver_0_1,uart_top,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_1_arch;
|
library verilog;
use verilog.vl_types.all;
entity ama_dynamic_signed_function is
generic(
port_sign : string := "PORT_UNUSED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_out_wire: vl_notype;
width_data_out_wire_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
sign : in vl_logic;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3;
end ama_dynamic_signed_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_dynamic_signed_function is
generic(
port_sign : string := "PORT_UNUSED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_out_wire: vl_notype;
width_data_out_wire_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
sign : in vl_logic;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3;
end ama_dynamic_signed_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_dynamic_signed_function is
generic(
port_sign : string := "PORT_UNUSED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_out_wire: vl_notype;
width_data_out_wire_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
sign : in vl_logic;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3;
end ama_dynamic_signed_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_dynamic_signed_function is
generic(
port_sign : string := "PORT_UNUSED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_out_wire: vl_notype;
width_data_out_wire_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
sign : in vl_logic;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3;
end ama_dynamic_signed_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_dynamic_signed_function is
generic(
port_sign : string := "PORT_UNUSED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_out_wire: vl_notype;
width_data_out_wire_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
sign : in vl_logic;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3;
end ama_dynamic_signed_function;
|
-------------------------------------------------------------------------------
-- Mojo_Top.vhd
--
-- This file is the top level of heirarchy for the mojo_modulator design.
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity mojo_top is
port (
i_clk50m : in std_logic; -- 50 MHZ XO on board
i_rst_n : in std_logic; -- Reset line on board
---------------------------------------
-- RS232 TTL lines comming from a USB <-> TTL SERIAL converter
o_serial_tx : out STD_LOGIC; -- 3rd pin up from uC outside.
i_serial_rx : in STD_LOGIC; -- 4th pin up from uC outside.
-- LEDS -------------------------------
o_led : out STD_LOGIC_VECTOR(7 downto 0 );
---------------------------------------
-- DAC Interface
-- Dac Interface
o_dac_pin_mode : out STD_LOGIC; -- select between pin mode and spi mode
o_dac_sleep : out STD_LOGIC; -- places dac in to sleep when '1'
o_dac_mode : out STD_LOGIC; -- 2's comp samples or offset binary
o_dac_cmode : out STD_LOGIC; -- clock mode (diff vs single ended)
o_dac_clk_p : out STD_LOGIC; -- differential clock (cmos)
o_dac_clk_n : out STD_LOGIC; -- inverted version of clk_p
o_dac_DB : out signed( 11 downto 0 ) -- sample data bits (12b dac)
);
end entity mojo_top;
architecture system of mojo_top is
----------------------------------
-- Components used in this level
----------------------------------
-- command interface
component command_interface is
port (
i_clk : in std_logic; -- databus clock
i_srst : in std_logic; -- sync reset to clock provided
-- Serial Interface ------------------------------------------
i_rx_serial_stream : in std_logic; -- received TTL rs232 stream
o_tx_serial_stream : out std_logic; -- transmit TTL rs232 stream
-- data bus interface to slave devices -----------------------
o_db_addr : out std_logic_vector( 6 downto 0); -- address bus (7 bits)
o_db_wdata : out std_logic_vector( 7 downto 0); -- write data
i_db_rdata : in std_logic_vector( 7 downto 0); -- read data
o_db_rstrb : out std_logic; -- db_read_strobe
o_db_wstrb : out std_logic -- db_write_strobe
);
end component command_interface;
-- component that allows us to set the LEDs from a the databus
component led_display is
generic (
led_reg_addr : integer := 0 -- address for the led display module to use
);
port (
i_clk : in std_logic;
i_srst : in std_logic;
-- Databus signals ------------------
i_db_addr : in std_logic_vector(6 downto 0);
i_db_wdata : in std_logic_vector(7 downto 0);
o_db_rdata : out std_logic_vector(7 downto 0);
i_db_rstrb : in std_logic;
i_db_wstrb : in std_logic;
-- LED output -----------------------
o_led : out std_logic_vector(7 downto 0)
);
end component;
-- Dynamic clock management title
-- use to generate a 100 MHz clock from the 50 MHz XO
-- 100 MHz clock is used for the DAC DSP.
component dcm_core
port (
-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component mojo_modulator is
generic (
ftw_reg0_addr : integer := 8; -- address in memory of this register
ftw_reg1_addr : integer := 9; -- "
ftw_reg2_addr : integer := 10; -- "
ftw_reg3_addr : integer := 11 -- "
);
port (
-- Databus Clock & reset ---------------------------------
i_clk_db : in std_logic; -- data bus clock
i_srst_db : in std_logic; -- reset for databus clk
-- Databus signals ---------------------------------------
i_db_addr : in std_logic_vector(6 downto 0);
i_db_wdata : in std_logic_vector(7 downto 0);
o_db_rdata : out std_logic_vector(7 downto 0);
i_db_rstrb : in std_logic;
i_db_wstrb : in std_logic;
-- DSP Sample Clocks & Reset -----------------------------
i_clk_dsp : in std_logic; -- dsp sample rate clock (>= db_clk)
i_srst_dsp : in std_logic; -- reset
---DSP Samples Out ---------------------------------------
o_dac_samples : out signed(15 downto 0)
);
end component mojo_modulator;
----------------------------------
-- Signal for this level
----------------------------------
signal db_addr : std_logic_vector(6 downto 0);
signal db_wdata : std_logic_vector(7 downto 0);
signal db_rdata : std_logic_vector(7 downto 0);
signal db_rstrb : std_logic;
signal db_wstrb : std_logic;
-- reset timer
signal reset_timer : unsigned( 15 downto 0 );
signal clk_50 : std_logic; -- input 50 MHz clock after clock buffer
signal srst_50 : std_logic; -- 50 MHz sync reset, active high..
-- DCM clock signals
signal clk_120m : std_logic; -- 100 Mhz clock before global buffer.
signal clk_120 : std_logic; -- 100 MHz clock
signal clk_120n : std_logic; -- inverted clock
signal dac_clk : std_logic;
signal clk_120_locked : std_logic; -- clock 100 is locked. (for srst_120)
signal clk_120_dcm_rst : std_logic; -- reset for dcm
signal srst_120 : std_logic; -- sync reset for 100 MHz clock domain (active high)
-- dac samples (from modulator)
signal dac_sample : signed(15 downto 0); -- gets scaled to 12 bits ..
begin
clk_120n <= not clk_120;
-- IO Interface and clocking stuff here.....
-- IBUFG: Single-ended global clock input buffer for 50 MHz clk
-- Spartan-6
IBUFG_inst : IBUFG
generic map (
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => clk_50, -- Clock buffer output
I => i_clk50m -- Clock buffer input (connect directly to top-level port)
);
-- End of IBUFG_inst instantiation
-- clocking for dac
-- single ended to differental IO driver block.. (Xilinx)
OBUF_inst : OBUF
generic map (
DRIVE => 4,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
O => o_dac_clk_p, -- P clk pin
I => clk_120n -- input clock
);
-- generate synchronious reset signal for
-- synchronious blocks
rst_sync : process( clk_50 )
begin
if ( rising_edge(clk_50) ) then
if ( i_rst_n = '0' ) then
-- reset active
srst_50 <= '1'; -- 50 MHz clk domain in reset
srst_120 <= '1'; -- 100 MHZ clk domain in reset
clk_120_dcm_rst <= '1'; -- dcm in reset at startup
-- timer to hold design in reset untill clocks are good.
-- for simulation hot wire this to 0xFFFF to by pass timer.
reset_timer <= x"FFFF";
-- normal case.
--reset_timer <= (others=>'0');
else
-- reset timer expires
if ( reset_timer = x"FFFF" ) then
srst_50 <= '0'; -- 50 MHZ reset will now de-assert..
clk_120_dcm_rst <= '0'; -- start PLL, XO is stable..
-- wait for PLL lock before releasing 100 MHz reset.
if ( clk_120_locked = '1' ) then
srst_120 <= '0'; -- start design up
end if;
else
-- reset time is not expired..
reset_timer <= reset_timer + 1;
end if;
end if;
end if;
end process;
-- DCM PLL for 100 MHz clock generation
u_clk_pll : dcm_core
port map (
-- Clock in ports
CLK_IN1 => clk_50,
-- Clock out ports
CLK_OUT1 => clk_120,
-- Status and control signals
RESET => clk_120_dcm_rst,
LOCKED => clk_120_locked
);
-- high level system blocks here...............
-- command interface
u_ci : command_interface
port map (
i_clk => clk_50, -- clock used for uart and databus transactions
i_srst => srst_50, -- reset sync to this clock
-- Serial Interface ------------------------------------------
i_rx_serial_stream => i_serial_rx,
o_tx_serial_stream => o_serial_tx,
-- data bus interface to slave devices -----------------------
o_db_addr => db_addr,
o_db_wdata => db_wdata,
i_db_rdata => db_rdata,
o_db_rstrb => db_rstrb,
o_db_wstrb => db_wstrb
);
-- block that controls the LED on the board
-- great for testing memory map control..
u_led_display : led_display
port map (
i_clk => clk_50,
i_srst => srst_50,
-- Databus signals ------------------
i_db_addr => db_addr,
i_db_wdata => db_wdata,
o_db_rdata => db_rdata,
i_db_rstrb => db_rstrb,
i_db_wstrb => db_wstrb,
-- LED output -----------------------
o_led => o_led
);
u_mojo_modulator : mojo_modulator
generic map(
ftw_reg0_addr => 8, -- address in memory of this register
ftw_reg1_addr => 9, -- "
ftw_reg2_addr => 10, -- "
ftw_reg3_addr => 11 -- "
)
port map (
-- Databus Clock & reset ---------------------------------
i_clk_db => clk_50,
i_srst_db => srst_50,
-- Databus signals ---------------------------------------
i_db_addr => db_addr,
i_db_wdata => db_wdata,
o_db_rdata => db_rdata,
i_db_rstrb => db_rstrb,
i_db_wstrb => db_wstrb,
-- DSP Sample Clocks & Reset -----------------------------
i_clk_dsp => clk_120,
i_srst_dsp => srst_120,
---DSP Samples Out ---------------------------------------
o_dac_samples => dac_sample
);
-- dac setup
o_dac_pin_mode <= '1'; -- place dac in pin mode..
o_dac_sleep <= '0'; -- dac not sleeping
o_dac_mode <= '1'; -- 2's complement samples
o_dac_cmode <= '0'; -- use single ended clocking
--o_dac_clk_p <= '0';
o_dac_clk_n <= '0'; -- not used, tie low.
o_dac_DB <= dac_sample(15 downto 4); -- scale down to top most 12 bits.
end architecture system;
|
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
type state_machine is (
idle, write, read, done
);
-- Violations below
type state_machine is (
idle, write, read, done
);
type state_machine is (
idle, write, read, done
);
begin
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company: RAT Technologies
-- Engineer: Various RAT rats
--
-- Create Date: 1/31/2012
-- Design Name:
-- Module Name: RAT_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Wrapper for RAT MCU including a VGA Driver. This model provides a
-- template to interface the RAT MCU and VGA Driver to the Nexys2 board.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAT_wrapper is
Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
SSEG_EN : out STD_LOGIC_VECTOR (3 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
-- VGA support signals -----------------------------
VGA_RGB : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic);
end RAT_wrapper;
architecture Behavioral of RAT_wrapper is
-------------------------------------------------------------------------------
-- INPUT PORT IDS -------------------------------------------------------------
-- Right now, the only possible inputs are the switches
-- In future labs you can add more port IDs, and you'll have
-- to add constants here for the mux below
CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := x"20";
CONSTANT VGA_READ_ID : STD_LOGIC_VECTOR(7 downto 0) := x"93";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OUTPUT PORT IDS ------------------------------------------------------------
-- In future labs you can add more port IDs
CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40";
CONSTANT SEGMENTS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"82";
CONSTANT DISP_EN_ID : STD_LOGIC_VECTOR (7 downto 0) := X"83";
CONSTANT VGA_HADDR_ID : STD_LOGIC_VECTOR(7 downto 0) := x"90";
CONSTANT VGA_LADDR_ID : STD_LOGIC_VECTOR(7 downto 0) := x"91";
CONSTANT VGA_WRITE_ID : STD_LOGIC_VECTOR(7 downto 0) := x"92";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Declare RAT_MCU ------------------------------------------------------------
component RAT_MCU
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_STRB : out STD_LOGIC;
RESET : in STD_LOGIC;
INT : in STD_LOGIC;
CLK : in STD_LOGIC);
end component RAT_MCU;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Declare VGA Driver ---------------------------------------------------------
component vgaDriverBuffer is
Port (CLK, we : in std_logic;
wa : in std_logic_vector (10 downto 0);
wd : in std_logic_vector (7 downto 0);
Rout : out std_logic_vector(2 downto 0);
Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
HS : out std_logic;
VS : out std_logic;
pixelData : out std_logic_vector(7 downto 0));
end component;
-------------------------------------------------------------------------------
-- Declare one_shot -----------------------------------------------------------
--component db_1shot
-- Port ( A, CLK: in STD_LOGIC;
-- A_DB : out STD_LOGIC);
--end component;
-- Signals for connecting RAT_MCU to RAT_wrapper -------------------------------
signal s_input_port : std_logic_vector (7 downto 0);
signal s_output_port : std_logic_vector (7 downto 0);
signal s_port_id : std_logic_vector (7 downto 0);
signal s_load : std_logic;
--signal s_interrupt : std_logic;
-- VGA signals
signal s_vga_we : std_logic; -- Write enable
signal r_vga_wa : std_logic_vector(10 downto 0); -- Address to read from/write to
signal r_vga_wd : std_logic_vector(7 downto 0); -- Pixel data to write to framebuffer
signal r_vgaData : std_logic_vector(7 downto 0); -- Pixel data read from framebuffer
-- Register definitions for output devices ------------------------------------
signal r_LEDS : std_logic_vector (7 downto 0) := (others => '0');
signal r_SEGMENTS : std_logic_vector (7 downto 0) := (others => '0');
signal r_DISP_EN : std_logic_vector (3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Instantiate the one-shot ---------------------------------------------
--my_db: db_1shot
--Port map ( A => BUTTON,
-- CLK => CLK,
-- A_DB => s_interrupt);
-------------------------------------------------------------------------------
-- Instantiate RAT_MCU --------------------------------------------------------
MCU: RAT_MCU
port map( IN_PORT => s_input_port,
OUT_PORT => s_output_port,
PORT_ID => s_port_id,
RESET => RESET,
IO_STRB => s_load,
INT => '0', -- s_interrupt,
CLK => CLK);
-------------------------------------------------------------------------------
-- Instantiate the VGA Driver
VGA: vgaDriverBuffer
port map(CLK => CLK,
WE => s_vga_we,
WA => r_vga_wa,
WD => r_vga_wd,
Rout => VGA_RGB(7 downto 5),
Gout => VGA_RGB(4 downto 2),
Bout => VGA_RGB(1 downto 0),
HS => VGA_HS,
VS => VGA_VS,
pixelData => r_vgaData);
-------------------------------------------------------------------------------
-- MUX for selecting what input to read ---------------------------------------
-------------------------------------------------------------------------------
inputs: process(s_port_id, SWITCHES)
begin
if (s_port_id = SWITCHES_ID) then
s_input_port <= SWITCHES;
elsif (s_port_id = VGA_READ_ID) then
s_input_port <= r_vgaData;
else
s_input_port <= x"00";
end if;
end process inputs;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for updating output registers ------------------------------------------
-- Register updates depend on rising clock edge and asserted load signal
-------------------------------------------------------------------------------
outputs: process(CLK)
begin
if (rising_edge(CLK)) then
if (s_load = '1') then
-- the register definition for the LEDS
if (s_port_id = LEDS_ID) then
r_LEDS <= s_output_port;
elsif (s_port_id = SEGMENTS_ID) then
r_SEGMENTS <= s_output_port;
elsif (s_port_id = DISP_EN_ID) then
r_DISP_EN <= s_output_port(3 downto 0);
-- VGA support -------------------------------------------
elsif (s_port_id = VGA_HADDR_ID) then
r_vga_wa(10 downto 8) <= s_output_port(2 downto 0);
elsif (s_port_id = VGA_LADDR_ID) then
r_vga_wa(7 downto 0) <= s_output_port;
elsif (s_port_id = VGA_WRITE_ID) then
r_vga_wd <= s_output_port;
end if;
if (s_port_id = VGA_WRITE_ID ) then
s_vga_we <= '1';
else
s_vga_we <= '0';
end if;
end if;
end if;
end process outputs;
-------------------------------------------------------------------------------
-- Register Interface Assignments ---------------------------------------------
LEDS <= r_LEDS;
SEGMENTS <= r_SEGMENTS;
SSEG_EN <= r_DISP_EN;
-------------------------------------------------------------------------------
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.defs.all;
-- Multiplex streams through the filter (currently four). One sample is
-- processed every four clock cycles, i.e., each stream gets 1 every
-- 16 cycles. The provider of the data should have carried out the second order
-- summation; we do the second order differencing. We output
-- x(t)-x(t-236)-x(t-244)+x(t-480)
-- with a latency of four (?) clock cycles, and t incrementing once every 4
-- cycles.
--
-- Phase 0: acc = -x(t-59*4), start load x(t-120*4), output prev,
-- Phase 1: acc -= x(t-61*4), start load x(t).
-- Phase 2: acc += x(t-120*4), start load x(t-59*4+"+1").
-- Phase 3: acc += x(t), start load x(t-61*4+"+1").
-- Phase 0, index += 120*4.
-- Phase 1, index += "+1"-59*4
-- Phase 2, index += -2*4
-- Phase 3, index += -59*4
-- Note that the "+1" is +1 mod 4, but is either +5 or +1, choosen so that
-- floor(t/4) increments, so that the total increment over 16 cycles is +16.
-- We store 1 sample per cycle. In phase 0, make sure that the store pointer
-- is not conflicting with the read pointer.
entity multifilter is
port (dd : in four_mf_signed;
qq : out mf_signed;
qq_last : out std_logic;
Clk : in std_logic);
end;
architecture multifilter of multifilter is
subtype index_t is unsigned9;
type ram_t is array(0 to 511) of mf_signed;
signal ram : ram_t;
signal rambuf : mf_signed;
signal ramout : mf_signed;
signal index, windex : index_t;
signal data : mf_signed;
alias phase : unsigned2 is windex(1 downto 0);
alias switch : std_logic is index(0);
signal acc : mf_signed;
attribute keep of rambuf : signal is "true";
begin
process
begin
wait until rising_edge(clk);
rambuf <= ram(to_integer(index));
ramout <= rambuf;
phase <= phase + 1;
ram(to_integer(windex)) <= data;
case phase is
when "00" =>
qq <= acc;
-- The index has already advanced, so we are outputing the last
-- channel (3) when the index is on channel 0.
qq_last <= b2s(index(1 downto 0) = "00");
index(8 downto 2) <= index(8 downto 2) + 120;
windex(8 downto 2) <= index(8 downto 2);
acc <= -ramout;
data <= dd(1);
when "01" =>
index(8 downto 2) <= index(8 downto 2) - 59 + 1;
index(1 downto 0) <= index(1 downto 0) + 1;
acc <= acc - ramout;
data <= dd(2);
when "10" =>
index(8 downto 2) <= index(8 downto 2) - 2;
acc <= acc + ramout;
data <= dd(3);
when others => -- "11"
index(8 downto 2) <= index(8 downto 2) - 59;
acc <= acc + ramout;
data <= dd(0);
end case;
end process;
end multifilter;
|
----------------------------------------
-- Datapath : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 20/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ControlPath is
port (
clock, reset : in std_logic; -- clock and reset signals
RF_Write : out std_logic; -- Reg File write enable
MemRead, MemWrite : out std_logic; -- Read / Write from / to the data memory
OpSel, ALUc, ALUz, Cen, Zen, ALUop : out std_logic; -- ALU & Flag block signals
M1_Sel, M2_Sel, M5_Sel, M3_Sel : out std_logic; -- Mux select lines
M4_Sel, M6_Sel, M7_Sel, M8_Sel, M9_Sel : out std_logic_vector(1 downto 0); -- Mux select lines
Instruction : in std_logic_vector(15 downto 0) -- Instruction to the CP
);
end ControlPath;
architecture behave of ControlPath is
begin
main: process(Instruction,reset)
begin
if (reset='1') then
RF_Write <= '0';
MemRead <= '0';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '0';
ALUz <= '0';
Cen <= '0';
Zen <= '0';
ALUOp <='0';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <=b"00";
M5_Sel <='0';
M6_Sel <=b"00";
M7_Sel <=b"00";
M8_Sel <=b"00";
M9_Sel <=b"00";
elsif (Instruction(15 downto 12) =X"0" and Instruction(1 downto 0) =b"00" ) then -- ADD
RF_Write <= '1';
MemRead <= '0';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '0';
ALUz <= '0';
Cen <= '1';
Zen <= '1';
ALUOp <= '1';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <= b"01";
M5_Sel <='0';
M6_Sel <= b"00";
M7_Sel <= b"10";
M8_Sel <= b"01";
M9_Sel <=b"00";
elsif (Instruction(15 downto 12) =X"1") then -- ADI
RF_Write <= '1';
MemRead <= '0';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '0';
ALUz <= '0';
Cen <= '1';
Zen <= '1';
ALUOp <= '1';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <= b"01";
M5_Sel <='0';
M6_Sel <= b"00";
M7_Sel <= b"10";
M8_Sel <= b"00";
M9_Sel <=b"00";
elsif (Instruction(15 downto 12) =X"0" and Instruction(1 downto 0) =b"10" ) then -- ADC
RF_Write <= '0';
MemRead <= '0';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '1';
ALUz <= '0';
Cen <= '1';
Zen <= '1';
ALUOp <= '0';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <= b"01";
M5_Sel <='0';
M6_Sel <= b"00";
M7_Sel <= b"10";
M8_Sel <= b"01";
M9_Sel <=b"00";
elsif (Instruction(15 downto 12) =X"0" and Instruction(1 downto 0) =b"01" ) then -- ADZ
RF_Write <= '0';
MemRead <= '0';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '0';
ALUz <= '1';
Cen <= '1';
Zen <= '1';
ALUOp <= '0';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <= b"01";
M5_Sel <='0';
M6_Sel <= b"00";
M7_Sel <= b"10";
M8_Sel <= b"01";
M9_Sel <=b"00";
elsif (Instruction(15 downto 12) =X"4") then
RF_Write <= '1';
MemRead <= '1';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '0';
ALUz <= '0';
Cen <= '0';
Zen <= '0';
ALUOp <= '1';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <= b"00";
M5_Sel <='0';
M6_Sel <= b"00";
M7_Sel <= b"10";
M8_Sel <= b"00";
M9_Sel <=b"00";
elsif (Instruction(15 downto 12) =X"6") then
RF_Write <= '0';
MemRead <= '0';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '0';
ALUz <= '0';
Cen <= '0';
Zen <= '0';
ALUOp <= '1';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <= b"00";
M5_Sel <='0';
M6_Sel <= b"00";
M7_Sel <= b"00";
M8_Sel <= b"00";
M9_Sel <=b"00";
elsif (Instruction(15 downto 12) =X"7") then
RF_Write <= '0';
MemRead <= '0';
MemWrite <= '0';
OpSel <= '0';
ALUc <= '0';
ALUz <= '0';
Cen <= '0';
Zen <= '0';
ALUOp <= '1';
M1_Sel <= '0';
M2_Sel <='0';
M3_Sel <='0';
M4_Sel <= b"00";
M5_Sel <='0';
M6_Sel <= b"00";
M7_Sel <= b"00";
M8_Sel <= b"00";
M9_Sel <=b"00";
end if;
end process main;
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Mod5Seu is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
SEUimm32 : out STD_LOGIC_VECTOR (31 downto 0)
);
end Mod5Seu;
architecture Behavioral of Mod5Seu is
begin
process (imm13)
begin
if imm13(12) = '1' then
SEUimm32 <= "1111111111111111111" & imm13;
else
SEUimm32 <= "0000000000000000000" & imm13;
end if;
end process;
end Behavioral;
|
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`protect end_protected
|
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: gudilkoalex@gmail.com
--
-- File: BCD_DECODER.vhd
-- File history:
-- <1.2>: <02/04/2015>: <added thousands and tens-thousands digits. MAX 65536 decimal>
-- <1.3>: <02/04/2015>: <MAX 131071 decimal>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Decode 16 bit input integer (max 99.999) into 5 digits in BCD code
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bcd_5dig is
Port (
number : in std_logic_vector (16 downto 0);
tensthousands : out std_logic_vector (3 downto 0);
thousands : out std_logic_vector (3 downto 0);
hundreds : out std_logic_vector (3 downto 0);
tens : out std_logic_vector (3 downto 0);
ones : out std_logic_vector (3 downto 0)
);
end bcd_5dig;
architecture Behavioral of bcd_5dig is
begin
bin_to_bcd : process (number)
-- Internal variable for storing bits
variable shift : unsigned(36 downto 0);
-- Alias for parts of shift register
alias num is shift(16 downto 0);
alias one is shift(20 downto 17);
alias ten is shift(24 downto 21);
alias hun is shift(28 downto 25);
alias thous is shift(32 downto 29);
alias tensthous is shift(36 downto 33);
--alias num is shift(7 downto 0);
--alias one is shift(11 downto 8);
--alias ten is shift(15 downto 12);
--alias hun is shift(19 downto 16);
--alias thous is shift(19 downto 16);
--alias tensthous is shift(19 downto 16);
begin
-- Clear previous number and store new number in shift register
num := unsigned(number);
one := X"0";
ten := X"0";
hun := X"0";
thous := X"0";
tensthous := X"0";
-- Loop eight times
for i in 1 to num'Length loop
-- Check if any digit is greater than or equal to 5
if one >= 5 then
one := one + 3;
end if;
if ten >= 5 then
ten := ten + 3;
end if;
if hun >= 5 then
hun := hun + 3;
end if;
if thous >= 5 then
thous := thous + 3;
end if;
if tensthous >= 5 then
tensthous := tensthous + 3;
end if;
-- Shift entire register left once
shift := shift_left(shift, 1);
end loop;
-- Push decimal numbers to output
tensthousands <= std_logic_vector(tensthous);
thousands <= std_logic_vector(thous);
hundreds <= std_logic_vector(hun);
tens <= std_logic_vector(ten);
ones <= std_logic_vector(one);
end process;
end Behavioral;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XORGATE IS
PORT( A,B:IN STD_LOGIC;
C:OUT STD_LOGIC);
END XORGATE;
ARCHITECTURE XORG OF XORGATE IS
BEGIN
C <= A XOR B;
END XORG;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
--entity rom_test01 is
entity duper_cartridge is
port (
pi_reset_n : in std_logic;
pi_base_clk : in std_logic;
--nes side
pi_phi2 : in std_logic;
--prgrom
pi_prg_ce_n : in std_logic;
pi_prg_r_nw : in std_logic;
pi_prg_addr : in std_logic_vector(14 downto 0);
pio_prg_data : inout std_logic_vector(7 downto 0);
--chrrom
pi_chr_ce_n : in std_logic;
pi_chr_oe_n : in std_logic;
pi_chr_we_n : in std_logic;
pi_chr_addr : in std_logic_vector(12 downto 0);
po_chr_data : out std_logic_vector(7 downto 0);
--i2c side
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
--bbb gpio
po_nes_f_full : out std_logic;
po_bbb_f_empty : out std_logic;
po_dbg_cnt : out std_logic_vector (63 downto 0)
);
--end rom_test01;
end duper_cartridge;
--architecture rtl of rom_test01 is
architecture rtl of duper_cartridge is
-------------------------------------------
-------------------------------------------
------------- definitions.... -------------
-------------------------------------------
-------------------------------------------
component synchronizer port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_async_input : in std_logic;
po_sync_output : out std_logic
);
end component;
component synchronized_vector
generic (abus_size : integer := 8);
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_async_input : in std_logic_vector(abus_size - 1 downto 0);
po_sync_output : out std_logic_vector(abus_size - 1 downto 0)
);
end component;
component prg_rom port (
pi_base_clk : in std_logic;
pi_ce_n : in std_logic;
pi_oe_n : in std_logic;
pi_addr : in std_logic_vector (14 downto 0);
po_data : out std_logic_vector (7 downto 0)
);
end component ;
component chr_rom port (
pi_base_clk : in std_logic;
pi_ce_n : in std_logic;
pi_oe_n : in std_logic;
pi_addr : in std_logic_vector (12 downto 0);
po_data : out std_logic_vector (7 downto 0)
);
end component;
component i2c_slave
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
---i2c bus lines...
pi_slave_addr : in std_logic_vector (6 downto 0);
pi_i2c_scl : in std_logic;
pi_i2c_sda : in std_logic;
po_i2c_sda : out std_logic;
---i2c bus contoler internal lines...
pi_i2c_read_data : in std_logic_vector (7 downto 0);
po_i2c_write_data : out std_logic_vector (7 downto 0);
po_i2c_status : out std_logic_vector (3 downto 0)
);
end component;
component fifo
generic (abus_size : integer := 8);
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_ce_n : in std_logic;
pi_oe_n : in std_logic;
pi_push_n : in std_logic;
pi_pop_n : in std_logic;
pi_data : in std_logic_vector (7 downto 0);
po_data : out std_logic_vector (7 downto 0);
po_stat_empty : out std_logic;
po_stat_full : out std_logic
);
end component;
---fifo status register
---bit
---7 always 0
---6 always 0
---5 read fifo full
---4 read fifo empty
---3 always 0
---2 always 0
---1 write fifo full
---0 write fifo empty
constant wfifo_empty_bit : integer := 0;
constant wfifo_full_bit : integer := 1;
constant rfifo_empty_bit : integer := 4;
constant rfifo_full_bit : integer := 5;
type duper_state_machine is (
idle,
rom_read,
rom_read_ok,
fifo_status_read,
nes_fifo_read,
nes_fifo_pop,
nes_fifo_read_ok,
nes_fifo_write,
nes_fifo_push,
nes_fifo_write_ok,
bbb_fifo_read,
bbb_fifo_pop,
bbb_fifo_read_ok,
bbb_fifo_write,
bbb_fifo_push,
bbb_fifo_write_ok
);
constant DATA_DELAY : integer := 18;
-------------------------------------------
-------------------------------------------
------------- declarations... -------------
-------------------------------------------
-------------------------------------------
--synchronized input.
--nes side
--signal reg_phi2 : std_logic;
signal reg_prg_ce_n : std_logic;
signal reg_prg_r_nw : std_logic;
signal reg_prg_addr : std_logic_vector(14 downto 0);
signal reg_prg_data_in : std_logic_vector(7 downto 0);
signal reg_chr_ce_n : std_logic;
signal reg_chr_oe_n : std_logic;
--signal reg_chr_we_n : std_logic;
signal reg_chr_addr : std_logic_vector(12 downto 0);
--bbb side
signal reg_i2c_scl : std_logic;
signal reg_i2c_sda_in : std_logic;
signal wr_prg_data_out : std_logic_vector(7 downto 0);
signal reg_prg_data_out : std_logic_vector(7 downto 0);
--duper state machine..
signal reg_cur_state : duper_state_machine;
signal reg_next_state : duper_state_machine;
signal reg_delay_cnt : integer range 0 to 31;
--prgrom reg
signal reg_prom_oe_n : std_logic;
--read fifo registers.
signal reg_ififo_ce_n : std_logic;
signal reg_ififo_oe_n : std_logic;
signal reg_ififo_push_n : std_logic;
signal reg_ififo_pop_n : std_logic;
signal reg_ififo_status : std_logic_vector (7 downto 0);
signal wr_ififo_empty : std_logic;
signal wr_ififo_full : std_logic;
signal wr_ififo_data : std_logic_vector (7 downto 0);
--write fifo registers.
signal reg_ofifo_ce_n : std_logic;
signal reg_ofifo_oe_n : std_logic;
signal reg_ofifo_push_n : std_logic;
signal reg_ofifo_pop_n : std_logic;
signal reg_ofifo_status : std_logic_vector (7 downto 0);
signal wr_ofifo_empty : std_logic;
signal wr_ofifo_full : std_logic;
signal wr_ofifo_data : std_logic_vector (7 downto 0);
--i2c registers.
signal wr_i2c_sda_out : std_logic;
signal wr_i2c_in_data : std_logic_vector (7 downto 0);
signal reg_i2c_rd_done : integer range 0 to 1;
signal reg_i2c_wr_done : integer range 0 to 1;
---po_i2c_status(3): '1' = bus transfering, '0' = stopped.
---po_i2c_status(2): '1' = read, '0' = write.
---po_i2c_status(1): '1' = data acknowleged, '0' = not acknowleged.
---po_i2c_status(0): '1' = addr acknowleged, '0' = not acknowleged.
signal wr_i2c_status : std_logic_vector (3 downto 0);
------------misc regs.
signal reg_dbg_cnt : std_logic_vector (63 downto 0);
-------------------------------------------
-------------------------------------------
------------ implementations... -----------
-------------------------------------------
-------------------------------------------
begin
--async input to be aligned to the base clock...
-- sync00 : synchronizer port map (pi_reset_n, pi_base_clk, pi_phi2, reg_phi2);
sync01 : synchronizer port map (pi_reset_n, pi_base_clk, pi_prg_ce_n, reg_prg_ce_n);
sync02 : synchronizer port map (pi_reset_n, pi_base_clk, pi_prg_r_nw, reg_prg_r_nw);
sync03 : synchronizer port map (pi_reset_n, pi_base_clk, pi_chr_ce_n, reg_chr_ce_n);
sync04 : synchronizer port map (pi_reset_n, pi_base_clk, pi_chr_oe_n, reg_chr_oe_n);
-- sync05 : synchronizer port map (pi_reset_n, pi_base_clk, pi_chr_we_n, reg_chr_we_n);
sync06 : synchronizer port map (pi_reset_n, pi_base_clk, pi_i2c_scl, reg_i2c_scl);
sync07 : synchronizer port map (pi_reset_n, pi_base_clk, pio_i2c_sda, reg_i2c_sda_in);
sync10 : synchronized_vector generic map (15) port map (pi_reset_n, pi_base_clk, pi_prg_addr, reg_prg_addr);
sync11 : synchronized_vector generic map (8) port map (pi_reset_n, pi_base_clk, pio_prg_data, reg_prg_data_in);
sync12 : synchronized_vector generic map (13) port map (pi_reset_n, pi_base_clk, pi_chr_addr, reg_chr_addr);
--base clock synchronized registers...
reg_p : process (pi_base_clk, pi_reset_n)
begin
if (pi_reset_n = '0') then
reg_ififo_status <= "00010001";
elsif (rising_edge(pi_base_clk)) then
reg_ififo_status(7 downto 6) <= (others => '0');
reg_ififo_status(rfifo_full_bit) <= wr_ififo_full;
reg_ififo_status(rfifo_empty_bit) <= wr_ififo_empty;
reg_ififo_status(3 downto 2) <= (others => '0');
reg_ififo_status(wfifo_full_bit) <= wr_ofifo_full;
reg_ififo_status(wfifo_empty_bit) <= wr_ofifo_empty;
end if;
end process;
po_nes_f_full <= reg_ififo_status(rfifo_full_bit);
po_bbb_f_empty <= reg_ififo_status(wfifo_empty_bit);
--state transition process...
set_stat_p : process (pi_reset_n, pi_base_clk)
begin
if (pi_reset_n = '0') then
reg_cur_state <= idle;
elsif (rising_edge(pi_base_clk)) then
reg_cur_state <= reg_next_state;
end if;--if (pi_rst_n = '0') then
end process;
--cpu data wait proc...
delay_cnt_p : process (pi_reset_n, pi_base_clk)
begin
if (pi_reset_n = '0') then
reg_delay_cnt <= 0;
elsif (rising_edge(pi_base_clk)) then
if (reg_cur_state = bbb_fifo_write) then
reg_delay_cnt <= reg_delay_cnt + 1;
else
reg_delay_cnt <= 0;
end if;
end if;--if (pi_rst_n = '0') then
end process;
--state change to next.
vac_next_stat_p : process (reg_cur_state, reg_prg_ce_n, reg_prg_r_nw, reg_prg_addr, wr_i2c_status,
reg_i2c_rd_done, reg_i2c_wr_done, reg_delay_cnt)
begin
case reg_cur_state is
when idle =>
--rom read 0x7ff9: fifo read.
if (reg_prg_ce_n = '0' and reg_prg_r_nw = '1' and reg_prg_addr = "111111111111001") then
reg_next_state <= nes_fifo_read;
--rom write 0x7ff9: fifo write.
elsif (reg_prg_ce_n = '0' and reg_prg_r_nw = '0' and reg_prg_addr = "111111111111001") then
reg_next_state <= bbb_fifo_write;
--rom read 0x7ff8: fifo status read.
elsif (reg_prg_ce_n = '0' and reg_prg_r_nw = '1' and reg_prg_addr = "111111111111000") then
reg_next_state <= fifo_status_read;
--other rom read.
elsif (reg_prg_ce_n = '0' and reg_prg_r_nw = '1') then
reg_next_state <= rom_read;
else
--no rom access...
---po_i2c_status(3): '1' = bus transfering, '0' = stopped.
---po_i2c_status(2): '1' = read, '0' = write.
---po_i2c_status(1): '1' = data acknowleged, '0' = not acknowleged.
---po_i2c_status(0): '1' = addr acknowleged, '0' = not acknowleged.
if (wr_i2c_status(1) = '1' and wr_i2c_status(2) = '0') then
--case bbb push fifo.
if (reg_i2c_wr_done = 0) then
reg_next_state <= nes_fifo_write;
else
reg_next_state <= idle;
end if;
elsif (wr_i2c_status(1) = '1' and wr_i2c_status(2) = '1') then
--case bbb pop fifo.
if (reg_i2c_rd_done = 0) then
reg_next_state <= bbb_fifo_read;
else
reg_next_state <= idle;
end if;
else
reg_next_state <= idle;
end if;
end if;
when rom_read =>
reg_next_state <= rom_read_ok;
when rom_read_ok =>
if (reg_prg_ce_n = '0' and reg_prg_r_nw = '1' and reg_prg_addr(14 downto 1) /= "11111111111100") then
reg_next_state <= rom_read_ok;
else
reg_next_state <= idle;
end if;
when fifo_status_read =>
if (reg_prg_ce_n = '0' and reg_prg_r_nw = '1' and reg_prg_addr = "111111111111000") then
reg_next_state <= fifo_status_read;
else
reg_next_state <= idle;
end if;
when nes_fifo_read =>
reg_next_state <= nes_fifo_pop;
when nes_fifo_pop =>
reg_next_state <= nes_fifo_read_ok;
when nes_fifo_read_ok =>
if (reg_prg_ce_n = '0' and reg_prg_r_nw = '1' and reg_prg_addr = "111111111111001") then
reg_next_state <= nes_fifo_read_ok;
else
reg_next_state <= idle;
end if;
when nes_fifo_write =>
reg_next_state <= nes_fifo_push;
when nes_fifo_push =>
reg_next_state <= nes_fifo_write_ok;
when nes_fifo_write_ok =>
reg_next_state <= idle;
when bbb_fifo_read =>
reg_next_state <= bbb_fifo_pop;
when bbb_fifo_pop =>
reg_next_state <= bbb_fifo_read_ok;
when bbb_fifo_read_ok =>
reg_next_state <= idle;
when bbb_fifo_write =>
if (reg_delay_cnt < DATA_DELAY) then
--wait for data to be available.
reg_next_state <= bbb_fifo_write;
else
reg_next_state <= bbb_fifo_push;
end if;
when bbb_fifo_push =>
reg_next_state <= bbb_fifo_write_ok;
when bbb_fifo_write_ok =>
if (reg_prg_ce_n = '0' and reg_prg_r_nw = '0' and reg_prg_addr = "111111111111001") then
reg_next_state <= bbb_fifo_write_ok;
else
reg_next_state <= idle;
end if;
end case;
end process;
push_handle_p : process (pi_reset_n, pi_base_clk)
begin
if (pi_reset_n = '0') then
reg_i2c_rd_done <= 0;
reg_i2c_wr_done <= 0;
elsif (rising_edge(pi_base_clk)) then
if (wr_i2c_status(1) = '0') then
reg_i2c_wr_done <= 0;
elsif (reg_cur_state = nes_fifo_push) then
reg_i2c_wr_done <= 1;
end if;
---po_i2c_status(3): '1' = bus transfering, '0' = stopped.
---po_i2c_status(2): '1' = read, '0' = write.
---po_i2c_status(1): '1' = data acknowleged, '0' = not acknowleged.
---po_i2c_status(0): '1' = addr acknowleged, '0' = not acknowleged.
if (reg_cur_state = bbb_fifo_pop) then
reg_i2c_rd_done <= 1;
elsif (reg_cur_state = idle and (wr_i2c_status(1) = '0')) then
reg_i2c_rd_done <= 0;
end if;
end if;--if (pi_rst_n = '0') then
end process;
--each register setting..
regs_p : process (pi_reset_n, pi_base_clk)
begin
if (pi_reset_n = '0') then
reg_prom_oe_n <= '1';
reg_ififo_ce_n <= '1';
reg_ififo_oe_n <= '1';
reg_ififo_push_n <= '1';
reg_ififo_pop_n <= '1';
reg_ofifo_ce_n <= '1';
reg_ofifo_oe_n <= '1';
reg_ofifo_push_n <= '1';
reg_ofifo_pop_n <= '1';
elsif (rising_edge(pi_base_clk)) then
case reg_cur_state is
when idle =>
reg_prom_oe_n <= '0';
reg_ififo_ce_n <= '0';
reg_ififo_oe_n <= '0';
reg_ififo_push_n <= '1';
reg_ififo_pop_n <= '1';
reg_ofifo_ce_n <= '0';
reg_ofifo_oe_n <= '0';
reg_ofifo_push_n <= '1';
reg_ofifo_pop_n <= '1';
when rom_read =>
when rom_read_ok =>
when fifo_status_read =>
when nes_fifo_read =>
reg_ififo_pop_n <= '1';
when nes_fifo_pop =>
reg_ififo_pop_n <= '0';
when nes_fifo_read_ok =>
reg_ififo_pop_n <= '1';
when nes_fifo_write =>
reg_ififo_push_n <= '1';
when nes_fifo_push =>
reg_ififo_push_n <= '0';
when nes_fifo_write_ok =>
reg_ififo_push_n <= '1';
when bbb_fifo_read =>
reg_ofifo_pop_n <= '1';
when bbb_fifo_pop =>
reg_ofifo_pop_n <= '0';
when bbb_fifo_read_ok =>
reg_ofifo_pop_n <= '1';
when bbb_fifo_write =>
reg_ofifo_push_n <= '1';
when bbb_fifo_push =>
reg_ofifo_push_n <= '0';
when bbb_fifo_write_ok =>
reg_ofifo_push_n <= '1';
end case;
end if;--if (pi_rst_n = '0') then
end process;
--prg rom
pio_prg_data <= reg_prg_data_out;
set_nes_out_p : process (pi_reset_n, pi_base_clk)
variable tmp_fifo : std_logic_vector(7 downto 0);
begin
if (pi_reset_n = '0') then
reg_prg_data_out <= (others => 'Z');
tmp_fifo := (others => '0');
elsif (rising_edge(pi_base_clk)) then
case reg_cur_state is
when rom_read_ok =>
reg_prg_data_out <= wr_prg_data_out;
when fifo_status_read =>
reg_prg_data_out <= reg_ififo_status;
when nes_fifo_read =>
reg_prg_data_out <= wr_ififo_data;
tmp_fifo := wr_ififo_data;
when nes_fifo_pop =>
reg_prg_data_out <= tmp_fifo;
when nes_fifo_read_ok =>
reg_prg_data_out <= tmp_fifo;
when others =>
reg_prg_data_out <= (others => 'Z');
end case;
end if;--if (pi_rst_n = '0') then
end process;
prom_inst : prg_rom port map (
pi_base_clk,
reg_prg_ce_n,
reg_prom_oe_n,
reg_prg_addr,
wr_prg_data_out
);
--i2c incoming fifo.
rd_fifo_inst : fifo generic map (8)
port map (
pi_reset_n,
pi_base_clk,
reg_ififo_ce_n,
reg_ififo_oe_n,
reg_ififo_push_n,
reg_ififo_pop_n,
wr_i2c_in_data,
wr_ififo_data,
wr_ififo_empty,
wr_ififo_full
);
--i2c outgoing fifo.
wr_fifo_inst : fifo generic map (8)
port map (
pi_reset_n,
pi_base_clk,
reg_ofifo_ce_n,
reg_ofifo_oe_n,
reg_ofifo_push_n,
reg_ofifo_pop_n,
reg_prg_data_in,
wr_ofifo_data,
wr_ofifo_empty,
wr_ofifo_full
);
--i2c slave
i2c_slave_inst : i2c_slave
port map (
pi_reset_n,
pi_base_clk,
conv_std_logic_vector(16#44#, 7),
reg_i2c_scl,
reg_i2c_sda_in,
wr_i2c_sda_out,
wr_ofifo_data,
wr_i2c_in_data,
wr_i2c_status
);
pio_i2c_sda <= wr_i2c_sda_out;
--character rom
crom_inst : chr_rom port map (
pi_base_clk,
reg_chr_ce_n,
reg_chr_oe_n,
reg_chr_addr,
po_chr_data
);
----------------------------------------------------------------------
----------------------------------------------------------------------
-------------------------- misc processes.... ------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
po_dbg_cnt <= reg_dbg_cnt;
deb_cnt_p : process (pi_base_clk, pi_reset_n)
use ieee.std_logic_unsigned.all;
begin
if (pi_reset_n = '0') then
reg_dbg_cnt <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
reg_dbg_cnt <= reg_dbg_cnt + 1;
end if;
end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc605.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00605ent IS
END c03s04b01x00p01n01i00605ent;
ARCHITECTURE c03s04b01x00p01n01i00605arch OF c03s04b01x00p01n01i00605ent IS
constant C4 : severity_level := note;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_st is severity_level_vector(0 to 15);
type severity_level_vector_st_file is file of severity_level_vector_st;
constant C27 : severity_level_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : severity_level_vector_st_file open write_mode is "iofile.29";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00605 - The output file will be verified by test s010258.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00605arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc605.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00605ent IS
END c03s04b01x00p01n01i00605ent;
ARCHITECTURE c03s04b01x00p01n01i00605arch OF c03s04b01x00p01n01i00605ent IS
constant C4 : severity_level := note;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_st is severity_level_vector(0 to 15);
type severity_level_vector_st_file is file of severity_level_vector_st;
constant C27 : severity_level_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : severity_level_vector_st_file open write_mode is "iofile.29";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00605 - The output file will be verified by test s010258.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00605arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc605.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00605ent IS
END c03s04b01x00p01n01i00605ent;
ARCHITECTURE c03s04b01x00p01n01i00605arch OF c03s04b01x00p01n01i00605ent IS
constant C4 : severity_level := note;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_st is severity_level_vector(0 to 15);
type severity_level_vector_st_file is file of severity_level_vector_st;
constant C27 : severity_level_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : severity_level_vector_st_file open write_mode is "iofile.29";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00605 - The output file will be verified by test s010258.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00605arch;
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_receiver_double_flipflop is
generic(
N : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREQ_DATA : in vl_logic_vector;
oOUT_DATA : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of N : constant is 1;
end mist1032sa_uart_receiver_double_flipflop;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
--======================================================================================--
entity rgb2hsv_tb is
generic (
input_file: string := "tst/input/smpte_bars.pnm"; --! Input file of test
output_file: string := "tst/output/rgb2hsv_smpte_bars.pnm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight --! Height of input image
);
end entity;
--======================================================================================--
architecture structural of rgb2hsv_tb is
--===================component declaration===================--
component test_bench_driver_color is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 6
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
red_pixel_from_file: out std_logic_vector;
green_pixel_from_file: out std_logic_vector;
blue_pixel_from_file: out std_logic_vector;
red_pixel_to_file: in std_logic_vector;
green_pixel_to_file: in std_logic_vector;
blue_pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component rgb2hsv is
generic (
wordsize: integer := 8 --! input image wordsize in bits
);
port (
-- inputs
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_red_i: in std_logic_vector; --! the input pixel
pixel_green_i: in std_logic_vector; --! the input pixel
pixel_blue_i: in std_logic_vector; --! the input pixel
-- outputs
pixel_hue_o: out std_logic_vector;
pixel_sat_o: out std_logic_vector;
pixel_val_o: out std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal red_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver_color
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
red_pixel_from_file => red_pixel_from_file,
green_pixel_from_file => green_pixel_from_file,
blue_pixel_from_file => blue_pixel_from_file,
red_pixel_to_file => red_pixel_to_file,
green_pixel_to_file => green_pixel_to_file,
blue_pixel_to_file => blue_pixel_to_file
);
device_under_test: rgb2hsv
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_red_i => red_pixel_from_file,
pixel_green_i => green_pixel_from_file,
pixel_blue_i => blue_pixel_from_file,
pixel_hue_o => red_pixel_to_file,
pixel_sat_o => green_pixel_to_file,
pixel_val_o => blue_pixel_to_file
);
end architecture;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
--======================================================================================--
entity rgb2hsv_tb is
generic (
input_file: string := "tst/input/smpte_bars.pnm"; --! Input file of test
output_file: string := "tst/output/rgb2hsv_smpte_bars.pnm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight --! Height of input image
);
end entity;
--======================================================================================--
architecture structural of rgb2hsv_tb is
--===================component declaration===================--
component test_bench_driver_color is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 6
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
red_pixel_from_file: out std_logic_vector;
green_pixel_from_file: out std_logic_vector;
blue_pixel_from_file: out std_logic_vector;
red_pixel_to_file: in std_logic_vector;
green_pixel_to_file: in std_logic_vector;
blue_pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component rgb2hsv is
generic (
wordsize: integer := 8 --! input image wordsize in bits
);
port (
-- inputs
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_red_i: in std_logic_vector; --! the input pixel
pixel_green_i: in std_logic_vector; --! the input pixel
pixel_blue_i: in std_logic_vector; --! the input pixel
-- outputs
pixel_hue_o: out std_logic_vector;
pixel_sat_o: out std_logic_vector;
pixel_val_o: out std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal red_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver_color
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
red_pixel_from_file => red_pixel_from_file,
green_pixel_from_file => green_pixel_from_file,
blue_pixel_from_file => blue_pixel_from_file,
red_pixel_to_file => red_pixel_to_file,
green_pixel_to_file => green_pixel_to_file,
blue_pixel_to_file => blue_pixel_to_file
);
device_under_test: rgb2hsv
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_red_i => red_pixel_from_file,
pixel_green_i => green_pixel_from_file,
pixel_blue_i => blue_pixel_from_file,
pixel_hue_o => red_pixel_to_file,
pixel_sat_o => green_pixel_to_file,
pixel_val_o => blue_pixel_to_file
);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_2to1 is
Port ( SEL : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
X : out STD_LOGIC_VECTOR (31 downto 0));
end mux_2to1;
architecture Behavioral of mux_2to1 is
begin
X <= A when (SEL = '1') else B;
end Behavioral;
|
end;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ctrlif is
generic
(
C_NUM_REG : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_FAMILY : string := "virtex6"
);
port
(
-- AXI bus interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
rd_addr : out integer range 0 to C_NUM_REG - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
rd_stb : in std_logic;
wr_addr : out integer range 0 to C_NUM_REG - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_ack : in std_logic;
wr_stb : out std_logic
);
end entity axi_ctrlif;
architecture Behavioral of axi_ctrlif is
type state_type is (IDLE, RESP, ACK);
signal rd_state : state_type;
signal wr_state : state_type;
begin
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
rd_state <= IDLE;
else
case rd_state is
when IDLE =>
if S_AXI_ARVALID = '1' then
rd_state <= RESP;
rd_addr <= to_integer(unsigned(S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH-1 downto 2)));
end if;
when RESP =>
if rd_stb = '1' and S_AXI_RREADY = '1' then
rd_state <= IDLE;
end if;
when others => null;
end case;
end if;
end if;
end process;
S_AXI_ARREADY <= '1' when rd_state = IDLE else '0';
S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0';
S_AXI_RRESP <= "00";
rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0';
S_AXI_RDATA <= rd_data;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
wr_state <= IDLE;
else
case wr_state is
when IDLE =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then
wr_state <= ACK;
end if;
when ACK =>
wr_state <= RESP;
when RESP =>
if S_AXI_BREADY = '1' then
wr_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0';
wr_data <= S_AXI_WDATA;
wr_addr <= to_integer(unsigned(S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH-1 downto 2)));
S_AXI_AWREADY <= '1' when wr_state = ACK else '0';
S_AXI_WREADY <= '1' when wr_state = ACK else '0';
S_AXI_BRESP <= "00";
S_AXI_BVALID <= '1' when wr_state = RESP else '0';
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register4 is
Port (
d : in STD_LOGIC_VECTOR(3 downto 0) := "0000"; --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(3 downto 0) :="0000" --Output
);
end Register4;
architecture Behavioral of Register4 is
begin
process(clk, clr)
begin
if rising_edge(clk) then
if clr = '1' then
q <= "0000";
elsif load = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral; |
---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <fabien.marteau@armadeus.com>
--
-- Creation Date : 03/09/2008
-- File : simplegpio.vhd
--
-- Abstract :
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity simplegpio is
---------------------------------------------------------------------------
generic(
id : natural := 3; -- identify id
size : natural := 16 -- wishbone data size 8,16 or 32
);
port
(
-- clock and reset
clk_i : in std_logic ; -- master clock input
rst_i : in std_logic ; -- asynchronous reset
-- wishbone
adr_i : in std_logic_vector( 1 downto 0);
dat_i : in std_logic_vector( size-1 downto 0);
dat_o : out std_logic_vector( size-1 downto 0);
we_i : in std_logic ;
stb_i : in std_logic ;
ack_o : out std_logic ;
cyc_i : in std_logic;
-- gpio
gpio : inout std_logic_vector( size-1 downto 0)
);
end entity;
---------------------------------------------------------------------------
Architecture simplegpio_1 of simplegpio is
---------------------------------------------------------------------------
signal write_register : std_logic_vector( size-1 downto 0);
signal ctrl_register : std_logic_vector( size-1 downto 0);
signal rd_ack : std_logic ;
signal wr_ack : std_logic ;
begin
-- register reading process
process(clk_i, rst_i)
begin
if(rst_i = '1') then
dat_o <= (others => '0');
rd_ack <= '0';
elsif(rising_edge(clk_i)) then
rd_ack <= '0';
if(stb_i = '1' and we_i = '0' and cyc_i = '1') then
rd_ack <= '1';
if(adr_i = "00") then
dat_o <= gpio;
elsif(adr_i = "01") then
dat_o <= ctrl_register;
elsif(adr_i = "10") then
dat_o <= std_logic_vector(to_unsigned(id,size));
else
dat_o <= (others => '0');
end if;
end if;
end if;
end process;
-- register write process
process(clk_i,rst_i)
begin
if(rst_i = '1') then
ctrl_register <= (others => '0');
write_register <= (others => '0');
wr_ack <= '0';
elsif(rising_edge(clk_i)) then
wr_ack <= '0';
if(stb_i = '1' and we_i = '1' and cyc_i = '1') then
wr_ack <= '1';
if(adr_i = "00") then
write_register <= dat_i;
elsif(adr_i = "01") then
ctrl_register <= dat_i;
end if;
end if;
end if;
end process;
-- acknowledge
ack_o <= rd_ack or wr_ack;
-- gpio write
gpiogen : for i in 0 to (size-1) generate
gpio(i) <= write_register(i) when ctrl_register(i) = '1' else 'Z';
end generate;
end architecture simplegpio_1;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_sin_taylor_ser is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Block_sin_taylor_ser is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal grp_fu_18_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_18_ce : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_return_preg : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component sin_taylor_seriesfYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesfYi_U12 : component sin_taylor_seriesfYi
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => p_read,
din1 => p_read1,
ce => grp_fu_18_ce,
dout => grp_fu_18_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv64_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return_preg <= grp_fu_18_p2;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(grp_fu_18_p2, ap_CS_fsm_state5, ap_return_preg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return <= grp_fu_18_p2;
else
ap_return <= ap_return_preg;
end if;
end process;
grp_fu_18_ce_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1)))) then
grp_fu_18_ce <= ap_const_logic_0;
else
grp_fu_18_ce <= ap_const_logic_1;
end if;
end process;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_sin_taylor_ser is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Block_sin_taylor_ser is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal grp_fu_18_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_18_ce : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_return_preg : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component sin_taylor_seriesfYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesfYi_U12 : component sin_taylor_seriesfYi
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => p_read,
din1 => p_read1,
ce => grp_fu_18_ce,
dout => grp_fu_18_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv64_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return_preg <= grp_fu_18_p2;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(grp_fu_18_p2, ap_CS_fsm_state5, ap_return_preg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return <= grp_fu_18_p2;
else
ap_return <= ap_return_preg;
end if;
end process;
grp_fu_18_ce_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1)))) then
grp_fu_18_ce <= ap_const_logic_0;
else
grp_fu_18_ce <= ap_const_logic_1;
end if;
end process;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_sin_taylor_ser is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Block_sin_taylor_ser is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal grp_fu_18_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_18_ce : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_return_preg : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component sin_taylor_seriesfYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesfYi_U12 : component sin_taylor_seriesfYi
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => p_read,
din1 => p_read1,
ce => grp_fu_18_ce,
dout => grp_fu_18_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv64_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return_preg <= grp_fu_18_p2;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(grp_fu_18_p2, ap_CS_fsm_state5, ap_return_preg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return <= grp_fu_18_p2;
else
ap_return <= ap_return_preg;
end if;
end process;
grp_fu_18_ce_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1)))) then
grp_fu_18_ce <= ap_const_logic_0;
else
grp_fu_18_ce <= ap_const_logic_1;
end if;
end process;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_sin_taylor_ser is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end;
architecture behav of Block_sin_taylor_ser is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_block_state1 : BOOLEAN;
signal grp_fu_18_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_18_ce : STD_LOGIC;
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_return_preg : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component sin_taylor_seriesfYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
sin_taylor_seriesfYi_U12 : component sin_taylor_seriesfYi
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => p_read,
din1 => p_read1,
ce => grp_fu_18_ce,
dout => grp_fu_18_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv64_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return_preg <= grp_fu_18_p2;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state5)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(grp_fu_18_p2, ap_CS_fsm_state5, ap_return_preg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_return <= grp_fu_18_p2;
else
ap_return <= ap_return_preg;
end if;
end process;
grp_fu_18_ce_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1)))) then
grp_fu_18_ce <= ap_const_logic_0;
else
grp_fu_18_ce <= ap_const_logic_1;
end if;
end process;
end behav;
|
----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(31 downto 24);
signal pio : std_logic_vector(17 downto 0);
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal wdogn,wdogn_local : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal erx_dv, erx_dv_d, etx_en: std_logic:='0';
signal erxd, erxd_d, etxd: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdint : std_ulogic;
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic := '0';
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal clk2 : std_ulogic := '0';
signal clk125 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(9 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
signal erx_er : std_logic := '0';
signal erx_col : std_logic := '0';
signal erx_crs : std_logic := '1';
signal etx_er : std_logic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 10 ns;
--erx_clk <= not erx_clk after 4 ns;
clk2 <= '0'; --not clk2 after 5 ns;
rst <= dsurst and wdogn_local;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
wdogn_local <= 'H';
switch(7) <= '1';
switch(8) <= '0';
emdio <= 'H';
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk2, clk125, wdogn, address(24 downto 0), data,
oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_we, ddr_ras, ddr_csb ,ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio, genio,
switch, led, erx_clk, emdio, erxd(3 downto 0)'delayed(1 ns), erx_dv'delayed(1 ns), emdint,
etx_clk, etxd(3 downto 0), etx_en, emdc,
ps2clk, ps2data, iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn,
spi_sel_n, spi_clk, spi_mosi
);
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
ddr2mem : if (CFG_MIG_DDR2 = 1) generate
u1: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (340 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(
address => 1,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125);
end generate;
rcxclkp : process(erx_clk) is
begin
erxd <= erxd_d;
erx_dv <= erx_dv_d;
end process;
--wdognp : process
-- begin
-- wdogn_local <= 'H';
-- if wdogn = '0' then
-- wdogn_local <= '0';
-- wait for 1 ms;
-- end if;
-- wait for 20 ns;
-- end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 201 us;
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
iuerr : process
begin
wait until dsurst = '1';
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
--! @file reset_sequencer_ea.vhd
--! @brief Reset Sequencer for multiple reset signals
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-09-25
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--! @brief Reset Sequencer. Sequences reset signals and can check status signals.
--! @details
--! The reset sequencer is used to turn on a system in sequence, with the initial
--! asynchronous reset signal being debounced and then used to start a sequence
--! of turning off reset signals. Each signal has a time-out period, after
--! which it checks to see if the associated "check_good" line is high. If it
--! is, then the sequencer moves to turning off the next reset signal. If it is
--! not, then the system brings the reset high again for retry_time before
--! trying again. If the bit in move_fast associated with the reset signal is
--! high, then it will move to the next reset signal in sequence immediately
--! when the associated check_good signal is high.
--!
--! Sequence
--! 1. Come out of reset (rst goes to '0')
--! 2. Set first reset signal (rst_vector(0)) to '0'.
--! 3. If check_good(0) = '1' and move_fast(0) = '1', then repeat from step 2
--! with next signal. Else wait for wait_times(0).
--! 4. If check_good(0) = '1', then repeat from step 2 with next signal. Else
--! set rst_vector(0) to '1' and wait for retry_time before repeating from
--! step 2 with same signal.
--! 5. Sequence complete, set done = '1'
entity reset_sequencer is
generic (
clk_period : time := 20 ns; --! Period of clk signal
--! Vector of times to wait/timeout for each reset signal
wait_times : time_vector;
retry_time : time := 80 ns; --! Time to keep reset high while retrying
move_fast : std_logic_vector; --! If '1', go to next once check_good = '1'
debounce_time : time := 1 ms --! Time to wait before rst can change again
);
port (
clk : in std_logic; --! Reference clock
rst : in std_logic; --! Asynchronous reset
check_good : in std_logic_vector; --! Signals showing subsystems are ready
rst_vector : out std_logic_vector; --! Reset signals to subsystems
done : out std_logic --! Indicates sequencer is finished
);
end entity reset_sequencer;
architecture rtl of reset_sequencer is
type unsigned_vector is array(natural range <>) of unsigned;
function get_count(clk_period, count_time : time) return integer is
begin
assert count_time > clk_period
report "All wait_times must be > clk_period" severity error;
return (count_time / clk_period) + 1;
end function;
function get_counts(clk_period : time;
count_times : time_vector) return integer_vector is
variable counts : integer_vector(count_times'range);
begin
for i in count_times'range loop
counts(i) := get_count(clk_period, count_times(i));
end loop;
return counts;
end function;
function counter_width(count : integer) return integer is
begin
return integer(ceil(log2(real(count))));
end function;
function counter_widths(counts : integer_vector) return integer is
variable max_count : integer;
begin
max_count := 1;
for i in counts'range loop
max_count := maximum(max_count, counts(i));
end loop;
return counter_width(max_count);
end function;
function to_unsigned_vector(vals : integer_vector; width : positive)
return unsigned_vector is
variable unsigneds : unsigned_vector(vals'range)((width - 1) downto 0);
begin
for i in vals'range loop
unsigneds(i) := to_unsigned(vals(i), width);
end loop;
return unsigneds;
end function;
-- Debounce Counter Constants and signals
--! Value debounce counter will count down from
constant db_count_val : integer := get_count(clk_period, debounce_time);
--! Minimum possible width of debounce counter
constant db_counter_width : positive := counter_width(db_count_val);
--! Unsigned type value of db_count_val
constant db_counter_init : unsigned((db_counter_width - 1) downto 0) :=
to_unsigned(db_count_val, db_counter_width);
--! Debounce Counter register. Initialize to zero for simulation.
signal debounce_counter : unsigned((db_counter_width - 1) downto 0) :=
(others => '0');
-- Timer constants and signals
--! Values timer counter will count down from during sequencing
constant timer_vals : integer_vector := get_counts(clk_period, wait_times);
--! Value timer counter will count down from when retrying
constant retry_val : integer := get_count(clk_period, retry_time);
--! Minimum possible width of timer counter register
constant timer_width : positive := counter_widths(timer_vals & retry_val);
--! Unsigned type value of retry_val
constant retry_init : unsigned((timer_width - 1) downto 0) :=
to_unsigned(retry_val, timer_width);
--! Unsigned type values of timer_vals
constant timer_inits : unsigned_vector
(timer_vals'range)((timer_width - 1) downto 0) :=
to_unsigned_vector(timer_vals, timer_width);
--! Timer Register
signal timer : unsigned((timer_width - 1) downto 0);
--! rst synchronized to clk and debounced
signal sync_rst : std_logic;
constant reset_width : positive := counter_width(rst_vector'length);
--! Record current location in reset sequence
signal reset_stage : unsigned((reset_width - 1) downto 0);
--! Indicates if currently retrying a reset.
signal retry : std_logic;
begin
-- Verify all vectors are of equal length, otherwise the reset sequencer will
-- act in an unknown manner and probably will fail badly.
assert rst_vector'length = check_good'length
report "check_good not same length as rst_vector" severity error;
assert rst_vector'length = wait_times'length
report "wait_times not same length as rst_vector" severity error;
assert rst_vector'length = move_fast'length
report "move_fast not same length as rst_vector" severity error;
reset_sync : process(clk, rst) is
begin
if rising_edge(clk) then
if debounce_counter = to_unsigned(0, db_counter_width) then
if rst /= sync_rst then
debounce_counter <= db_counter_init;
sync_rst <= rst;
end if;
else
debounce_counter <= debounce_counter - 1;
end if;
end if;
end process;
boot_up : process(clk, sync_rst) is
begin
if rising_edge(clk) then
if sync_rst = '1' then
timer <= timer_inits(0);
reset_stage <= (others => '0');
retry <= '0';
done <= '0';
else
done <= '0';
timer <= timer - 1; -- Decrement unless overriden.
if retry <= '0' then
-- Go to next as soon as signal is good
if move_fast(to_integer(reset_stage)) = '1' then
-- System is good
if check_good(to_integer(reset_stage)) = '1' then
-- Check to see if done with sequence
if to_integer(reset_stage) = (rst_vector'length - 1) then
done <= '1';
timer <= (others => '0');
else
reset_stage <= reset_stage + 1;
timer <= timer_inits(to_integer(reset_stage) + 1);
end if;
else
-- Expired before it went good
if timer = to_unsigned(0, timer_width) then
timer <= retry_init;
reset_stage <= reset_stage - 1;
retry <= '1';
end if; -- timer
end if; -- check_good
-- Change state once timer expires
else
if timer = to_unsigned(0, timer_width) then
-- Next in sequence if check_good is good
if check_good(to_integer(reset_stage)) = '1' then
-- Check to see if doen with sequence
if to_integer(reset_stage) = (rst_vector'length - 1) then
done <= '1';
timer <= (others => '0');
else
reset_stage <= reset_stage + 1;
timer <= timer_inits(to_integer(reset_stage) + 1);
end if;
-- Retry if check_good is bad
else
reset_stage <= reset_stage - 1;
timer <= retry_init;
retry <= '1';
end if;
end if;
end if; -- move_fast
else -- retry = '1'
if timer = to_unsigned(0, timer_width) then
reset_stage <= reset_stage + 1;
timer <= timer_inits(to_integer(reset_stage) + 1);
retry <= '0';
end if;
end if; -- retry
end if; -- sync_rst
end if; -- clk
end process;
--! Sets reset vector according to what stage the reset sequencer is at.
set_resets : process(clk)
begin
if rising_edge(clk) then
if sync_rst = '1' then
rst_vector <= (rst_vector'range => '1');
else
for i in rst_vector'range loop
if reset_stage >= to_unsigned(i, reset_width) then
rst_vector(i) <= '1';
else
rst_vector(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
end rtl;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Delay signal through an N-stage shift register.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay is
generic (
-- Initial value of input signal
init_value_g : std_ulogic := '0';
-- Number of delay stages
num_delay_g : positive := 2);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Input signal
sig_i : in std_ulogic;
-- Delayed signal
dlyd_o : out std_ulogic);
end entity delay;
architecture rtl of delay is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal sig : std_ulogic_vector(num_delay_g - 1 downto 0) := (others => init_value_g);
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_sig : std_ulogic_vector(num_delay_g - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
dlyd_o <= sig(sig'high);
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Delay only for one clock cycle
single_delay_gen : if num_delay_g = 1 generate
next_sig(0) <= sig_i;
end generate single_delay_gen;
-- Delay for multiple clock cycles
multiple_delays_gen : if num_delay_g > 1 generate
next_sig <= sig(sig'high - 1 downto sig'low) & sig_i;
end generate multiple_delays_gen;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
sig <= (others => init_value_g);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
elsif en_i = '1' then
sig <= next_sig;
end if;
end if;
end process regs;
end architecture rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY name_detector IS
PORT (
b6, a, b, c, d, e: IN STD_LOGIC;
first_cond, last_cond, first_sel, last_sel: OUT STD_LOGIC);
END name_detector;
ARCHITECTURE selective_name OF name_detector IS
SIGNAL inputs: STD_LOGIC_VECTOR (5 DOWNTO 0);
BEGIN
inputs <= b6 & a & b & c & d & e;
WITH inputs SELECT
first_sel <= '1' WHEN "100011" | "100110" | "101100" | "101001",
'0' WHEN OTHERS;
WITH inputs SELECT
last_sel <= '1' WHEN "100001" | "100011" | "101101" | "101110" | "101000" | "110000",
'0' WHEN OTHERS;
first_cond <= '1' WHEN inputs = "100011" ELSE
'1' WHEN inputs = "100110" ELSE
'1' WHEN inputs = "101100" ELSE
'1' WHEN inputs = "101001" ELSE
'0';
last_cond <= '1' WHEN inputs = "100001" ELSE
'1' WHEN inputs = "100011" ELSE
'1' WHEN inputs = "101101" ELSE
'1' WHEN inputs = "101110" ELSE
'1' WHEN inputs = "101000" ELSE
'1' WHEN inputs = "110000" ELSE
'0';
END selective_name; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 2;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 16;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := 1;
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := 1;
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := 16;
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 1;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY default_entity IS
END ENTITY default_entity;
|
-------------------------------------------------------------------------------
-- Title : Delta-sigma with k multipliers
-- Project :
-------------------------------------------------------------------------------
-- File : delta_sigma_k.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-26
-- Last update: 2014-05-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Make delta-sigma calculations and multiply end result by K
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-26 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity delta_sigma_k is
generic (
g_input_width : natural := 16;
g_div_precision : natural := 16;
g_k_width : natural := 16;
g_output_width : natural := 16;
);
port (
a_i : in std_logic_vector(g_input_width-1 downto 0);
b_i : in std_logic_vector(g_input_width-1 downto 0);
c_i : in std_logic_vector(g_input_width-1 downto 0);
d_i : in std_logic_vector(g_input_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0);
sum_o : out std_logic_vector(g_width-1 downto 0)
);
end entity delta_sigma_k;
-------------------------------------------------------------------------------
architecture str of delta_sigma_k is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
begin -- architecture str
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
end architecture str;
-------------------------------------------------------------------------------
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.numeric_std.ALL;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY project_testbench IS
END project_testbench;
ARCHITECTURE behavior OF project_testbench IS
-- ------------------ Add Componenets ------------------
-- Add your components here
COMPONENT my_little_processor PORT (
clock, reset : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
flag_out : OUT STD_LOGIC;
done_out : OUT STD_LOGIC;
read_addr, main_bus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- ------------------ Add Componenets ------------------
-- cnt is for the testbench only, use to set test values for every clock cycle
signal cnt: integer:= 0;
-- Internal Signals
-- Your circuit will need clk and reset signals.
signal clk_in : STD_LOGIC:= '0';
signal reset_in: STD_LOGIC;
-- For the initial part, it will also need an assembly code input
signal code : std_logic_vector(22 downto 0);
-- For the testbench, the assembly code is 23 bits of the following form
-- Load: 3 bit operation code (000), 4-bit destination register (note x""
-- means hex, so for example, x"A" would mean register 10), then 16-bit data
-- value (note once again this is defined using hex. e.g x"12AB" would equal
-- "0001 0010 1010 1011")
-- mov: 3 bit operation code (001), 4-bit destination register, 4-bit input register, 12 unused bits
-- add: 3 bit operation code (010), 4-bit input and destination register, 4-bit input register, 12 unused bits
-- add: 3 bit operation code (011), 4-bit input and destination register, 4-bit input register, 12 unused bits
-- ldpc: 3 bit operation code (100), 4-bit destination register, 16 unused bits
-- branch: 3 bit operation code (101), 4-bit destination register, 16 unused bits
-- Feel free to create your own assembly code
-- ------------------ Add Your Internal Signals (if needed) ------------------
-- You may not need anything, you can design your processor to only
-- use clk_in, reset_in and (assembly) code signals.
-- If you instatiate multiple modules, you may need them
SIGNAL flag,done : STD_LOGIC;
SIGNAL read_addr : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL main_bus : STD_LOGIC_VECTOR(15 downto 0);
-- ------------------ Add Your Internal Signals (if needed) ------------------
BEGIN
instance0: my_little_processor PORT MAP(
clock => clk_in,
reset => reset_in,
flag_out => flag,
done_out => done,
read_addr => read_addr,
data_in => code(15 downto 0),
main_bus_out => main_bus
);
-- ------------------ Instantiate modules ------------------
-- Instantiate your processor here
-- ------------------ Instantiate modules ------------------
-- Create a clk
stim_proc: process
begin
wait for 50 ns;
clk_in <= not(clk_in);
end process;
-- cnt is for the testbench only, use to set test values for every clock cycle
stim_proc2: process(clk_in)
begin
if rising_edge(clk_in) then
cnt <= cnt+1;
end if;
end process;
-- This is the 'program'. It loads 4 values into r0 to r3.
-- It then stores the current address location in r4
-- It then branches to the 'sum' procedure, located at 50 in memory
-- To do this, the value 50 is loaded into r5, then you branch to r5.
-- After returning from branch, store the value in r6
-- (IMPORTANT: you can use this testbench irrespective of the branching,
-- just do nothing for these commands)
-- It then loads another 4 values into r0 to r3
-- Performs the sum of these values and returns
-- Finally it computes the xor of the two sums
process (cnt)
begin
case cnt is
-- Reset
when 0 to 4 => reset_in <= '1'; code <= ("000" & x"0" & x"0000");
-- load r0 x"0001"
when 5 to 9 => reset_in <= '0'; code <= ("000" & x"0" & x"0001");
-- load r1 x"0001"
when 10 to 14 => reset_in <= '0'; code <= ("000" & x"1" & x"0001");
-- load r2 x"0020"
when 15 to 19 => reset_in <= '0'; code <= ("000" & x"2" & x"0020");
-- load r3 x"0020"
when 20 to 24 => reset_in <= '0'; code <= ("000" & x"3" & x"0020");
-- load r5 x"0050"
when 25 to 29 => reset_in <= '0'; code <= ("000" & x"5" & x"0050");
-- ldpc r4
when 30 to 34 => reset_in <= '0'; code <= ("100" & x"4" & x"0000");
-- branch r5
when 35 to 39 => reset_in <= '0'; code <= ("101" & x"5" & x"0000");
-- add r0 r1
when 40 to 44 => reset_in <= '0'; code <= ("010" & x"0" & x"1" & x"000");
-- add r0 r2
when 45 to 49 => reset_in <= '0'; code <= ("010" & x"0" & x"2" & x"000");
-- add r0 r3
when 50 to 54 => reset_in <= '0'; code <= ("010" & x"0" & x"3" & x"000");
-- branch r4
when 55 to 59 => reset_in <= '0'; code <= ("101" & x"4" & x"0000");
-- mov r6 r0
when 60 to 64 => reset_in <= '0'; code <= ("001" & x"6" & x"0" & x"000");
-- load r0 x"0003"
when 65 to 69 => reset_in <= '0'; code <= ("000" & x"0" & x"0003");
-- load r1 x"0004"
when 70 to 74 => reset_in <= '0'; code <= ("000" & x"1" & x"0004");
-- load r2 x"001B"
when 75 to 79 => reset_in <= '0'; code <= ("000" & x"2" & x"001B");
-- load r3 x"0034"
when 80 to 84 => reset_in <= '0'; code <= ("000" & x"3" & x"0050");
-- ldpc r4
when 85 to 89 => reset_in <= '0'; code <= ("100" & x"4" & x"0000");
-- branch r5
when 90 to 94 => reset_in <= '0'; code <= ("101" & x"5" & x"0000");
-- add r0 r1
when 95 to 99 => reset_in <= '0'; code <= ("010" & x"0" & x"1" & x"000");
-- add r0 r2
when 100 to 104 => reset_in <= '0'; code <= ("010" & x"0" & x"2" & x"000");
-- add r0 r3
when 105 to 109 => reset_in <= '0'; code <= ("010" & x"0" & x"3" & x"000");
-- branch r4
when 110 to 114 => reset_in <= '0'; code <= ("101" & x"4" & x"0000");
-- xor r0 r6
when 115 to 120 => reset_in <= '0'; code <= ("001" & x"6" & x"0" & x"000");
when others => reset_in <= '0'; code <= ("001" & x"6" & x"0" & x"000");
end case;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eaa_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eaa_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:22 wig Exp $
-- $Date: 2004/04/06 10:50:22 $
-- $Log: inst_eaa_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:22 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eaa_e
--
architecture rtl of inst_eaa_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- The skip unit.
-- Skip conditions are checked here and communicated to the decoder unit.
--
-- $Id: t400_skip-c.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_skip_rtl_c0 of t400_skip is
for rtl
end for;
end t400_skip_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Merge is
Port (
CLK : in std_logic;
RST : in std_logic; -- low active
VALID_IN : in std_logic; -- high active
READY_IN : in std_logic;
IN_3 : in std_logic_vector(31 downto 0);
IN_2 : in std_logic_vector(31 downto 0);
IN_1 : in std_logic_vector(31 downto 0);
IN_0 : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic; -- high active
READY_OUT : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0)
);
end Merge;
architecture merge_behave of Merge is
begin
DATA_OUT <= IN_3(7 downto 0) & IN_2(7 downto 0) & IN_1(7 downto 0) & IN_0(7 downto 0);
VALID_OUT <= VALID_IN;
READY_OUT <= READY_IN;
end merge_behave;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 12-02-2016
-- Module Name: sr-latch_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity sr_latch_t is
end entity;
architecture arch_sr_latch_t of sr_latch_t is
signal s, r, q, q_not : std_logic;
begin
sr_latch_1 : entity work.sr_latch(arch_sr_latch) port map(s, r, q, q_not);
s <= '1', '0' after 5 ns, '0' after 10 ns, '1' after 15 ns;
r <= '0', '1' after 5 ns, '0' after 10 ns, '1' after 15 ns;
end architecture arch_sr_latch_t;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: FrameBuffer.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Standard Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity FrameBuffer is
port
(
data : in std_logic_vector (7 downto 0);
rdaddress : in std_logic_vector (14 downto 0);
rdclock : in std_logic;
wraddress : in std_logic_vector (14 downto 0);
wrclock : in std_logic := '1';
wren : in std_logic := '0';
q : out std_logic_vector (7 downto 0)
);
end FrameBuffer;
architecture SYN of framebuffer is
signal sub_wire0 : std_logic_vector (7 downto 0);
begin
q <= sub_wire0(7 downto 0);
altsyncram_component : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
init_file => "./frame_buffer/frame-buffer.mif",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 32768,
numwords_b => 32768,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 15,
widthad_b => 15,
width_a => 8,
width_b => 8,
width_byteena_a => 1
)
port map (
address_a => wraddress,
address_b => rdaddress,
clock0 => wrclock,
clock1 => rdclock,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
end SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING "./frame_buffer/frame-buffer.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./frame_buffer/frame-buffer.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 15 0 INPUT NODEFVAL "rdaddress[14..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 15 0 INPUT NODEFVAL "wraddress[14..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 wraddress 0 0 15 0
-- Retrieval info: CONNECT: @address_b 0 0 15 0 rdaddress 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FrameBuffer_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
----------------------------------------------------------------------------------
-- SpiRx40.vhd: 40-bit SPI receiveer
-- receives 5 bytes (1 control + 4 data) from an SPI bus
-- acts as an SPI slave
-- Author: JPP
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_unsigned.all;
entity SpiRx40 is
port(
sck : in std_logic;
mosi : in std_logic;
ctrlout : out std_logic_vector( 7 downto 0);
dataout : out std_logic_vector(31 downto 0)
);
end SpiRx40;
architecture behavioral of SpiRx40 is
signal msg : std_logic_vector(39 downto 0);
begin
process(sck) begin
if (sck = '1' and sck'event) then
msg <= msg(38 downto 0) & mosi;
end if;
end process;
ctrlout <= msg(39 downto 32);
dataout <= msg(31 downto 0);
end behavioral;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.protected_types_pkg.all;
package global_signals_and_shared_variables_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_MSG_ID_PANEL_DEFAULT;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
shared variable shared_flag_array : t_sync_flag_record_array(1 to C_NUM_SYNC_FLAGS) := (others => C_SYNC_FLAG_DEFAULT);
shared variable protected_semaphore : t_protected_semaphore;
shared variable protected_broadcast_semaphore : t_protected_semaphore;
shared variable protected_response_semaphore : t_protected_semaphore;
shared variable shared_uvvm_status : t_uvvm_status := C_UVVM_STATUS_DEFAULT;
shared variable protected_covergroup_status : t_protected_covergroup_status;
-- Global signals
signal global_trigger : std_logic := 'L';
signal global_barrier : std_logic := 'X';
end package global_signals_and_shared_variables_pkg; |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:50:00 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/mult_gen_1_synth_1/mult_gen_1_sim_netlist.vhdl
-- Design : mult_gen_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_gen_1_mult_gen_v12_0_9 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 11 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 32 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mult_gen_1_mult_gen_v12_0_9 : entity is 12;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mult_gen_1_mult_gen_v12_0_9 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mult_gen_1_mult_gen_v12_0_9 : entity is 14;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 1;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mult_gen_1_mult_gen_v12_0_9 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mult_gen_1_mult_gen_v12_0_9 : entity is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mult_gen_1_mult_gen_v12_0_9 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mult_gen_1_mult_gen_v12_0_9 : entity is "mult_gen_v12_0_9";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_gen_1_mult_gen_v12_0_9 : entity is "yes";
end mult_gen_1_mult_gen_v12_0_9;
architecture STRUCTURE of mult_gen_1_mult_gen_v12_0_9 is
attribute C_A_TYPE of i_mult : label is 0;
attribute C_A_WIDTH of i_mult : label is 12;
attribute C_B_TYPE of i_mult : label is 0;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 14;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 0;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 1;
attribute C_OPTIMIZE_GOAL of i_mult : label is 1;
attribute C_OUT_HIGH of i_mult : label is 32;
attribute C_OUT_LOW of i_mult : label is 0;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "artix7";
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
i_mult: entity work.mult_gen_1_mult_gen_v12_0_9_viv
port map (
A(11 downto 0) => A(11 downto 0),
B(13 downto 0) => B(13 downto 0),
CE => CE,
CLK => CLK,
P(32 downto 0) => P(32 downto 0),
PCASC(47 downto 0) => PCASC(47 downto 0),
SCLR => SCLR,
ZERO_DETECT(1 downto 0) => ZERO_DETECT(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_gen_1 is
port (
A : in STD_LOGIC_VECTOR ( 11 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
P : out STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mult_gen_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mult_gen_1 : entity is "mult_gen_1,mult_gen_v12_0_9,{}";
attribute core_generation_info : string;
attribute core_generation_info of mult_gen_1 : entity is "mult_gen_1,mult_gen_v12_0_9,{x_ipProduct=Vivado 2015.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=artix7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=12,C_A_TYPE=0,C_B_WIDTH=14,C_B_TYPE=0,C_OUT_HIGH=32,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_gen_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mult_gen_1 : entity is "mult_gen_v12_0_9,Vivado 2015.3";
end mult_gen_1;
architecture STRUCTURE of mult_gen_1 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 12;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 14;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 1;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of U0 : label is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of U0 : label is "xilinx.com:signal:data:1.0 p_intf DATA";
begin
U0: entity work.mult_gen_1_mult_gen_v12_0_9
port map (
A(11 downto 0) => A(11 downto 0),
B(13 downto 0) => B(13 downto 0),
CE => '1',
CLK => '1',
P(32 downto 0) => P(32 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:50:00 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/mult_gen_1_synth_1/mult_gen_1_sim_netlist.vhdl
-- Design : mult_gen_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_gen_1_mult_gen_v12_0_9 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 11 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 32 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mult_gen_1_mult_gen_v12_0_9 : entity is 12;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mult_gen_1_mult_gen_v12_0_9 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mult_gen_1_mult_gen_v12_0_9 : entity is 14;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mult_gen_1_mult_gen_v12_0_9 : entity is 1;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mult_gen_1_mult_gen_v12_0_9 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mult_gen_1_mult_gen_v12_0_9 : entity is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mult_gen_1_mult_gen_v12_0_9 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mult_gen_1_mult_gen_v12_0_9 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mult_gen_1_mult_gen_v12_0_9 : entity is "mult_gen_v12_0_9";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_gen_1_mult_gen_v12_0_9 : entity is "yes";
end mult_gen_1_mult_gen_v12_0_9;
architecture STRUCTURE of mult_gen_1_mult_gen_v12_0_9 is
attribute C_A_TYPE of i_mult : label is 0;
attribute C_A_WIDTH of i_mult : label is 12;
attribute C_B_TYPE of i_mult : label is 0;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 14;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 0;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 1;
attribute C_OPTIMIZE_GOAL of i_mult : label is 1;
attribute C_OUT_HIGH of i_mult : label is 32;
attribute C_OUT_LOW of i_mult : label is 0;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "artix7";
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
i_mult: entity work.mult_gen_1_mult_gen_v12_0_9_viv
port map (
A(11 downto 0) => A(11 downto 0),
B(13 downto 0) => B(13 downto 0),
CE => CE,
CLK => CLK,
P(32 downto 0) => P(32 downto 0),
PCASC(47 downto 0) => PCASC(47 downto 0),
SCLR => SCLR,
ZERO_DETECT(1 downto 0) => ZERO_DETECT(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_gen_1 is
port (
A : in STD_LOGIC_VECTOR ( 11 downto 0 );
B : in STD_LOGIC_VECTOR ( 13 downto 0 );
P : out STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mult_gen_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mult_gen_1 : entity is "mult_gen_1,mult_gen_v12_0_9,{}";
attribute core_generation_info : string;
attribute core_generation_info of mult_gen_1 : entity is "mult_gen_1,mult_gen_v12_0_9,{x_ipProduct=Vivado 2015.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=artix7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=12,C_A_TYPE=0,C_B_WIDTH=14,C_B_TYPE=0,C_OUT_HIGH=32,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_gen_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mult_gen_1 : entity is "mult_gen_v12_0_9,Vivado 2015.3";
end mult_gen_1;
architecture STRUCTURE of mult_gen_1 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 12;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 14;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 0;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 1;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of U0 : label is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of U0 : label is "xilinx.com:signal:data:1.0 p_intf DATA";
begin
U0: entity work.mult_gen_1_mult_gen_v12_0_9
port map (
A(11 downto 0) => A(11 downto 0),
B(13 downto 0) => B(13 downto 0),
CE => '1',
CLK => '1',
P(32 downto 0) => P(32 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
|
----------------------------------------------------------------------------------------------------
-- inverter_maia_2.vhd ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the Modified Almost Inverse Algorithm.
-- Diferent to the first implementation, here the test g(U) < g(V) is
-- performed directly by a m+1 bit comparer.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
--------------------------------------------------------
entity inverter_maia_233 is
generic(
NUM_BITS : positive := 233 -- The order of the finite field
);
port(
ax : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- input polynomial of grade m-1
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
z : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end ;
---------------------------------------------------------
architecture behave of inverter_maia_233 is
---------------------------------------------------------
signal B,C,U,V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal processing registers, one bit more
signal Bx_Op1 : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Multiplexer which depends on if B is ever or odd
signal Ux_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- U and B divided by x
signal Bx_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0);
--163
--constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--233
constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--277
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--283
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--409
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--571
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--
-- m = 163 x163 + x7 + x6 + x3 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
constant Fx: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant Fx: std_logic_vector(NUM_BITS1 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------
-- States fot the FSM controlling the execution of the algorithm
----------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, LOOP_U0, NEXT_STEP);
signal State: CurrentState_type;
----------------------------------------------------------------------------------
begin
------------------------------------------------------
Ux_div_x <= '0' & U(NUM_BITS downto 1); -- Dividing U and B by x
Bx_div_x <= '0' & Bx_Op1(NUM_BITS downto 1);
------------------------------------------------------
Bx_Op1 <= B xor Fx when B(0) = '1' else -- Multiplexer for operand B
B;
-------------------------------------------------------
-- The Modified ALmost Inverse Algorithm implementation
-------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then -- initialize internal registers
State <= LOOP_U0;
B <= UNO;
U <= '0'&Ax;
V <= Fx;
C <= (others => '0');
z <= (others => '0'); -- set to zero the output register
Done <= '0';
else
case State is
-----------------------------------------------------------------------------------
when LOOP_U0 => -- Stay here while U be even
if U(0) = '1' then
if U = UNO then -- The algorithm finishes when U = 1
Z <= B(NUM_BITS-1 downto 0);
Done <= '1';
State <= END_STATE;
else
if U < V then -- Interchange the registers U <-> V and B <-> C
U <= V;
V <= U;
B <= C;
C <= B;
end if;
State <= NEXT_STEP;
end if;
else -- Divide U and B and repeat the process
U <= Ux_div_x;
B <= Bx_div_x;
end if;
-----------------------------------------------------------------------------------
when NEXT_STEP => -- update U and B with the values previously assigned
U <= U xor V;
B <= B xor C;
State <= LOOP_U0;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
State <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Creates periodic signals (e.g. sine, square, and sawtooth) using a phase
-- accumulator. The current phase is also available.
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FunctionGenerator_Declarations.all;
entity SignalGenerator is
generic
(
-- The width of the phase values.
phase_width: natural := 32;
-- The width of the phase values of the waveform lookup table (must not
-- exceed phase_width).
lookup_table_phase_width: natural := 12;
-- The width of the level values.
level_width: natural := 16;
-- The width of the sample values.
sample_width: natural := 16
);
port
(
-- The system clock.
clk: in std_logic;
-- The configuration (e.g. waveform).
config: in generator_config;
-- The increment to be added to the phase accumulator in each clock cycle.
phase_increment: in unsigned (phase_width-1 downto 0);
-- The phase value to be added to the current phase value before determining
-- the sample value. Corresponds to a range of 0..2*Pi.
phase_shift: in unsigned(phase_width-1 downto 0);
-- The level value used to attenuate the sample signal.
level: in signed (level_width-1 downto 0);
-- A signal used to reset the generator´s phase.
reset_phase: in std_logic;
-- The current internal phase value. This is exactly synchronized to sample.
-- Its MSB is 0 for the first half of the period and 1 for the second half.
phase: out unsigned (phase_width-1 downto 0);
-- The sample value according to the current phase.
sample: out signed (sample_width-1 downto 0)
);
end entity;
architecture stdarch of SignalGenerator is
signal phase_int, phase_int_reg: unsigned(phase_width-1 downto 0) := (others => '0');
signal phase_int_shifted: unsigned(phase_width-1 downto 0) := (others => '0');
signal limited_level: signed (level_width-1 downto 0) := (others => '0');
signal sample_int, sample_int_reg: signed (sample_width-1 downto 0) := (others => '0');
signal sample_level_product: signed (2*sample_width-1 downto 0) := (others => '0');
-- Declarations necessary to delay phase to get in sync with sample.
constant phase_sync_delay: integer := 3; -- delay in clk cycles
type phase_vector is array (natural range <>) of unsigned(phase_width-1 downto 0);
signal phase_int_sync: phase_vector(phase_sync_delay-1 downto 0) := (others => (others => '0'));
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- Add one clock cycle latency to meet timing requirements when adding phase shift.
add_phase_shift: process is
begin
wait until rising_edge(clk);
phase_int_reg <= phase_int;
end process;
-- Shift the current phase value before determining the sample value.
phase_int_shifted <= phase_int_reg + phase_shift;
-- The MSB of the multiplier output is only needed if both inputs have the
-- smallest possible values: -(2**(n-1)). If at least one of the inputs is
-- limited to -(2**(n-1)-1), the MSB is always identical to the next lower-order
-- bit. To use the entire multiplier output range (and thus the entire sample
-- value range), we limit the level´s value here.
process (level) is
begin
limited_level <= level;
if (level(level_width-1) = '1' and
level(level_width-2 downto 0) = (level_width-2 downto 0 => '0'))
then
limited_level(0) <= '1';
end if;
end process;
-- Attenuate the sample value according to the level.
attenuate_sample: process is
begin
-- Xilinx XST will infer a multiplier here. As an alternative, a multiplier can
-- be instantiated explicitly. Either a multiplier supplied by the FPGA vendor
-- or an own implementation can be used. Portable implementations can be found
-- e.g. in that book: Pong P. Chu, "RTL Hardware Design Using VHDL".
wait until rising_edge(clk);
sample_level_product <= limited_level * sample_int_reg;
end process;
-- Delay returned signals to get them in sync with the sample signal.
delay_signals: process is
begin
wait until rising_edge(clk);
phase_int_sync(phase_int_sync'high downto 1) <=
phase_int_sync(phase_int_sync'high-1 downto 0);
phase_int_sync(0) <= phase_int_reg;
end process;
-- Add one clock cycle latency to satisfy timing constraints between function
-- generator and level multiplier.
decouple_sample: process is
begin
wait until rising_edge(clk);
sample_int_reg <= sample_int;
end process;
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
-- The phase generator controlled by a phase accumulator. Generates cyclic
-- phase values used for DDS signal generation.
phase_generator: entity work.PhaseGenerator
generic map
(
phase_width => phase_width
)
port map
(
clk => clk,
phase_increment => phase_increment,
reset_phase => reset_phase,
phase => phase_int
);
-- The function generator producing miscellaneous waveforms using cyclic phase
-- values.
function_generator: entity work.FunctionGenerator
generic map
(
phase_width => phase_width,
lookup_table_phase_width => lookup_table_phase_width,
sample_width => sample_width
)
port map
(
clk => clk,
config => config,
phase => phase_int_shifted,
sample => sample_int
);
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- Provides the output signals synchronously, i.e. registered. This is done to
-- satisfy the timing requirements. Otherwise all delays including those of the
-- multiplier are too long for one clock cycle.
provide_output: process is
begin
wait until rising_edge(clk);
-- Provide the MSB´s of the product created from the level and sample values.
-- We have ensured that only one input value of the multiplier can be
-- -(2**(n-1)). Thus we can ignore the result´s MSB and use the full output
-- range.
sample <= sample_level_product(2*sample_width-2 downto sample_width-1);
-- Return the phase value that´s synchronized to the sample value.
phase <= phase_int_sync(phase_int_sync'high);
end process;
end architecture;
|
--/////////////////////////////////////////////////////////////////////////
--// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
--//
--// XILINX CONFIDENTIAL PROPERTY
--// This document contains proprietary information which is
--// protected by copyright. All rights are reserved. This notice
--// refers to original work by Xilinx, Inc. which may be derivitive
--// of other work distributed under license of the authors. In the
--// case of derivitive work, nothing in this notice overrides the
--// original author's license agreeement. Where applicable, the
--// original license agreement is included in it's original
--// unmodified form immediately below this header.
--//
--// Xilinx, Inc.
--// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
--// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
--// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
--// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
--// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
--// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
--// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
--// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
--// AND FITNESS FOR A PARTICULAR PURPOSE.
--//
--/////////////////////////////////////////////////////////////////////////
-- This is round_3 of the FFT calculation
-- Step size is 4 so X and X +4 are mixed together
-- X0 with X4, X1 with X5 and etc
-- U is a constant with a bogus value - you will want to change it
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
library bftLib;
use bftLib.bftPackage.all;
entity round_3 is
port (
clk: in std_logic;
x : in xType;
xOut : out xType
);
end entity round_3;
architecture aR3 of round_3 is
constant u : uType :=
(X"AA55",
X"55AA",
X"AA55",
X"55AA",
X"AA55",
X"55AA",
X"AA55",
X"55AA");
begin
transformLoop: for N in 0 to 3 generate
ct0: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(N), xStep=>x(N+4), u=>u(N), xOut=>xOut(N), xOutStep =>xOut(N+4));
ct1: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(N+8), xStep=>x(N+12), u=>u(N+4), xOut=>xOut(N+8), xOutStep =>xOut(N+12));
end generate transformLoop;
end architecture aR3;
|
add_i : add
port map (
clk => clk,
in => in,
output => output
);
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 32;
-- CFG_AHB_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
-- The value of CFG_AHB_ACDM is assigned to the constant CORE_ACDM in the
-- grlib.amba package. Note that this setting is separate from the ACDM setting
-- of the AHBCTRL core (which is set directly via a AHBCTRL VHDL generic).
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
grlib_techmap_testin_extra => 0,
grlib_sync_reset_enable_all => 0,
grlib_async_reset_enable => 0,
grlib_amba_inc_nirq => 0,
others => 0);
end;
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file tb_gmii.vhd
--! @brief gmii testbench adopted from the opencores udp ip stack
--! @author Benjamin Bässler
--! @email ccl@xunit.de
--! @date 2013-11-13
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity tb_gmii is
end tb_gmii;
architecture behavior of tb_gmii is
signal gmii_txd_s : std_logic_vector(7 downto 0);
signal gmii_tx_en_s : std_logic;
signal gmii_tx_er_s : std_logic;
signal gmii_tx_clk_s : std_logic;
signal gmii_rxd_s : std_logic_vector(7 downto 0);
signal gmii_rx_dv_s : std_logic;
signal gmii_rx_er_s : std_logic;
signal gmii_rx_clk_s : std_logic;
signal gmii_col_s : std_logic;
signal gmii_crs_s : std_logic;
signal mii_tx_clk_s : std_logic;
signal cfg_busy_s : boolean;
signal m_1g_done_s : boolean;
signal m_100m_done_s : boolean;
signal m_10m_done_s : boolean;
signal reset_s_n : std_logic := '1';
signal clk_int : std_logic;
signal clk200_int : std_logic;
signal clk250_int : std_logic;
begin
my_top : entity work.top_udp
port map(
-- System signals
------------------
rst_in_n => reset_s_n,
clk_in => clk_int,
led_out => open,
-- GMII Interface
-----------------
phy_resetn => open,
gmii_txd => gmii_txd_s,
gmii_tx_en => gmii_tx_en_s,
gmii_tx_er => gmii_tx_er_s,
gmii_tx_clk => gmii_tx_clk_s,
gmii_rxd => gmii_rxd_s,
gmii_rx_dv => gmii_rx_dv_s,
gmii_rx_er => gmii_rx_er_s,
gmii_rx_clk => gmii_rx_clk_s,
gmii_col => gmii_col_s,
gmii_crs => gmii_crs_s,
mii_tx_clk => mii_tx_clk_s
);
xilinx_tb : entity work.tb_xilinx_mac
port map(
------------------------------------------------------------------
-- GMII Interface
------------------------------------------------------------------
gmii_txd => gmii_txd_s,
gmii_tx_en => gmii_tx_en_s,
gmii_tx_er => gmii_tx_er_s,
gmii_tx_clk => gmii_tx_clk_s,
gmii_rxd => gmii_rxd_s,
gmii_rx_dv => gmii_rx_dv_s,
gmii_rx_er => gmii_rx_er_s,
gmii_rx_clk => gmii_rx_clk_s,
gmii_col => gmii_col_s,
gmii_crs => gmii_crs_s,
mii_tx_clk => mii_tx_clk_s,
------------------------------------------------------------------
-- Test Bench Semaphores
------------------------------------------------------------------
configuration_busy => cfg_busy_s,
monitor_finished_1g => m_1g_done_s,
monitor_finished_100m => m_100m_done_s,
monitor_finished_10m => m_10m_done_s
);
-- Clock process definitions
clk_process :process
begin
clk_int <= '0';
wait for 10 ns;
loop
clk_int <= '1';
wait for 5 ns;
clk_int <= '0';
wait for 5 ns;
end loop;
end process;
-- Stimulus process
stim_proc: process
begin
cfg_busy_s <= TRUE;
reset_s_n <= '0';
wait for 5000 ns;
for j in 0 to 49 loop
wait until rising_edge(clk_int);
end loop;
cfg_busy_s <= FALSE;
wait until m_1g_done_s;
cfg_busy_s <= TRUE;
report "--- end of tests ---";
wait;
end process;
END;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:55 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
------------------------------------------------------------------------
-- vga_controller_800_60.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic to generate the synchronization signals,
-- horizontal and vertical pixel counter and video disable signal
-- for the 800x600@60Hz resolution.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web regarding the
-- vga video timings:
-- http://www.epanorama.net/documents/pc/vga_timing.html
-- This module generates the video synch pulses for the monitor to
-- enter 800x600@60Hz resolution state. It also provides horizontal
-- and vertical counters for the currently displayed pixel and a blank
-- signal that is active when the pixel is not inside the visible screen
-- and the color outputs should be reset to 0.
-- timing diagram for the horizontal synch signal (HS)
-- 0 840 968 1056 (pixels)
-- _________________________|------|_________________
-- timing diagram for the vertical synch signal (VS)
-- 0 601 605 628 (lines)
-- __________________________________|------|________
-- The blank signal is delayed one pixel clock period (25ns) from where
-- the pixel leaves the visible screen, according to the counters, to
-- account for the pixel pipeline delay. This delay happens because
-- it takes time from when the counters indicate current pixel should
-- be displayed to when the color data actually arrives at the monitor
-- pins (memory read delays, synchronization delays).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- rst - global reset signal
-- pixel_clk - input pin, from dcm_40MHz
-- - the clock signal generated by a DCM that has
-- - a frequency of 40MHz.
-- HS - output pin, to monitor
-- - horizontal synch pulse
-- VS - output pin, to monitor
-- - vertical synch pulse
-- hcount - output pin, 11 bits, to clients
-- - horizontal count of the currently displayed
-- - pixel (even if not in visible area)
-- vcount - output pin, 11 bits, to clients
-- - vertical count of the currently active video
-- - line (even if not in visible area)
-- blank - output pin, to clients
-- - active when pixel is not in visible area.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the vga_controller_800_60 entity declaration
-- read above for behavioral description and port definitions.
entity vga_controller_800_60 is
port(
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
hcount : out std_logic_vector(10 downto 0);
vcount : out std_logic_vector(10 downto 0);
blank : out std_logic
);
end vga_controller_800_60;
architecture Behavioral of vga_controller_800_60 is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- maximum value for the horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "10000100000"; -- 1056
-- maximum value for the vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01001110100"; -- 628
-- total number of visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- value for the horizontal counter where front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01101001000"; -- 840
-- value for the horizontal counter where the synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01111001000"; -- 968
-- total number of visible lines
constant VLINES: std_logic_vector(10 downto 0) := "01001011000"; -- 600
-- value for the vertical counter where the front porch ends
constant VFP : std_logic_vector(10 downto 0) := "01001011001"; -- 601
-- value for the vertical counter where the synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "01001011101"; -- 605
-- polarity of the horizontal and vertical synch pulse
-- only one polarity used, because for this resolution they coincide.
constant SPP : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- horizontal and vertical counters
signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
-- active when inside visible screen area.
signal video_enable: std_logic;
begin
-- output horizontal and vertical counters
hcount <= hcounter;
vcount <= vcounter;
-- blank is active when outside screen visible area
-- color output should be blacked (put on 0) when blank in active
-- blank is delayed one pixel clock period from the video_enable
-- signal to account for the pixel pipeline delay.
blank <= not video_enable when rising_edge(pixel_clk);
-- increment horizontal counter at pixel_clk rate
-- until HMAX is reached, then reset and keep counting
h_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
hcounter <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
else
hcounter <= hcounter + 1;
end if;
end if;
end process h_count;
-- increment vertical counter when one line is finished
-- (horizontal counter reached HMAX)
-- until VMAX is reached, then reset and keep counting
v_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
vcounter <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
else
vcounter <= vcounter + 1;
end if;
end if;
end if;
end process v_count;
-- generate horizontal synch pulse
-- when horizontal counter is between where the
-- front porch ends and the synch pulse ends.
-- The HS is active (with polarity SPP) for a total of 128 pixels.
do_hs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
-- when vertical counter is between where the
-- front porch ends and the synch pulse ends.
-- The VS is active (with polarity SPP) for a total of 4 video lines
-- = 4*HMAX = 4224 pixels.
do_vs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
-- enable video output when pixel is in visible area
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_3 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_3;
ARCHITECTURE bram_1024_3_arch OF bram_1024_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_3_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_3_arch : ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_3_arch: ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_3.mi" &
"f,C_INIT_FILE=bram_1024_3.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_3.mif",
C_INIT_FILE => "bram_1024_3.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_3_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_3 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_3;
ARCHITECTURE bram_1024_3_arch OF bram_1024_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_3_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_3_arch : ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_3_arch: ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_3.mi" &
"f,C_INIT_FILE=bram_1024_3.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_3.mif",
C_INIT_FILE => "bram_1024_3.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_3_arch;
|
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