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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_3 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_3;
ARCHITECTURE bram_1024_3_arch OF bram_1024_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_3_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_3_arch : ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_3_arch: ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_3.mi" &
"f,C_INIT_FILE=bram_1024_3.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_3.mif",
C_INIT_FILE => "bram_1024_3.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_3_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_3 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_3;
ARCHITECTURE bram_1024_3_arch OF bram_1024_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_3_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_3_arch : ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_3_arch: ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_3.mi" &
"f,C_INIT_FILE=bram_1024_3.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_3.mif",
C_INIT_FILE => "bram_1024_3.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_3_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity top is
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end top;
architecture behavioral of top is
signal data : std_logic;
begin
mylabel: process (clk)
variable tmp : std_logic;
begin
if rising_edge(clk) then
tmp := di; -- Post-synthesis name : mylabel.tmp
end if;
data <= not(tmp);
end process;
do <= not(data);
end behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weights_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weights_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END weights_exdes;
ARCHITECTURE xilinx OF weights_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT weights IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : weights
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
--! @file trig_table_ea.vhd
--! @brief sin/cos lookup table generator
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-09-30
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use work.fixed_pkg.all;
--! @brief Sin & Cos lookup table
--! @details
--! Outputs cos(2*pi*angle) and sin(2*pi*angle), where 0 <= angle < 1.
entity trig_table is
port (
clk : in std_logic;
rst : in std_logic;
angle : in ufixed
);
end entity;
architecture rtl of trig_table is
begin
end rtl;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitset_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of bitset_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_true : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal reg_123 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_5_fu_143_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_1_fu_148_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_1_fu_153_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_bit_read_reg_196 : STD_LOGIC_VECTOR (7 downto 0);
signal p_read_1_reg_202 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_202_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_127_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_reg_210 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_210_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal bus_assign_fu_137_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_216 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_bus_assign_reg_216_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_reg_223 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_1_reg_227 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_1_reg_231 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bit_write_assign_trunc3_ext_fu_163_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_trunc_ext_fu_158_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_3_fu_131_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_write_assign_cast_fu_168_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_113 : BOOLEAN;
signal ap_sig_bdd_104 : BOOLEAN;
signal ap_sig_bdd_121 : BOOLEAN;
signal ap_sig_bdd_125 : BOOLEAN;
signal ap_sig_bdd_61 : BOOLEAN;
signal ap_sig_bdd_73 : BOOLEAN;
signal ap_sig_bdd_59 : BOOLEAN;
component p_bsf32_hw IS
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) );
end component;
begin
grp_p_bsf32_hw_fu_118 : component p_bsf32_hw
port map (
bus_r => grp_p_bsf32_hw_fu_118_bus_r,
ap_return => grp_p_bsf32_hw_fu_118_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2))))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 <= r_bit_read_reg_196;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2))))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 <= ap_const_lv2_2;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_61) then
if (ap_sig_bdd_125) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= p_read_1_reg_202;
elsif (ap_sig_bdd_121) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= ap_const_lv32_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 assign process. --
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_bus_assign_reg_216_pp0_it1 <= bus_assign_reg_216;
ap_reg_ppstg_p_read_1_reg_202_pp0_it1 <= p_read_1_reg_202;
ap_reg_ppstg_tmp_reg_210_pp0_it1 <= tmp_reg_210;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
bus_assign_reg_216 <= bus_assign_fu_137_p2;
p_read_1_reg_202 <= p_read;
r_bit_read_reg_196 <= r_bit;
tmp_reg_210 <= tmp_fu_127_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and (tmp_5_fu_143_p2 = ap_const_lv1_0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_153_p2)))) then
reg_123 <= grp_p_bsf32_hw_fu_118_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)))) then
tmp_11_1_reg_231 <= tmp_11_1_fu_153_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
tmp_5_reg_223 <= tmp_5_fu_143_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)))) then
tmp_9_1_reg_227 <= tmp_9_1_fu_148_p2;
end if;
end if;
end process;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2(0) <= '1';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- agg_result_bit_write_assign_phi_fu_107_p8 assign process. --
agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(tmp_5_reg_223, agg_result_bit_write_assign_trunc3_ext_fu_163_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2, agg_result_bit_write_assign_trunc_ext_fu_158_p1, ap_sig_bdd_113, ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
if ((ap_const_lv1_0 = tmp_5_reg_223)) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_158_p1;
elsif (ap_sig_bdd_113) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_163_p1;
else
agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2;
end if;
else
agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2;
end if;
end process;
agg_result_bit_write_assign_trunc3_ext_fu_163_p1 <= std_logic_vector(resize(unsigned(reg_123),8));
agg_result_bit_write_assign_trunc_ext_fu_158_p1 <= std_logic_vector(resize(unsigned(reg_123),8));
agg_result_bucket_index_write_assign_cast_fu_168_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8));
-- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. --
agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_210_pp0_it1, tmp_5_reg_223, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2, ap_sig_bdd_113, ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
if ((ap_const_lv1_0 = tmp_5_reg_223)) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_210_pp0_it1;
elsif (ap_sig_bdd_113) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1;
else
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2;
end if;
else
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2;
end if;
end process;
-- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. --
agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_202_pp0_it1, ap_reg_ppstg_bus_assign_reg_216_pp0_it1, tmp_5_reg_223, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2, ap_sig_bdd_113, ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
if ((ap_const_lv1_0 = tmp_5_reg_223)) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_216_pp0_it1;
elsif (ap_sig_bdd_113) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_202_pp0_it1;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2;
end if;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2;
end if;
end process;
-- agg_result_end_write_assign_phi_fu_73_p8 assign process. --
agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, tmp_5_reg_223, tmp_9_1_reg_227, tmp_11_1_reg_231, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2)
begin
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((ap_const_lv1_0 = tmp_5_reg_223)) and not((ap_const_lv1_0 = tmp_9_1_reg_227)) and (ap_const_lv1_0 = tmp_11_1_reg_231)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = tmp_5_reg_223)))) then
agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0;
else
agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1 <= ap_const_lv8_1;
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1 <= ap_const_lv2_1;
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= ap_const_lv32_1;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_const_lv1_1;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8;
ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_168_p1;
ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8;
ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8;
-- ap_sig_bdd_104 assign process. --
ap_sig_bdd_104_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2)
begin
ap_sig_bdd_104 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2));
end process;
-- ap_sig_bdd_113 assign process. --
ap_sig_bdd_113_assign_proc : process(tmp_5_reg_223, tmp_9_1_reg_227, tmp_11_1_reg_231)
begin
ap_sig_bdd_113 <= (not((ap_const_lv1_0 = tmp_5_reg_223)) and not((ap_const_lv1_0 = tmp_9_1_reg_227)) and (ap_const_lv1_0 = tmp_11_1_reg_231));
end process;
-- ap_sig_bdd_121 assign process. --
ap_sig_bdd_121_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2)
begin
ap_sig_bdd_121 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2));
end process;
-- ap_sig_bdd_125 assign process. --
ap_sig_bdd_125_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2, tmp_11_1_fu_153_p2)
begin
ap_sig_bdd_125 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2)));
end process;
-- ap_sig_bdd_59 assign process. --
ap_sig_bdd_59_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1)
begin
ap_sig_bdd_59 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1));
end process;
-- ap_sig_bdd_61 assign process. --
ap_sig_bdd_61_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce)
begin
ap_sig_bdd_61 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_73 assign process. --
ap_sig_bdd_73_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2, tmp_11_1_fu_153_p2)
begin
ap_sig_bdd_73 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_153_p2));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
bus_assign_fu_137_p2 <= (tmp_3_fu_131_p2 and r_bucket);
-- grp_p_bsf32_hw_fu_118_bus_r assign process. --
grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(tmp_5_fu_143_p2, p_read_1_reg_202, bus_assign_reg_216, ap_sig_bdd_73, ap_sig_bdd_59)
begin
if (ap_sig_bdd_59) then
if (ap_sig_bdd_73) then
grp_p_bsf32_hw_fu_118_bus_r <= p_read_1_reg_202;
elsif ((tmp_5_fu_143_p2 = ap_const_lv1_0)) then
grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_216;
else
grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
tmp_11_1_fu_153_p2 <= "1" when (p_read_1_reg_202 = ap_const_lv32_0) else "0";
tmp_3_fu_131_p2 <= std_logic_vector(unsigned(r_bucket) + unsigned(ap_const_lv32_FFFFFFFF));
tmp_5_fu_143_p2 <= "1" when (bus_assign_reg_216 = ap_const_lv32_0) else "0";
tmp_9_1_fu_148_p2 <= "1" when (tmp_reg_210 = ap_const_lv2_0) else "0";
tmp_fu_127_p1 <= r_bucket_index(2 - 1 downto 0);
end behav;
|
-- File: gray_counter_28.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_28 is
port (
gray_count: out unsigned(27 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_28;
architecture MyHDL of gray_counter_28 is
signal even: std_logic;
signal gray: unsigned(27 downto 0);
begin
GRAY_COUNTER_28_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(27 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((28 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 28-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_28_SEQ;
gray_count <= gray;
end architecture MyHDL;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <kubakici@wp.pl>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Binary wrap-around counter with enable
entity counter_en is
generic (N_BITS : integer);
port (Clk : in std_logic;
Rst : in std_logic;
Enable : in std_logic;
Cnt : out std_logic_vector (N_BITS - 1 downto 0));
end counter_en;
-- Operation:
-- Count number of cycles @Enable is up.
-- Increase input from 0 to 2^N_BITS - 1 then start from zero again.
architecture Behavioral of counter_en is
signal count : std_logic_vector (N_BITS - 1 downto 0);
begin
Cnt <= count;
inc : process (Clk)
begin
if RISING_EDGE(Clk) then
if Enable = '1' then
count <= count + 1;
end if;
if Rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(clk : in std_logic;
rst : in std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1'; -- rising-edge first clock since we use negative-edge triggered registers
signal rst : std_logic := '1';
signal v_k : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rst => rst,
v_in => v_in,
v_k => v_k,
v_out => v_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k <= X"03020100";
-- init
rst <= '1';
wait for clk_period;
-- run
rst <= '0';
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
v_in <= v_out;
v_k <= X"0B0A0908";
wait for clk_period;
assert v_out = X"154D4E7FFC8B8A84"
report "ROUND_F ERROR (r_1)" severity FAILURE;
v_in <= v_out;
v_k <= X"13121110";
wait for clk_period;
assert v_out = X"B2A6BE7C154D4E7F"
report "ROUND_F ERROR (r_2)" severity FAILURE;
v_in <= v_out;
v_k <= X"1B1A1918";
wait for clk_period;
assert v_out = X"E0C1D225B2A6BE7C"
report "ROUND_F ERROR (r_3)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity character_write is
end character_write;
architecture test0 of character_write is
type character_file is file of character;
begin
doit: process
file fileout : character_file open write_mode is "character.file";
begin
write(fileout, '1');
write(fileout, 'A');
write(fileout, '$');
write(fileout, '+');
assert false
report "PASSED TEST: character_write."
severity note;
wait;
end process;
end test0;
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity character_write is
end character_write;
architecture test0 of character_write is
type character_file is file of character;
begin
doit: process
file fileout : character_file open write_mode is "character.file";
begin
write(fileout, '1');
write(fileout, 'A');
write(fileout, '$');
write(fileout, '+');
assert false
report "PASSED TEST: character_write."
severity note;
wait;
end process;
end test0;
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity character_write is
end character_write;
architecture test0 of character_write is
type character_file is file of character;
begin
doit: process
file fileout : character_file open write_mode is "character.file";
begin
write(fileout, '1');
write(fileout, 'A');
write(fileout, '$');
write(fileout, '+');
assert false
report "PASSED TEST: character_write."
severity note;
wait;
end process;
end test0;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_0_2 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC
);
END sys_router_0_2;
ARCHITECTURE sys_router_0_2_arch OF sys_router_0_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_0_2_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sys_router_0_2_arch: ARCHITECTURE IS "router_struct,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sys_router_0_2_arch : ARCHITECTURE IS "sys_router_0_2,router_struct,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 0,
ADDR_Y => 2,
N_INST => false,
S_INST => true,
E_INST => true,
W_INST => false
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
N_VIN => '0',
N_ROUT => '0',
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
W_VIN => '0',
W_ROUT => '0'
);
END sys_router_0_2_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ClockDivider is
Generic (
DEVIDER : integer := 2
);
Port (
clk_in : in STD_LOGIC := '0';
clk_out : out STD_LOGIC := '0'
);
end ClockDivider;
architecture Behavioral of ClockDivider is
signal temp : STD_LOGIC := '0';
signal counter : integer range 0 to DEVIDER := 0;
begin
process(clk_in) begin
if (rising_edge(clk_in)) then
if (counter = DEVIDER) then
counter <= 0;
temp <= NOT(temp);
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temp;
end Behavioral; |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- std_logic values test.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_logic is
port (low, high, hiz, dontcare, uninitialized, unknown : out std_logic);
end vhdl_logic;
architecture test of vhdl_logic is begin
low <= '0';
high <= '1';
hiz <= 'Z';
dontcare <= '-';
uninitialized <= 'U';
unknown <= 'X';
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- std_logic values test.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_logic is
port (low, high, hiz, dontcare, uninitialized, unknown : out std_logic);
end vhdl_logic;
architecture test of vhdl_logic is begin
low <= '0';
high <= '1';
hiz <= 'Z';
dontcare <= '-';
uninitialized <= 'U';
unknown <= 'X';
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- std_logic values test.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_logic is
port (low, high, hiz, dontcare, uninitialized, unknown : out std_logic);
end vhdl_logic;
architecture test of vhdl_logic is begin
low <= '0';
high <= '1';
hiz <= 'Z';
dontcare <= '-';
uninitialized <= 'U';
unknown <= 'X';
end architecture test;
|
entity repro is
end entity;
architecture a of repro is
constant C_PATTERN_0 : bit_vector(31 downto 0) := (
1 downto 0 => "01",
3 downto 2 => "11",
5 downto 4 => "01",
7 downto 6 => "10",
others => '0'
);
begin
end architecture;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the function generator.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.FunctionGenerator_Declarations.all;
entity FunctionGenerator_Tester is
end entity;
architecture stdarch of FunctionGenerator_Tester is
--------------------
-- Constants
--------------------
constant clk_period: time := 10ns;
constant phase_width: natural := 32;
constant sample_width: natural := 16;
constant lookup_table_phase_width: natural := 12;
constant phase_increment: integer := 16#1000000#;
constant no_of_sample_periods: integer := 3;
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal config: generator_config :=
(
waveform => waveform_square
);
signal phase: unsigned (phase_width-1 downto 0) := (others => '0');
--------------------
-- Outputs
--------------------
signal sample: signed(sample_width-1 downto 0);
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
begin
--------------------------------------------------------------------------------
-- UUT instantiation.
--------------------------------------------------------------------------------
uut: entity work.FunctionGenerator
generic map
(
phase_width => phase_width,
lookup_table_phase_width => lookup_table_phase_width,
sample_width => sample_width
)
port map
(
clk => clk,
config => config,
phase => phase,
sample => sample
);
--------------------------------------------------------------------------------
-- UUT stimulation.
--------------------------------------------------------------------------------
-- Generates the system clock.
clk <= not clk after clk_period/2 when run_test;
-- Generates a periodically incremented phase.
increment_phase: process is
begin
-- Do the tests for the specified duration.
wait until rising_edge(clk);
phase <= phase + to_unsigned(phase_increment, phase_width);
end process;
-- Stimulates and controls the UUT and the tests at all.
stimulus: process is
constant configurations: generator_config_vector :=
(
(waveform => waveform_square),
(waveform => waveform_sawtooth),
(waveform => waveform_sine)
);
begin
-- For each configuration, do the tests for the specified duration.
for i in configurations'range loop
config <= configurations(i);
for sample_cycle in 0 to no_of_sample_periods loop
wait until falling_edge(phase(phase'high));
end loop;
end loop;
run_test <= false;
wait;
end process;
--------------------------------------------------------------------------------
-- Specifications.
--------------------------------------------------------------------------------
-- Verifies proper waveworm generation.
must_create_waveform_from_phase: process is
constant positive_sample_maximum: signed(sample_width-1 downto 0) :=
to_signed(2**(sample_width-1)-1, sample_width);
constant negative_sample_maximum: signed(sample_width-1 downto 0) :=
to_signed(-(2**(sample_width-1)), sample_width);
variable previous_phase: unsigned(phase_width-1 downto 0) := (others => '0');
variable previous_values_set: boolean := false;
variable previous_config: generator_config :=
(
waveform => "111"
);
begin
wait until falling_edge(clk);
-- Skip the first clock cycle after each configuration change to let
-- previous_phase settle down.
if (config.waveform /= previous_config.waveform) then
previous_values_set := false;
previous_config.waveform := config.waveform;
end if;
-- The waveform is delayed by one clock cycle, thus check the sample
-- values against the previous cycle´s phase if they´re valid.
if (previous_values_set) then
-- Verify the waveform depending on the currently selected configuration.
case config.waveform is
when waveform_square =>
-- The sample must be the positive or negative maximum corresponding
-- to the phase's sign.
assert (previous_phase(previous_phase'high) = '0' and sample = positive_sample_maximum) or
(previous_phase(previous_phase'high) = '1' and sample = negative_sample_maximum)
report "Square sample not set correctly." severity error;
when waveform_sawtooth =>
-- The sample must be 0 at a phase of 0°, otherwise match the phase's sign.
assert (
previous_phase = (previous_phase'range => '0')
and
sample = (sample'range => '0')
)
or
(
previous_phase /= (previous_phase'range => '0')
and
previous_phase(previous_phase'high) = sample(sample'high)
)
report "Sawtooth sample has wrong zero or sign." severity error;
when waveform_sine =>
-- The sample must be 0 at a phase of 0° or 180°, otherwise match the phase's sign.
assert (
previous_phase(previous_phase'left-1 downto 0) = (previous_phase'left-1 downto 0 => '0')
and
sample = (sample'range => '0')
)
or
(
previous_phase(previous_phase'left-1 downto 0) /= (previous_phase'left-1 downto 0 => '0')
and
previous_phase(previous_phase'high) = sample(sample'high)
)
report "Sine sample has wrong zero or sign." severity error;
when others =>
report "Unknown waveform set." severity error;
end case;
end if;
-- Memorize the current phase for the next cycle.
previous_phase := phase;
previous_values_set := true;
end process;
end architecture;
|
-- VHDL do Sistema Digital
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registrador_jogada is
port(
clock: in std_logic;
reset: in std_logic;
guarda_jogada: in std_logic;
jogador: in std_logic;
entrada: in std_logic_vector(3 downto 0);
jogadas_realizadas: out std_logic_vector(8 downto 0);
jogadas_jogador: out std_logic_vector(8 downto 0)
);
end registrador_jogada;
architecture comportamental of registrador_jogada is
signal sinal_jogadas: std_logic_vector(8 downto 0) := "000000000";
signal sinal_jogador: std_logic_vector(8 downto 0) := "000000000";
begin
process(clock, reset, guarda_jogada, jogador, entrada)
begin
if reset='1' then
sinal_jogadas <= (others => '0');
sinal_jogador <= (others => '0');
elsif clock'event and clock='1' then
if guarda_jogada='1' then
sinal_jogadas(to_integer(unsigned(entrada))) <= '1';
if jogador = '1' then
sinal_jogador(to_integer(unsigned(entrada))) <= '1';
end if;
end if;
end if;
jogadas_realizadas <= sinal_jogadas;
jogadas_jogador <= sinal_jogador;
end process;
end comportamental;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee.math_real.all;
use ieee_proposed.energy_systems.all;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.thermal_systems.all;
entity diode is
port ( terminal p, m : electrical;
terminal j : thermal );
end entity diode;
----------------------------------------------------------------
architecture one of diode is
constant area : real := 1.0e-3;
constant Dn : real := 30.0; -- electron diffusion coefficient
constant Dp : real := 15.0; -- hole diffusion coefficient
constant np : real := 6.77e-5; -- minority charge density
constant pn : real := 6.77e-6; -- minority charge density
constant Ln : real := 5.47e-6; -- diffusion length for electrons
constant Lp : real := 12.25e-6; -- diffusion length for holes
quantity v across id through p to m;
quantity vt : voltage := 1.0; -- threshold voltage
quantity temp across power through j;
begin
vt == temp * K / Q;
id == Q * area * (Dp * (pn / Lp) + Dn * (np / Ln)) * (exp(v / vt) - 1.0);
power == v * id;
end architecture one;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee.math_real.all;
use ieee_proposed.energy_systems.all;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.thermal_systems.all;
entity diode is
port ( terminal p, m : electrical;
terminal j : thermal );
end entity diode;
----------------------------------------------------------------
architecture one of diode is
constant area : real := 1.0e-3;
constant Dn : real := 30.0; -- electron diffusion coefficient
constant Dp : real := 15.0; -- hole diffusion coefficient
constant np : real := 6.77e-5; -- minority charge density
constant pn : real := 6.77e-6; -- minority charge density
constant Ln : real := 5.47e-6; -- diffusion length for electrons
constant Lp : real := 12.25e-6; -- diffusion length for holes
quantity v across id through p to m;
quantity vt : voltage := 1.0; -- threshold voltage
quantity temp across power through j;
begin
vt == temp * K / Q;
id == Q * area * (Dp * (pn / Lp) + Dn * (np / Ln)) * (exp(v / vt) - 1.0);
power == v * id;
end architecture one;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee.math_real.all;
use ieee_proposed.energy_systems.all;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.thermal_systems.all;
entity diode is
port ( terminal p, m : electrical;
terminal j : thermal );
end entity diode;
----------------------------------------------------------------
architecture one of diode is
constant area : real := 1.0e-3;
constant Dn : real := 30.0; -- electron diffusion coefficient
constant Dp : real := 15.0; -- hole diffusion coefficient
constant np : real := 6.77e-5; -- minority charge density
constant pn : real := 6.77e-6; -- minority charge density
constant Ln : real := 5.47e-6; -- diffusion length for electrons
constant Lp : real := 12.25e-6; -- diffusion length for holes
quantity v across id through p to m;
quantity vt : voltage := 1.0; -- threshold voltage
quantity temp across power through j;
begin
vt == temp * K / Q;
id == Q * area * (Dp * (pn / Lp) + Dn * (np / Ln)) * (exp(v / vt) - 1.0);
power == v * id;
end architecture one;
|
--!
--! \file wait_and_yield.vhd
--!
--! Benchmark for cooperative multithreading
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 13.03.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 13.03.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wait_and_yield is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end wait_and_yield;
architecture Behavioral of wait_and_yield is
-- OS synchronization state machine states
type state_t is (STATE_CHECK,
STATE_INIT,
STATE_WAIT_BEFORE,
STATE_DELAY,
STATE_RESUME,
STATE_WAIT_AFTER,
STATE_EXIT);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06");
constant decode : decode_t := (STATE_CHECK,
STATE_INIT,
STATE_WAIT_BEFORE,
STATE_DELAY,
STATE_RESUME,
STATE_WAIT_AFTER,
STATE_EXIT);
signal state : state_t := STATE_CHECK;
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : state_t := STATE_CHECK;
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable delay : std_logic_vector(0 to C_OSIF_DATA_WIDTH/2-1) := (others => '0');
variable wait_before_after : std_logic_vector(0 to C_OSIF_DATA_WIDTH/2-2) := (others => '0'); -- possible values: 0..32767 (x 1.31 ms)
variable do_yield : std_logic := '0';
variable counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_CHECK;
next_state := STATE_CHECK;
resume_state_enc := (others => '0');
done := false;
success := false;
delay := (others => '0');
wait_before_after := (others => '0');
do_yield := '0';
counter := (others => '0');
init_data := (others => '0');
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if success then
next_state := decode(to_integer(unsigned(resume_state_enc)));
else
next_state := STATE_INIT;
end if;
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, init_data);
do_yield := init_data(0);
wait_before_after := init_data(1 to 15);
delay := init_data(16 to 31);
counter := wait_before_after & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT_BEFORE;
when STATE_WAIT_BEFORE =>
if counter = X"00000000" then
next_state := STATE_DELAY;
else
counter := counter - 1;
end if;
when STATE_DELAY =>
reconos_thread_delay(o_osif, i_osif, (X"0000" & delay)); -- delay for 'delay' timer ticks
if do_yield = '1' then
reconos_flag_yield(o_osif, i_osif, encode(STATE_RESUME));
end if;
counter := wait_before_after & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT_AFTER;
when STATE_RESUME =>
reconos_get_init_data(done, o_osif, i_osif, init_data);
wait_before_after := init_data(1 to 15);
counter := wait_before_after & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT_AFTER;
when STATE_WAIT_AFTER =>
if counter = X"00000000" then
next_state := STATE_EXIT;
else
counter := counter - 1;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
next_state := STATE_EXIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 16,
C_DOUT_WIDTH => 16,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 16,
C_DIN_WIDTH => 16,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 16,
C_DIN_WIDTH => 16,
C_WR_PNTR_WIDTH => 6,
C_RD_PNTR_WIDTH => 6,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : FIFO_DDR_DATA_IN_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:50 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title3/title3_stub.vhdl
-- Design : title3
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity title3 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end title3;
architecture stub of title3 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:50 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title3/title3_stub.vhdl
-- Design : title3
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity title3 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end title3;
architecture stub of title3 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
entity bounds34 is
end entity;
architecture test of bounds34 is
begin
main: process is
variable x : integer_vector(1 to 4);
variable y, z : integer_vector(1 to 2);
begin
x := ( integer_vector'(1, 2), integer_vector'(3, 4) );
assert x = (1, 2, 3, 4);
y := (5, 6);
z := (7, 8);
x := ( y, 0, integer_vector'(1, 2, 3) ); -- Error
assert x = (5, 6, 7, 8);
wait;
end process;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_instructionMemory IS
END Test_instructionMemory;
ARCHITECTURE behavior OF Test_instructionMemory IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT instructionMemory
PORT(
address : IN std_logic_vector(3 downto 0);
reset : IN std_logic;
clkFPGA : IN std_logic;
outInstruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal address : std_logic_vector(3 downto 0) := (others => '0');
signal reset : std_logic := '0';
signal clkFPGA : std_logic := '0';
--Outputs
signal outInstruction : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clkFPGA_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: instructionMemory PORT MAP (
address => address,
reset => reset,
clkFPGA => clkFPGA,
outInstruction => outInstruction
);
-- Clock process definitions
clkFPGA_process :process
begin
clkFPGA <= '0';
wait for clkFPGA_period/2;
clkFPGA <= '1';
wait for clkFPGA_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset<='1';
address <= "0000";
wait for 100 ns;
reset<='0';
address <= "1110";
wait;
end process;
END; |
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity mc6847t1_ntsc_plus_keith is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of mc6847t1_ntsc_plus_keith is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"00";
when x"001" => DATA <= x"00";
when x"002" => DATA <= x"38";
when x"003" => DATA <= x"44";
when x"004" => DATA <= x"04";
when x"005" => DATA <= x"34";
when x"006" => DATA <= x"4C";
when x"007" => DATA <= x"4C";
when x"008" => DATA <= x"38";
when x"009" => DATA <= x"00";
when x"00A" => DATA <= x"00";
when x"00B" => DATA <= x"00";
when x"00C" => DATA <= x"00";
when x"00D" => DATA <= x"00";
when x"00E" => DATA <= x"00";
when x"00F" => DATA <= x"00";
when x"010" => DATA <= x"00";
when x"011" => DATA <= x"00";
when x"012" => DATA <= x"10";
when x"013" => DATA <= x"28";
when x"014" => DATA <= x"44";
when x"015" => DATA <= x"44";
when x"016" => DATA <= x"7C";
when x"017" => DATA <= x"44";
when x"018" => DATA <= x"44";
when x"019" => DATA <= x"00";
when x"01A" => DATA <= x"00";
when x"01B" => DATA <= x"00";
when x"01C" => DATA <= x"00";
when x"01D" => DATA <= x"00";
when x"01E" => DATA <= x"00";
when x"01F" => DATA <= x"00";
when x"020" => DATA <= x"00";
when x"021" => DATA <= x"00";
when x"022" => DATA <= x"78";
when x"023" => DATA <= x"24";
when x"024" => DATA <= x"24";
when x"025" => DATA <= x"38";
when x"026" => DATA <= x"24";
when x"027" => DATA <= x"24";
when x"028" => DATA <= x"78";
when x"029" => DATA <= x"00";
when x"02A" => DATA <= x"00";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"00";
when x"02D" => DATA <= x"00";
when x"02E" => DATA <= x"00";
when x"02F" => DATA <= x"00";
when x"030" => DATA <= x"00";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"38";
when x"033" => DATA <= x"44";
when x"034" => DATA <= x"40";
when x"035" => DATA <= x"40";
when x"036" => DATA <= x"40";
when x"037" => DATA <= x"44";
when x"038" => DATA <= x"38";
when x"039" => DATA <= x"00";
when x"03A" => DATA <= x"00";
when x"03B" => DATA <= x"00";
when x"03C" => DATA <= x"00";
when x"03D" => DATA <= x"00";
when x"03E" => DATA <= x"00";
when x"03F" => DATA <= x"00";
when x"040" => DATA <= x"00";
when x"041" => DATA <= x"00";
when x"042" => DATA <= x"78";
when x"043" => DATA <= x"24";
when x"044" => DATA <= x"24";
when x"045" => DATA <= x"24";
when x"046" => DATA <= x"24";
when x"047" => DATA <= x"24";
when x"048" => DATA <= x"78";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"00";
when x"04C" => DATA <= x"00";
when x"04D" => DATA <= x"00";
when x"04E" => DATA <= x"00";
when x"04F" => DATA <= x"00";
when x"050" => DATA <= x"00";
when x"051" => DATA <= x"00";
when x"052" => DATA <= x"7C";
when x"053" => DATA <= x"40";
when x"054" => DATA <= x"40";
when x"055" => DATA <= x"70";
when x"056" => DATA <= x"40";
when x"057" => DATA <= x"40";
when x"058" => DATA <= x"7C";
when x"059" => DATA <= x"00";
when x"05A" => DATA <= x"00";
when x"05B" => DATA <= x"00";
when x"05C" => DATA <= x"00";
when x"05D" => DATA <= x"00";
when x"05E" => DATA <= x"00";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"00";
when x"061" => DATA <= x"00";
when x"062" => DATA <= x"7C";
when x"063" => DATA <= x"40";
when x"064" => DATA <= x"40";
when x"065" => DATA <= x"70";
when x"066" => DATA <= x"40";
when x"067" => DATA <= x"40";
when x"068" => DATA <= x"40";
when x"069" => DATA <= x"00";
when x"06A" => DATA <= x"00";
when x"06B" => DATA <= x"00";
when x"06C" => DATA <= x"00";
when x"06D" => DATA <= x"00";
when x"06E" => DATA <= x"00";
when x"06F" => DATA <= x"00";
when x"070" => DATA <= x"00";
when x"071" => DATA <= x"00";
when x"072" => DATA <= x"38";
when x"073" => DATA <= x"44";
when x"074" => DATA <= x"40";
when x"075" => DATA <= x"40";
when x"076" => DATA <= x"4C";
when x"077" => DATA <= x"44";
when x"078" => DATA <= x"38";
when x"079" => DATA <= x"00";
when x"07A" => DATA <= x"00";
when x"07B" => DATA <= x"00";
when x"07C" => DATA <= x"00";
when x"07D" => DATA <= x"00";
when x"07E" => DATA <= x"00";
when x"07F" => DATA <= x"00";
when x"080" => DATA <= x"00";
when x"081" => DATA <= x"00";
when x"082" => DATA <= x"44";
when x"083" => DATA <= x"44";
when x"084" => DATA <= x"44";
when x"085" => DATA <= x"7C";
when x"086" => DATA <= x"44";
when x"087" => DATA <= x"44";
when x"088" => DATA <= x"44";
when x"089" => DATA <= x"00";
when x"08A" => DATA <= x"00";
when x"08B" => DATA <= x"00";
when x"08C" => DATA <= x"00";
when x"08D" => DATA <= x"00";
when x"08E" => DATA <= x"00";
when x"08F" => DATA <= x"00";
when x"090" => DATA <= x"00";
when x"091" => DATA <= x"00";
when x"092" => DATA <= x"38";
when x"093" => DATA <= x"10";
when x"094" => DATA <= x"10";
when x"095" => DATA <= x"10";
when x"096" => DATA <= x"10";
when x"097" => DATA <= x"10";
when x"098" => DATA <= x"38";
when x"099" => DATA <= x"00";
when x"09A" => DATA <= x"00";
when x"09B" => DATA <= x"00";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"00";
when x"09E" => DATA <= x"00";
when x"09F" => DATA <= x"00";
when x"0A0" => DATA <= x"00";
when x"0A1" => DATA <= x"00";
when x"0A2" => DATA <= x"04";
when x"0A3" => DATA <= x"04";
when x"0A4" => DATA <= x"04";
when x"0A5" => DATA <= x"04";
when x"0A6" => DATA <= x"04";
when x"0A7" => DATA <= x"44";
when x"0A8" => DATA <= x"38";
when x"0A9" => DATA <= x"00";
when x"0AA" => DATA <= x"00";
when x"0AB" => DATA <= x"00";
when x"0AC" => DATA <= x"00";
when x"0AD" => DATA <= x"00";
when x"0AE" => DATA <= x"00";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"00";
when x"0B1" => DATA <= x"00";
when x"0B2" => DATA <= x"44";
when x"0B3" => DATA <= x"48";
when x"0B4" => DATA <= x"50";
when x"0B5" => DATA <= x"60";
when x"0B6" => DATA <= x"50";
when x"0B7" => DATA <= x"48";
when x"0B8" => DATA <= x"44";
when x"0B9" => DATA <= x"00";
when x"0BA" => DATA <= x"00";
when x"0BB" => DATA <= x"00";
when x"0BC" => DATA <= x"00";
when x"0BD" => DATA <= x"00";
when x"0BE" => DATA <= x"00";
when x"0BF" => DATA <= x"00";
when x"0C0" => DATA <= x"00";
when x"0C1" => DATA <= x"00";
when x"0C2" => DATA <= x"40";
when x"0C3" => DATA <= x"40";
when x"0C4" => DATA <= x"40";
when x"0C5" => DATA <= x"40";
when x"0C6" => DATA <= x"40";
when x"0C7" => DATA <= x"40";
when x"0C8" => DATA <= x"7C";
when x"0C9" => DATA <= x"00";
when x"0CA" => DATA <= x"00";
when x"0CB" => DATA <= x"00";
when x"0CC" => DATA <= x"00";
when x"0CD" => DATA <= x"00";
when x"0CE" => DATA <= x"00";
when x"0CF" => DATA <= x"00";
when x"0D0" => DATA <= x"00";
when x"0D1" => DATA <= x"00";
when x"0D2" => DATA <= x"44";
when x"0D3" => DATA <= x"6C";
when x"0D4" => DATA <= x"54";
when x"0D5" => DATA <= x"54";
when x"0D6" => DATA <= x"44";
when x"0D7" => DATA <= x"44";
when x"0D8" => DATA <= x"44";
when x"0D9" => DATA <= x"00";
when x"0DA" => DATA <= x"00";
when x"0DB" => DATA <= x"00";
when x"0DC" => DATA <= x"00";
when x"0DD" => DATA <= x"00";
when x"0DE" => DATA <= x"00";
when x"0DF" => DATA <= x"00";
when x"0E0" => DATA <= x"00";
when x"0E1" => DATA <= x"00";
when x"0E2" => DATA <= x"44";
when x"0E3" => DATA <= x"44";
when x"0E4" => DATA <= x"64";
when x"0E5" => DATA <= x"54";
when x"0E6" => DATA <= x"4C";
when x"0E7" => DATA <= x"44";
when x"0E8" => DATA <= x"44";
when x"0E9" => DATA <= x"00";
when x"0EA" => DATA <= x"00";
when x"0EB" => DATA <= x"00";
when x"0EC" => DATA <= x"00";
when x"0ED" => DATA <= x"00";
when x"0EE" => DATA <= x"00";
when x"0EF" => DATA <= x"00";
when x"0F0" => DATA <= x"00";
when x"0F1" => DATA <= x"00";
when x"0F2" => DATA <= x"38";
when x"0F3" => DATA <= x"44";
when x"0F4" => DATA <= x"44";
when x"0F5" => DATA <= x"44";
when x"0F6" => DATA <= x"44";
when x"0F7" => DATA <= x"44";
when x"0F8" => DATA <= x"38";
when x"0F9" => DATA <= x"00";
when x"0FA" => DATA <= x"00";
when x"0FB" => DATA <= x"00";
when x"0FC" => DATA <= x"00";
when x"0FD" => DATA <= x"00";
when x"0FE" => DATA <= x"00";
when x"0FF" => DATA <= x"00";
when x"100" => DATA <= x"00";
when x"101" => DATA <= x"00";
when x"102" => DATA <= x"78";
when x"103" => DATA <= x"44";
when x"104" => DATA <= x"44";
when x"105" => DATA <= x"78";
when x"106" => DATA <= x"40";
when x"107" => DATA <= x"40";
when x"108" => DATA <= x"40";
when x"109" => DATA <= x"00";
when x"10A" => DATA <= x"00";
when x"10B" => DATA <= x"00";
when x"10C" => DATA <= x"00";
when x"10D" => DATA <= x"00";
when x"10E" => DATA <= x"00";
when x"10F" => DATA <= x"00";
when x"110" => DATA <= x"00";
when x"111" => DATA <= x"00";
when x"112" => DATA <= x"38";
when x"113" => DATA <= x"44";
when x"114" => DATA <= x"44";
when x"115" => DATA <= x"44";
when x"116" => DATA <= x"54";
when x"117" => DATA <= x"48";
when x"118" => DATA <= x"34";
when x"119" => DATA <= x"00";
when x"11A" => DATA <= x"00";
when x"11B" => DATA <= x"00";
when x"11C" => DATA <= x"00";
when x"11D" => DATA <= x"00";
when x"11E" => DATA <= x"00";
when x"11F" => DATA <= x"00";
when x"120" => DATA <= x"00";
when x"121" => DATA <= x"00";
when x"122" => DATA <= x"78";
when x"123" => DATA <= x"44";
when x"124" => DATA <= x"44";
when x"125" => DATA <= x"78";
when x"126" => DATA <= x"50";
when x"127" => DATA <= x"48";
when x"128" => DATA <= x"44";
when x"129" => DATA <= x"00";
when x"12A" => DATA <= x"00";
when x"12B" => DATA <= x"00";
when x"12C" => DATA <= x"00";
when x"12D" => DATA <= x"00";
when x"12E" => DATA <= x"00";
when x"12F" => DATA <= x"00";
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when x"79A" => DATA <= x"00";
when x"79B" => DATA <= x"00";
when x"79C" => DATA <= x"00";
when x"79D" => DATA <= x"00";
when x"79E" => DATA <= x"00";
when x"79F" => DATA <= x"00";
when x"7A0" => DATA <= x"00";
when x"7A1" => DATA <= x"00";
when x"7A2" => DATA <= x"00";
when x"7A3" => DATA <= x"1C";
when x"7A4" => DATA <= x"22";
when x"7A5" => DATA <= x"22";
when x"7A6" => DATA <= x"22";
when x"7A7" => DATA <= x"1C";
when x"7A8" => DATA <= x"00";
when x"7A9" => DATA <= x"00";
when x"7AA" => DATA <= x"00";
when x"7AB" => DATA <= x"00";
when x"7AC" => DATA <= x"00";
when x"7AD" => DATA <= x"00";
when x"7AE" => DATA <= x"00";
when x"7AF" => DATA <= x"00";
when x"7B0" => DATA <= x"00";
when x"7B1" => DATA <= x"00";
when x"7B2" => DATA <= x"00";
when x"7B3" => DATA <= x"00";
when x"7B4" => DATA <= x"28";
when x"7B5" => DATA <= x"14";
when x"7B6" => DATA <= x"0A";
when x"7B7" => DATA <= x"14";
when x"7B8" => DATA <= x"28";
when x"7B9" => DATA <= x"00";
when x"7BA" => DATA <= x"00";
when x"7BB" => DATA <= x"00";
when x"7BC" => DATA <= x"00";
when x"7BD" => DATA <= x"00";
when x"7BE" => DATA <= x"00";
when x"7BF" => DATA <= x"00";
when x"7C0" => DATA <= x"00";
when x"7C1" => DATA <= x"00";
when x"7C2" => DATA <= x"00";
when x"7C3" => DATA <= x"20";
when x"7C4" => DATA <= x"20";
when x"7C5" => DATA <= x"20";
when x"7C6" => DATA <= x"22";
when x"7C7" => DATA <= x"06";
when x"7C8" => DATA <= x"0E";
when x"7C9" => DATA <= x"02";
when x"7CA" => DATA <= x"00";
when x"7CB" => DATA <= x"00";
when x"7CC" => DATA <= x"00";
when x"7CD" => DATA <= x"00";
when x"7CE" => DATA <= x"00";
when x"7CF" => DATA <= x"00";
when x"7D0" => DATA <= x"00";
when x"7D1" => DATA <= x"00";
when x"7D2" => DATA <= x"00";
when x"7D3" => DATA <= x"20";
when x"7D4" => DATA <= x"20";
when x"7D5" => DATA <= x"20";
when x"7D6" => DATA <= x"2E";
when x"7D7" => DATA <= x"02";
when x"7D8" => DATA <= x"04";
when x"7D9" => DATA <= x"0E";
when x"7DA" => DATA <= x"00";
when x"7DB" => DATA <= x"00";
when x"7DC" => DATA <= x"00";
when x"7DD" => DATA <= x"00";
when x"7DE" => DATA <= x"00";
when x"7DF" => DATA <= x"00";
when x"7E0" => DATA <= x"00";
when x"7E1" => DATA <= x"00";
when x"7E2" => DATA <= x"00";
when x"7E3" => DATA <= x"70";
when x"7E4" => DATA <= x"10";
when x"7E5" => DATA <= x"70";
when x"7E6" => DATA <= x"12";
when x"7E7" => DATA <= x"76";
when x"7E8" => DATA <= x"0E";
when x"7E9" => DATA <= x"02";
when x"7EA" => DATA <= x"00";
when x"7EB" => DATA <= x"00";
when x"7EC" => DATA <= x"00";
when x"7ED" => DATA <= x"00";
when x"7EE" => DATA <= x"00";
when x"7EF" => DATA <= x"00";
when x"7F0" => DATA <= x"00";
when x"7F1" => DATA <= x"00";
when x"7F2" => DATA <= x"00";
when x"7F3" => DATA <= x"08";
when x"7F4" => DATA <= x"00";
when x"7F5" => DATA <= x"08";
when x"7F6" => DATA <= x"08";
when x"7F7" => DATA <= x"10";
when x"7F8" => DATA <= x"12";
when x"7F9" => DATA <= x"0C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw_xilinx
--
-- Description:
-- ------------------------------------
-- Implements wide addition providing several options all based
-- on an adaptation of a carry-select approach.
--
-- Xilinx-specific optimizations.
--
-- References:
-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
-- FPL 2011.
-- -> ARCH: AAM, CAI, CCA
-- -> SKIPPING: CCC
--
-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
-- A Novel Modular Adder for One Thousand Bits and More
-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
-- -> ARCH: PAI
-- -> SKIPPING: PPN_KS, PPN_BK
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.arith.all;
entity arith_addw_xilinx is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := CAI; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC -- Carry Skip Scheme
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end entity;
use std.textio.all;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library PoC;
use PoC.utils.all;
architecture rtl of arith_addw_xilinx is
-- Determine Block Boundaries
type tBlocking_vector is array(tArch) of tBlocking;
constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => ASC, PAI => DESC, CCA => DESC);
type integer_vector is array(natural range<>) of integer;
function compute_blocks return integer_vector is
variable bs : tBlocking := BLOCKING;
variable res : integer_vector(K-1 downto 0);
variable l : line;
begin
if bs = DFLT then
bs := DEFAULT_BLOCKING(ARCH);
end if;
case bs is
when FIX =>
assert N >= K
report "Cannot have more blocks than input bits."
severity failure;
for i in res'range loop
res(i) := ((i+1)*N+K/2)/K;
end loop;
when ASC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
end loop;
when DESC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
end loop;
when others =>
report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
end case;
--synthesis translate_off
write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
", BLOCKING="&tBlocking'image(bs)&'[');
for i in K-1 downto 1 loop
write(l, res(i)-res(i-1));
write(l, ',');
end loop;
write(l, res(0));
write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
writeline(output, l);
--synthesis translate_on
return res;
end compute_blocks;
constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
signal g : std_logic_vector(K-1 downto 1); -- Block Generate
signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
begin
-----------------------------------------------------------------------------
-- Rightmost Block and Core Carry Chain
blkCore: block
constant M : positive := BLOCKS(0); -- Rightmost Block Width
signal cc : std_logic_vector(K+M-1 downto 0);
begin
cc(0) <= cin;
-- Rightmost Block
genChain: for i in 0 to M-1 generate
signal pp : std_logic;
begin
pp <= a(i) xor b(i);
cc_mux: MUXCY
port map (
O => cc(i+1),
CI => cc(i),
DI => a(i),
S => pp
);
cc_xor: XORCY
port map (
O => s(i),
CI => cc(i),
LI => pp
);
end generate genChain;
-- Carry Computation with Carry Chain
genCCC: if SKIPPING = CCC generate
genChain: for i in 1 to K-1 generate
cc_mux: MUXCY
port map (
O => cc(M+i),
CI => cc(M+i-1),
DI => g(i),
S => p(i)
);
end generate genChain;
end generate genCCC;
-- Plain linear LUT-based Carry Forwarding
genPlain: if SKIPPING = PLAIN generate
cc(cc'left downto M+1) <= g or (p and cc(K+M-2 downto M));
end generate genPlain;
-- Kogge-Stone Parallel Prefix Network
genPPN_KS: if SKIPPING = PPN_KS generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to LEVELS);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & cc(M);
genLevels: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
end generate genLevels;
cc(cc'left downto M+1) <= gg(gg'high)(K-1 downto 1);
end generate genPPN_KS;
-- Brent-Kung Parallel Prefix Network
genPPN_BK: if SKIPPING = PPN_BK generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to 2*LEVELS-1);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & cc(M);
genMerge: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j mod (2*D) = 2*D-1 generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j mod (2*D) /= 2*D-1 generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genMerge;
genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
constant D : positive := 2**(2*LEVELS-i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j > D and (j+1) mod (2*D) = D generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j <= D or (j+1) mod (2*D) /= D generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genSpread;
cc(cc'left downto M+1) <= gg(gg'high)(K-1 downto 1);
end generate genPPN_BK;
c <= cc(K+M-2 downto M);
cout <= cc(cc'left);
end block blkCore;
-----------------------------------------------------------------------------
-- Implement Carry-Select Variant
--
-- all but rightmost block, implementation architecture selected by ARCH
genBlocks: for i in 1 to K-1 generate
-- Covered Index Range
constant LO : positive := BLOCKS(i-1); -- Low Bit Index
constant HI : positive := BLOCKS(i)-1; -- High Bit Index
begin
-- ARCH-specific Implementations
--Add-Add-Multiplex
genAAM: if ARCH = AAM generate
signal c0 : std_logic_vector(HI+1 downto LO);
signal c1 : std_logic_vector(HI+1 downto LO);
begin
c0(LO) <= '0';
c1(LO) <= '1';
genChain: for j in LO to HI generate
signal p0, s0 : std_logic;
signal p1, s1 : std_logic;
begin
p0 <= a(j) xor b(j);
-- Computation of (c0, s0)
c0_mux: MUXCY
port map (
O => c0(j+1),
CI => c0(j),
DI => a(j),
S => p0
);
c0_xor: XORCY
port map (
O => s0,
CI => c0(j),
LI => p0
);
-- Computation of (c1, s1) and Block Sum
c1_lut: LUT6_2
generic map (
INIT => x"66666666_FF00F0F0"
)
port map (
O6 => p1,
O5 => s(j),
I5 => '1',
I4 => c(i),
I3 => s1,
I2 => s0,
I1 => b(j),
I0 => a(j)
);
c1_mux: MUXCY
port map (
O => c1(j+1),
CI => c1(j),
DI => a(j),
S => p1
);
c1_xor: XORCY
port map (
O => s1,
CI => c1(j),
LI => p1
);
end generate genChain;
g(i) <= c0(HI+1);
p(i) <= c1(HI+1) xor c0(HI+1);
end generate genAAM;
-- Compare-Add-Increment
genCAI: if ARCH = CAI generate
constant MD : natural := (HI-LO+1)/2; -- Full double blocks
constant MR : natural := HI-LO+1 - 2*MD; -- Single closing block
signal c0 : std_logic_vector(HI+1 downto LO);
signal pp : std_logic_vector(MR+MD downto 0); -- Cumulative Propagates
begin
-- Computation of P and s
c0(LO) <= '0';
pp(0) <= '1';
genDoubles: for j in 0 to MD-1 generate
constant BASE : natural := LO + 2*j;
signal pl, pr : std_logic; -- Left / right propagates
signal sl, sr : std_logic; -- Left / right sum bits
signal pd : std_logic; -- Joint propagate
begin
-- Sum Bit Computations
ps_lut_r: LUT6_2
generic map (
INIT => x"66666666_9F60FF00"
)
port map (
O6 => pr,
O5 => s(BASE+1),
I5 => '1',
I4 => c(i),
I3 => sl,
I2 => pp(j),
I1 => b(BASE),
I0 => a(BASE)
);
ps_lut_l: LUT6_2
generic map (
INIT => x"66666666_0FF0FF00"
)
port map (
O6 => pl,
O5 => s(BASE),
I5 => '1',
I4 => c(i),
I3 => sr,
I2 => pp(j),
I1 => b(BASE+1),
I0 => a(BASE+1)
);
c0_mux_r: MUXCY
port map (
O => c0(BASE+1),
CI => c0(BASE),
DI => a(BASE),
S => pr
);
c0_mux_l: MUXCY
port map (
O => c0(BASE+2),
CI => c0(BASE+1),
DI => a(BASE+1),
S => pl
);
genLSB: if j = 0 generate
sr <= pr;
end generate;
genHSB: if j > 0 generate
s0_xor_r: XORCY
port map (
O => sr,
CI => c0(BASE),
LI => pr
);
end generate;
s0_xor_l: XORCY
port map (
O => sl,
CI => c0(BASE+1),
LI => pl
);
-- Propagate Chain
pd <= (a(BASE+1) xor b(BASE+1)) and (a(BASE) xor b(BASE));
pp_mux: MUXCY
port map (
O => pp(j+1),
CI => pp(j),
DI => '0',
S => pd
);
end generate genDoubles;
genLast: if MR > 0 generate
constant BASE : natural := LO+2*MD;
signal p, s0 : std_logic;
begin
ps_lut_l: LUT6_2
generic map (
INIT => x"66666666_0FF0FF00"
)
port map (
O6 => p,
O5 => s(BASE),
I5 => '1',
I4 => c(i),
I3 => s0,
I2 => pp(MD),
I1 => b(BASE),
I0 => a(BASE)
);
c0_mux: MUXCY
port map (
O => c0(BASE+1),
CI => c0(BASE),
DI => a(BASE),
S => p
);
s0_xor: XORCY
port map (
O => s0,
CI => c0(BASE),
LI => p
);
-- Let synthesis merge it into carry computation
pp(pp'left) <= (a(BASE) xor b(BASE)) and pp(MD);
end generate genLast;
g(i) <= c0(c0'left);
p(i) <= pp(pp'left);
end generate genCAI;
genCCA: if ARCH = CCA generate
constant M : positive := HI-LO+1;
constant D : positive := M/2;
constant H : positive := (D+5)/6;
signal pl : std_logic_vector(M-D-1 downto 0);
signal pc : std_logic_vector(M-D downto 0);
begin
pc(0) <= '0';
genDoubles: for j in 0 to D-1 generate
signal gl : std_logic;
begin
gp_lut: LUT6_2
generic map (
INIT => x"12480000_EE880000"
)
port map (
O6 => pl(j),
O5 => gl,
I5 => '1',
I4 => '1',
I3 => a(LO+2*j+1),
I2 => a(LO+2*j),
I1 => b(LO+2*j+1),
I0 => b(LO+2*j)
);
c0_mux: MUXCY
port map (
O => pc(j+1),
CI => pc(j),
DI => gl,
S => pl(j)
);
end generate genDoubles;
genOdd: if M-D > D generate
pl(D) <= a(HI) xnor b(HI);
pc(D+1) <= pl(D) and pc(D);
end generate genOdd;
g(i) <= pc(pc'left);
p(i) <= 'X' when Is_X(pl) else
'1' when pl = (pl'range => '1') else
'0';
s(HI downto LO) <= std_logic_vector(unsigned(a(HI downto LO)) + unsigned(b(HI downto LO)) +
(0 to 0 => c(i)));
end generate genCCA;
end generate genBlocks;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw_xilinx
--
-- Description:
-- ------------------------------------
-- Implements wide addition providing several options all based
-- on an adaptation of a carry-select approach.
--
-- Xilinx-specific optimizations.
--
-- References:
-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
-- FPL 2011.
-- -> ARCH: AAM, CAI, CCA
-- -> SKIPPING: CCC
--
-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
-- A Novel Modular Adder for One Thousand Bits and More
-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
-- -> ARCH: PAI
-- -> SKIPPING: PPN_KS, PPN_BK
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.arith.all;
entity arith_addw_xilinx is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := CAI; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC -- Carry Skip Scheme
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end entity;
use std.textio.all;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library PoC;
use PoC.utils.all;
architecture rtl of arith_addw_xilinx is
-- Determine Block Boundaries
type tBlocking_vector is array(tArch) of tBlocking;
constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => ASC, PAI => DESC, CCA => DESC);
type integer_vector is array(natural range<>) of integer;
function compute_blocks return integer_vector is
variable bs : tBlocking := BLOCKING;
variable res : integer_vector(K-1 downto 0);
variable l : line;
begin
if bs = DFLT then
bs := DEFAULT_BLOCKING(ARCH);
end if;
case bs is
when FIX =>
assert N >= K
report "Cannot have more blocks than input bits."
severity failure;
for i in res'range loop
res(i) := ((i+1)*N+K/2)/K;
end loop;
when ASC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
end loop;
when DESC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
end loop;
when others =>
report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
end case;
--synthesis translate_off
write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
", BLOCKING="&tBlocking'image(bs)&'[');
for i in K-1 downto 1 loop
write(l, res(i)-res(i-1));
write(l, ',');
end loop;
write(l, res(0));
write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
writeline(output, l);
--synthesis translate_on
return res;
end compute_blocks;
constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
signal g : std_logic_vector(K-1 downto 1); -- Block Generate
signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
begin
-----------------------------------------------------------------------------
-- Rightmost Block and Core Carry Chain
blkCore: block
constant M : positive := BLOCKS(0); -- Rightmost Block Width
signal cc : std_logic_vector(K+M-1 downto 0);
begin
cc(0) <= cin;
-- Rightmost Block
genChain: for i in 0 to M-1 generate
signal pp : std_logic;
begin
pp <= a(i) xor b(i);
cc_mux: MUXCY
port map (
O => cc(i+1),
CI => cc(i),
DI => a(i),
S => pp
);
cc_xor: XORCY
port map (
O => s(i),
CI => cc(i),
LI => pp
);
end generate genChain;
-- Carry Computation with Carry Chain
genCCC: if SKIPPING = CCC generate
genChain: for i in 1 to K-1 generate
cc_mux: MUXCY
port map (
O => cc(M+i),
CI => cc(M+i-1),
DI => g(i),
S => p(i)
);
end generate genChain;
end generate genCCC;
-- Plain linear LUT-based Carry Forwarding
genPlain: if SKIPPING = PLAIN generate
cc(cc'left downto M+1) <= g or (p and cc(K+M-2 downto M));
end generate genPlain;
-- Kogge-Stone Parallel Prefix Network
genPPN_KS: if SKIPPING = PPN_KS generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to LEVELS);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & cc(M);
genLevels: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
end generate genLevels;
cc(cc'left downto M+1) <= gg(gg'high)(K-1 downto 1);
end generate genPPN_KS;
-- Brent-Kung Parallel Prefix Network
genPPN_BK: if SKIPPING = PPN_BK generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to 2*LEVELS-1);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & cc(M);
genMerge: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j mod (2*D) = 2*D-1 generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j mod (2*D) /= 2*D-1 generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genMerge;
genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
constant D : positive := 2**(2*LEVELS-i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j > D and (j+1) mod (2*D) = D generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j <= D or (j+1) mod (2*D) /= D generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genSpread;
cc(cc'left downto M+1) <= gg(gg'high)(K-1 downto 1);
end generate genPPN_BK;
c <= cc(K+M-2 downto M);
cout <= cc(cc'left);
end block blkCore;
-----------------------------------------------------------------------------
-- Implement Carry-Select Variant
--
-- all but rightmost block, implementation architecture selected by ARCH
genBlocks: for i in 1 to K-1 generate
-- Covered Index Range
constant LO : positive := BLOCKS(i-1); -- Low Bit Index
constant HI : positive := BLOCKS(i)-1; -- High Bit Index
begin
-- ARCH-specific Implementations
--Add-Add-Multiplex
genAAM: if ARCH = AAM generate
signal c0 : std_logic_vector(HI+1 downto LO);
signal c1 : std_logic_vector(HI+1 downto LO);
begin
c0(LO) <= '0';
c1(LO) <= '1';
genChain: for j in LO to HI generate
signal p0, s0 : std_logic;
signal p1, s1 : std_logic;
begin
p0 <= a(j) xor b(j);
-- Computation of (c0, s0)
c0_mux: MUXCY
port map (
O => c0(j+1),
CI => c0(j),
DI => a(j),
S => p0
);
c0_xor: XORCY
port map (
O => s0,
CI => c0(j),
LI => p0
);
-- Computation of (c1, s1) and Block Sum
c1_lut: LUT6_2
generic map (
INIT => x"66666666_FF00F0F0"
)
port map (
O6 => p1,
O5 => s(j),
I5 => '1',
I4 => c(i),
I3 => s1,
I2 => s0,
I1 => b(j),
I0 => a(j)
);
c1_mux: MUXCY
port map (
O => c1(j+1),
CI => c1(j),
DI => a(j),
S => p1
);
c1_xor: XORCY
port map (
O => s1,
CI => c1(j),
LI => p1
);
end generate genChain;
g(i) <= c0(HI+1);
p(i) <= c1(HI+1) xor c0(HI+1);
end generate genAAM;
-- Compare-Add-Increment
genCAI: if ARCH = CAI generate
constant MD : natural := (HI-LO+1)/2; -- Full double blocks
constant MR : natural := HI-LO+1 - 2*MD; -- Single closing block
signal c0 : std_logic_vector(HI+1 downto LO);
signal pp : std_logic_vector(MR+MD downto 0); -- Cumulative Propagates
begin
-- Computation of P and s
c0(LO) <= '0';
pp(0) <= '1';
genDoubles: for j in 0 to MD-1 generate
constant BASE : natural := LO + 2*j;
signal pl, pr : std_logic; -- Left / right propagates
signal sl, sr : std_logic; -- Left / right sum bits
signal pd : std_logic; -- Joint propagate
begin
-- Sum Bit Computations
ps_lut_r: LUT6_2
generic map (
INIT => x"66666666_9F60FF00"
)
port map (
O6 => pr,
O5 => s(BASE+1),
I5 => '1',
I4 => c(i),
I3 => sl,
I2 => pp(j),
I1 => b(BASE),
I0 => a(BASE)
);
ps_lut_l: LUT6_2
generic map (
INIT => x"66666666_0FF0FF00"
)
port map (
O6 => pl,
O5 => s(BASE),
I5 => '1',
I4 => c(i),
I3 => sr,
I2 => pp(j),
I1 => b(BASE+1),
I0 => a(BASE+1)
);
c0_mux_r: MUXCY
port map (
O => c0(BASE+1),
CI => c0(BASE),
DI => a(BASE),
S => pr
);
c0_mux_l: MUXCY
port map (
O => c0(BASE+2),
CI => c0(BASE+1),
DI => a(BASE+1),
S => pl
);
genLSB: if j = 0 generate
sr <= pr;
end generate;
genHSB: if j > 0 generate
s0_xor_r: XORCY
port map (
O => sr,
CI => c0(BASE),
LI => pr
);
end generate;
s0_xor_l: XORCY
port map (
O => sl,
CI => c0(BASE+1),
LI => pl
);
-- Propagate Chain
pd <= (a(BASE+1) xor b(BASE+1)) and (a(BASE) xor b(BASE));
pp_mux: MUXCY
port map (
O => pp(j+1),
CI => pp(j),
DI => '0',
S => pd
);
end generate genDoubles;
genLast: if MR > 0 generate
constant BASE : natural := LO+2*MD;
signal p, s0 : std_logic;
begin
ps_lut_l: LUT6_2
generic map (
INIT => x"66666666_0FF0FF00"
)
port map (
O6 => p,
O5 => s(BASE),
I5 => '1',
I4 => c(i),
I3 => s0,
I2 => pp(MD),
I1 => b(BASE),
I0 => a(BASE)
);
c0_mux: MUXCY
port map (
O => c0(BASE+1),
CI => c0(BASE),
DI => a(BASE),
S => p
);
s0_xor: XORCY
port map (
O => s0,
CI => c0(BASE),
LI => p
);
-- Let synthesis merge it into carry computation
pp(pp'left) <= (a(BASE) xor b(BASE)) and pp(MD);
end generate genLast;
g(i) <= c0(c0'left);
p(i) <= pp(pp'left);
end generate genCAI;
genCCA: if ARCH = CCA generate
constant M : positive := HI-LO+1;
constant D : positive := M/2;
constant H : positive := (D+5)/6;
signal pl : std_logic_vector(M-D-1 downto 0);
signal pc : std_logic_vector(M-D downto 0);
begin
pc(0) <= '0';
genDoubles: for j in 0 to D-1 generate
signal gl : std_logic;
begin
gp_lut: LUT6_2
generic map (
INIT => x"12480000_EE880000"
)
port map (
O6 => pl(j),
O5 => gl,
I5 => '1',
I4 => '1',
I3 => a(LO+2*j+1),
I2 => a(LO+2*j),
I1 => b(LO+2*j+1),
I0 => b(LO+2*j)
);
c0_mux: MUXCY
port map (
O => pc(j+1),
CI => pc(j),
DI => gl,
S => pl(j)
);
end generate genDoubles;
genOdd: if M-D > D generate
pl(D) <= a(HI) xnor b(HI);
pc(D+1) <= pl(D) and pc(D);
end generate genOdd;
g(i) <= pc(pc'left);
p(i) <= 'X' when Is_X(pl) else
'1' when pl = (pl'range => '1') else
'0';
s(HI downto LO) <= std_logic_vector(unsigned(a(HI downto LO)) + unsigned(b(HI downto LO)) +
(0 to 0 => c(i)));
end generate genCCA;
end generate genBlocks;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_295 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_295;
architecture augh of add_295 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_295 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_295;
architecture augh of add_295 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ft a : wr_block and rd_block must be synchronized with clk
entity fifo_block is
generic (
DWIDTH : integer; -- 8
BLOCK_AWIDTH : integer; -- 5
FIFO_AWIDTH : integer; -- 2
RAM_TYPE : string(1 to 7)
);
port (
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector(BLOCK_AWIDTH - 1 downto 0);
wdata : in std_logic_vector(DWIDTH - 1 downto 0);
rd_block : in std_logic;
rd_clk : in std_logic; -- zcpsm_clk
raddr : in std_logic_vector(BLOCK_AWIDTH - 1 downto 0); -- ÓÉzcpsmÌṩ
rdata : out std_logic_vector(DWIDTH - 1 downto 0); -- Ìṩ¸øzcpsm
full : out std_logic;
empty : out std_logic
);
end fifo_block;
architecture behave of fifo_block is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal wp_block : std_logic_vector(FIFO_AWIDTH - 1 downto 0) := (others => '0');
signal rp_block : std_logic_vector(FIFO_AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal ram_waddr : std_logic_vector(FIFO_AWIDTH + BLOCK_AWIDTH - 1 downto 0) := (others => '0');
signal ram_raddr : std_logic_vector(FIFO_AWIDTH + BLOCK_AWIDTH - 1 downto 0) := (others => '0');
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
signal rdata_buf : std_logic_vector(DWIDTH - 1 downto 0);
constant FIFO_DEPTH : natural := 2 ** FIFO_AWIDTH;
constant BLOCK_DEPTH : natural := 2 ** BLOCK_AWIDTH;
begin
use_block_ram : if RAM_TYPE = "BLK_RAM" generate
ram : blockdram
generic map(
depth => FIFO_DEPTH * BLOCK_DEPTH,
Dwidth => DWIDTH,
Awidth => FIFO_AWIDTH + BLOCK_AWIDTH
)
port map(
addra => ram_waddr,
clka => wr_clk,
addrb => ram_raddr,
clkb => rd_clk,
dia => wdata,
wea => ram_we,
dob => rdata
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => FIFO_DEPTH * BLOCK_DEPTH,
Dwidth => DWIDTH,
Awidth => FIFO_AWIDTH + BLOCK_AWIDTH
)
port map(
A => ram_waddr,
CLK => wr_clk,
D => wdata,
WE => ram_we,
DPRA => ram_raddr,
DPO => rdata_buf,
QDPO => open
);
process(rd_clk)
begin
if rising_edge(rd_clk) then
rdata <= rdata_buf;
end if;
end process;
end generate use_dis_ram;
g_multi_block : if FIFO_AWIDTH > 0 generate
ram_we <= wren and (not full_flag); -- ram_write_enable
ram_waddr <= wp_block & waddr; -- ram_write_addr
ram_raddr <= rp_block & raddr; -- ram_read_addr
WritePointerCtrl : process(clk, reset) -- УÑé´íÎóʱ°ü¶ªÆú
begin
if reset = '1' then
wp_block <= (others => '0');
elsif rising_edge(clk) then
if clr = '1' then
wp_block <= (others => '0');
elsif full_flag = '0' and wr_block = '1' then -- ·ÇÂúʱ£¬Ò»¸öÒÔÌ«°ü·¢ËÍÍê±ÏдÊý¾Ý¿éµØÖ·¼Ó1
wp_block <= wp_block + 1;
end if;
end if;
end process;
ReadPointerCtrl : process(clk, reset)
begin
if reset = '1' then
rp_block <= (others => '0');
elsif rising_edge(clk) then
if clr = '1' then
rp_block <= (others => '0');
elsif empty_flag = '0' and rd_block = '1' then -- ·Ç¿Õʱ£¬¶ÁÊý¾Ý¿éµØÖ·¼Ó1
rp_block <= rp_block + 1;
end if;
end if;
end process;
GetEmptyFlag : process(clk, reset)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clk) then
if clr = '1' then
empty_flag <= '1';
elsif (wp_block = rp_block) and (wr_block = '1') then
empty_flag <= '0';
elsif (wp_block = rp_block + 1) and (rd_block = '1'and wr_block = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(clk, reset)
begin
if reset = '1' then
full_flag <= '0';
elsif rising_edge(clk) then
if clr = '1' then
full_flag <= '0';
elsif (wp_block = rp_block - 1) and (wr_block = '1' and rd_block = '0') then
full_flag <= '1';
elsif (wp_block = rp_block) and (rd_block = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
end generate;
g_single_block : if FIFO_AWIDTH = 0 generate
ram_we <= wren and (not full_flag);
ram_waddr <= waddr;
ram_raddr <= raddr;
GetEmptyFlag : process(clk, reset)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clk) then
if clr = '1' then
empty_flag <= '1';
elsif wr_block = '1' then
empty_flag <= '0';
elsif rd_block = '1'and wr_block = '0' then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(clk, reset)
begin
if reset = '1' then
full_flag <= '0';
elsif rising_edge(clk) then
if clr = '1' then
full_flag <= '0';
elsif wr_block = '1' and rd_block = '0' then
full_flag <= '1';
elsif rd_block = '1' then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
end generate;
end behave;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ok_4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_4_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_ok_4_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ok_4_rtl_conf / inst_ok_4_e
--
configuration inst_ok_4_rtl_conf of inst_ok_4_e is
for rtl
-- Generated Configuration
end for;
end inst_ok_4_rtl_conf;
--
-- End of Generated Configuration inst_ok_4_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AsyncDataRegisterAdapter is
Generic ( Size : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
-- Data interface
DI : in STD_LOGIC_VECTOR (Size-1 downto 0);
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)
);
end AsyncDataRegisterAdapter;
architecture AsyncDataRegisterAdapter_arch of AsyncDataRegisterAdapter is
signal DI_sync_first, DI_sync: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_do: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_so: STD_LOGIC;
signal sticky_flags, sticky_flags_mux: STD_LOGIC_VECTOR (Size-1 downto 0);
signal flag_mask_strobe: STD_LOGIC;
component SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
begin
sticky_flags_mux <= (sticky_flags or DI_sync) and not sreg_do when flag_mask_strobe = '1' else sticky_flags or DI_sync;
synchronizer_di : process(TCK,RST)
begin
if RST = '1' then
DI_sync_first <= (others => '0');
DI_sync <= (others => '0');
elsif TCK'event and TCK = '1' then
DI_sync_first <= DI;
DI_sync <= DI_sync_first;
end if ;
end process ; -- synchronizer
sticky_flag_update : process(TCK,RST)
begin
if RST = '1' then
sticky_flags <= (others => '0');
elsif TCK'event and TCK = '1' then
sticky_flags <= sticky_flags_mux;
end if ;
end process ;
sticky_flag_update_strobe : process(TCK)
begin
if TCK'event and TCK = '1' then
flag_mask_strobe <= SEL and UE;
end if;
end process;
SO <= sreg_so;
DO <= sreg_do;
shiftreg : SReg
Generic map ( Size => Size)
Port map ( -- Scan Interface scan_client ----------
SI => SI, -- Input Port SI = SI
SO => sreg_so,
SEL => SEL,
----------------------------------------
SE => SE,
CE => CE,
UE => UE,
RST => RST,
TCK => TCK,
DI => sticky_flags,
DO => sreg_do);
end AsyncDataRegisterAdapter_arch; |
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AsyncDataRegisterAdapter is
Generic ( Size : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
-- Data interface
DI : in STD_LOGIC_VECTOR (Size-1 downto 0);
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)
);
end AsyncDataRegisterAdapter;
architecture AsyncDataRegisterAdapter_arch of AsyncDataRegisterAdapter is
signal DI_sync_first, DI_sync: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_do: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_so: STD_LOGIC;
signal sticky_flags, sticky_flags_mux: STD_LOGIC_VECTOR (Size-1 downto 0);
signal flag_mask_strobe: STD_LOGIC;
component SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
begin
sticky_flags_mux <= (sticky_flags or DI_sync) and not sreg_do when flag_mask_strobe = '1' else sticky_flags or DI_sync;
synchronizer_di : process(TCK,RST)
begin
if RST = '1' then
DI_sync_first <= (others => '0');
DI_sync <= (others => '0');
elsif TCK'event and TCK = '1' then
DI_sync_first <= DI;
DI_sync <= DI_sync_first;
end if ;
end process ; -- synchronizer
sticky_flag_update : process(TCK,RST)
begin
if RST = '1' then
sticky_flags <= (others => '0');
elsif TCK'event and TCK = '1' then
sticky_flags <= sticky_flags_mux;
end if ;
end process ;
sticky_flag_update_strobe : process(TCK)
begin
if TCK'event and TCK = '1' then
flag_mask_strobe <= SEL and UE;
end if;
end process;
SO <= sreg_so;
DO <= sreg_do;
shiftreg : SReg
Generic map ( Size => Size)
Port map ( -- Scan Interface scan_client ----------
SI => SI, -- Input Port SI = SI
SO => sreg_so,
SEL => SEL,
----------------------------------------
SE => SE,
CE => CE,
UE => UE,
RST => RST,
TCK => TCK,
DI => sticky_flags,
DO => sreg_do);
end AsyncDataRegisterAdapter_arch; |
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AsyncDataRegisterAdapter is
Generic ( Size : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
-- Data interface
DI : in STD_LOGIC_VECTOR (Size-1 downto 0);
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)
);
end AsyncDataRegisterAdapter;
architecture AsyncDataRegisterAdapter_arch of AsyncDataRegisterAdapter is
signal DI_sync_first, DI_sync: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_do: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_so: STD_LOGIC;
signal sticky_flags, sticky_flags_mux: STD_LOGIC_VECTOR (Size-1 downto 0);
signal flag_mask_strobe: STD_LOGIC;
component SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
begin
sticky_flags_mux <= (sticky_flags or DI_sync) and not sreg_do when flag_mask_strobe = '1' else sticky_flags or DI_sync;
synchronizer_di : process(TCK,RST)
begin
if RST = '1' then
DI_sync_first <= (others => '0');
DI_sync <= (others => '0');
elsif TCK'event and TCK = '1' then
DI_sync_first <= DI;
DI_sync <= DI_sync_first;
end if ;
end process ; -- synchronizer
sticky_flag_update : process(TCK,RST)
begin
if RST = '1' then
sticky_flags <= (others => '0');
elsif TCK'event and TCK = '1' then
sticky_flags <= sticky_flags_mux;
end if ;
end process ;
sticky_flag_update_strobe : process(TCK)
begin
if TCK'event and TCK = '1' then
flag_mask_strobe <= SEL and UE;
end if;
end process;
SO <= sreg_so;
DO <= sreg_do;
shiftreg : SReg
Generic map ( Size => Size)
Port map ( -- Scan Interface scan_client ----------
SI => SI, -- Input Port SI = SI
SO => sreg_so,
SEL => SEL,
----------------------------------------
SE => SE,
CE => CE,
UE => UE,
RST => RST,
TCK => TCK,
DI => sticky_flags,
DO => sreg_do);
end AsyncDataRegisterAdapter_arch; |
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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geGq62l+Lm/hk7CAIio8Wb5k5weg2+Pg9THkxA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51456)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_sort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_sort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_sort is
component mergesort is
port
(
array0_addr0 : out std_logic_vector(0 to (32 - 1));
array0_dIN0 : out std_logic_vector(0 to (32 - 1));
array0_dOUT0 : in std_logic_vector(0 to (32 - 1));
array0_rENA0 : out std_logic;
array0_wENA0 : out std_logic;
array1_addr0 : out std_logic_vector(0 to (32 - 1));
array1_dIN0 : out std_logic_vector(0 to (32 - 1));
array1_dOUT0 : in std_logic_vector(0 to (32 - 1));
array1_rENA0 : out std_logic;
array1_wENA0 : out std_logic;
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
signal in_BRAM_A_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_A_wEN : std_logic;
signal in_BRAM_B_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_B_wEN : std_logic;
signal in_BRAM_C_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_C_wEN : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
BRAM_A_addr <= in_BRAM_A_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_A_wEN <= in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN;
BRAM_B_addr <= in_BRAM_B_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_B_wEN <= in_BRAM_B_WEN&in_BRAM_B_WEN&in_BRAM_B_WEN&in_BRAM_B_WEN;
BRAM_C_addr <= in_BRAM_C_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_C_wEN <= in_BRAM_C_WEN&in_BRAM_C_WEN&in_BRAM_C_WEN&in_BRAM_C_WEN;
uut : mergesort
port map (
array0_addr0 => in_BRAM_A_addr,
array0_dIN0 => BRAM_A_dout,
array0_dOUT0 => BRAM_A_din,
array0_rENA0 => BRAM_A_en,
array0_wENA0 => in_BRAM_A_wen,
array1_addr0 => in_BRAM_B_addr,
array1_dIN0 => BRAM_B_dout,
array1_dOUT0 => BRAM_B_din,
array1_rENA0 => BRAM_B_en,
array1_wENA0 => in_BRAM_B_wen,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
|
entity repro2 is
generic (depth : natural := 7);
port (foo: in boolean);
end entity;
architecture foo of repro2 is
signal foo_int: boolean;
begin
cond: if depth > 0 generate
FUMBLE:
entity work.repro2
generic map (depth => depth - 1)
port map (foo => foo_int);
end generate;
end architecture;
|
entity repro2 is
generic (depth : natural := 7);
port (foo: in boolean);
end entity;
architecture foo of repro2 is
signal foo_int: boolean;
begin
cond: if depth > 0 generate
FUMBLE:
entity work.repro2
generic map (depth => depth - 1)
port map (foo => foo_int);
end generate;
end architecture;
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_1
-- Component declaration for blk_mem_gen_v8_1 pulled from the blk_mem_gen_v8_1.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_1
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
-- C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v8_1
END coregen_comp_defs;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Nox && Gabbe
--
-- Create Date: 14:49:40 09/16/2014
-- Design Name:
-- Module Name: big_little_endian - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Converts big endian in-data to little endian out-data
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity big_little_endian is
port (
in_data : in std_logic_vector(31 downto 0);
out_data : out std_logic_vector(31 downto 0)
);
end big_little_endian;
architecture Behavioral of big_little_endian is
begin
out_data <= in_data(7 downto 0) & in_data(15 downto 8) & in_data(23 downto 16) & in_data(31 downto 24);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Nox && Gabbe
--
-- Create Date: 14:49:40 09/16/2014
-- Design Name:
-- Module Name: big_little_endian - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Converts big endian in-data to little endian out-data
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity big_little_endian is
port (
in_data : in std_logic_vector(31 downto 0);
out_data : out std_logic_vector(31 downto 0)
);
end big_little_endian;
architecture Behavioral of big_little_endian is
begin
out_data <= in_data(7 downto 0) & in_data(15 downto 8) & in_data(23 downto 16) & in_data(31 downto 24);
end Behavioral;
|
entity while1 is
end entity;
architecture test of while1 is
begin
process is
variable n : integer := 5;
begin
while n > 0 loop
n := n - 1;
end loop;
wait;
end process;
end architecture;
|
entity while1 is
end entity;
architecture test of while1 is
begin
process is
variable n : integer := 5;
begin
while n > 0 loop
n := n - 1;
end loop;
wait;
end process;
end architecture;
|
entity while1 is
end entity;
architecture test of while1 is
begin
process is
variable n : integer := 5;
begin
while n > 0 loop
n := n - 1;
end loop;
wait;
end process;
end architecture;
|
entity while1 is
end entity;
architecture test of while1 is
begin
process is
variable n : integer := 5;
begin
while n > 0 loop
n := n - 1;
end loop;
wait;
end process;
end architecture;
|
-- Wait in procedure
entity test is
end entity test;
architecture test_arch of test is
signal s : integer;
procedure p1(signal s1 : inout integer; variable v1 : inout integer) is
begin
s1 <= 0;
v1 := 0;
wait for 4 us;
s1 <= 1;
v1 := 1;
wait for 4 us;
s1 <= 2;
v1 := 2;
end procedure;
begin
main: process
variable v : integer;
begin
p1(s,v);
report "s = " & integer'image(s);
report "v = " & integer'image(v);
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity increment is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
start : in STD_LOGIC;
x_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
step : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
x : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
stop : out std_logic);
end increment;
architecture Behavioral of increment is
signal xs, ys : signed(XY_RANGE-1 downto 0);
signal xcount : integer range 0 to XRES-1:=0;
signal ycount : integer range 0 to YRES-1:=0;
begin
process(clock, reset,start,x_start,y_start,step)
begin
if reset='1' then
xcount<=0;
ycount<=0;
xs<= signed(x_start);
ys<= signed(y_start);
stop<='0';
elsif rising_edge(clock) then
if(start='1') then
if xcount = XRES-1 then
if ycount = YRES-1 then
xcount <= 0;
ycount <= 0;
xs<=signed(x_start);
ys<=signed(y_start);
stop<='1';
else
xcount <= 0;
ycount <= ycount+1;
ys<=ys+signed(step);
xs<=signed(x_start);
stop<='0';
end if;
else
stop<='0';
xs<=xs+signed(step);
xcount<=xcount+1;
end if;
end if;
end if;
end process;
x<=std_logic_vector(xs);
y<=std_logic_vector(ys);
end Behavioral; |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02000_bad.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of Finite State Machine: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_02000_bad is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end CNE_02000_bad;
architecture Behavioral of CNE_02000_bad is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
--CODE
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal State : t_state; -- State signal
--CODE
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter:Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
State <= init;
elsif (rising_edge(i_Clock)) then
case State is
when init =>
-- Set the length value
Length <= c_Length;
State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count='0') then
Enable <= i_Start xor not i_Stop;
State <= Enabled;
else
Enable <= '0';
State <= finished;
end if;
when others =>
State <= init;
end case;
end if;
end process;
end Behavioral; |
-- NEED RESULT: ENT00013: Associated scalar generics with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00013
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.1 (2)
-- 1.1.1.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00013(ARCH00013)
-- ENT00013_Test_Bench(ARCH00013_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00013 is
generic (
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) ;
begin
end ENT00013 ;
--
architecture ARCH00013 of ENT00013 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_2
and i_boolean_2 = c_boolean_2 ;
correct := correct and i_bit_1 = c_bit_2
and i_bit_2 = c_bit_2 ;
correct := correct and i_severity_level_1 = c_severity_level_2
and i_severity_level_2 = c_severity_level_2 ;
correct := correct and i_character_1 = c_character_2
and i_character_2 = c_character_2 ;
correct := correct and i_t_enum1_1 = c_t_enum1_2
and i_t_enum1_2 = c_t_enum1_2 ;
correct := correct and i_st_enum1_1 = c_st_enum1_2
and i_st_enum1_2 = c_st_enum1_2 ;
correct := correct and i_integer_1 = c_integer_2
and i_integer_2 = c_integer_2 ;
correct := correct and i_t_int1_1 = c_t_int1_2
and i_t_int1_2 = c_t_int1_2 ;
correct := correct and i_st_int1_1 = c_st_int1_2
and i_st_int1_2 = c_st_int1_2 ;
correct := correct and i_time_1 = c_time_2
and i_time_2 = c_time_2 ;
correct := correct and i_t_phys1_1 = c_t_phys1_2
and i_t_phys1_2 = c_t_phys1_2 ;
correct := correct and i_st_phys1_1 = c_st_phys1_2
and i_st_phys1_2 = c_st_phys1_2 ;
correct := correct and i_real_1 = c_real_2
and i_real_2 = c_real_2 ;
correct := correct and i_t_real1_1 = c_t_real1_2
and i_t_real1_2 = c_t_real1_2 ;
correct := correct and i_st_real1_1 = c_st_real1_2
and i_st_real1_2 = c_st_real1_2 ;
test_report ( "ENT00013" ,
"Associated scalar generics with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00013 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00013_Test_Bench is
end ENT00013_Test_Bench ;
--
architecture ARCH00013_Test_Bench of ENT00013_Test_Bench is
begin
L1:
block
component UUT
generic (
i_boolean_1, i_boolean_2 : boolean ;
i_bit_1, i_bit_2 : bit ;
i_severity_level_1, i_severity_level_2 : severity_level ;
i_character_1, i_character_2 : character ;
i_t_enum1_1, i_t_enum1_2 : t_enum1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1 ;
i_integer_1, i_integer_2 : integer ;
i_t_int1_1, i_t_int1_2 : t_int1 ;
i_st_int1_1, i_st_int1_2 : st_int1 ;
i_time_1, i_time_2 : time ;
i_t_phys1_1, i_t_phys1_2 : t_phys1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1 ;
i_real_1, i_real_2 : real ;
i_t_real1_1, i_t_real1_2 : t_real1 ;
i_st_real1_1, i_st_real1_2 : st_real1
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00013 ( ARCH00013 ) ;
begin
CIS1 : UUT
generic map (
c_boolean_2, c_boolean_2,
c_bit_2, c_bit_2,
c_severity_level_2, c_severity_level_2,
c_character_2, c_character_2,
c_t_enum1_2, c_t_enum1_2,
c_st_enum1_2, c_st_enum1_2,
c_integer_2, c_integer_2,
c_t_int1_2, c_t_int1_2,
c_st_int1_2, c_st_int1_2,
c_time_2, c_time_2,
c_t_phys1_2, c_t_phys1_2,
c_st_phys1_2, c_st_phys1_2,
c_real_2, c_real_2,
c_t_real1_2, c_t_real1_2,
c_st_real1_2, c_st_real1_2
) ;
end block L1 ;
end ARCH00013_Test_Bench ;
|
-- file: clkGen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______200.000____150.000
-- CLK_OUT2____50.000______0.000______50.0______600.000____150.000
-- CLK_OUT3____10.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clkGen is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic
);
end clkGen;
architecture xilinx of clkGen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clkGen,clk_wiz_v3_6,{component_name=clkGen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 10.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK_OUT1 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkfx);
clkout3_buf : BUFG
port map
(O => CLK_OUT3,
I => clkdv);
end xilinx;
|
-- file: clkGen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______200.000____150.000
-- CLK_OUT2____50.000______0.000______50.0______600.000____150.000
-- CLK_OUT3____10.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clkGen is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic
);
end clkGen;
architecture xilinx of clkGen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clkGen,clk_wiz_v3_6,{component_name=clkGen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 10.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK_OUT1 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkfx);
clkout3_buf : BUFG
port map
(O => CLK_OUT3,
I => clkdv);
end xilinx;
|
-- file: clkGen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______200.000____150.000
-- CLK_OUT2____50.000______0.000______50.0______600.000____150.000
-- CLK_OUT3____10.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clkGen is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic
);
end clkGen;
architecture xilinx of clkGen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clkGen,clk_wiz_v3_6,{component_name=clkGen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 10.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK_OUT1 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkfx);
clkout3_buf : BUFG
port map
(O => CLK_OUT3,
I => clkdv);
end xilinx;
|
-------------------------------------------------------------------------------
--
-- File: MIPI_DPHY_Receiver.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- The MIPI_DPHY_Receiver IP is an implementation of a subset of the PHY-level
-- protocol of the MIPI D-PHY 1.0 specification. It bundles a SCNN clock lane
-- and one or more SFEN data lanes to implement the reciever end of a Lane
-- Interconnect. In an FPGA implementation of the communication stack
-- it occupies the lowest level. On top of it, over the PHY-Protocol Interface
-- (PPI) connects the protocol layer specific to the application, like the Camera
-- Serial Interface (CSI).
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
use work.DPHY_types.ALL;
use work.DebugLib.all;
entity MIPI_DPHY_Receiver is
generic (
-- Users to add parameters here
kVersionMajor : natural := 0; -- TCL-propagated from VLNV
kVersionMinor : natural := 0; -- TCL-propagated from VLNV
kNoOfDataLanes : natural range 1 to 2:= 2;
kGenerateMMCM : boolean := false;
kGenerateAXIL : boolean := false;
kAddDelayClk_ps : integer := 0;
kAddDelayData0_ps : integer := 0;
kAddDelayData1_ps : integer := 0;
kRefClkFreqHz : integer := 200_000_000; -- TCL-propagated
kDebug : boolean := true;
kLPFromLane0 : boolean := true;
kSharedLogic : boolean := true;
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 4;
C_S_AXI_LITE_FREQ_HZ : integer := 100_000_000 -- TCL-propagated
);
port (
-- Users to add ports here
dphy_clk_hs_p : in std_logic;
dphy_clk_hs_n : in std_logic;
dphy_clk_lp_p : in std_logic;
dphy_clk_lp_n : in std_logic;
dphy_data_hs_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_hs_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
RefClk : in std_logic; --200MHz
aRst : in std_logic; --Only to be de-asserted when RefClk is valid
rDlyCtrlLockedIn : in std_logic; --if IDELAYCTRL instantiated externally, input its locked signal
rDlyCtrlLockedOut : out std_logic; --if IDELAYCTRL instantiated internally, output its locked signal
--PHY-Protocol Interface (PPI)
--Clock lane
RxDDRClkHS : out std_logic; --Receiver DDR Clock (may be used by the protocol)
aRxClkActiveHS : out std_logic; --Receiver Clock Active
aClkStopstate : out std_logic; --Lane is in Stop state
aClkEnable : in std_logic; --Enable Lane Module
aClkUlpsActiveNot : out std_logic; --ULP State (not) Active
aRxUlpsClkNot : out std_logic; --Receive Ultra-Low Power State on Clock Lane
aClkForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
aClkErrControl : out std_logic; --Control Error
RxByteClkHS : out std_logic; --High-Speed Receive Byte Clock
--Data lane 0
aD0Stopstate : out std_logic; --Lane is in Stop state
aD0Enable : in std_logic; --Enable Lane Module
aD0UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD0RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD0RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD0RxActiveHS : out std_logic; --High-Speed Reception Active
rbD0RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD0ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD0ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD0ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D0RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD0RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD0RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD0RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD0RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD0RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD0ErrEsc : out std_logic; --Escape Entry Error
aD0ErrControl : out std_logic; --Control Error
--Data lane 1
aD1Stopstate : out std_logic; --Lane is in Stop state
aD1Enable : in std_logic; --Enable Lane Module
aD1UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD1RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD1RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD1RxActiveHS : out std_logic; --High-Speed Reception Active
rbD1RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD1ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD1ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD1ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D1RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD1RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD1RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD1RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD1RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD1RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD1ErrEsc : out std_logic; --Escape Entry Error
aD1ErrControl : out std_logic; --Control Error
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end MIPI_DPHY_Receiver;
architecture arch_imp of MIPI_DPHY_Receiver is
function MIN(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end;
constant kDlyRstDelay : natural := 32;
constant kGenerateIDELAYCTRL : boolean := kSharedLogic;
constant kCtlClkFreqHz : natural := kRefClkFreqHz;
--make all delays positive
constant kDelayAdjust : integer := MIN(kAddDelayClk_ps, MIN(kAddDelayData0_ps, kAddDelayData1_ps));
constant kAddAdjDelayClk_ps : integer := kAddDelayClk_ps - kDelayAdjust;
constant kAddAdjDelayData0_ps : integer := kAddDelayData0_ps - kDelayAdjust;
constant kAddAdjDelayData1_ps : integer := kAddDelayData1_ps - kDelayAdjust;
type dataLaneHSType is array(kNoOfDataLanes-1 downto 0) of std_logic;
type dataLaneLPType is array(kNoOfDataLanes-1 downto 0) of std_logic_vector(1 downto 0);
type dataLaneWordType is array(kNoOfDataLanes-1 downto 0) of std_logic_vector(7 downto 0);
type dLP_int_t is array (kNoOfDataLanes-1 downto 0) of std_logic_vector(7 downto 0);
signal dLP0_in, dLP1_in, dLP0_out, dLP1_out : dLP_int_t;
signal HS_Clock : std_logic;
signal HS_Data : dataLaneHSType;
signal LP_Clock : std_logic_vector(1 downto 0);
signal aLPBuf, cLP_in, cLP_out : dataLaneLPType;
signal dDataWord : dataLaneWordType;
signal dDataAligned : dataLaneHSType;
signal RxDDRClkHS_int, RxByteClkHS_int, aRxClkActiveHS_int : std_logic;
signal cHSClkLocked : std_logic;
signal xEnable, xSoftRst : std_logic;
signal rDlyLckd, rDlyRst, rExtRst, rSoftRst, rSoftEnable, rIntRst : std_logic;
signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1;
signal aLaneSCNNEnable : std_logic;
signal aLaneSFENEnable : std_logic_vector(kNoOfDataLanes-1 downto 0);
type PPIRxLaneType is record
aStopstate : std_logic; --Lane is in Stop state
aEnable : std_logic; --Enable Lane Module
aUlpsActiveNot : std_logic; --ULP State (not) Active
rbRxDataHS : std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbRxValidHS : std_logic; --High-Speed Receive Data Valid
rbRxActiveHS : std_logic; --High-Speed Reception Active
rbRxSyncHS : std_logic; --Receiver Synchronization Observed (pulse)
rbErrSotHS : std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbErrSotSyncHS : std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aForceRxmode : std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
RxClkEsc : std_logic; --Escape mode Receive Clock (not periodic)
aRxDataEsc : std_logic_vector(7 downto 0); --Escape mode Receive Data
aRxValidEsc : std_logic; --Escape mode Receive Data Valid
aRxLpdtEsc : std_logic; --Escape Low-Power Data Receive Mode
aRxUlpsEsc : std_logic; --Escape Ultra-Low Power (Receive) mode
aRxTriggerEsc : std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aErrEsc : std_logic; --Escape Entry Error
aErrControl : std_logic; --Control Error
end record PPIRxLaneType;
type PPIRxType is array(kNoOfDataLanes-1 downto 0) of PPIRxLaneType;
signal SFEN_Lanes : PPIRxType;
signal debugSCNN : DebugSCNN_Type;
type DebugSFEN_Lanes_Type is array(kNoOfDataLanes-1 downto 0) of DebugSFEN_Type;
signal debugSFEN : DebugSFEN_Lanes_Type;
signal rTrigOut : std_logic;
signal rTrigInAck, rSFEN_TrigOut, rbSFEN_TrigOut, rbSFEN_TrigInAck, rSFEN_TrigInAck : std_logic_vector(kNoOfDataLanes-1 downto 0);
begin
-------------------------------------------------------------------------------
-- Map PPI ports to array type signals for easier module instantiation below
-------------------------------------------------------------------------------
PPIGen1: if kNoOfDataLanes >= 1 generate
aD0Stopstate <= SFEN_Lanes(0).aStopstate;
SFEN_Lanes(0).aEnable <= aD0Enable;
aD0UlpsActiveNot <= SFEN_Lanes(0).aUlpsActiveNot;
rbD0RxDataHS <= SFEN_Lanes(0).rbRxDataHS;
rbD0RxValidHS <= SFEN_Lanes(0).rbRxValidHS;
rbD0RxActiveHS <= SFEN_Lanes(0).rbRxActiveHS;
rbD0RxSyncHS <= SFEN_Lanes(0).rbRxSyncHS;
rbD0ErrSotHS <= SFEN_Lanes(0).rbErrSotHS;
rbD0ErrSotSyncHS <= SFEN_Lanes(0).rbErrSotSyncHS;
SFEN_Lanes(0).aForceRxmode <= aD0ForceRxmode;
D0RxClkEsc <= SFEN_Lanes(0).RxClkEsc;
aD0RxDataEsc <= SFEN_Lanes(0).aRxDataEsc;
aD0RxValidEsc <= SFEN_Lanes(0).aRxValidEsc;
aD0RxLpdtEsc <= SFEN_Lanes(0).aRxLpdtEsc;
aD0RxUlpsEsc <= SFEN_Lanes(0).aRxUlpsEsc;
aD0RxTriggerEsc <= SFEN_Lanes(0).aRxTriggerEsc;
aD0ErrEsc <= SFEN_Lanes(0).aErrEsc;
aD0ErrControl <= SFEN_Lanes(0).aErrControl;
end generate;
PPIGen2: if kNoOfDataLanes >= 2 generate
aD1Stopstate <= SFEN_Lanes(1).aStopstate;
SFEN_Lanes(1).aEnable <= aD1Enable;
aD1UlpsActiveNot <= SFEN_Lanes(1).aUlpsActiveNot;
rbD1RxDataHS <= SFEN_Lanes(1).rbRxDataHS;
rbD1RxValidHS <= SFEN_Lanes(1).rbRxValidHS;
rbD1RxActiveHS <= SFEN_Lanes(1).rbRxActiveHS;
rbD1RxSyncHS <= SFEN_Lanes(1).rbRxSyncHS;
rbD1ErrSotHS <= SFEN_Lanes(1).rbErrSotHS;
rbD1ErrSotSyncHS <= SFEN_Lanes(1).rbErrSotSyncHS;
SFEN_Lanes(1).aForceRxmode <= aD1ForceRxmode;
D1RxClkEsc <= SFEN_Lanes(1).RxClkEsc;
aD1RxDataEsc <= SFEN_Lanes(1).aRxDataEsc;
aD1RxValidEsc <= SFEN_Lanes(1).aRxValidEsc;
aD1RxLpdtEsc <= SFEN_Lanes(1).aRxLpdtEsc;
aD1RxUlpsEsc <= SFEN_Lanes(1).aRxUlpsEsc;
aD1RxTriggerEsc <= SFEN_Lanes(1).aRxTriggerEsc;
aD1ErrEsc <= SFEN_Lanes(1).aErrEsc;
aD1ErrControl <= SFEN_Lanes(1).aErrControl;
end generate;
-------------------------------------------------------------------------------
-- AXI-Lite interface for control and status
-------------------------------------------------------------------------------
YesAXILITE: if kGenerateAXIL generate
AXI_Lite_Control: entity work.MIPI_DPHY_Receiver_S_AXI_Lite
generic map (
kVersionMajor => kVersionMajor,
kVersionMinor => kVersionMinor,
C_S_AXI_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH
)
port map (
xEnable => xEnable,
xRst => xSoftRst,
S_AXI_ACLK => s_axi_lite_aclk,
S_AXI_ARESETN => s_axi_lite_aresetn,
S_AXI_AWADDR => s_axi_lite_awaddr,
S_AXI_AWPROT => s_axi_lite_awprot,
S_AXI_AWVALID => s_axi_lite_awvalid,
S_AXI_AWREADY => s_axi_lite_awready,
S_AXI_WDATA => s_axi_lite_wdata,
S_AXI_WSTRB => s_axi_lite_wstrb,
S_AXI_WVALID => s_axi_lite_wvalid,
S_AXI_WREADY => s_axi_lite_wready,
S_AXI_BRESP => s_axi_lite_bresp,
S_AXI_BVALID => s_axi_lite_bvalid,
S_AXI_BREADY => s_axi_lite_bready,
S_AXI_ARADDR => s_axi_lite_araddr,
S_AXI_ARPROT => s_axi_lite_arprot,
S_AXI_ARVALID => s_axi_lite_arvalid,
S_AXI_ARREADY => s_axi_lite_arready,
S_AXI_RDATA => s_axi_lite_rdata,
S_AXI_RRESP => s_axi_lite_rresp,
S_AXI_RVALID => s_axi_lite_rvalid,
S_AXI_RREADY => s_axi_lite_rready
);
CoreSoftReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => xSoftRst,
OutClk => RefClk,
oRst => rSoftRst);
SyncAsyncClkEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0', --lane-level enable
aIn => xEnable,
OutClk => RefClk,
oOut => rSoftEnable);
end generate;
NoAXILITE: if not kGenerateAXIL generate
rSoftEnable <= '1';
rSoftRst <= '0';
end generate;
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal rExtRst can be used as
-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted
-- synchronously.
CoreAsyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => RefClk,
oRst => rExtRst);
rIntRst <= rSoftRst or rExtRst;
-------------------------------------------------------------------------------
-- IDELAYCTRL needed by the IDELAYE2 primitives on the data lanes
-------------------------------------------------------------------------------
GenIDELAYCTRL: if (kGenerateIDELAYCTRL) generate
--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least
ResetIDELAYCTRL: process(rIntRst, RefClk)
begin
if Rising_Edge(RefClk) then
if (rIntRst = '1') then
rDlyRstCnt <= kDlyRstDelay - 1;
rDlyRst <= '1';
elsif (rDlyRstCnt /= 0) then
rDlyRstCnt <= rDlyRstCnt - 1;
else
rDlyRst <= '0';
end if;
end if;
end process;
IDelayCtrlX: IDELAYCTRL
port map (
RDY => rDlyLckd,
REFCLK => RefClk,
RST => rDlyRst);
rDlyCtrlLockedOut <= rDlyLckd;
end generate GenIDELAYCTRL;
GenNoIDELAYCTRL: if (not kGenerateIDELAYCTRL) generate
rDlyLckd <= not rIntRst and rDlyCtrlLockedIn;
end generate GenNoIDELAYCTRL;
-------------------------------------------------------------------------------
-- Clock lane modules: enable, input buffer, D-PHY SCNN module
-------------------------------------------------------------------------------
aLaneSCNNEnable <= aClkEnable and rSoftEnable and rDlyLckd;
ClockInputBuffer: entity work.InputBuffer
Port map (
HS_p => dphy_clk_hs_p,
HS_n => dphy_clk_hs_n,
LP_n => dphy_clk_lp_n,
LP_p => dphy_clk_lp_p,
aHS => HS_Clock,
aLP => LP_Clock
);
ClockLane: entity work.DPHY_LaneSCNN
Generic map (
kGenerateMMCM => false,
kRefClkFreqHz => kRefClkFreqHz,
kAddDelay_ps => kAddAdjDelayClk_ps
)
Port map (
aLP => LP_Clock,
aHS => HS_Clock,
RefClk => RefClk,
RxDDRClkHS => RxDDRClkHS_int,
RxByteClkHS => RxByteClkHS_int,
aRxClkActiveHS => aRxClkActiveHS_int,
aForceRxmode => aClkForceRxmode,
aStopstate => aClkStopstate,
aEnable => aLaneSCNNEnable,
aRxUlpsClkNot => aRxUlpsClkNot,
aUlpsActiveNot => aClkUlpsActiveNot,
debug => debugSCNN
);
-------------------------------------------------------------------------------
-- Date lane modules: enable, input buffer, D-PHY SFEN module
-------------------------------------------------------------------------------
DataLaneGen: for i in kNoOfDataLanes-1 downto 0 generate
InputBufferDataX: entity work.InputBuffer
Generic map (
kNoLP => kLPFromLane0 and i /= 0
)
Port map (
HS_p => dphy_data_hs_p(i),
HS_n => dphy_data_hs_n(i),
LP_n => dphy_data_lp_n(i),
LP_p => dphy_data_lp_p(i),
aHS => HS_Data(i),
aLP => aLPBuf(i)
);
aLaneSFENEnable(i) <= SFEN_Lanes(i).aEnable and rSoftEnable and rDlyLckd;
DPHY_LaneSFEN_X: entity work.DPHY_LaneSFEN
Generic map (
kRefClkFreqHz => kRefClkFreqHz,
kAddDelay_ps => kAddAdjDelayData0_ps,
kNoLP => kLPFromLane0 and i /= 0
)
Port map (
dLP0_in => dLP0_in(i),
dLP1_in => dLP1_in(i),
dLP0_out => dLP0_out(i),
dLP1_out => dLP1_out(i),
cLP_in => cLP_in(i),
cLP_out => cLP_out(i),
aLP => aLPBuf(i),
aHS => HS_Data(i),
RefClk => RefClk,
SerClkHS => RxDDRClkHS_int,
DivClk => RxByteClkHS_int,
aRxClkActiveHS => aRxClkActiveHS_int,
--PPI
RxByteClkHS => open, --see RxByteClkHS_int below
rbRxDataHS => SFEN_Lanes(i).rbRxDataHS,
rbRxValidHS => SFEN_Lanes(i).rbRxValidHS,
rbRxActiveHS => SFEN_Lanes(i).rbRxActiveHS,
rbRxSyncHS => SFEN_Lanes(i).rbRxSyncHS,
rbErrSotHS => SFEN_Lanes(i).rbErrSotHS,
rbErrSotSyncHS => SFEN_Lanes(i).rbErrSotSyncHS,
aEnable => aLaneSFENEnable(i),
aStopstate => SFEN_Lanes(i).aStopstate,
aForceRxmode => SFEN_Lanes(i).aForceRxmode,
aErrEsc => SFEN_Lanes(i).aErrEsc,
aErrControl => SFEN_Lanes(i).aErrControl,
debug => debugSFEN(i)
);
ShareLPFromOtherLane: if kLPFromLane0 and i /= 0 generate
dLP0_in(i) <= dLP0_out(0);
dLP1_in(i) <= dLP0_out(0);
cLP_in(i) <= cLP_out(0);
end generate ShareLPFromOtherLane;
--D0RxClkEsc <=
--aD0RxDataEsc <=
--aD0RxValidEsc <=
--aD0RxLpdtEsc <=
--aD0RxUlpsEsc <=
--aD0RxTriggerEsc <=
end generate DataLaneGen;
-- We output a single divided clock common for all data lanes
RxByteClkHS <= RxByteClkHS_int;
RxDDRClkHS <= RxDDRClkHS_int;
aRxClkActiveHS <= aRxClkActiveHS_int;
----------------------------------------------------------------------------------
-- Debug modules
----------------------------------------------------------------------------------
GenerateDebug: if kDebug generate
ILA_SCNN_RefClkX : ila_scnn_refclk
PORT MAP (
clk => RefClk,
trig_out => rTrigOut,
trig_out_ack => rTrigInAck(0),
probe0(0) => debugSCNN.cIntRst,
probe1 => debugSCNN.cLP,
probe2(0) => debugSCNN.cHSRst,
probe3(0) => debugSCNN.cHSClkLocked,
probe4 => debugSCNN.state,
probe5(0) => debugSCNN.cClkSettleTout,
probe6(0) => debugSCNN.cBUFR_Rst,
probe7(0) => debugSCNN.cMMCM_Rst,
probe8(0) => debugSCNN.cMMCM_RstTout,
probe9(0) => debugSCNN.cMMCM_Locked
);
ILA_SFEN_Gen: for i in kNoOfDataLanes-1 downto 0 generate
ILA_SFEN_RefClkX : ila_sfen_refclk
PORT MAP (
clk => RefClk,
trig_out => rSFEN_TrigOut(i),
trig_out_ack => rSFEN_TrigInAck(i),
trig_in => rTrigOut,
trig_in_ack => rTrigInAck(i),
probe0(0) => debugSFEN(i).cIntRst,
probe1 => debugSFEN(i).cLP,
probe2 => debugSFEN(i).state,
probe3(0) => debugSFEN(i).cHSClkRst,
probe4(0) => debugSFEN(i).cForceRxmode,
probe5(0) => debugSFEN(i).cInitTout,
probe6(0) => debugSFEN(i).cHSSettleTout,
probe7(0) => debugSFEN(i).cHSSettled,
probe8(0) => debugSFEN(i).cHSReset
);
SyncAsyncTrigAck: entity work.SyncAsync
port map (
aReset => '0',
aIn => rbSFEN_TrigInAck(i),
OutClk => RefClk,
oOut => rSFEN_TrigInAck(i));
SyncAsyncTrigOut: entity work.SyncAsync
port map (
aReset => '0',
aIn => rSFEN_TrigOut(i),
OutClk => RxByteClkHS_int,
oOut => rbSFEN_TrigOut(i));
ILA_SFEN_RxClkX : ila_sfen_rxclk
PORT MAP (
clk => RxByteClkHS_int,
trig_in => rbSFEN_TrigOut(i),
trig_in_ack => rbSFEN_TrigInAck(i),
probe0(0) => debugSFEN(i).dSyncHard,
probe1(0) => debugSFEN(i).dSyncSoft,
probe2(0) => debugSFEN(i).dSyncErr,
probe3(0) => SFEN_Lanes(i).rbRxActiveHS,
probe4(0) => SFEN_Lanes(i).rbRxSyncHS,
probe5(0) => SFEN_Lanes(i).rbRxValidHS,
probe6(0) => SFEN_Lanes(i).rbErrSotHS,
probe7(0) => SFEN_Lanes(i).rbErrSotSyncHS,
probe8 => SFEN_Lanes(i).rbRxDataHS
);
end generate ILA_SFEN_Gen;
end generate;
end arch_imp;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:41 04/17/2015
-- Design Name:
-- Module Name: AmplifierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AmplifierFP is
generic ( INTBIT_WIDTH : positive := 24;
FRACBIT_WIDTH : positive := 8);
Port ( CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --amplifying coefficient
OUT_AMP : out signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end AmplifierFP;
architecture Behavioral of AmplifierFP is
COMPONENT MultiplierFP
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
IN_SIG : IN signed((INTBIT_WIDTH - 1) downto 0);
IN_COEF : IN signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
OUT_MULT : OUT signed((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
READY : OUT std_logic
);
END COMPONENT;
signal mult_out : signed ((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0) := (others => '0');
signal AMP_OUT_in, AMP_OUT_out : signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal mult_ready : std_logic := '0';
begin
Amp_multiplier: MultiplierFP PORT MAP(
CLK => CLK,
RESET => RESET,
IN_SIG => IN_SIG,
IN_COEF => IN_COEF,
OUT_MULT => mult_out,
READY => mult_ready
);
-- for fixed point
-- AMP_OUT_in <= mult_out(2*BIT_WIDTH - BIT_WIDTH - 1 downto 0);
-- for integers
AMP_OUT_in <= mult_out((2*FRACBIT_WIDTH + INTBIT_WIDTH) - 1 downto (2*FRACBIT_WIDTH ));
seq_proc : process (CLK)
begin
if(CLK'event and CLK = '1')then
-- update the ready signal when new values gets written to the buffer
if (mult_ready = '1') then
AMP_OUT_out <= AMP_OUT_in;
end if;
end if;
end process;
OUT_RDY <= mult_ready;
OUT_AMP <= AMP_OUT_out;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:41 04/17/2015
-- Design Name:
-- Module Name: AmplifierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AmplifierFP is
generic ( INTBIT_WIDTH : positive := 24;
FRACBIT_WIDTH : positive := 8);
Port ( CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --amplifying coefficient
OUT_AMP : out signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end AmplifierFP;
architecture Behavioral of AmplifierFP is
COMPONENT MultiplierFP
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
IN_SIG : IN signed((INTBIT_WIDTH - 1) downto 0);
IN_COEF : IN signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
OUT_MULT : OUT signed((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
READY : OUT std_logic
);
END COMPONENT;
signal mult_out : signed ((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0) := (others => '0');
signal AMP_OUT_in, AMP_OUT_out : signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal mult_ready : std_logic := '0';
begin
Amp_multiplier: MultiplierFP PORT MAP(
CLK => CLK,
RESET => RESET,
IN_SIG => IN_SIG,
IN_COEF => IN_COEF,
OUT_MULT => mult_out,
READY => mult_ready
);
-- for fixed point
-- AMP_OUT_in <= mult_out(2*BIT_WIDTH - BIT_WIDTH - 1 downto 0);
-- for integers
AMP_OUT_in <= mult_out((2*FRACBIT_WIDTH + INTBIT_WIDTH) - 1 downto (2*FRACBIT_WIDTH ));
seq_proc : process (CLK)
begin
if(CLK'event and CLK = '1')then
-- update the ready signal when new values gets written to the buffer
if (mult_ready = '1') then
AMP_OUT_out <= AMP_OUT_in;
end if;
end if;
end process;
OUT_RDY <= mult_ready;
OUT_AMP <= AMP_OUT_out;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:41 04/17/2015
-- Design Name:
-- Module Name: AmplifierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AmplifierFP is
generic ( INTBIT_WIDTH : positive := 24;
FRACBIT_WIDTH : positive := 8);
Port ( CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --amplifying coefficient
OUT_AMP : out signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end AmplifierFP;
architecture Behavioral of AmplifierFP is
COMPONENT MultiplierFP
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
IN_SIG : IN signed((INTBIT_WIDTH - 1) downto 0);
IN_COEF : IN signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
OUT_MULT : OUT signed((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
READY : OUT std_logic
);
END COMPONENT;
signal mult_out : signed ((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0) := (others => '0');
signal AMP_OUT_in, AMP_OUT_out : signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal mult_ready : std_logic := '0';
begin
Amp_multiplier: MultiplierFP PORT MAP(
CLK => CLK,
RESET => RESET,
IN_SIG => IN_SIG,
IN_COEF => IN_COEF,
OUT_MULT => mult_out,
READY => mult_ready
);
-- for fixed point
-- AMP_OUT_in <= mult_out(2*BIT_WIDTH - BIT_WIDTH - 1 downto 0);
-- for integers
AMP_OUT_in <= mult_out((2*FRACBIT_WIDTH + INTBIT_WIDTH) - 1 downto (2*FRACBIT_WIDTH ));
seq_proc : process (CLK)
begin
if(CLK'event and CLK = '1')then
-- update the ready signal when new values gets written to the buffer
if (mult_ready = '1') then
AMP_OUT_out <= AMP_OUT_in;
end if;
end if;
end process;
OUT_RDY <= mult_ready;
OUT_AMP <= AMP_OUT_out;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:41 04/17/2015
-- Design Name:
-- Module Name: AmplifierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AmplifierFP is
generic ( INTBIT_WIDTH : positive := 24;
FRACBIT_WIDTH : positive := 8);
Port ( CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --amplifying coefficient
OUT_AMP : out signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end AmplifierFP;
architecture Behavioral of AmplifierFP is
COMPONENT MultiplierFP
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
IN_SIG : IN signed((INTBIT_WIDTH - 1) downto 0);
IN_COEF : IN signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
OUT_MULT : OUT signed((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
READY : OUT std_logic
);
END COMPONENT;
signal mult_out : signed ((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0) := (others => '0');
signal AMP_OUT_in, AMP_OUT_out : signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal mult_ready : std_logic := '0';
begin
Amp_multiplier: MultiplierFP PORT MAP(
CLK => CLK,
RESET => RESET,
IN_SIG => IN_SIG,
IN_COEF => IN_COEF,
OUT_MULT => mult_out,
READY => mult_ready
);
-- for fixed point
-- AMP_OUT_in <= mult_out(2*BIT_WIDTH - BIT_WIDTH - 1 downto 0);
-- for integers
AMP_OUT_in <= mult_out((2*FRACBIT_WIDTH + INTBIT_WIDTH) - 1 downto (2*FRACBIT_WIDTH ));
seq_proc : process (CLK)
begin
if(CLK'event and CLK = '1')then
-- update the ready signal when new values gets written to the buffer
if (mult_ready = '1') then
AMP_OUT_out <= AMP_OUT_in;
end if;
end if;
end process;
OUT_RDY <= mult_ready;
OUT_AMP <= AMP_OUT_out;
end Behavioral; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2919.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p06n01i02919ent IS
END c02s01b01x02p06n01i02919ent;
ARCHITECTURE c02s01b01x02p06n01i02919arch OF c02s01b01x02p06n01i02919ent IS
procedure proc1 (signal x1 : bit; z1 : boolean);
procedure proc1 (signal x1 : bit; z1 : boolean) is
begin
null;
end proc1;
signal b: bit_vector (4 downto 1);
BEGIN
TESTING: PROCESS
variable i : integer := 1;
BEGIN
proc1 (b(i), true); -- Failure_here
-- b(i) is not a static name.
assert FALSE
report "***FAILED TEST: c02s01b01x02p06n01i02919 - The actual signal associated with a signal parameter must be denoted by a static name."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p06n01i02919arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2919.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p06n01i02919ent IS
END c02s01b01x02p06n01i02919ent;
ARCHITECTURE c02s01b01x02p06n01i02919arch OF c02s01b01x02p06n01i02919ent IS
procedure proc1 (signal x1 : bit; z1 : boolean);
procedure proc1 (signal x1 : bit; z1 : boolean) is
begin
null;
end proc1;
signal b: bit_vector (4 downto 1);
BEGIN
TESTING: PROCESS
variable i : integer := 1;
BEGIN
proc1 (b(i), true); -- Failure_here
-- b(i) is not a static name.
assert FALSE
report "***FAILED TEST: c02s01b01x02p06n01i02919 - The actual signal associated with a signal parameter must be denoted by a static name."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p06n01i02919arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2919.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p06n01i02919ent IS
END c02s01b01x02p06n01i02919ent;
ARCHITECTURE c02s01b01x02p06n01i02919arch OF c02s01b01x02p06n01i02919ent IS
procedure proc1 (signal x1 : bit; z1 : boolean);
procedure proc1 (signal x1 : bit; z1 : boolean) is
begin
null;
end proc1;
signal b: bit_vector (4 downto 1);
BEGIN
TESTING: PROCESS
variable i : integer := 1;
BEGIN
proc1 (b(i), true); -- Failure_here
-- b(i) is not a static name.
assert FALSE
report "***FAILED TEST: c02s01b01x02p06n01i02919 - The actual signal associated with a signal parameter must be denoted by a static name."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p06n01i02919arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc135.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p08n01i00135ent IS
END c04s03b02x02p08n01i00135ent;
ARCHITECTURE c04s03b02x02p08n01i00135arch OF c04s03b02x02p08n01i00135ent IS
type AT1 is array (INTEGER range <>, INTEGER range <>) of INTEGER;
subtype ST1 is AT1(1 to 2, 1 to 2);
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
begin
if (P=ref) then
P := set;
end if;
end;
variable V : ST1 := ((1, 2), (3, 4));
BEGIN
V := ((1, 2), (3, 4));
Proc1( P(1,1) => V(2,2), P(1,2) => V(2,1),
P(2,1) => V(1,2), P(2,2) => V(1,1),
ref => ((4, 3), (2, 1)), set => ((9, 8), (7, 6))); -- test here
assert V = ((6, 7), (8, 9)) report "FAIL: actual V didn't get set right";
assert NOT( V = ((6,7),(8,9)) )
report "***PASSED TEST: c04s03b02x02p08n01i00135"
severity NOTE;
assert ( V = ((6,7),(8,9)) )
report "***FAILED TEST: c04s03b02x02p08n01i00135 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00135arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc135.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p08n01i00135ent IS
END c04s03b02x02p08n01i00135ent;
ARCHITECTURE c04s03b02x02p08n01i00135arch OF c04s03b02x02p08n01i00135ent IS
type AT1 is array (INTEGER range <>, INTEGER range <>) of INTEGER;
subtype ST1 is AT1(1 to 2, 1 to 2);
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
begin
if (P=ref) then
P := set;
end if;
end;
variable V : ST1 := ((1, 2), (3, 4));
BEGIN
V := ((1, 2), (3, 4));
Proc1( P(1,1) => V(2,2), P(1,2) => V(2,1),
P(2,1) => V(1,2), P(2,2) => V(1,1),
ref => ((4, 3), (2, 1)), set => ((9, 8), (7, 6))); -- test here
assert V = ((6, 7), (8, 9)) report "FAIL: actual V didn't get set right";
assert NOT( V = ((6,7),(8,9)) )
report "***PASSED TEST: c04s03b02x02p08n01i00135"
severity NOTE;
assert ( V = ((6,7),(8,9)) )
report "***FAILED TEST: c04s03b02x02p08n01i00135 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00135arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc135.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p08n01i00135ent IS
END c04s03b02x02p08n01i00135ent;
ARCHITECTURE c04s03b02x02p08n01i00135arch OF c04s03b02x02p08n01i00135ent IS
type AT1 is array (INTEGER range <>, INTEGER range <>) of INTEGER;
subtype ST1 is AT1(1 to 2, 1 to 2);
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
begin
if (P=ref) then
P := set;
end if;
end;
variable V : ST1 := ((1, 2), (3, 4));
BEGIN
V := ((1, 2), (3, 4));
Proc1( P(1,1) => V(2,2), P(1,2) => V(2,1),
P(2,1) => V(1,2), P(2,2) => V(1,1),
ref => ((4, 3), (2, 1)), set => ((9, 8), (7, 6))); -- test here
assert V = ((6, 7), (8, 9)) report "FAIL: actual V didn't get set right";
assert NOT( V = ((6,7),(8,9)) )
report "***PASSED TEST: c04s03b02x02p08n01i00135"
severity NOTE;
assert ( V = ((6,7),(8,9)) )
report "***FAILED TEST: c04s03b02x02p08n01i00135 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00135arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:59:20 05/21/2016
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use work.CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.CONSTANTS.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity muxperso is
Port ( ADDR1 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
data_write1 : in STD_LOGIC;
data_in1 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
ADDR2 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
data_write2 : in STD_LOGIC;
data_in2 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
-- ADDR3 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
-- data_write3 : in STD_LOGIC;
-- data_in3 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
-- ADDR4 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
-- data_write4 : in STD_LOGIC;
-- data_in4 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
ADDR : out STD_LOGIC_vector(ADDR_BIT-1 downto 0);
data_write : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0));
end muxperso;
architecture Behavioral of muxperso is
begin
ADDR<= std_logic_vector( unsigned("00" & ADDR1) + to_unsigned(38400, ADDR_BIT)) when (data_write1 = '1') else std_logic_vector(unsigned("00" & ADDR2) + to_unsigned(38400, ADDR_BIT)) ;
data_out<=data_in1 when(data_write1 = '1') else data_in2;
data_write<='1' when (data_write1 = '1') else data_write2;
end Behavioral;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base;
architecture xilinx of clk_base is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_base_clk_wiz
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_base_clk_wiz
port map (
-- Clock in ports
clk_raw => clk_raw,
-- Clock out ports
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Mux4x1:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Mux4x1_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END Program_Counter_Mux4x1_0_1;
ARCHITECTURE Program_Counter_Mux4x1_0_1_arch OF Program_Counter_Mux4x1_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "Mux4x1,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Program_Counter_Mux4x1_0_1_arch : ARCHITECTURE IS "Program_Counter_Mux4x1_0_1,Mux4x1,{}";
BEGIN
U0 : Mux4x1
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END Program_Counter_Mux4x1_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Mux4x1:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Mux4x1_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END Program_Counter_Mux4x1_0_1;
ARCHITECTURE Program_Counter_Mux4x1_0_1_arch OF Program_Counter_Mux4x1_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "Mux4x1,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Program_Counter_Mux4x1_0_1_arch : ARCHITECTURE IS "Program_Counter_Mux4x1_0_1,Mux4x1,{}";
BEGIN
U0 : Mux4x1
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END Program_Counter_Mux4x1_0_1_arch;
|
-------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
|
-- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- Entity Declaration
ENTITY baud_tick IS
PORT(
clk : IN std_logic;
baud_tick : OUT std_logic;
reset_n : IN std_logic;
start_bit : in std_logic
);
END baud_tick;
-- Architecture Declaration
ARCHITECTURE rtl OF baud_tick IS
CONSTANT period : unsigned(9 downto 0) := to_unsigned(434, 10);
CONSTANT init_period : unsigned(9 downto 0) := to_unsigned(651, 10);
-- length of a byte (8) for byte countdown
CONSTANT byte_countdown_length : unsigned(3 downto 0) := to_unsigned(8, 4);
-- signals for baud tick period counter
SIGNAL count, next_count : unsigned(9 downto 0);
-- signals for byte counter
SIGNAL byte_countdown : unsigned(3 downto 0);
SIGNAL next_byte_countdown : unsigned(3 downto 0);
-- Begin Architecture
BEGIN
-- input logic for baud tick
input_logic: PROCESS(count, start_bit)
BEGIN
IF start_bit = '1' THEN
next_count <= init_period;
-- decrement
ELSIF count > 0 THEN
next_count <= count - 1 ;
-- start new period
ELSE
next_count <= period;
END IF;
END PROCESS input_logic;
-- baud tick period countdown
baud_flip_flops : PROCESS(clk, reset_n)
BEGIN
IF reset_n = '0' THEN
count <= init_period;
ELSIF rising_edge(clk) THEN
count <= next_count;
END IF;
END PROCESS baud_flip_flops;
-- baud tick output logic
output_logic: PROCESS(count, byte_countdown)
BEGIN
-- send a baud tick, if we reached zero from the counter
-- only send a baud tick, if we didnt count down from 8 ticks yet
IF (count = 0 AND byte_countdown > 0) THEN
baud_tick <= '1';
-- send no baud tick, if we didnt reach the next baud tick yet
ELSE
baud_tick <= '0';
END IF;
END PROCESS output_logic;
-- byte countdown logic
countdown_logic: PROCESS(start_bit, count, byte_countdown)
BEGIN
IF start_bit = '1' THEN
next_byte_countdown <= byte_countdown_length;
-- decrement
ELSIF (count = 0 AND byte_countdown > 0) THEN
next_byte_countdown <= byte_countdown - 1;
-- freeze
ELSIF (count = 0 AND byte_countdown = 0) THEN
next_byte_countdown <= to_unsigned(0, 4);
-- else dont touch the flip flops
ELSE
next_byte_countdown <= byte_countdown;
END IF;
END PROCESS countdown_logic;
-- byte countdown flip flops
countdown_flop_flops: PROCESS(clk, count, reset_n)
BEGIN
IF reset_n = '0' THEN
byte_countdown <= to_unsigned(0, 4);
ELSIF rising_edge(clk) THEN
byte_countdown <= next_byte_countdown;
END IF;
END PROCESS countdown_flop_flops;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use work.rec02_pkg.all;
entity rec02 is
port (inp : myrec;
o : out std_logic);
end rec02;
architecture behav of rec02 is
begin
o <= inp.b when inp.a > 3 else '0';
end behav;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:17:17)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY epic_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5, output6, output7, output8, output9: OUT unsigned(0 TO 4));
END epic_random_entity;
ARCHITECTURE epic_random_description OF epic_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
register2 := register2 + 4;
register3 := input3 + 5;
register4 := input4 - 6;
register1 := register1 * 8;
WHEN "00000011" =>
register5 := ((NOT register2) + 1) XOR register2;
register4 := register4 * 12;
register6 := input5 - 13;
WHEN "00000100" =>
register7 := register6 + register3;
register8 := input6 srl 14;
register9 := register3 * 16;
register3 := register6 - register3;
register5 := register5 + 18;
register10 := register6 + 20;
WHEN "00000101" =>
output1 <= register2(0 TO 1) & register5(0 TO 2);
register2 := register4 + 23;
register3 := register3 * 25;
register4 := register8 srl 27;
WHEN "00000110" =>
register5 := register8 sll to_integer(register4);
register11 := ((NOT register2) + 1) XOR register2;
WHEN "00000111" =>
register11 := register8 - register11;
register12 := register6 - 31;
WHEN "00001000" =>
output2 <= register2(0 TO 1) & register11(0 TO 2);
register2 := register10 * 34;
register3 := register3 + 36;
WHEN "00001001" =>
register10 := ((NOT register3) + 1) XOR register3;
register9 := register9 + 40;
register1 := register1 + 42;
WHEN "00001010" =>
register11 := ((NOT register9) + 1) XOR register9;
register10 := register8 + register4 + register10;
register12 := register12 * 46;
register7 := register7 * 48;
WHEN "00001011" =>
register13 := ((NOT register1) + 1) XOR register1;
register7 := register7 + 52;
register2 := register2 + 54;
WHEN "00001100" =>
register13 := register8 - register13;
output3 <= register3(0 TO 1) & register10(0 TO 2);
register3 := ((NOT register2) + 1) XOR register2;
WHEN "00001101" =>
register10 := ((NOT register7) + 1) XOR register7;
register3 := register8 + register4 + register3;
register12 := register12 + 61;
register5 := register11 - register5;
WHEN "00001110" =>
output4 <= register9(0 TO 1) & register5(0 TO 2);
register5 := ((NOT register12) + 1) XOR register12;
register9 := register8 + register4 + register10;
WHEN "00001111" =>
output5 <= register2(0 TO 1) & register3(0 TO 2);
register2 := register4 + register5;
WHEN "00010000" =>
output6 <= register7(0 TO 1) & register9(0 TO 2);
WHEN "00010001" =>
output7 <= register1(0 TO 1) & register13(0 TO 2);
WHEN "00010010" =>
output8 <= register12(0 TO 1) & register2(0 TO 2);
register1 := register6 * 70;
WHEN "00010011" =>
register1 := register1 + 72;
WHEN "00010100" =>
register2 := ((NOT register1) + 1) XOR register1;
WHEN "00010101" =>
register2 := register8 - register2;
WHEN "00010110" =>
output9 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END epic_random_description; |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_sg_wrdata_cntl;
architecture implementation of axi_sg_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
-- coverage off
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-- coverage on
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_s2mm_strm_wready_del : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
-- sig_s2mm_strm_wready_del;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
sig_s2mm_strm_wready_del <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
sig_s2mm_strm_wready_del <= sig_s2mm_strm_wready;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= (others => '1') when mmap_reset = '0' else (others => '0'); --sig_strt_strb_reg
-- data2skid_wstrb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1')
-- Else sig_last_strb_reg
-- When (sig_last_dbeat = '1')
-- Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
-- coverage off
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
-- coverage on
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
-- coverage off
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
-- coverage on
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
-- GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
--
-- -- local constants
-- Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
-- Constant NUM_ZEROS_WIDTH : integer := 8;
-- Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
-- Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
-- funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
--
-- Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
--
--
--
-- -- local signals
-- signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_ld_byte_cntr : std_logic := '0';
-- signal lsig_incr_byte_cntr : std_logic := '0';
-- signal lsig_clr_byte_cntr : std_logic := '0';
-- signal lsig_end_of_cmd_reg : std_logic := '0';
-- signal lsig_eop_s_h_reg : std_logic := '0';
-- signal lsig_eop_reg : std_logic := '0';
-- signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
--
--
--
--
-- begin
--
--
-- -- Assign the outputs to the Write Status Controller
-- data2wsc_eop <= lsig_eop_reg and
-- not(sig_next_calc_error_reg);
--
-- data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
--
--
--
-- -- WRSTRB logic ------------------------------
--
--
--
-- --sig_strbgen_bytes <= (others => '1'); -- set to the max value
--
--
-- -- set the length to the max number of bytes per databeat
-- sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
--
--
--
--
--
--
-- sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
-- STRBGEN_ADDR_SLICE_WIDTH)) ;
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_STRT_STRB_GEN
-- --
-- -- Description:
-- -- Strobe generator used to generate the starting databeat
-- -- strobe value for soft shutdown case where the S2MM has to
-- -- flush out all of the transfers that have been committed
-- -- to the AXI Write address channel. Starting Strobes must
-- -- match the committed address offest for each transfer.
-- --
-- ------------------------------------------------------------
-- I_STRT_STRB_GEN : entity axi_sg_v4_1_3.axi_sg_strb_gen2
-- generic map (
--
-- C_OP_MODE => 0 , -- 0 = Offset/Length mode
-- C_STRB_WIDTH => BYTES_PER_DBEAT ,
-- C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
-- C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
--
-- )
-- port map (
--
-- start_addr_offset => sig_strbgen_addr ,
-- end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
-- num_valid_bytes => sig_strbgen_bytes ,
-- strb_out => sig_sfhalt_next_strt_strb
--
-- );
--
--
--
--
--
--
--
-- -- Generate the WSTRB to use during soft shutdown
-- sig_halt_strb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1' or
-- sig_single_dbeat = '1')
-- Else (others => '1');
--
--
--
-- -- Generate the Write Strobes for the MMap Write Data Channel
-- -- for the Indeterminate BTT case. Strobes come from the Stream
-- -- input from the Indeterminate BTT module during normal operation.
-- -- However, during soft shutdown, those strobes become unpredictable
-- -- so generated strobes have to be used.
-- data2skid_wstrb <= sig_halt_strb
-- When (sig_halt_reg = '1')
--
-- Else s2mm_strm_wstrb;
--
--
--
-- -- Generate the Stream Ready for the Stream input side
-- sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
-- (sig_mmap2data_ready and -- MMap is accepting the xfers
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
-- -- MMap Write Data Channel Valid Handshaking
-- sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
-- sig_halt_reg ) and -- force valid if halt requested
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
--
-- -- TLAST Error housekeeping for Indeterminate BTT Mode
-- -- There is no Underrun/overrun in Stroe and Forward mode
--
-- sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_EOP_REG_FLOP
-- --
-- -- Process Description:
-- -- Register the End of Packet marker.
-- --
-- -------------------------------------------------------------
-- IMP_EOP_REG_FLOP : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_end_of_cmd_reg <= '0';
-- lsig_eop_reg <= '0';
--
--
-- Elsif (sig_good_strm_dbeat = '1') Then
--
--
-- lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
-- s2mm_strm_wlast;
--
-- lsig_eop_reg <= s2mm_strm_eop;
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_EOP_REG_FLOP;
--
--
--
--
--
-- ----- Byte Counter Logic -----------------------------------------------
-- -- The Byte counter reflects the actual byte count received on the
-- -- Stream input for each parent command loaded into the S2MM command
-- -- FIFO. Thus it counts input bytes until the command complete qualifier
-- -- is set and the TLAST input from the Stream input.
--
--
-- lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
-- not(sig_good_strm_dbeat); -- immediately after the previous one finished.
--
--
-- lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
-- sig_good_strm_dbeat; -- immediately after the previous one finished.
--
-- lsig_incr_byte_cntr <= sig_good_strm_dbeat;
--
--
-- lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
-- BYTE_CNTR_WIDTH);
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_BYTE_CMTR
-- --
-- -- Process Description:
-- -- Keeps a running byte count per burst packet loaded into the
-- -- xfer FIFO. It is based on the strobes set on the incoming
-- -- Stream dbeat.
-- --
-- -------------------------------------------------------------
-- IMP_BYTE_CMTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- lsig_clr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= (others => '0');
--
-- elsif (lsig_ld_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr_incr_value;
--
-- elsif (lsig_incr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
--
-- else
-- null; -- hold current value
-- end if;
-- end if;
-- end process IMP_BYTE_CMTR;
--
--
--
--
--
-- end generate GEN_INDET_BTT;
--
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- ci_bridge_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ci_bridge_0 is
port (
clk : in std_logic := '0'; -- clock.clk
address : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(15 downto 0); -- .readdata
rst : in std_logic := '0'; -- reset_sink.reset
cia_reset : out std_logic; -- conduit_end.export
cib_reset : out std_logic; -- .export
cia_ce_n : out std_logic; -- .export
cib_ce_n : out std_logic; -- .export
ci_reg_n : out std_logic; -- .export
ci_a : out std_logic_vector(14 downto 0); -- .export
ci_we_n : out std_logic; -- .export
ci_oe_n : out std_logic; -- .export
ci_iowr_n : out std_logic; -- .export
ci_iord_n : out std_logic; -- .export
cia_wait_n : in std_logic := '0'; -- .export
cib_wait_n : in std_logic := '0'; -- .export
cia_ireq_n : in std_logic := '0'; -- .export
cib_ireq_n : in std_logic := '0'; -- .export
cia_cd_n : in std_logic_vector(1 downto 0) := (others => '0'); -- .export
cib_cd_n : in std_logic_vector(1 downto 0) := (others => '0'); -- .export
cia_overcurrent_n : in std_logic := '0'; -- .export
cib_overcurrent_n : in std_logic := '0'; -- .export
cia_reset_buf_oe_n : out std_logic; -- .export
cib_reset_buf_oe_n : out std_logic; -- .export
cia_data_buf_oe_n : out std_logic; -- .export
cib_data_buf_oe_n : out std_logic; -- .export
ci_bus_dir : out std_logic; -- .export
interrupt : out std_logic; -- .export
cam_interrupts : out std_logic_vector(1 downto 0); -- .export
cam0_ready : out std_logic; -- .export
cam0_bypass : out std_logic; -- .export
cam1_ready : out std_logic; -- .export
cam1_bypass : out std_logic; -- .export
cam0_fail : out std_logic; -- .export
cam1_fail : out std_logic; -- .export
ci_d_out : out std_logic_vector(7 downto 0); -- .export
ci_d_in : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
ci_d_en : out std_logic; -- .export
cam_writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
cam_write : in std_logic := '0'; -- .export
cam_readdata : out std_logic_vector(7 downto 0); -- .export
cam_read : in std_logic := '0'; -- .export
cam_address : in std_logic_vector(17 downto 0) := (others => '0'); -- .export
cam_waitreq : out std_logic -- .export
);
end entity ci_bridge_0;
architecture rtl of ci_bridge_0 is
component ci_bridge is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(15 downto 0); -- readdata
rst : in std_logic := 'X'; -- reset
cia_reset : out std_logic; -- export
cib_reset : out std_logic; -- export
cia_ce_n : out std_logic; -- export
cib_ce_n : out std_logic; -- export
ci_reg_n : out std_logic; -- export
ci_a : out std_logic_vector(14 downto 0); -- export
ci_we_n : out std_logic; -- export
ci_oe_n : out std_logic; -- export
ci_iowr_n : out std_logic; -- export
ci_iord_n : out std_logic; -- export
cia_wait_n : in std_logic := 'X'; -- export
cib_wait_n : in std_logic := 'X'; -- export
cia_ireq_n : in std_logic := 'X'; -- export
cib_ireq_n : in std_logic := 'X'; -- export
cia_cd_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
cib_cd_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
cia_overcurrent_n : in std_logic := 'X'; -- export
cib_overcurrent_n : in std_logic := 'X'; -- export
cia_reset_buf_oe_n : out std_logic; -- export
cib_reset_buf_oe_n : out std_logic; -- export
cia_data_buf_oe_n : out std_logic; -- export
cib_data_buf_oe_n : out std_logic; -- export
ci_bus_dir : out std_logic; -- export
interrupt : out std_logic; -- export
cam_interrupts : out std_logic_vector(1 downto 0); -- export
cam0_ready : out std_logic; -- export
cam0_bypass : out std_logic; -- export
cam1_ready : out std_logic; -- export
cam1_bypass : out std_logic; -- export
cam0_fail : out std_logic; -- export
cam1_fail : out std_logic; -- export
ci_d_out : out std_logic_vector(7 downto 0); -- export
ci_d_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
ci_d_en : out std_logic; -- export
cam_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
cam_write : in std_logic := 'X'; -- export
cam_readdata : out std_logic_vector(7 downto 0); -- export
cam_read : in std_logic := 'X'; -- export
cam_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- export
cam_waitreq : out std_logic -- export
);
end component ci_bridge;
begin
ci_bridge_0 : component ci_bridge
port map (
clk => clk, -- clock.clk
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
rst => rst, -- reset_sink.reset
cia_reset => cia_reset, -- conduit_end.export
cib_reset => cib_reset, -- .export
cia_ce_n => cia_ce_n, -- .export
cib_ce_n => cib_ce_n, -- .export
ci_reg_n => ci_reg_n, -- .export
ci_a => ci_a, -- .export
ci_we_n => ci_we_n, -- .export
ci_oe_n => ci_oe_n, -- .export
ci_iowr_n => ci_iowr_n, -- .export
ci_iord_n => ci_iord_n, -- .export
cia_wait_n => cia_wait_n, -- .export
cib_wait_n => cib_wait_n, -- .export
cia_ireq_n => cia_ireq_n, -- .export
cib_ireq_n => cib_ireq_n, -- .export
cia_cd_n => cia_cd_n, -- .export
cib_cd_n => cib_cd_n, -- .export
cia_overcurrent_n => cia_overcurrent_n, -- .export
cib_overcurrent_n => cib_overcurrent_n, -- .export
cia_reset_buf_oe_n => cia_reset_buf_oe_n, -- .export
cib_reset_buf_oe_n => cib_reset_buf_oe_n, -- .export
cia_data_buf_oe_n => cia_data_buf_oe_n, -- .export
cib_data_buf_oe_n => cib_data_buf_oe_n, -- .export
ci_bus_dir => ci_bus_dir, -- .export
interrupt => interrupt, -- .export
cam_interrupts => cam_interrupts, -- .export
cam0_ready => cam0_ready, -- .export
cam0_bypass => cam0_bypass, -- .export
cam1_ready => cam1_ready, -- .export
cam1_bypass => cam1_bypass, -- .export
cam0_fail => cam0_fail, -- .export
cam1_fail => cam1_fail, -- .export
ci_d_out => ci_d_out, -- .export
ci_d_in => ci_d_in, -- .export
ci_d_en => ci_d_en, -- .export
cam_writedata => cam_writedata, -- .export
cam_write => cam_write, -- .export
cam_readdata => cam_readdata, -- .export
cam_read => cam_read, -- .export
cam_address => cam_address, -- .export
cam_waitreq => cam_waitreq -- .export
);
end architecture rtl; -- of ci_bridge_0
|
-- -------------------------------------------------------------
--
-- Generated Entity Declaration for %ENTYNAME%
--
-- Based on Mix Entity Template mix_template-e.vhd
--
-- (C) 2002 Micronas GmbH
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: lutscher $
-- $Id: mix_template-e.vhd,v 1.1 2009/12/15 12:02:53 lutscher Exp $
-- $Date: 2009/12/15 12:02:53 $
-- $Log: mix_template-e.vhd,v $
-- Revision 1.1 2009/12/15 12:02:53 lutscher
-- initial release
--
-- Revision 1.1 2003/03/25 13:49:00 wig
-- VHDL Templates
--
--
-- Generator: %0%%VERSION%, wilfried.gaensheimer@micronas.com
--
-- --------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
entity %ENTYNAME% is
generic(
-- %GEN% : %TYPE% := %VALUE;
-- generic list
);
port(
-- generated
%S% : %IO% %TYPE%;
-- %IO% := in|out|inout|buffer
-- CLK : in std_ulogic;
-- RESET : in std_ulogic;
-- TEST_SE : in std_ulogic;
-- AM_PM_DISPLAY : out std_ulogic;
-- DISP1 : out std_ulogic_vector(13 downto 0);
-- DISP2 : out std_ulogic_vector(13 downto 0)
);
end %ENTYNAME%;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific RAM selector
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity Ram32_tech is
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of Ram32_tech is
component Ram32_inferred
generic (
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
-- micron 180 nm tech
component micron180_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
-- TODO: add there other ASIC components
begin
genmem0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
ram_infer : Ram32_inferred generic map
(
generic_kWords => generic_kWords
) port map
(
i_clk,
i_address,
i_wr_ena,
i_data,
o_data
);
end generate;
genmem1 : if generic_tech = micron180 generate
k4 : if generic_kWords = 4 generate
x0 : micron180_syncram
generic map (12, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
k8 : if generic_kWords = 8 generate
x0 : micron180_syncram
generic map (13, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
end generate;
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific RAM selector
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity Ram32_tech is
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of Ram32_tech is
component Ram32_inferred
generic (
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
-- micron 180 nm tech
component micron180_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
-- TODO: add there other ASIC components
begin
genmem0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
ram_infer : Ram32_inferred generic map
(
generic_kWords => generic_kWords
) port map
(
i_clk,
i_address,
i_wr_ena,
i_data,
o_data
);
end generate;
genmem1 : if generic_tech = micron180 generate
k4 : if generic_kWords = 4 generate
x0 : micron180_syncram
generic map (12, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
k8 : if generic_kWords = 8 generate
x0 : micron180_syncram
generic map (13, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
end generate;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
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